} drm_device_t;
#if __OS_HAS_AGP
- typedef struct drm_agp_ttm_priv {
+ typedef struct drm_agp_ttm_backend {
+ drm_ttm_backend_t backend;
DRM_AGP_MEM *mem;
struct agp_bridge_data *bridge;
- unsigned alloc_type;
- unsigned cached_type;
- unsigned uncached_type;
int populated;
- } drm_agp_ttm_priv;
+ } drm_agp_ttm_backend_t;
#endif
+#define ATI_PCIGART_FLAG_VMALLOC 1
+struct ati_pcigart_memory {
+ size_t page_count;
+ unsigned long *memory;
+ int flags;
+};
+
+typedef struct ati_pcigart_ttm_priv {
+ int populated;
+ struct ati_pcigart_memory *mem;
+} ati_pcigart_ttm_priv;
static __inline__ int drm_core_check_feature(struct drm_device *dev,
int feature)
*/
#define DRIVER_MAJOR 1
- #define DRIVER_MINOR 26
+ #define DRIVER_MINOR 28
#define DRIVER_PATCHLEVEL 0
+#if defined(__linux__)
+#define RADEON_HAVE_FENCE
+#define RADEON_HAVE_BUFFER
+#endif
+
/*
* Radeon chip families
*/
struct mem_block *fb_heap;
/* SW interrupt */
- wait_queue_head_t swi_queue;
- atomic_t swi_emitted;
+ wait_queue_head_t irq_queue;
+ int counter;
+
+ int vblank_crtc;
+ uint32_t irq_enable_reg;
+ int irq_enabled;
+
struct radeon_surface surfaces[RADEON_MAX_SURFACES];
struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES];
drm_radeon_private_t *dev_priv =
(drm_radeon_private_t *) dev->dev_private;
- atomic_set(&dev_priv->swi_emitted, 0);
- DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
+ dev_priv->counter = 0;
+ DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
- /* Turn on SW and VBL ints */
- RADEON_WRITE(RADEON_GEN_INT_CNTL,
- RADEON_CRTC_VBLANK_MASK | RADEON_SW_INT_ENABLE);
+ radeon_enable_interrupt(dev);
}
void radeon_driver_irq_uninstall(drm_device_t * dev)