[RISCV] Add mnemonic alias: move, sbreak and scall.

Further improve compatibility with the GNU assembler.

Differential Revision: https://reviews.llvm.org/D50217
Patch by Kito Cheng.

llvm-svn: 339255

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 7327d42..dd19e31 100644 (file)
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -581,6 +581,14 @@ def : InstAlias<"sltu $rd, $rs1, $imm12",
                 (SLTIU  GPR:$rd, GPR:$rs1, simm12:$imm12)>;
 }
 
+def : MnemonicAlias<"move", "mv">;
+
+// The SCALL and SBREAK instructions wererenamed to ECALL and EBREAK in
+// version 2.1 of the user-level ISA. Like the GNU toolchain, we still accept
+// the old name for backwards compatibility.
+def : MnemonicAlias<"scall", "ecall">;
+def : MnemonicAlias<"sbreak", "ebreak">;
+
 //===----------------------------------------------------------------------===//
 // Pseudo-instructions and codegen patterns
 //

diff --git a/llvm/test/MC/RISCV/rvi-aliases-valid.s b/llvm/test/MC/RISCV/rvi-aliases-valid.s
index e2b22c1..6e402b1 100644 (file)
--- a/llvm/test/MC/RISCV/rvi-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rvi-aliases-valid.s
@@ -35,6 +35,9 @@ nop
 # CHECK-INST: addi t6, zero, 0
 # CHECK-ALIAS: mv t6, zero
 mv x31, zero
+# CHECK-INST: addi a2, a3, 0
+# CHECK-ALIAS: mv a2, a3
+move a2,a3
 # CHECK-INST: xori t6, ra, -1
 # CHECK-ALIAS: not t6, ra
 not x31, x1
@@ -193,3 +196,11 @@ slt a2,a3,4
 # CHECK-INST: sltiu a2, a3, 4
 # CHECK-ALIAS: sltiu a2, a3, 4
 sltu a2,a3,4
+
+# CHECK-INST: ebreak
+# CHECK-ALIAS: ebreak
+sbreak
+
+# CHECK-INST: ecall
+# CHECK-ALIAS: ecall
+scall