PMC405 board added.
authorstroese <stroese>
Fri, 23 May 2003 11:35:47 +0000 (11:35 +0000)
committerstroese <stroese>
Fri, 23 May 2003 11:35:47 +0000 (11:35 +0000)
board/esd/pmc405/Makefile [new file with mode: 0644]
board/esd/pmc405/config.mk [new file with mode: 0644]
board/esd/pmc405/pmc405.c [new file with mode: 0644]
board/esd/pmc405/strataflash.c [new file with mode: 0644]
board/esd/pmc405/u-boot.lds [new file with mode: 0644]
include/configs/PMC405.h [new file with mode: 0644]

diff --git a/board/esd/pmc405/Makefile b/board/esd/pmc405/Makefile
new file mode 100644 (file)
index 0000000..2fa097a
--- /dev/null
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = lib$(BOARD).a
+
+OBJS   = $(BOARD).o strataflash.o
+
+$(LIB):        $(OBJS) $(SOBJS)
+       $(AR) crv $@ $^
+
+clean:
+       rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:       Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+               $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/esd/pmc405/config.mk b/board/esd/pmc405/config.mk
new file mode 100644 (file)
index 0000000..fc2794d
--- /dev/null
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd PMC405 boards
+#
+
+TEXT_BASE = 0xFFFC0000
diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c
new file mode 100644 (file)
index 0000000..78eed9f
--- /dev/null
@@ -0,0 +1,229 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <cmd_boot.h>
+#include <malloc.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+/* Prototypes */
+int gunzip(void *, int, unsigned char *, int *);
+
+
+int board_pre_init (void)
+{
+       /*
+        * IRQ 0-15  405GP internally generated; active high; level sensitive
+        * IRQ 16    405GP internally generated; active low; level sensitive
+        * IRQ 17-24 RESERVED
+        * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+        * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+        * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+        * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+        * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+        * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+        * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+        */
+       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(uicer, 0x00000000);       /* disable all ints */
+       mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
+       mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
+       mtdcr(uictr, 0x10000000);       /* set int trigger levels */
+       mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+
+       /*
+        * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+        */
+       mtebc (epcr, 0xa8400000);
+
+       return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_f (void)
+{
+       return 0;  /* dummy implementation */
+}
+
+
+int misc_init_r (void)
+{
+#if 0 /* test-only */
+       DECLARE_GLOBAL_DATA_PTR;
+       volatile unsigned short *fpga_mode =
+               (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+       volatile unsigned char *duart0_mcr =
+               (unsigned char *)((ulong)DUART0_BA + 4);
+       volatile unsigned char *duart1_mcr =
+               (unsigned char *)((ulong)DUART1_BA + 4);
+       bd_t *bd = gd->bd;
+       char *  tmp;                    /* Temporary char pointer      */
+       unsigned char *dst;
+       ulong len = sizeof(fpgadata);
+       int status;
+       int index;
+       int i;
+       unsigned long cntrl0Reg;
+
+       /*
+        * Setup GPIO pins (CS6+CS7 as GPIO)
+        */
+       cntrl0Reg = mfdcr(cntrl0);
+       mtdcr(cntrl0, cntrl0Reg | 0x00300000);
+
+       dst = malloc(CFG_FPGA_MAX_SIZE);
+       if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
+               printf ("GUNZIP ERROR - must RESET board to recover\n");
+               do_reset (NULL, 0, 0, NULL);
+       }
+
+       status = fpga_boot(dst, len);
+       if (status != 0) {
+               printf("\nFPGA: Booting failed ");
+               switch (status) {
+               case ERROR_FPGA_PRG_INIT_LOW:
+                       printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+                       break;
+               case ERROR_FPGA_PRG_INIT_HIGH:
+                       printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+                       break;
+               case ERROR_FPGA_PRG_DONE:
+                       printf("(Timeout: DONE not high after programming FPGA)\n ");
+                       break;
+               }
+
+               /* display infos on fpgaimage */
+               index = 15;
+               for (i=0; i<4; i++) {
+                       len = dst[index];
+                       printf("FPGA: %s\n", &(dst[index+1]));
+                       index += len+3;
+               }
+               putc ('\n');
+               /* delayed reboot */
+               for (i=20; i>0; i--) {
+                       printf("Rebooting in %2d seconds \r",i);
+                       for (index=0;index<1000;index++)
+                               udelay(1000);
+               }
+               putc ('\n');
+               do_reset(NULL, 0, 0, NULL);
+       }
+
+       /* restore gpio/cs settings */
+       mtdcr(cntrl0, cntrl0Reg);
+
+       puts("FPGA:  ");
+
+       /* display infos on fpgaimage */
+       index = 15;
+       for (i=0; i<4; i++) {
+               len = dst[index];
+               printf("%s ", &(dst[index+1]));
+               index += len+3;
+       }
+       putc ('\n');
+
+       free(dst);
+
+       /*
+        * Reset FPGA via FPGA_DATA pin
+        */
+       SET_FPGA(FPGA_PRG | FPGA_CLK);
+       udelay(1000); /* wait 1ms */
+       SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+       udelay(1000); /* wait 1ms */
+
+       /*
+        * Enable power on PS/2 interface
+        */
+       *fpga_mode |= CFG_FPGA_CTRL_PS2_RESET;
+
+       /*
+        * Enable interrupts in exar duart mcr[3]
+        */
+       *duart0_mcr = 0x08;
+       *duart1_mcr = 0x08;
+#endif
+
+       return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+       unsigned char str[64];
+       int i = getenv_r ("serial#", str, sizeof(str));
+
+       puts ("Board: ");
+
+       if (i == -1) {
+               puts ("### No HW ID - assuming ABG405");
+       } else {
+               puts(str);
+       }
+
+       putc ('\n');
+
+       return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+       unsigned long val;
+
+       mtdcr(memcfga, mem_mb0cf);
+       val = mfdcr(memcfgd);
+
+#if 0
+       printf("\nmb0cf=%x\n", val); /* test-only */
+       printf("strap=%x\n", mfdcr(strap)); /* test-only */
+#endif
+
+       return (4*1024*1024 << ((val & 0x000e0000) >> 17));
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+       /* TODO: XXX XXX XXX */
+       printf ("test: 16 MB - ok\n");
+
+       return (0);
+}
+
+/* ------------------------------------------------------------------------- */
diff --git a/board/esd/pmc405/strataflash.c b/board/esd/pmc405/strataflash.c
new file mode 100644 (file)
index 0000000..6578ed9
--- /dev/null
@@ -0,0 +1,796 @@
+/*
+ * (C) Copyright 2002
+ * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#undef  DEBUG_FLASH 
+/*
+ * This file implements a Common Flash Interface (CFI) driver for ppcboot.
+ * The width of the port and the width of the chips are determined at initialization.
+ * These widths are used to calculate the address for access CFI data structures.
+ * It has been tested on an Intel Strataflash implementation.
+ *
+ * References
+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
+ *
+ * TODO
+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
+ * Add support for other command sets Use the PRI and ALT to determine command set
+ * Verify erase and program timeouts.
+ */
+
+#define FLASH_CMD_CFI                  0x98
+#define FLASH_CMD_READ_ID              0x90
+#define FLASH_CMD_RESET                        0xff
+#define FLASH_CMD_BLOCK_ERASE          0x20
+#define FLASH_CMD_ERASE_CONFIRM                0xD0
+#define FLASH_CMD_WRITE                        0x40
+#define FLASH_CMD_PROTECT              0x60
+#define FLASH_CMD_PROTECT_SET          0x01
+#define FLASH_CMD_PROTECT_CLEAR                0xD0
+#define FLASH_CMD_CLEAR_STATUS         0x50
+#define FLASH_CMD_WRITE_TO_BUFFER       0xE8
+#define FLASH_CMD_WRITE_BUFFER_CONFIRM  0xD0
+
+#define FLASH_STATUS_DONE              0x80
+#define FLASH_STATUS_ESS               0x40
+#define FLASH_STATUS_ECLBS             0x20
+#define FLASH_STATUS_PSLBS             0x10
+#define FLASH_STATUS_VPENS             0x08
+#define FLASH_STATUS_PSS               0x04
+#define FLASH_STATUS_DPS               0x02
+#define FLASH_STATUS_R                 0x01
+#define FLASH_STATUS_PROTECT           0x01
+
+#define FLASH_OFFSET_CFI               0x55
+#define FLASH_OFFSET_CFI_RESP          0x10
+#define FLASH_OFFSET_WTOUT             0x1F
+#define FLASH_OFFSET_WBTOUT             0x20
+#define FLASH_OFFSET_ETOUT             0x21
+#define FLASH_OFFSET_CETOUT             0x22
+#define FLASH_OFFSET_WMAX_TOUT         0x23
+#define FLASH_OFFSET_WBMAX_TOUT         0x24
+#define FLASH_OFFSET_EMAX_TOUT         0x25
+#define FLASH_OFFSET_CEMAX_TOUT         0x26
+#define FLASH_OFFSET_SIZE              0x27
+#define FLASH_OFFSET_INTERFACE          0x28
+#define FLASH_OFFSET_BUFFER_SIZE        0x2A
+#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
+#define FLASH_OFFSET_ERASE_REGIONS     0x2D
+#define FLASH_OFFSET_PROTECT           0x02
+#define FLASH_OFFSET_USER_PROTECTION    0x85
+#define FLASH_OFFSET_INTEL_PROTECTION   0x81
+
+
+#define FLASH_MAN_CFI                  0x01000000
+
+
+
+
+typedef union {
+       unsigned char c;
+       unsigned short w;
+       unsigned long l;
+} cfiword_t;
+
+typedef union {
+       unsigned char * cp;
+       unsigned short *wp;
+       unsigned long *lp;
+} cfiptr_t;
+
+#define NUM_ERASE_REGIONS 4
+
+flash_info_t   flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips        */
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+
+
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c);
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_detect_cfi(flash_info_t * info);
+static ulong flash_get_size (ulong base, int banknum);
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
+#endif
+/*-----------------------------------------------------------------------
+ * create an address based on the offset and the port width
+ */
+inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset)
+{
+       return ((uchar *)(info->start[sect] + (offset * info->portwidth)));
+}
+/*-----------------------------------------------------------------------
+ * read a character at a port width address
+ */
+inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
+{
+       uchar *cp;
+       cp = flash_make_addr(info, 0, offset);
+       return (cp[info->portwidth - 1]);
+}
+
+/*-----------------------------------------------------------------------
+ * read a short word by swapping for ppc format.
+ */
+ushort flash_read_ushort(flash_info_t * info, int sect,  uchar offset)
+{
+    uchar * addr;
+
+    addr = flash_make_addr(info, sect, offset);
+    return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ * read a long word by picking the least significant byte of each maiximum
+ * port size word. Swap for ppc format.
+ */
+ulong flash_read_long(flash_info_t * info, int sect,  uchar offset)
+{
+    uchar * addr;
+
+    addr = flash_make_addr(info, sect, offset);
+    return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) |
+           (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+       unsigned long size;
+       int i;
+       unsigned long  address;
+
+
+       /* The flash is positioned back to back, with the demultiplexing of the chip
+        * based on the A24 address line.
+        *
+        */
+
+       address = CFG_FLASH_BASE;
+       size = 0;
+
+       /* Init: no FLASHes known */
+       for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+               flash_info[i].flash_id = FLASH_UNKNOWN;
+               size += flash_info[i].size = flash_get_size(address, i);
+               address += CFG_FLASH_INCREMENT;
+               if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+                       printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
+                               flash_info[0].size, flash_info[i].size<<20);
+               }
+       }
+
+#if 0 /* test-only */
+       /* Monitor protection ON by default */
+#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
+       for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+CFG_MONITOR_LEN-1; i++)
+               (void)flash_real_protect(&flash_info[0], i, 1);
+#endif
+#else
+       /* monitor protection ON by default */
+       flash_protect (FLAG_PROTECT_SET,
+                      - CFG_MONITOR_LEN,
+                      - 1, &flash_info[1]);
+#endif
+
+       return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+       int rcode = 0;
+       int prot;
+       int sect;
+
+       if( info->flash_id != FLASH_MAN_CFI) {
+               printf ("Can't erase unknown flash type - aborted\n");
+               return 1;
+       }
+       if ((s_first < 0) || (s_first > s_last)) {
+               printf ("- no sectors to erase\n");
+               return 1;
+       }
+
+       prot = 0;
+       for (sect=s_first; sect<=s_last; ++sect) {
+               if (info->protect[sect]) {
+                       prot++;
+               }
+       }
+       if (prot) {
+               printf ("- Warning: %d protected sectors will not be erased!\n",
+                       prot);
+       } else {
+               printf ("\n");
+       }
+
+
+       for (sect = s_first; sect<=s_last; sect++) {
+               if (info->protect[sect] == 0) { /* not protected */
+                       flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
+                       flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
+                       flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
+                       
+                       if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
+                               rcode = 1;
+                       } else
+                               printf(".");
+               }
+       }
+       printf (" done\n");
+       return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+       int i;
+
+       if (info->flash_id != FLASH_MAN_CFI) {
+               printf ("missing or unknown FLASH type\n");
+               return;
+       }
+
+       printf("CFI conformant FLASH (%d x %d)",
+              (info->portwidth  << 3 ), (info->chipwidth  << 3 ));
+       printf ("  Size: %ld MB in %d Sectors\n",
+               info->size >> 20, info->sector_count);
+       printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
+              info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
+      
+       printf ("  Sector Start Addresses:");
+       for (i=0; i<info->sector_count; ++i) {
+#ifdef CFG_FLASH_EMPTY_INFO
+               int k;
+               int size;
+               int erased;
+               volatile unsigned long *flash;
+
+                /*
+                 * Check if whole sector is erased
+                 */
+                if (i != (info->sector_count-1))
+                  size = info->start[i+1] - info->start[i];
+                else
+                  size = info->start[0] + info->size - info->start[i];
+                erased = 1;
+                flash = (volatile unsigned long *)info->start[i];
+                size = size >> 2;        /* divide by 4 for longword access */
+                for (k=0; k<size; k++)
+                  {
+                    if (*flash++ != 0xffffffff)
+                      {
+                        erased = 0;
+                        break;
+                      }
+                  }
+
+               if ((i % 5) == 0)
+                       printf ("\n   ");
+                /* print empty and read-only info */
+               printf (" %08lX%s%s",
+                       info->start[i],
+                       erased ? " E" : "  ",
+                       info->protect[i] ? "RO " : "   ");
+#else
+               if ((i % 5) == 0)
+                       printf ("\n   ");
+               printf (" %08lX%s",
+                       info->start[i],
+                       info->protect[i] ? " (RO)" : "     ");
+#endif
+       }
+       printf ("\n");
+       return;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+       ulong wp;
+       ulong cp;
+       int aln;
+       cfiword_t cword;
+       int i, rc;
+
+       /* get lower aligned address */
+       wp = (addr & ~(info->portwidth - 1));
+
+       /* handle unaligned start */
+       if((aln = addr - wp) != 0) {
+               cword.l = 0;
+               cp = wp;
+               for(i=0;i<aln; ++i, ++cp)
+                       flash_add_byte(info, &cword, (*(uchar *)cp));
+
+               for(; (i< info->portwidth) && (cnt > 0) ; i++) {
+                       flash_add_byte(info, &cword, *src++);
+                       cnt--;
+                       cp++;
+               }
+               for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
+                       flash_add_byte(info, &cword, (*(uchar *)cp));
+               if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+                       return rc;
+               wp = cp;
+       }
+
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+       while(cnt >= info->portwidth) {
+               i = info->buffer_size > cnt? cnt: info->buffer_size;
+               if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
+                       return rc;
+               wp += i;
+               src += i;
+               cnt -=i;
+       }
+#else
+       /* handle the aligned part */
+       while(cnt >= info->portwidth) {
+               cword.l = 0;
+               for(i = 0; i < info->portwidth; i++) {
+                       flash_add_byte(info, &cword, *src++);
+               }
+               if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+                       return rc;
+               wp += info->portwidth;
+               cnt -= info->portwidth;
+       }
+#endif /* CFG_FLASH_USE_BUFFER_WRITE */
+       if (cnt == 0) {
+               return (0);
+       }
+
+       /*
+        * handle unaligned tail bytes
+        */
+       cword.l = 0;
+       for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) {
+               flash_add_byte(info, &cword, *src++);
+               --cnt;
+       }
+       for (; i<info->portwidth; ++i, ++cp) {
+               flash_add_byte(info, & cword, (*(uchar *)cp));
+       }
+
+       return flash_write_cfiword(info, wp, cword);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+       int retcode = 0;
+
+       flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+       flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
+       if(prot)
+               flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
+       else
+               flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
+
+       if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, 
+                                        prot?"protect":"unprotect")) == 0) {
+
+               info->protect[sector] = prot;
+               /* Intel's unprotect unprotects all locking */
+               if(prot == 0) {
+                       int i;
+                       for(i = 0 ; i<info->sector_count; i++) {
+                               if(info->protect[i])
+                                       flash_real_protect(info, i, 1);
+                       }
+               }
+       }
+
+       return retcode;
+}
+/*-----------------------------------------------------------------------
+ *  wait for XSR.7 to be set. Time out with an error if it does not.
+ *  This routine does not set the flash to read-array mode.
+ */
+static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+       ulong start;
+
+       /* Wait for command completion */
+       start = get_timer (0);
+       while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
+               if (get_timer(start) > info->erase_blk_tout) {
+                       printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]);
+                       flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+                       return ERR_TIMOUT;
+               }
+       }
+       return ERR_OK;
+}
+/*-----------------------------------------------------------------------
+ * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
+ * This routine sets the flash to read-array mode.
+ */
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+       int retcode;
+       retcode = flash_status_check(info, sector, tout, prompt);
+       if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
+               retcode = ERR_INVAL;
+               printf("Flash %s error at address %lx\n", prompt,info->start[sector]);
+               if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){
+                       printf("Command Sequence Error.\n");
+               } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
+                       printf("Block Erase Error.\n");
+                       retcode = ERR_NOT_ERASED;
+               } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
+                       printf("Locking Error\n");
+               }
+               if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){
+                       printf("Block locked.\n");
+                       retcode = ERR_PROTECTED;
+               }
+               if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
+                       printf("Vpp Low Error.\n");
+       }
+       flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+       return retcode;
+}
+/*-----------------------------------------------------------------------
+ */
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c)
+{
+       switch(info->portwidth) {
+       case FLASH_CFI_8BIT:
+               cword->c = c;
+               break;
+       case FLASH_CFI_16BIT:
+               cword->w = (cword->w << 8) | c;
+               break;
+       case FLASH_CFI_32BIT:
+               cword->l = (cword->l << 8) | c;
+       }
+}
+
+
+/*-----------------------------------------------------------------------
+ * make a proper sized command based on the port and chip widths
+ */
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
+{
+       int i;
+       uchar *cp = (uchar *)cmdbuf;
+       for(i=0; i< info->portwidth; i++)
+               *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
+}
+
+/*
+ * Write a proper sized command to the correct address
+ */
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+
+       volatile cfiptr_t addr;
+       cfiword_t cword;
+       addr.cp = flash_make_addr(info, sect, offset);
+       flash_make_cmd(info, cmd, &cword);
+       switch(info->portwidth) {
+       case FLASH_CFI_8BIT:
+               *addr.cp = cword.c;
+               break;
+       case FLASH_CFI_16BIT:
+               *addr.wp = cword.w;
+               break;
+       case FLASH_CFI_32BIT:
+               *addr.lp = cword.l;
+               break;
+       }
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+       cfiptr_t cptr;
+       cfiword_t cword;
+       int retval;
+       cptr.cp = flash_make_addr(info, sect, offset);
+       flash_make_cmd(info, cmd, &cword);
+       switch(info->portwidth) {
+       case FLASH_CFI_8BIT:
+               retval = (cptr.cp[0] == cword.c);
+               break;
+       case FLASH_CFI_16BIT:
+               retval = (cptr.wp[0] == cword.w);
+               break;
+       case FLASH_CFI_32BIT:
+               retval = (cptr.lp[0] == cword.l);
+               break;
+       default:
+               retval = 0;
+               break;
+       }
+       return retval;
+}
+/*-----------------------------------------------------------------------
+ */
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+       cfiptr_t cptr;
+       cfiword_t cword;
+       int retval;
+       cptr.cp = flash_make_addr(info, sect, offset);
+       flash_make_cmd(info, cmd, &cword);
+       switch(info->portwidth) {
+       case FLASH_CFI_8BIT:
+               retval = ((cptr.cp[0] & cword.c) == cword.c);
+               break;
+       case FLASH_CFI_16BIT:
+               retval = ((cptr.wp[0] & cword.w) == cword.w);
+               break;
+       case FLASH_CFI_32BIT:
+               retval = ((cptr.lp[0] & cword.l) == cword.l);
+               break;
+       default:
+               retval = 0;
+               break;
+       }
+       return retval;
+}
+
+/*-----------------------------------------------------------------------
+ * detect if flash is compatible with the Common Flash Interface (CFI)
+ * http://www.jedec.org/download/search/jesd68.pdf
+ *
+*/
+static int flash_detect_cfi(flash_info_t * info)
+{
+
+       for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT;
+           info->portwidth <<= 1) {
+               for(info->chipwidth =FLASH_CFI_BY8;
+                   info->chipwidth <= info->portwidth;
+                   info->chipwidth <<= 1) {
+                       flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+                       flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
+                       if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
+                          flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
+                          flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y'))
+                               return 1;
+               }
+       }
+       return 0;
+}
+/*
+ * The following code cannot be run from FLASH!
+ *
+ */
+static ulong flash_get_size (ulong base, int banknum)
+{
+       flash_info_t * info = &flash_info[banknum];
+       int i, j;
+       int sect_cnt;
+       unsigned long sector;
+       unsigned long tmp;
+       int size_ratio;
+       uchar num_erase_regions;
+       int  erase_region_size;
+       int  erase_region_count;
+
+       info->start[0] = base;
+
+       if(flash_detect_cfi(info)){
+#ifdef DEBUG_FLASH
+               printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
+#endif
+               size_ratio = info->portwidth / info->chipwidth;
+               num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
+#ifdef DEBUG_FLASH
+               printf("found %d erase regions\n", num_erase_regions);
+#endif
+               sect_cnt = 0;
+               sector = base;
+               for(i = 0 ; i < num_erase_regions; i++) {
+                       if(i > NUM_ERASE_REGIONS) {
+                               printf("%d erase regions found, only %d used\n",
+                                      num_erase_regions, NUM_ERASE_REGIONS);
+                               break;
+                       }
+                       tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS);
+                       erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
+                       tmp >>= 16;
+                       erase_region_count = (tmp & 0xffff) +1;
+                       for(j = 0; j< erase_region_count; j++) {
+                               info->start[sect_cnt] = sector;
+                               sector += (erase_region_size * size_ratio);
+                               info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
+                               sect_cnt++;
+                       }
+               }
+
+               info->sector_count = sect_cnt;
+               /* multiply the size by the number of chips */
+               info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
+               info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
+               tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
+               info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
+               tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
+               info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
+               tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
+               info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
+               info->flash_id = FLASH_MAN_CFI;
+       }
+
+       flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+       return(info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
+{
+
+       cfiptr_t ctladdr;
+       cfiptr_t cptr;
+       int flag;
+
+       ctladdr.cp = flash_make_addr(info, 0, 0);
+       cptr.cp = (uchar *)dest;
+
+
+       /* Check if Flash is (sufficiently) erased */
+       switch(info->portwidth) {
+       case FLASH_CFI_8BIT:
+               flag = ((cptr.cp[0] & cword.c) == cword.c);
+               break;
+       case FLASH_CFI_16BIT:
+               flag = ((cptr.wp[0] & cword.w) == cword.w);
+               break;
+       case FLASH_CFI_32BIT:
+               flag = ((cptr.lp[0] & cword.l)  == cword.l);
+               break;
+       default:
+               return 2;
+       }
+       if(!flag)
+               return 2;
+
+       /* Disable interrupts which might cause a timeout here */
+       flag = disable_interrupts();
+
+       flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
+       flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
+
+       switch(info->portwidth) {
+       case FLASH_CFI_8BIT:
+               cptr.cp[0] = cword.c;
+               break;
+       case FLASH_CFI_16BIT:
+               cptr.wp[0] = cword.w;
+               break;
+       case FLASH_CFI_32BIT:
+               cptr.lp[0] = cword.l;
+               break;
+       }
+
+       /* re-enable interrupts if necessary */
+       if(flag)
+               enable_interrupts();
+
+       return flash_full_status_check(info, 0, info->write_tout, "write");
+}
+
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+
+/* loop through the sectors from the highest address
+ * when the passed address is greater or equal to the sector address
+ * we have a match
+ */
+static int find_sector(flash_info_t *info, ulong addr)
+{
+       int sector;
+       for(sector = info->sector_count - 1; sector >= 0; sector--) {
+               if(addr >= info->start[sector]) 
+                       break;
+       }
+       return sector;
+}
+
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
+{
+       
+       int sector;
+       int cnt;
+       int retcode;
+       volatile cfiptr_t src;
+       volatile cfiptr_t dst;
+
+       src.cp = cp;
+       dst.cp = (uchar *)dest;
+       sector = find_sector(info, dest);
+       flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+       flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
+       if((retcode = flash_status_check(info, sector, info->buffer_write_tout,
+                                        "write to buffer")) == ERR_OK) {
+               switch(info->portwidth) {
+               case FLASH_CFI_8BIT:
+                       cnt = len;
+                       break;
+               case FLASH_CFI_16BIT:
+                       cnt = len >> 1;
+                       break;
+               case FLASH_CFI_32BIT:
+                       cnt = len >> 2;
+                       break;
+               default:
+                       return ERR_INVAL;
+                       break;
+               }
+               flash_write_cmd(info, sector, 0, (uchar)cnt-1);
+               while(cnt-- > 0) {
+                       switch(info->portwidth) {
+                       case FLASH_CFI_8BIT:
+                               *dst.cp++ = *src.cp++;
+                               break;
+                       case FLASH_CFI_16BIT:
+                               *dst.wp++ = *src.wp++;
+                               break;
+                       case FLASH_CFI_32BIT:
+                               *dst.lp++ = *src.lp++;
+                               break;
+                       default:
+                               return ERR_INVAL;
+                               break;
+                       }
+               }
+               flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
+               retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
+                                            "buffer write");
+       } 
+       flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+       return retcode;
+}      
+#endif /* CFG_USE_FLASH_BUFFER_WRITE */
diff --git a/board/esd/pmc405/u-boot.lds b/board/esd/pmc405/u-boot.lds
new file mode 100644 (file)
index 0000000..2667560
--- /dev/null
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)          }
+  .dynsym        : { *(.dynsym)                }
+  .dynstr        : { *(.dynstr)                }
+  .rel.text      : { *(.rel.text)              }
+  .rela.text     : { *(.rela.text)     }
+  .rel.data      : { *(.rel.data)              }
+  .rela.data     : { *(.rela.data)     }
+  .rel.rodata    : { *(.rel.rodata)    }
+  .rela.rodata   : { *(.rela.rodata)   }
+  .rel.got       : { *(.rel.got)               }
+  .rela.got      : { *(.rela.got)              }
+  .rel.ctors     : { *(.rel.ctors)     }
+  .rela.ctors    : { *(.rela.ctors)    }
+  .rel.dtors     : { *(.rel.dtors)     }
+  .rela.dtors    : { *(.rela.dtors)    }
+  .rel.bss       : { *(.rel.bss)               }
+  .rela.bss      : { *(.rela.bss)              }
+  .rel.plt       : { *(.rel.plt)               }
+  .rela.plt      : { *(.rela.plt)              }
+  .init          : { *(.init)  }
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within */
+    /* the sector layout of our flash chips!   XXX FIXME XXX   */
+
+    cpu/ppc4xx/start.o (.text)
+    cpu/ppc4xx/traps.o (.text)
+    cpu/ppc4xx/interrupts.o    (.text)
+    cpu/ppc4xx/serial.o        (.text)
+    cpu/ppc4xx/cpu_init.o      (.text)
+    cpu/ppc4xx/speed.o (.text)
+    cpu/ppc4xx/405gp_enet.o    (.text)
+    common/dlmalloc.o  (.text)
+    lib_generic/crc32.o                (.text)
+    lib_ppc/extable.o  (.text)
+    lib_generic/zlib.o         (.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h
new file mode 100644 (file)
index 0000000..6965ebe
--- /dev/null
@@ -0,0 +1,277 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP           1       /* This is a PPC405 CPU         */
+#define CONFIG_4xx             1       /* ...member of PPC4xx family   */
+#define CONFIG_PMC405          1       /* ...on a PMC405 board         */
+
+#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
+#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
+
+#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
+
+#define CONFIG_BAUDRATE                9600
+#define CONFIG_BOOTDELAY       3       /* autoboot after 3 seconds     */
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_RAMBOOTCOMMAND                                                  \
+       "setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) "     \
+       "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"    \
+       "bootm ffc00000 ffca0000"
+#define CONFIG_NFSBOOTCOMMAND                                                  \
+       "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "     \
+       "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"    \
+       "bootm ffc00000"
+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+
+#define CONFIG_LOADS_ECHO      1       /* echo on for serial download  */
+#define CFG_LOADS_BAUD_CHANGE  1       /* allow baudrate change        */
+
+#define CONFIG_MII             1       /* MII PHY management           */
+#define        CONFIG_PHY_ADDR         0       /* PHY address                  */
+
+#define CONFIG_COMMANDS              ( CONFIG_CMD_DFL  | \
+                               CFG_CMD_PCI     | \
+                               CFG_CMD_IRQ     | \
+                               CFG_CMD_ELF     | \
+                               CFG_CMD_DATE    | \
+                               CFG_CMD_JFFS2   | \
+                               CFG_CMD_MII     | \
+                               CFG_CMD_I2C     | \
+                               CFG_CMD_EEPROM  )
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef  CONFIG_WATCHDOG                        /* watchdog disabled            */
+
+#define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
+#define CFG_RTC_REG_BASE_ADDR   0xF0000300 /* RTC Base Address         */
+
+#define        CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP                   /* undef to save memory         */
+#define CFG_PROMPT     "=> "           /* Monitor Command Prompt       */
+
+#undef CFG_HUSH_PARSER                 /* use "hush" command parser    */
+#ifdef CFG_HUSH_PARSER
+#define        CFG_PROMPT_HUSH_PS2     "> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define        CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
+#else
+#define        CFG_CBSIZE      256             /* Console I/O Buffer Size      */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS    16              /* max number of command args   */
+#define CFG_BARGSIZE   CFG_CBSIZE      /* Boot Argument Buffer Size    */
+
+#define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
+
+#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
+
+#define CFG_MEMTEST_START      0x0400000       /* memtest works on     */
+#define CFG_MEMTEST_END                0x0C00000       /* 4 ... 12 MB in DRAM  */
+
+#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
+#define CFG_BASE_BAUD       691200
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE      \
+        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+         57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR  0x100000        /* default load address */
+#define CFG_EXTBDINFO  1               /* To use extended board_into (bd_t) */
+
+#define        CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK    /* check for keypress on bootdelay==0 */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI                     /* include pci support          */
+#define CONFIG_PCI_HOST        PCI_HOST_FORCE  /* select pci host function     */
+#define CONFIG_PCI_PNP                 /* do pci plug-and-play         */
+                                        /* resource configuration       */
+
+#undef CONFIG_PCI_SCAN_SHOW             /* print pci devices @ startup  */
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0408  /* PCI Device ID: PMC-405       */
+#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE         0x00000000
+#define CFG_MONITOR_BASE       0xFFFC0000
+#define CFG_MONITOR_LEN                (256 * 1024)    /* Reserve 256 kB for Monitor   */
+#define CFG_MALLOC_LEN         (128 * 1024)    /* Reserve 128 kB for malloc()  */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ          (8 << 20)       /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI          1       /* Flash is CFI conformant              */
+#define CFG_MAX_FLASH_SECT     128     /* max number of sectors on one chip    */
+#define CFG_MAX_FLASH_BANKS    2       /* max number of memory banks           */
+#undef CFG_FLASH_PROTECTION            /* don't use hardware protection        */
+#define CFG_FLASH_USE_BUFFER_WRITE 1   /* use buffered writes (20x faster)     */
+#define CFG_FLASH_BASE         0xFE000000
+#define CFG_FLASH_INCREMENT    0x01000000
+
+#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+
+#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains u-boot    */
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE            0x800   /* 2048 bytes may be used for env vars*/
+                                   /* total size of a CAT24WC16 is 2048 bytes */
+
+#define CFG_NVRAM_BASE_ADDR    0xF0000500              /* NVRAM base address   */
+#define CFG_NVRAM_SIZE         242                     /* NVRAM size           */
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C                        /* I2c with hardware support */
+#define CFG_I2C_SPEED          400000  /* I2C speed and slave address */
+#define CFG_I2C_SLAVE          0x7F
+
+#define CFG_I2C_EEPROM_ADDR    0x50    /* EEPROM CAT28WC08             */
+#define CFG_I2C_EEPROM_ADDR_LEN        1       /* Bytes of address             */
+/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW   0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4   /* The Catalyst CAT24WC08 has   */
+                                       /* 16 byte page write mode using*/
+                                       /* last 4 bits of the address   */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE                16384   /* For IBM 405 CPUs, older 405 ppc's    */
+                                        /* have only 8kB, 16kB is save here     */
+#define CFG_CACHELINE_SIZE     32      /* ...                  */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
+#endif
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+#define FLASH0_BA       0xFF000000          /* FLASH 0 Base Address             */
+#define FLASH1_BA       0xFE000000          /* FLASH 1 Base Address             */
+#define CAN_BA          0xF0000000          /* CAN Base Address                 */
+#define RTC_BA          0xF0000500          /* RTC Base Address                 */
+#define CF_BA           0xF0100000          /* CompactFlash Base Address        */
+
+/* Memory Bank 0 (Flash Bank 0) initialization                                  */
+#define CFG_EBC_PB0AP   0x92015480
+#define CFG_EBC_PB0CR   FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
+
+/* Memory Bank 1 (Flash Bank 1) initialization                                  */
+#define CFG_EBC_PB1AP   0x92015480
+#define CFG_EBC_PB1CR   FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
+
+/* Memory Bank 2 (CAN0, 1, RTC) initialization                                  */
+#define CFG_EBC_PB2AP   0x03000040   /* TWT=6,TH=0,CSN=0,OEN=0,WBN=0,WBF=0      */
+#define CFG_EBC_PB2CR   CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+
+/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization               */
+#define CFG_EBC_PB3AP   0x010059C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR   CF_BA | 0x1A000     /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM      1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR      0xF8000000
+#define CFG_OCM_DATA_SIZE      0x1000
+
+#define CFG_INIT_RAM_ADDR      CFG_OCM_DATA_ADDR /* inside of SDRAM            */
+#define CFG_INIT_RAM_END       CFG_OCM_DATA_SIZE /* End of used area in RAM    */
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD  0x01            /* Normal Power-On: Boot from FLASH     */
+#define BOOTFLAG_WARM  0x02            /* Software reboot                      */
+
+#endif /* __CONFIG_H */