osd: mali afbcd memory out of bound [1/1]

PD#TV-6683

Problem:
DMC error log as "ID:VPU READ1, sub: 7"

Solution:
make afbc disable, if afbc phy addr is 0

Verify:
verified on TL1-X301

Change-Id: I111c8e2e922877904dd8b8d1f276f79ca4f68e94
Signed-off-by: Jian Cao <jian.cao@amlogic.com>

diff --git a/drivers/amlogic/media/osd/osd_hw.c b/drivers/amlogic/media/osd/osd_hw.c
index 54b9c26..0ff5d33 100644 (file)
--- a/drivers/amlogic/media/osd/osd_hw.c
+++ b/drivers/amlogic/media/osd/osd_hw.c
@@ -5399,13 +5399,16 @@ static void osd_update_enable(u32 index)
                if ((osd_hw.osd_afbcd[index].enable == ENABLE)
                        && (osd_hw.enable[index] == ENABLE)
                        && !osd_hw.dim_layer[index]) {
-                       /* enable mali afbc */
-                       VSYNCOSD_WR_MPEG_REG(
-                               VPU_MAFBC_IRQ_MASK, 0xf);
-                       VSYNCOSD_WR_MPEG_REG_BITS(
-                               VPU_MAFBC_SURFACE_CFG,
-                               1, index, 1);
-                       osd_hw.osd_afbcd[index].afbc_start = 1;
+                       if (!osd_hw.osd_afbcd[index].afbc_start &&
+                                       osd_hw.osd_afbcd[index].phy_addr != 0) {
+                               /* enable mali afbc */
+                               VSYNCOSD_WR_MPEG_REG(
+                                       VPU_MAFBC_IRQ_MASK, 0xf);
+                               VSYNCOSD_WR_MPEG_REG_BITS(
+                                       VPU_MAFBC_SURFACE_CFG,
+                                       1, index, 1);
+                               osd_hw.osd_afbcd[index].afbc_start = 1;
+                       }
                } else {
                        /* disable mali afbc */
                        VSYNCOSD_WR_MPEG_REG_BITS(