drm/i915: abstract display suspend/resume operations

Increase abstraction of display suspend/resume operations by providing
higher level functions, and hiding the details inside
intel_display_power.c.

v2: Make checkpatch happy:
    - braces {} are not necessary for single statement blocks
v3: Also move hsw/bdw PC8 sequences since they are related to
    display PM anyways. (Ville)
v4: Rebase after a long time, plus Move functions to the new
    intel_display_power so we can stop exporting platform specific
    functions as pointed by Jani.
v5: Remove unnecessary braces.
v6 by Jani: make this purely non-functional cleanup, make functions static

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190806122208.16786-2-jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index e201dc6f977a1ccad7d4d904067b696943c5bd15..e3bea2b74ce2515fee0767fdab5ecd9d26319c19 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -727,7 +727,7 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
        return mask;
 }
 
-void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
+static void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
 {
        u32 val;
 
@@ -787,7 +787,7 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
        dev_priv->csr.dc_state = val & mask;
 }
 
-void bxt_enable_dc9(struct drm_i915_private *dev_priv)
+static void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 {
        assert_can_enable_dc9(dev_priv);
 
@@ -802,7 +802,7 @@ void bxt_enable_dc9(struct drm_i915_private *dev_priv)
        gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
 }
 
-void bxt_disable_dc9(struct drm_i915_private *dev_priv)
+static void bxt_disable_dc9(struct drm_i915_private *dev_priv)
 {
        assert_can_disable_dc9(dev_priv);
 
@@ -856,7 +856,7 @@ static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
        assert_csr_loaded(dev_priv);
 }
 
-void gen9_enable_dc5(struct drm_i915_private *dev_priv)
+static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 {
        assert_can_enable_dc5(dev_priv);
 
@@ -880,7 +880,7 @@ static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
        assert_csr_loaded(dev_priv);
 }
 
-void skl_enable_dc6(struct drm_i915_private *dev_priv)
+static void skl_enable_dc6(struct drm_i915_private *dev_priv)
 {
        assert_can_enable_dc6(dev_priv);
 
@@ -4441,7 +4441,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
  * For more, read "Display Sequences for Package C8" on the hardware
  * documentation.
  */
-void hsw_enable_pc8(struct drm_i915_private *dev_priv)
+static void hsw_enable_pc8(struct drm_i915_private *dev_priv)
 {
        u32 val;
 
@@ -4457,7 +4457,7 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv)
        hsw_disable_lcpll(dev_priv, true, true);
 }
 
-void hsw_disable_pc8(struct drm_i915_private *dev_priv)
+static void hsw_disable_pc8(struct drm_i915_private *dev_priv)
 {
        u32 val;
 
@@ -4557,8 +4557,7 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
        usleep_range(10, 30);           /* 10 us delay per Bspec */
 }
 
-void bxt_display_core_init(struct drm_i915_private *dev_priv,
-                          bool resume)
+static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume)
 {
        struct i915_power_domains *power_domains = &dev_priv->power_domains;
        struct i915_power_well *well;
@@ -4589,7 +4588,7 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
                intel_csr_load_program(dev_priv);
 }
 
-void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
+static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
 {
        struct i915_power_domains *power_domains = &dev_priv->power_domains;
        struct i915_power_well *well;
@@ -4680,8 +4679,8 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
        intel_combo_phy_uninit(dev_priv);
 }
 
-void icl_display_core_init(struct drm_i915_private *dev_priv,
-                          bool resume)
+static void icl_display_core_init(struct drm_i915_private *dev_priv,
+                                 bool resume)
 {
        struct i915_power_domains *power_domains = &dev_priv->power_domains;
        struct i915_power_well *well;
@@ -4716,7 +4715,7 @@ void icl_display_core_init(struct drm_i915_private *dev_priv,
                intel_csr_load_program(dev_priv);
 }
 
-void icl_display_core_uninit(struct drm_i915_private *dev_priv)
+static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
 {
        struct i915_power_domains *power_domains = &dev_priv->power_domains;
        struct i915_power_well *well;
@@ -5193,3 +5192,58 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915)
 }
 
 #endif
+
+void intel_display_power_suspend_late(struct drm_i915_private *i915)
+{
+       if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915))
+               bxt_enable_dc9(i915);
+       else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
+               hsw_enable_pc8(i915);
+}
+
+void intel_display_power_resume_early(struct drm_i915_private *i915)
+{
+       if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915)) {
+               gen9_sanitize_dc_state(i915);
+               bxt_disable_dc9(i915);
+       } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
+               hsw_disable_pc8(i915);
+       }
+}
+
+void intel_display_power_suspend(struct drm_i915_private *i915)
+{
+       if (INTEL_GEN(i915) >= 11) {
+               icl_display_core_uninit(i915);
+               bxt_enable_dc9(i915);
+       } else if (IS_GEN9_LP(i915)) {
+               bxt_display_core_uninit(i915);
+               bxt_enable_dc9(i915);
+       } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
+               hsw_enable_pc8(i915);
+       }
+}
+
+void intel_display_power_resume(struct drm_i915_private *i915)
+{
+       if (INTEL_GEN(i915) >= 11) {
+               bxt_disable_dc9(i915);
+               icl_display_core_init(i915, true);
+               if (i915->csr.dmc_payload) {
+                       if (i915->csr.allowed_dc_mask &
+                           DC_STATE_EN_UPTO_DC6)
+                               skl_enable_dc6(i915);
+                       else if (i915->csr.allowed_dc_mask &
+                                DC_STATE_EN_UPTO_DC5)
+                               gen9_enable_dc5(i915);
+               }
+       } else if (IS_GEN9_LP(i915)) {
+               bxt_disable_dc9(i915);
+               bxt_display_core_init(i915, true);
+               if (i915->csr.dmc_payload &&
+                   (i915->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
+                       gen9_enable_dc5(i915);
+       } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
+               hsw_disable_pc8(i915);
+       }
+}

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index e4d2c1ba24b0e4b951720a3195a7d5ae92bad94f..97f2562fc5d3b26f28d7b179fcd48b7dddf4548d 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -232,27 +232,20 @@ struct i915_power_domains {
        for_each_power_well_reverse(__dev_priv, __power_well)                   \
                for_each_if((__power_well)->desc->domains & (__domain_mask))
 
-void skl_enable_dc6(struct drm_i915_private *dev_priv);
-void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
-void bxt_enable_dc9(struct drm_i915_private *dev_priv);
-void bxt_disable_dc9(struct drm_i915_private *dev_priv);
-void gen9_enable_dc5(struct drm_i915_private *dev_priv);
-
 int intel_power_domains_init(struct drm_i915_private *dev_priv);
 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
 void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv);
-void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
-void icl_display_core_uninit(struct drm_i915_private *dev_priv);
 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
 void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
                                 enum i915_drm_suspend_mode);
 void intel_power_domains_resume(struct drm_i915_private *dev_priv);
-void hsw_enable_pc8(struct drm_i915_private *dev_priv);
-void hsw_disable_pc8(struct drm_i915_private *dev_priv);
-void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
-void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
+
+void intel_display_power_suspend_late(struct drm_i915_private *i915);
+void intel_display_power_resume_early(struct drm_i915_private *i915);
+void intel_display_power_suspend(struct drm_i915_private *i915);
+void intel_display_power_resume(struct drm_i915_private *i915);
 
 const char *
 intel_display_power_domain_str(struct drm_i915_private *i915,

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index ff26c4d1f20dfdb411cfe9a1a979b2f546f2177a..76ee67b901045e956d163a2e26f1a8c1f9ab5b60 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2166,7 +2166,7 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
        struct drm_i915_private *dev_priv = to_i915(dev);
        struct pci_dev *pdev = dev_priv->drm.pdev;
        struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
-       int ret;
+       int ret = 0;
 
        disable_rpm_wakeref_asserts(rpm);
 
@@ -2177,12 +2177,9 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
        intel_power_domains_suspend(dev_priv,
                                    get_suspend_mode(dev_priv, hibernation));
 
-       ret = 0;
-       if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv))
-               bxt_enable_dc9(dev_priv);
-       else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
-               hsw_enable_pc8(dev_priv);
-       else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+       intel_display_power_suspend_late(dev_priv);
+
+       if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
                ret = vlv_suspend_complete(dev_priv);
 
        if (ret) {
@@ -2367,12 +2364,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
 
        intel_gt_check_and_clear_faults(&dev_priv->gt);
 
-       if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
-               gen9_sanitize_dc_state(dev_priv);
-               bxt_disable_dc9(dev_priv);
-       } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
-               hsw_disable_pc8(dev_priv);
-       }
+       intel_display_power_resume_early(dev_priv);
 
        intel_sanitize_gt_powersave(dev_priv);
 
@@ -2912,7 +2904,7 @@ static int intel_runtime_suspend(struct device *kdev)
 {
        struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
        struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
-       int ret;
+       int ret = 0;
 
        if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
                return -ENODEV;
@@ -2936,18 +2928,10 @@ static int intel_runtime_suspend(struct device *kdev)
 
        intel_uncore_suspend(&dev_priv->uncore);
 
-       ret = 0;
-       if (INTEL_GEN(dev_priv) >= 11) {
-               icl_display_core_uninit(dev_priv);
-               bxt_enable_dc9(dev_priv);
-       } else if (IS_GEN9_LP(dev_priv)) {
-               bxt_display_core_uninit(dev_priv);
-               bxt_enable_dc9(dev_priv);
-       } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
-               hsw_enable_pc8(dev_priv);
-       } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+       intel_display_power_suspend(dev_priv);
+
+       if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
                ret = vlv_suspend_complete(dev_priv);
-       }
 
        if (ret) {
                DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
@@ -3023,28 +3007,10 @@ static int intel_runtime_resume(struct device *kdev)
        if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
                DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
 
-       if (INTEL_GEN(dev_priv) >= 11) {
-               bxt_disable_dc9(dev_priv);
-               icl_display_core_init(dev_priv, true);
-               if (dev_priv->csr.dmc_payload) {
-                       if (dev_priv->csr.allowed_dc_mask &
-                           DC_STATE_EN_UPTO_DC6)
-                               skl_enable_dc6(dev_priv);
-                       else if (dev_priv->csr.allowed_dc_mask &
-                                DC_STATE_EN_UPTO_DC5)
-                               gen9_enable_dc5(dev_priv);
-               }
-       } else if (IS_GEN9_LP(dev_priv)) {
-               bxt_disable_dc9(dev_priv);
-               bxt_display_core_init(dev_priv, true);
-               if (dev_priv->csr.dmc_payload &&
-                   (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
-                       gen9_enable_dc5(dev_priv);
-       } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
-               hsw_disable_pc8(dev_priv);
-       } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+       intel_display_power_resume(dev_priv);
+
+       if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
                ret = vlv_resume_prepare(dev_priv, true);
-       }
 
        intel_uncore_runtime_resume(&dev_priv->uncore);