drm/amdgpu: switch to use df callback functions

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index e687363..070946e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -714,7 +714,6 @@ static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
  */
 static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
 {
-       u32 tmp;
        int chansize, numchan;
        int r;
 
@@ -727,39 +726,7 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
                else
                        chansize = 128;
 
-               tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
-               tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
-               tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
-               switch (tmp) {
-               case 0:
-               default:
-                       numchan = 1;
-                       break;
-               case 1:
-                       numchan = 2;
-                       break;
-               case 2:
-                       numchan = 0;
-                       break;
-               case 3:
-                       numchan = 4;
-                       break;
-               case 4:
-                       numchan = 0;
-                       break;
-               case 5:
-                       numchan = 8;
-                       break;
-               case 6:
-                       numchan = 0;
-                       break;
-               case 7:
-                       numchan = 16;
-                       break;
-               case 8:
-                       numchan = 2;
-                       break;
-               }
+               numchan = adev->df_funcs->get_hbm_channel_number(adev);
                adev->gmc.vram_width = numchan * chansize;
        }
 

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 51cf8a3..654b015 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -52,6 +52,7 @@
 #include "gmc_v9_0.h"
 #include "gfxhub_v1_0.h"
 #include "mmhub_v1_0.h"
+#include "df_v1_7.h"
 #include "vega10_ih.h"
 #include "sdma_v4_0.h"
 #include "uvd_v7_0.h"
@@ -60,33 +61,6 @@
 #include "dce_virtual.h"
 #include "mxgpu_ai.h"
 
-#define mmFabricConfigAccessControl                                                                    0x0410
-#define mmFabricConfigAccessControl_BASE_IDX                                                           0
-#define mmFabricConfigAccessControl_DEFAULT                                      0x00000000
-//FabricConfigAccessControl
-#define FabricConfigAccessControl__CfgRegInstAccEn__SHIFT                                                     0x0
-#define FabricConfigAccessControl__CfgRegInstAccRegLock__SHIFT                                                0x1
-#define FabricConfigAccessControl__CfgRegInstID__SHIFT                                                        0x10
-#define FabricConfigAccessControl__CfgRegInstAccEn_MASK                                                       0x00000001L
-#define FabricConfigAccessControl__CfgRegInstAccRegLock_MASK                                                  0x00000002L
-#define FabricConfigAccessControl__CfgRegInstID_MASK                                                          0x00FF0000L
-
-
-#define mmDF_PIE_AON0_DfGlobalClkGater                                                                 0x00fc
-#define mmDF_PIE_AON0_DfGlobalClkGater_BASE_IDX                                                        0
-//DF_PIE_AON0_DfGlobalClkGater
-#define DF_PIE_AON0_DfGlobalClkGater__MGCGMode__SHIFT                                                         0x0
-#define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK                                                           0x0000000FL
-
-enum {
-       DF_MGCG_DISABLE = 0,
-       DF_MGCG_ENABLE_00_CYCLE_DELAY =1,
-       DF_MGCG_ENABLE_01_CYCLE_DELAY =2,
-       DF_MGCG_ENABLE_15_CYCLE_DELAY =13,
-       DF_MGCG_ENABLE_31_CYCLE_DELAY =14,
-       DF_MGCG_ENABLE_63_CYCLE_DELAY =15
-};
-
 #define mmMP0_MISC_CGTT_CTRL0                                                                   0x01b9
 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX                                                          0
 #define mmMP0_MISC_LIGHT_SLEEP_CTRL                                                             0x01ba
@@ -521,6 +495,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
        else
                adev->nbio_funcs = &nbio_v6_1_funcs;
 
+       adev->df_funcs = &df_v1_7_funcs;
        adev->nbio_funcs->detect_hw_virt(adev);
 
        if (amdgpu_sriov_vf(adev))
@@ -871,32 +846,6 @@ static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *ade
                WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
 }
 
-static void soc15_update_df_medium_grain_clock_gating(struct amdgpu_device *adev,
-                                                      bool enable)
-{
-       uint32_t data;
-
-       /* Put DF on broadcast mode */
-       data = RREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl));
-       data &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
-       WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl), data);
-
-       if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
-               data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
-               data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
-               data |= DF_MGCG_ENABLE_15_CYCLE_DELAY;
-               WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data);
-       } else {
-               data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
-               data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
-               data |= DF_MGCG_DISABLE;
-               WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data);
-       }
-
-       WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl),
-              mmFabricConfigAccessControl_DEFAULT);
-}
-
 static int soc15_common_set_clockgating_state(void *handle,
                                            enum amd_clockgating_state state)
 {
@@ -920,7 +869,7 @@ static int soc15_common_set_clockgating_state(void *handle,
                                state == AMD_CG_STATE_GATE ? true : false);
                soc15_update_rom_medium_grain_clock_gating(adev,
                                state == AMD_CG_STATE_GATE ? true : false);
-               soc15_update_df_medium_grain_clock_gating(adev,
+               adev->df_funcs->update_medium_grain_clock_gating(adev,
                                state == AMD_CG_STATE_GATE ? true : false);
                break;
        case CHIP_RAVEN:
@@ -973,10 +922,7 @@ static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
        if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
                *flags |= AMD_CG_SUPPORT_ROM_MGCG;
 
-       /* AMD_CG_SUPPORT_DF_MGCG */
-       data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
-       if (data & DF_MGCG_ENABLE_15_CYCLE_DELAY)
-               *flags |= AMD_CG_SUPPORT_DF_MGCG;
+       adev->df_funcs->get_clockgating_state(adev, flags);
 }
 
 static int soc15_common_set_powergating_state(void *handle,