[DirectivePwr9,
FeatureP9Altivec,
FeatureP9Vector,
+ FeaturePPCPreRASched,
+ FeaturePPCPostRASched,
FeatureISA3_0,
FeaturePredictableSelectIsExpensive
];
// dispatch for vector operations than scalar ones. For the time being,
// this list also includes scheduling-related features since we do not have
// enough info to create custom scheduling strategies for future CPUs.
- list<SubtargetFeature> P9SpecificFeatures = [FeatureVectorsUseTwoUnits,
- FeaturePPCPreRASched,
- FeaturePPCPostRASched];
+ list<SubtargetFeature> P9SpecificFeatures = [FeatureVectorsUseTwoUnits];
list<SubtargetFeature> P9InheritableFeatures =
!listconcat(P8InheritableFeatures, P9AdditionalFeatures);
list<SubtargetFeature> P9Features =
def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>;
def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>;
// No scheduler model yet.
-def : ProcessorModel<"pwr10", NoSchedModel, ProcessorFeatures.P10Features>;
+def : ProcessorModel<"pwr10", P9Model, ProcessorFeatures.P10Features>;
// No scheduler model for future CPU.
def : ProcessorModel<"future", NoSchedModel,
ProcessorFeatures.FutureFeatures>;
; CHECK-LARGE: ld r2, .Lfunc_toc2-.Lfunc_gep2(r12)
; CHECK-LARGE: add r2, r2, r12
; CHECK-S: .localentry AsmClobberX2WithTOC
-; CHECK-S: #APP
+; CHECK-S: add r3, r4, r3
+; CHECK-S-NEXT: #APP
; CHECK-S-NEXT: li r2, 0
; CHECK-S-NEXT: #NO_APP
-; CHECK-S-NEXT: plwz r5, global_int@PCREL(0), 1
-; CHECK-S-NEXT: add r3, r4, r3
-; CHECK-S-NEXT: add r3, r3, r5
+; CHECK-S-NEXT: plwz r4, global_int@PCREL(0), 1
+; CHECK-S-NEXT: add r3, r3, r4
; CHECK-S-NEXT: extsw r3, r3
; CHECK-S-NEXT: blr
entry:
; CHECK-P9-NOT: .localentry
; CHECK-ALL: # %bb.0: # %entry
; CHECK-S-NEXT: add r3, r4, r3
-; CHECK-S-NEXT: extsw r3, r3
; CHECK-S-NEXT: #APP
; CHECK-S-NEXT: nop
; CHECK-S-NEXT: #NO_APP
+; CHECK-S-NEXT: extsw r3, r3
; CHECK-S-NEXT: blr
entry:
%add = add nsw i32 %b, %a
; CHECK-S-NEXT: add r9, r10, r9
; CHECK-S-NEXT: sub r10, r10, r3
; CHECK-S-NEXT: mullw r3, r4, r3
+; CHECK-S-NEXT: sub r12, r4, r5
+; CHECK-S-NEXT: add r0, r6, r5
+; CHECK-S-NEXT: sub r2, r6, r7
+; CHECK-S-NEXT: std r30, -16(r1) # 8-byte Folded Spill
+; CHECK-S-NEXT: add r30, r8, r7
; CHECK-S-NEXT: mullw r3, r3, r11
; CHECK-S-NEXT: mullw r3, r3, r5
-; CHECK-S-NEXT: sub r12, r4, r5
; CHECK-S-NEXT: mullw r3, r3, r6
-; CHECK-S-NEXT: add r0, r6, r5
; CHECK-S-NEXT: mullw r3, r3, r12
; CHECK-S-NEXT: mullw r3, r3, r0
; CHECK-S-NEXT: mullw r3, r3, r7
-; CHECK-S-NEXT: sub r2, r6, r7
; CHECK-S-NEXT: mullw r3, r3, r8
-; CHECK-S-NEXT: std r30, -16(r1) # 8-byte Folded Spill
-; CHECK-S-NEXT: add r30, r8, r7
; CHECK-S-NEXT: mullw r3, r3, r2
; CHECK-S-NEXT: mullw r3, r3, r30
-; CHECK-S-NEXT: mullw r3, r3, r29
-; CHECK-S-NEXT: mullw r3, r3, r9
; CHECK-S-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
+; CHECK-S-NEXT: mullw r3, r3, r29
; CHECK-S-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
+; CHECK-S-NEXT: mullw r3, r3, r9
; CHECK-S-NEXT: mullw r3, r3, r10
; CHECK-S-NEXT: extsw r3, r3
; CHECK-S-NEXT: blr