Merge drm/drm-next into drm-intel-next

Catch-up with 5.17-rc2 and trying to align with drm-intel-gt-next
for a possible topic branch for merging the split of i915_regs...

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --cc arch/x86/kernel/early-quirks.c
Simple merge

diff --cc drivers/gpu/drm/drm_panel_orientation_quirks.c
Simple merge

diff --cc drivers/gpu/drm/i915/Makefile
Simple merge

diff --cc drivers/gpu/drm/i915/display/intel_atomic_plane.c
Simple merge

diff --cc drivers/gpu/drm/i915/display/intel_bw.c
Simple merge

diff --cc drivers/gpu/drm/i915/display/intel_display.c
Simple merge

diff --cc drivers/gpu/drm/i915/display/intel_fbc.c
Simple merge

diff --cc drivers/gpu/drm/i915/display/intel_overlay.c
Simple merge

diff --cc drivers/gpu/drm/i915/display/skl_universal_plane.c
Simple merge

diff --cc drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
Simple merge

diff --cc drivers/gpu/drm/i915/gem/i915_gem_userptr.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/gen6_ppgtt.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_engine_cs.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_execlists_submission.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_gt.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_lrc.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_rc6.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_reset.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_ring_submission.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_rps.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_workarounds.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/selftest_engine_pm.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/selftest_gt_pm.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/selftest_hangcheck.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/selftest_timeline.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 4333d13,e751720..e21505c
--- 1/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
--- 2/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@@ -9,11 -9,11 +9,12 @@@
  #include "gt/gen8_engine_cs.h"
  #include "gt/intel_breadcrumbs.h"
  #include "gt/intel_context.h"
 -#include "gt/intel_engine_pm.h"
  #include "gt/intel_engine_heartbeat.h"
 +#include "gt/intel_engine_pm.h"
 +#include "gt/intel_engine_regs.h"
  #include "gt/intel_gpu_commands.h"
  #include "gt/intel_gt.h"
+ #include "gt/intel_gt_clock_utils.h"
  #include "gt/intel_gt_irq.h"
  #include "gt/intel_gt_pm.h"
  #include "gt/intel_gt_requests.h"

diff --cc drivers/gpu/drm/i915/gvt/gtt.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_driver.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_drv.h
Simple merge

diff --cc drivers/gpu/drm/i915/i915_gem.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_getparam.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_gpu_error.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_irq.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_pci.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_perf.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_pmu.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_reg.h
index ef8ae40,c32420c..acd0904
--- 1/drivers/gpu/drm/i915/i915_reg.h
--- 2/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@@ -1825,7 -2661,52 +1843,9 @@@
  #define   AUX_INV             REG_BIT(0)
  #define BLT_HWS_PGA_GEN7      _MMIO(0x04280)
  #define VEBOX_HWS_PGA_GEN7    _MMIO(0x04380)
 -#define RING_ACTHD(base)      _MMIO((base) + 0x74)
 -#define RING_ACTHD_UDW(base)  _MMIO((base) + 0x5c)
 -#define RING_NOPID(base)      _MMIO((base) + 0x94)
 -#define RING_IMR(base)                _MMIO((base) + 0xa8)
 -#define RING_HWSTAM(base)     _MMIO((base) + 0x98)
 -#define RING_TIMESTAMP(base)          _MMIO((base) + 0x358)
 -#define RING_TIMESTAMP_UDW(base)      _MMIO((base) + 0x358 + 4)
 -#define   TAIL_ADDR           0x001FFFF8
 -#define   HEAD_WRAP_COUNT     0xFFE00000
 -#define   HEAD_WRAP_ONE               0x00200000
 -#define   HEAD_ADDR           0x001FFFFC
 -#define   RING_NR_PAGES               0x001FF000
 -#define   RING_REPORT_MASK    0x00000006
 -#define   RING_REPORT_64K     0x00000002
 -#define   RING_REPORT_128K    0x00000004
 -#define   RING_NO_REPORT      0x00000000
 -#define   RING_VALID_MASK     0x00000001
 -#define   RING_VALID          0x00000001
 -#define   RING_INVALID                0x00000000
 -#define   RING_WAIT_I8XX      (1 << 0) /* gen2, PRBx_HEAD */
 -#define   RING_WAIT           (1 << 11) /* gen3+, PRBx_CTL */
 -#define   RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */
  
 -/* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */
 -#define GEN8_RING_CS_GPR(base, n)     _MMIO((base) + 0x600 + (n) * 8)
 -#define GEN8_RING_CS_GPR_UDW(base, n) _MMIO((base) + 0x600 + (n) * 8 + 4)
 -
 -#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
 -#define   RING_FORCE_TO_NONPRIV_ADDRESS_MASK  REG_GENMASK(25, 2)
 -#define   RING_FORCE_TO_NONPRIV_ACCESS_RW     (0 << 28)    /* CFL+ & Gen11+ */
 -#define   RING_FORCE_TO_NONPRIV_ACCESS_RD     (1 << 28)
 -#define   RING_FORCE_TO_NONPRIV_ACCESS_WR     (2 << 28)
 -#define   RING_FORCE_TO_NONPRIV_ACCESS_INVALID        (3 << 28)
 -#define   RING_FORCE_TO_NONPRIV_ACCESS_MASK   (3 << 28)
 -#define   RING_FORCE_TO_NONPRIV_RANGE_1               (0 << 0)     /* CFL+ & Gen11+ */
 -#define   RING_FORCE_TO_NONPRIV_RANGE_4               (1 << 0)
 -#define   RING_FORCE_TO_NONPRIV_RANGE_16      (2 << 0)
 -#define   RING_FORCE_TO_NONPRIV_RANGE_64      (3 << 0)
 -#define   RING_FORCE_TO_NONPRIV_RANGE_MASK    (3 << 0)
 -#define   RING_FORCE_TO_NONPRIV_MASK_VALID    \
 -                                      (RING_FORCE_TO_NONPRIV_RANGE_MASK \
 -                                      | RING_FORCE_TO_NONPRIV_ACCESS_MASK)
 -#define   RING_MAX_NONPRIV_SLOTS  12
 -
+ #define GUCPMTIMESTAMP          _MMIO(0xC3E8)
+ 
  #define GEN7_TLB_RD_ADDR      _MMIO(0x4700)
  
  #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
@@@ -1885,7 -2784,27 +1911,10 @@@
  #define GEN2_INSTDONE _MMIO(0x2090)
  #define NOPID         _MMIO(0x2094)
  #define HWSTAM                _MMIO(0x2098)
 -#define DMA_FADD_I8XX(base)   _MMIO((base) + 0xd0)
 -#define RING_BBSTATE(base)    _MMIO((base) + 0x110)
 -#define   RING_BB_PPGTT               (1 << 5)
 -#define RING_SBBADDR(base)    _MMIO((base) + 0x114) /* hsw+ */
 -#define RING_SBBSTATE(base)   _MMIO((base) + 0x118) /* hsw+ */
 -#define RING_SBBADDR_UDW(base)        _MMIO((base) + 0x11c) /* gen8+ */
 -#define RING_BBADDR(base)     _MMIO((base) + 0x140)
 -#define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */
 -#define RING_BB_PER_CTX_PTR(base)     _MMIO((base) + 0x1c0) /* gen8+ */
 -#define RING_INDIRECT_CTX(base)               _MMIO((base) + 0x1c4) /* gen8+ */
 -#define RING_INDIRECT_CTX_OFFSET(base)        _MMIO((base) + 0x1c8) /* gen8+ */
 -#define RING_CTX_TIMESTAMP(base)      _MMIO((base) + 0x3a8) /* gen8+ */
 -
 -#define VDBOX_CGCTL3F10(base)         _MMIO((base) + 0x3f10)
 -#define   IECPUNIT_CLKGATE_DIS                REG_BIT(22)
  
+ #define VDBOX_CGCTL3F18(base)         _MMIO((base) + 0x3f18)
+ #define   ALNUNIT_CLKGATE_DIS         REG_BIT(13)
+ 
  #define ERROR_GEN6    _MMIO(0x40a0)
  #define GEN7_ERR_INT  _MMIO(0x44040)
  #define   ERR_INT_POISON              (1 << 31)

diff --cc drivers/gpu/drm/i915/i915_request.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_vma.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_device_info.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_device_info.h
Simple merge

diff --cc drivers/gpu/drm/i915/intel_pm.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_uncore.c
index 703061e,778da31..7219125
--- 1/drivers/gpu/drm/i915/intel_uncore.c
--- 2/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@@ -2261,10 -2271,78 +2271,8 @@@ void intel_uncore_fini_mmio(struct inte
                intel_uncore_fw_domains_fini(uncore);
                iosf_mbi_punit_release();
        }
- 
-       uncore_mmio_cleanup(uncore);
  }
  
 -static const struct reg_whitelist {
 -      i915_reg_t offset_ldw;
 -      i915_reg_t offset_udw;
 -      u8 min_graphics_ver;
 -      u8 max_graphics_ver;
 -      u8 size;
 -} reg_read_whitelist[] = { {
 -      .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
 -      .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
 -      .min_graphics_ver = 4,
 -      .max_graphics_ver = 12,
 -      .size = 8
 -} };
 -
 -int i915_reg_read_ioctl(struct drm_device *dev,
 -                      void *data, struct drm_file *file)
 -{
 -      struct drm_i915_private *i915 = to_i915(dev);
 -      struct intel_uncore *uncore = &i915->uncore;
 -      struct drm_i915_reg_read *reg = data;
 -      struct reg_whitelist const *entry;
 -      intel_wakeref_t wakeref;
 -      unsigned int flags;
 -      int remain;
 -      int ret = 0;
 -
 -      entry = reg_read_whitelist;
 -      remain = ARRAY_SIZE(reg_read_whitelist);
 -      while (remain) {
 -              u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);
 -
 -              GEM_BUG_ON(!is_power_of_2(entry->size));
 -              GEM_BUG_ON(entry->size > 8);
 -              GEM_BUG_ON(entry_offset & (entry->size - 1));
 -
 -              if (IS_GRAPHICS_VER(i915, entry->min_graphics_ver, entry->max_graphics_ver) &&
 -                  entry_offset == (reg->offset & -entry->size))
 -                      break;
 -              entry++;
 -              remain--;
 -      }
 -
 -      if (!remain)
 -              return -EINVAL;
 -
 -      flags = reg->offset & (entry->size - 1);
 -
 -      with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
 -              if (entry->size == 8 && flags == I915_REG_READ_8B_WA)
 -                      reg->val = intel_uncore_read64_2x32(uncore,
 -                                                          entry->offset_ldw,
 -                                                          entry->offset_udw);
 -              else if (entry->size == 8 && flags == 0)
 -                      reg->val = intel_uncore_read64(uncore,
 -                                                     entry->offset_ldw);
 -              else if (entry->size == 4 && flags == 0)
 -                      reg->val = intel_uncore_read(uncore, entry->offset_ldw);
 -              else if (entry->size == 2 && flags == 0)
 -                      reg->val = intel_uncore_read16(uncore,
 -                                                     entry->offset_ldw);
 -              else if (entry->size == 1 && flags == 0)
 -                      reg->val = intel_uncore_read8(uncore,
 -                                                    entry->offset_ldw);
 -              else
 -                      ret = -EINVAL;
 -      }
 -
 -      return ret;
 -}
 -
  /**
   * __intel_wait_for_register_fw - wait until register matches expected state
   * @uncore: the struct intel_uncore