INTEL_RKL_IDS(&gen11_early_ops),
INTEL_ADLS_IDS(&gen11_early_ops),
INTEL_ADLP_IDS(&gen11_early_ops),
+ INTEL_ADLN_IDS(&gen11_early_ops),
INTEL_RPLS_IDS(&gen11_early_ops),
};
DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "MicroPC"),
},
.driver_data = (void *)&lcd720x1280_rightside_up,
+ }, { /* GPD Win Max */
+ .matches = {
+ DMI_EXACT_MATCH(DMI_SYS_VENDOR, "GPD"),
+ DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "G1619-01"),
+ },
+ .driver_data = (void *)&lcd800x1280_rightside_up,
}, { /*
* GPD Pocket, note that the the DMI data is less generic then
* it seems, devices with a board-vendor of "AMI Corporation"
# core driver code
i915-y += i915_driver.o \
i915_config.o \
- i915_irq.o \
i915_getparam.o \
+ i915_ioctl.o \
+ i915_irq.o \
i915_mitigations.o \
i915_module.o \
i915_params.o \
enum i9xx_plane_id i9xx_plane)
{
if (i9xx_plane_has_fbc(dev_priv, i9xx_plane))
- return dev_priv->fbc;
+ return dev_priv->fbc[INTEL_FBC_A];
else
return NULL;
}
unsigned int rotation = plane_state->hw.rotation;
u32 dspcntr;
- dspcntr = DISPLAY_PLANE_ENABLE;
+ dspcntr = DISP_ENABLE;
if (IS_G4X(dev_priv) || IS_IRONLAKE(dev_priv) ||
IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
- dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
+ dspcntr |= DISP_TRICKLE_FEED_DISABLE;
switch (fb->format->format) {
case DRM_FORMAT_C8:
- dspcntr |= DISPPLANE_8BPP;
+ dspcntr |= DISP_FORMAT_8BPP;
break;
case DRM_FORMAT_XRGB1555:
- dspcntr |= DISPPLANE_BGRX555;
+ dspcntr |= DISP_FORMAT_BGRX555;
break;
case DRM_FORMAT_ARGB1555:
- dspcntr |= DISPPLANE_BGRA555;
+ dspcntr |= DISP_FORMAT_BGRA555;
break;
case DRM_FORMAT_RGB565:
- dspcntr |= DISPPLANE_BGRX565;
+ dspcntr |= DISP_FORMAT_BGRX565;
break;
case DRM_FORMAT_XRGB8888:
- dspcntr |= DISPPLANE_BGRX888;
+ dspcntr |= DISP_FORMAT_BGRX888;
break;
case DRM_FORMAT_XBGR8888:
- dspcntr |= DISPPLANE_RGBX888;
+ dspcntr |= DISP_FORMAT_RGBX888;
break;
case DRM_FORMAT_ARGB8888:
- dspcntr |= DISPPLANE_BGRA888;
+ dspcntr |= DISP_FORMAT_BGRA888;
break;
case DRM_FORMAT_ABGR8888:
- dspcntr |= DISPPLANE_RGBA888;
+ dspcntr |= DISP_FORMAT_RGBA888;
break;
case DRM_FORMAT_XRGB2101010:
- dspcntr |= DISPPLANE_BGRX101010;
+ dspcntr |= DISP_FORMAT_BGRX101010;
break;
case DRM_FORMAT_XBGR2101010:
- dspcntr |= DISPPLANE_RGBX101010;
+ dspcntr |= DISP_FORMAT_RGBX101010;
break;
case DRM_FORMAT_ARGB2101010:
- dspcntr |= DISPPLANE_BGRA101010;
+ dspcntr |= DISP_FORMAT_BGRA101010;
break;
case DRM_FORMAT_ABGR2101010:
- dspcntr |= DISPPLANE_RGBA101010;
+ dspcntr |= DISP_FORMAT_RGBA101010;
break;
case DRM_FORMAT_XBGR16161616F:
- dspcntr |= DISPPLANE_RGBX161616;
+ dspcntr |= DISP_FORMAT_RGBX161616;
break;
default:
MISSING_CASE(fb->format->format);
if (DISPLAY_VER(dev_priv) >= 4 &&
fb->modifier == I915_FORMAT_MOD_X_TILED)
- dspcntr |= DISPPLANE_TILED;
+ dspcntr |= DISP_TILED;
if (rotation & DRM_MODE_ROTATE_180)
- dspcntr |= DISPPLANE_ROTATE_180;
+ dspcntr |= DISP_ROTATE_180;
if (rotation & DRM_MODE_REFLECT_X)
- dspcntr |= DISPPLANE_MIRROR;
+ dspcntr |= DISP_MIRROR;
return dspcntr;
}
u32 dspcntr = 0;
if (crtc_state->gamma_enable)
- dspcntr |= DISPPLANE_GAMMA_ENABLE;
+ dspcntr |= DISP_PIPE_GAMMA_ENABLE;
if (crtc_state->csc_enable)
- dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
+ dspcntr |= DISP_PIPE_CSC_ENABLE;
if (DISPLAY_VER(dev_priv) < 5)
- dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
+ dspcntr |= DISP_PIPE_SEL(crtc->pipe);
return dspcntr;
}
* program whatever is there.
*/
intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
- (crtc_y << 16) | crtc_x);
+ DISP_POS_Y(crtc_y) | DISP_POS_X(crtc_x));
intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
- ((crtc_h - 1) << 16) | (crtc_w - 1));
+ DISP_HEIGHT(crtc_h - 1) | DISP_WIDTH(crtc_w - 1));
}
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
int crtc_h = drm_rect_height(&plane_state->uapi.dst);
intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane),
- (crtc_y << 16) | crtc_x);
+ PRIM_POS_Y(crtc_y) | PRIM_POS_X(crtc_x));
intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane),
- ((crtc_h - 1) << 16) | (crtc_w - 1));
+ PRIM_HEIGHT(crtc_h - 1) | PRIM_WIDTH(crtc_w - 1));
intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0);
}
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane),
- (y << 16) | x);
+ DISP_OFFSET_Y(y) | DISP_OFFSET_X(x));
} else if (DISPLAY_VER(dev_priv) >= 4) {
intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane),
linear_offset);
intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane),
- (y << 16) | x);
+ DISP_OFFSET_Y(y) | DISP_OFFSET_X(x));
}
/*
unsigned long irqflags;
if (async_flip)
- dspcntr |= DISPPLANE_ASYNC_FLIP;
+ dspcntr |= DISP_ASYNC_FLIP;
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
- ret = val & DISPLAY_PLANE_ENABLE;
+ ret = val & DISP_ENABLE;
if (DISPLAY_VER(dev_priv) >= 5)
*pipe = plane->pipe;
else
- *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
- DISPPLANE_SEL_PIPE_SHIFT;
+ *pipe = REG_FIELD_GET(DISP_PIPE_SEL_MASK, val);
intel_display_power_put(dev_priv, power_domain, wakeref);
static int i9xx_format_to_fourcc(int format)
{
switch (format) {
- case DISPPLANE_8BPP:
+ case DISP_FORMAT_8BPP:
return DRM_FORMAT_C8;
- case DISPPLANE_BGRA555:
+ case DISP_FORMAT_BGRA555:
return DRM_FORMAT_ARGB1555;
- case DISPPLANE_BGRX555:
+ case DISP_FORMAT_BGRX555:
return DRM_FORMAT_XRGB1555;
- case DISPPLANE_BGRX565:
+ case DISP_FORMAT_BGRX565:
return DRM_FORMAT_RGB565;
default:
- case DISPPLANE_BGRX888:
+ case DISP_FORMAT_BGRX888:
return DRM_FORMAT_XRGB8888;
- case DISPPLANE_RGBX888:
+ case DISP_FORMAT_RGBX888:
return DRM_FORMAT_XBGR8888;
- case DISPPLANE_BGRA888:
+ case DISP_FORMAT_BGRA888:
return DRM_FORMAT_ARGB8888;
- case DISPPLANE_RGBA888:
+ case DISP_FORMAT_RGBA888:
return DRM_FORMAT_ABGR8888;
- case DISPPLANE_BGRX101010:
+ case DISP_FORMAT_BGRX101010:
return DRM_FORMAT_XRGB2101010;
- case DISPPLANE_RGBX101010:
+ case DISP_FORMAT_RGBX101010:
return DRM_FORMAT_XBGR2101010;
- case DISPPLANE_BGRA101010:
+ case DISP_FORMAT_BGRA101010:
return DRM_FORMAT_ARGB2101010;
- case DISPPLANE_RGBA101010:
+ case DISP_FORMAT_RGBA101010:
return DRM_FORMAT_ABGR2101010;
- case DISPPLANE_RGBX161616:
+ case DISP_FORMAT_RGBX161616:
return DRM_FORMAT_XBGR16161616F;
}
}
val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
if (DISPLAY_VER(dev_priv) >= 4) {
- if (val & DISPPLANE_TILED) {
+ if (val & DISP_TILED) {
plane_config->tiling = I915_TILING_X;
fb->modifier = I915_FORMAT_MOD_X_TILED;
}
- if (val & DISPPLANE_ROTATE_180)
+ if (val & DISP_ROTATE_180)
plane_config->rotation = DRM_MODE_ROTATE_180;
}
if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
- val & DISPPLANE_MIRROR)
+ val & DISP_MIRROR)
plane_config->rotation |= DRM_MODE_REFLECT_X;
- pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
+ pixel_format = val & DISP_FORMAT_MASK;
fourcc = i9xx_format_to_fourcc(pixel_format);
fb->format = drm_format_info(fourcc);
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
- base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
+ base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK;
} else if (DISPLAY_VER(dev_priv) >= 4) {
if (plane_config->tiling)
offset = intel_de_read(dev_priv,
else
offset = intel_de_read(dev_priv,
DSPLINOFF(i9xx_plane));
- base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
+ base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK;
} else {
base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));
}
plane_config->base = base;
val = intel_de_read(dev_priv, PIPESRC(pipe));
- fb->width = ((val >> 16) & 0xfff) + 1;
- fb->height = ((val >> 0) & 0xfff) + 1;
+ fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1;
+ fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1;
val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
fb->pitches[0] = val & 0xffffffc0;
#include "intel_atomic.h"
#include "intel_backlight.h"
#include "intel_combo_phy.h"
+#include "intel_combo_phy_regs.h"
#include "intel_connector.h"
#include "intel_crtc.h"
#include "intel_ddi.h"
/* wait for transcoder to be enabled */
if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans),
- I965_PIPECONF_ACTIVE, 10))
+ PIPECONF_STATE_ENABLE, 10))
drm_err(&dev_priv->drm,
"DSI transcoder not enabled\n");
}
intel_dsc_dsi_pps_write(encoder, pipe_config);
- intel_dsc_enable(pipe_config);
-
/* step6c: configure transcoder timings */
gen11_dsi_set_transcoder_timings(encoder, pipe_config);
}
/* wait for transcoder to be disabled */
if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans),
- I965_PIPECONF_ACTIVE, 50))
+ PIPECONF_STATE_ENABLE, 50))
drm_err(&dev_priv->drm,
"DSI trancoder not disabled\n");
}
#include <drm/drm_fourcc.h>
#include <drm/drm_plane_helper.h>
+#include "i915_drv.h"
#include "intel_atomic.h"
#include "intel_cdclk.h"
#include "intel_display_types.h"
intel_state->ggtt_vma = NULL;
intel_state->dpt_vma = NULL;
intel_state->flags = 0;
+ intel_state->do_async_flip = false;
/* add reference to fb */
if (intel_state->hw.fb)
trace_intel_plane_update_arm(&plane->base, crtc);
- if (crtc_state->uapi.async_flip && plane->async_flip)
+ if (plane_state->do_async_flip)
plane->async_flip(plane, crtc_state, plane_state, true);
else
plane->update_arm(plane, crtc_state, plane_state);
int min_scale, int max_scale,
bool can_position)
{
+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
struct drm_framebuffer *fb = plane_state->hw.fb;
struct drm_rect *src = &plane_state->uapi.src;
struct drm_rect *dst = &plane_state->uapi.dst;
hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
if (hscale < 0 || vscale < 0) {
- DRM_DEBUG_KMS("Invalid scaling of plane\n");
+ drm_dbg_kms(&i915->drm, "Invalid scaling of plane\n");
drm_rect_debug_print("src: ", src, true);
drm_rect_debug_print("dst: ", dst, false);
return -ERANGE;
if (!can_position && plane_state->uapi.visible &&
!drm_rect_equals(dst, &clip)) {
- DRM_DEBUG_KMS("Plane must cover entire CRTC\n");
+ drm_dbg_kms(&i915->drm, "Plane must cover entire CRTC\n");
drm_rect_debug_print("dst: ", dst, false);
drm_rect_debug_print("clip: ", &clip, false);
return -EINVAL;
struct intel_crtc_state;
struct intel_plane;
struct intel_plane_state;
+enum plane_id;
unsigned int intel_adjusted_rate(const struct drm_rect *src,
const struct drm_rect *dst,
#include "intel_dp_aux_backlight.h"
#include "intel_dsi_dcs_backlight.h"
#include "intel_panel.h"
+#include "intel_pci_config.h"
/**
* scale - scale values from one range to another
struct intel_connector *connector = to_intel_connector(old_conn_state->connector);
struct intel_panel *panel = &connector->panel;
+ intel_backlight_set_pwm_level(old_conn_state, level);
+
panel->backlight.pwm_state.enabled = false;
pwm_apply_state(panel->backlight.pwm, &panel->backlight.pwm_state);
}
i915->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 :
psr_table->idle_frames > 15 ? 15 : psr_table->idle_frames;
- switch (psr_table->lines_to_wait) {
- case 0:
- i915->vbt.psr.lines_to_wait = PSR_0_LINES_TO_WAIT;
- break;
- case 1:
- i915->vbt.psr.lines_to_wait = PSR_1_LINE_TO_WAIT;
- break;
- case 2:
- i915->vbt.psr.lines_to_wait = PSR_4_LINES_TO_WAIT;
- break;
- case 3:
- i915->vbt.psr.lines_to_wait = PSR_8_LINES_TO_WAIT;
- break;
- default:
- drm_dbg_kms(&i915->drm,
- "VBT has unknown PSR lines to wait %u\n",
- psr_table->lines_to_wait);
- break;
- }
-
/*
* New psr options 0=500us, 1=100us, 2=2500us, 3=0us
* Old decimal value is wake up time in multiples of 100 us.
i915->vbt.ports[port] = devdata;
}
+static bool has_ddi_port_info(struct drm_i915_private *i915)
+{
+ return DISPLAY_VER(i915) >= 5 || IS_G4X(i915);
+}
+
static void parse_ddi_ports(struct drm_i915_private *i915)
{
struct intel_bios_encoder_data *devdata;
- if (!HAS_DDI(i915) && !IS_CHERRYVIEW(i915))
- return;
-
- if (i915->vbt.version < 155)
+ if (!has_ddi_port_info(i915))
return;
list_for_each_entry(devdata, &i915->vbt.display_devices, node)
return vbt;
}
+static struct vbt_header *spi_oprom_get_vbt(struct drm_i915_private *i915)
+{
+ u32 count, data, found, store = 0;
+ u32 static_region, oprom_offset;
+ u32 oprom_size = 0x200000;
+ u16 vbt_size;
+ u32 *vbt;
+
+ static_region = intel_uncore_read(&i915->uncore, SPI_STATIC_REGIONS);
+ static_region &= OPTIONROM_SPI_REGIONID_MASK;
+ intel_uncore_write(&i915->uncore, PRIMARY_SPI_REGIONID, static_region);
+
+ oprom_offset = intel_uncore_read(&i915->uncore, OROM_OFFSET);
+ oprom_offset &= OROM_OFFSET_MASK;
+
+ for (count = 0; count < oprom_size; count += 4) {
+ intel_uncore_write(&i915->uncore, PRIMARY_SPI_ADDRESS, oprom_offset + count);
+ data = intel_uncore_read(&i915->uncore, PRIMARY_SPI_TRIGGER);
+
+ if (data == *((const u32 *)"$VBT")) {
+ found = oprom_offset + count;
+ break;
+ }
+ }
+
+ if (count >= oprom_size)
+ goto err_not_found;
+
+ /* Get VBT size and allocate space for the VBT */
+ intel_uncore_write(&i915->uncore, PRIMARY_SPI_ADDRESS, found +
+ offsetof(struct vbt_header, vbt_size));
+ vbt_size = intel_uncore_read(&i915->uncore, PRIMARY_SPI_TRIGGER);
+ vbt_size &= 0xffff;
+
+ vbt = kzalloc(round_up(vbt_size, 4), GFP_KERNEL);
+ if (!vbt)
+ goto err_not_found;
+
+ for (count = 0; count < vbt_size; count += 4) {
+ intel_uncore_write(&i915->uncore, PRIMARY_SPI_ADDRESS, found + count);
+ data = intel_uncore_read(&i915->uncore, PRIMARY_SPI_TRIGGER);
+ *(vbt + store++) = data;
+ }
+
+ if (!intel_bios_is_valid_vbt(vbt, vbt_size))
+ goto err_free_vbt;
+
+ drm_dbg_kms(&i915->drm, "Found valid VBT in SPI flash\n");
+
+ return (struct vbt_header *)vbt;
+
+err_free_vbt:
+ kfree(vbt);
+err_not_found:
+ return NULL;
+}
+
static struct vbt_header *oprom_get_vbt(struct drm_i915_private *i915)
{
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
pci_unmap_rom(pdev, oprom);
+ drm_dbg_kms(&i915->drm, "Found valid VBT in PCI ROM\n");
+
return vbt;
err_free_vbt:
init_vbt_defaults(i915);
- /* If the OpRegion does not have VBT, look in PCI ROM. */
+ /*
+ * If the OpRegion does not have VBT, look in SPI flash through MMIO or
+ * PCI mapping
+ */
+ if (!vbt && IS_DGFX(i915)) {
+ oprom_vbt = spi_oprom_get_vbt(i915);
+ vbt = oprom_vbt;
+ }
+
if (!vbt) {
oprom_vbt = oprom_get_vbt(i915);
- if (!oprom_vbt)
- goto out;
-
vbt = oprom_vbt;
-
- drm_dbg_kms(&i915->drm, "Found valid VBT in PCI ROM\n");
}
+ if (!vbt)
+ goto out;
+
bdb = get_bdb_header(vbt);
i915->vbt.version = bdb->version;
*/
bool intel_bios_is_port_present(struct drm_i915_private *i915, enum port port)
{
- const struct intel_bios_encoder_data *devdata;
- const struct child_device_config *child;
- static const struct {
- u16 dp, hdmi;
- } port_mapping[] = {
- [PORT_B] = { DVO_PORT_DPB, DVO_PORT_HDMIB, },
- [PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, },
- [PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, },
- [PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, },
- [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, },
- };
-
- if (HAS_DDI(i915))
- return i915->vbt.ports[port];
-
- /* FIXME maybe deal with port A as well? */
- if (drm_WARN_ON(&i915->drm,
- port == PORT_A) || port >= ARRAY_SIZE(port_mapping))
- return false;
-
- list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
- child = &devdata->child;
-
- if ((child->dvo_port == port_mapping[port].dp ||
- child->dvo_port == port_mapping[port].hdmi) &&
- (child->device_type & (DEVICE_TYPE_TMDS_DVI_SIGNALING |
- DEVICE_TYPE_DISPLAYPORT_OUTPUT)))
- return true;
- }
+ if (WARN_ON(!has_ddi_port_info(i915)))
+ return true;
- return false;
+ return i915->vbt.ports[port];
}
/**
*/
bool intel_bios_is_port_edp(struct drm_i915_private *i915, enum port port)
{
- const struct intel_bios_encoder_data *devdata;
- const struct child_device_config *child;
- static const short port_mapping[] = {
- [PORT_B] = DVO_PORT_DPB,
- [PORT_C] = DVO_PORT_DPC,
- [PORT_D] = DVO_PORT_DPD,
- [PORT_E] = DVO_PORT_DPE,
- [PORT_F] = DVO_PORT_DPF,
- };
-
- if (HAS_DDI(i915)) {
- const struct intel_bios_encoder_data *devdata;
-
- devdata = intel_bios_encoder_data_lookup(i915, port);
-
- return devdata && intel_bios_encoder_supports_edp(devdata);
- }
-
- list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
- child = &devdata->child;
-
- if (child->dvo_port == port_mapping[port] &&
- (child->device_type & DEVICE_TYPE_eDP_BITS) ==
- (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
- return true;
- }
+ const struct intel_bios_encoder_data *devdata =
+ intel_bios_encoder_data_lookup(i915, port);
- return false;
+ return devdata && intel_bios_encoder_supports_edp(devdata);
}
-static bool child_dev_is_dp_dual_mode(const struct child_device_config *child)
+static bool intel_bios_encoder_supports_dp_dual_mode(const struct intel_bios_encoder_data *devdata)
{
- if ((child->device_type & DEVICE_TYPE_DP_DUAL_MODE_BITS) !=
- (DEVICE_TYPE_DP_DUAL_MODE & DEVICE_TYPE_DP_DUAL_MODE_BITS))
+ const struct child_device_config *child = &devdata->child;
+
+ if (!intel_bios_encoder_supports_dp(devdata) ||
+ !intel_bios_encoder_supports_hdmi(devdata))
return false;
if (dvo_port_type(child->dvo_port) == DVO_PORT_DPA)
bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *i915,
enum port port)
{
- static const struct {
- u16 dp, hdmi;
- } port_mapping[] = {
- /*
- * Buggy VBTs may declare DP ports as having
- * HDMI type dvo_port :( So let's check both.
- */
- [PORT_B] = { DVO_PORT_DPB, DVO_PORT_HDMIB, },
- [PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, },
- [PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, },
- [PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, },
- [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, },
- };
- const struct intel_bios_encoder_data *devdata;
-
- if (HAS_DDI(i915)) {
- const struct intel_bios_encoder_data *devdata;
-
- devdata = intel_bios_encoder_data_lookup(i915, port);
-
- return devdata && child_dev_is_dp_dual_mode(&devdata->child);
- }
-
- if (port == PORT_A || port >= ARRAY_SIZE(port_mapping))
- return false;
-
- list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
- if ((devdata->child.dvo_port == port_mapping[port].dp ||
- devdata->child.dvo_port == port_mapping[port].hdmi) &&
- child_dev_is_dp_dual_mode(&devdata->child))
- return true;
- }
+ const struct intel_bios_encoder_data *devdata =
+ intel_bios_encoder_data_lookup(i915, port);
- return false;
+ return devdata && intel_bios_encoder_supports_dp_dual_mode(devdata);
}
/**
u16 dclk;
int ret;
- ret = sandybridge_pcode_read(dev_priv,
- ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
- ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
- &val, &val2);
+ ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
+ ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
+ &val, &val2);
if (ret)
return ret;
int ret;
int i;
- ret = sandybridge_pcode_read(dev_priv,
- ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
- ADL_PCODE_MEM_SS_READ_PSF_GV_INFO,
- &val, NULL);
+ ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
+ ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, &val, NULL);
if (ret)
return ret;
#include "intel_crtc.h"
#include "intel_de.h"
#include "intel_display_types.h"
+#include "intel_pci_config.h"
#include "intel_pcode.h"
#include "intel_psr.h"
#include "vlv_sideband.h"
* dividers can be programmed correctly.
*/
+struct intel_cdclk_funcs {
+ void (*get_cdclk)(struct drm_i915_private *i915,
+ struct intel_cdclk_config *cdclk_config);
+ void (*set_cdclk)(struct drm_i915_private *i915,
+ const struct intel_cdclk_config *cdclk_config,
+ enum pipe pipe);
+ int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
+ int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
+ u8 (*calc_voltage_level)(int cdclk);
+};
+
void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config)
{
"trying to change cdclk frequency with cdclk not enabled\n"))
return;
- ret = sandybridge_pcode_write(dev_priv,
- BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
+ ret = snb_pcode_write(dev_priv, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
if (ret) {
drm_err(&dev_priv->drm,
"failed to inform pcode about cdclk change\n");
LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n");
- sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
- cdclk_config->voltage_level);
+ snb_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
+ cdclk_config->voltage_level);
intel_de_write(dev_priv, CDCLK_FREQ,
DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
intel_de_posting_read(dev_priv, CDCLK_CTL);
/* inform PCU of the change */
- sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
- cdclk_config->voltage_level);
+ snb_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+ cdclk_config->voltage_level);
intel_update_cdclk(dev_priv);
}
goto sanitize;
intel_update_cdclk(dev_priv);
- intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
+ intel_cdclk_dump_config(dev_priv, &dev_priv->cdclk.hw, "Current CDCLK");
/* Is PLL enabled and locked ? */
if (dev_priv->cdclk.hw.vco == 0 ||
/* Timeout 200us */
if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE,
BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1))
- DRM_ERROR("timeout waiting for FREQ change request ack\n");
+ drm_err(&dev_priv->drm, "timeout waiting for FREQ change request ack\n");
val &= ~BXT_DE_PLL_FREQ_REQ;
intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
* BSpec requires us to wait up to 150usec, but that leads to
* timeouts; the 2ms used here is based on experiment.
*/
- ret = sandybridge_pcode_write_timeout(dev_priv,
- HSW_PCODE_DE_WRITE_FREQ_REQ,
- 0x80000000, 150, 2);
-
+ ret = snb_pcode_write_timeout(dev_priv,
+ HSW_PCODE_DE_WRITE_FREQ_REQ,
+ 0x80000000, 150, 2);
if (ret) {
drm_err(&dev_priv->drm,
"Failed to inform PCU about cdclk change (err %d, freq %d)\n",
intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
if (DISPLAY_VER(dev_priv) >= 11) {
- ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
- cdclk_config->voltage_level);
+ ret = snb_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+ cdclk_config->voltage_level);
} else {
/*
* The timeout isn't specified, the 2ms used here is based on
* FIXME: Waiting for the request completion could be delayed
* until the next PCODE request based on BSpec.
*/
- ret = sandybridge_pcode_write_timeout(dev_priv,
- HSW_PCODE_DE_WRITE_FREQ_REQ,
- cdclk_config->voltage_level,
- 150, 2);
+ ret = snb_pcode_write_timeout(dev_priv,
+ HSW_PCODE_DE_WRITE_FREQ_REQ,
+ cdclk_config->voltage_level,
+ 150, 2);
}
if (ret) {
int cdclk, clock, vco;
intel_update_cdclk(dev_priv);
- intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
+ intel_cdclk_dump_config(dev_priv, &dev_priv->cdclk.hw, "Current CDCLK");
if (dev_priv->cdclk.hw.vco == 0 ||
dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
a->voltage_level != b->voltage_level;
}
-void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
+void intel_cdclk_dump_config(struct drm_i915_private *i915,
+ const struct intel_cdclk_config *cdclk_config,
const char *context)
{
- DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
- context, cdclk_config->cdclk, cdclk_config->vco,
- cdclk_config->ref, cdclk_config->bypass,
- cdclk_config->voltage_level);
+ drm_dbg_kms(&i915->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
+ context, cdclk_config->cdclk, cdclk_config->vco,
+ cdclk_config->ref, cdclk_config->bypass,
+ cdclk_config->voltage_level);
}
/**
if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->cdclk_funcs->set_cdclk))
return;
- intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
+ intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK to");
for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
if (drm_WARN(&dev_priv->drm,
intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config),
"cdclk state doesn't match!\n")) {
- intel_dump_cdclk_config(&dev_priv->cdclk.hw, "[hw state]");
- intel_dump_cdclk_config(cdclk_config, "[sw state]");
+ intel_cdclk_dump_config(dev_priv, &dev_priv->cdclk.hw, "[hw state]");
+ intel_cdclk_dump_config(dev_priv, cdclk_config, "[sw state]");
}
}
#include <linux/types.h>
-#include "i915_drv.h"
#include "intel_display.h"
#include "intel_global_state.h"
struct intel_atomic_state;
struct intel_crtc_state;
+struct intel_cdclk_config {
+ unsigned int cdclk, vco, ref, bypass;
+ u8 voltage_level;
+};
+
struct intel_cdclk_state {
struct intel_global_state base;
const struct intel_cdclk_config *b);
void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
-void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
+void intel_cdclk_dump_config(struct drm_i915_private *i915,
+ const struct intel_cdclk_config *cdclk_config,
const char *context);
int intel_modeset_calc_cdclk(struct intel_atomic_state *state);
void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
*/
#include "intel_combo_phy.h"
+#include "intel_combo_phy_regs.h"
#include "intel_de.h"
#include "intel_display_types.h"
--- /dev/null
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_COMBO_PHY_REGS__
+#define __INTEL_COMBO_PHY_REGS__
+
+#include "i915_reg_defs.h"
+
+#define _ICL_COMBOPHY_A 0x162000
+#define _ICL_COMBOPHY_B 0x6C000
+#define _EHL_COMBOPHY_C 0x160000
+#define _RKL_COMBOPHY_D 0x161000
+#define _ADL_COMBOPHY_E 0x16B000
+
+#define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \
+ _ICL_COMBOPHY_B, \
+ _EHL_COMBOPHY_C, \
+ _RKL_COMBOPHY_D, \
+ _ADL_COMBOPHY_E)
+
+/* ICL Port CL_DW registers */
+#define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
+ 4 * (dw))
+
+#define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy))
+#define CL_POWER_DOWN_ENABLE (1 << 4)
+#define SUS_CLOCK_CONFIG (3 << 0)
+
+#define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy))
+#define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25)
+#define PG_SEQ_DELAY_OVERRIDE_SHIFT 25
+#define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24)
+#define PWR_UP_ALL_LANES (0x0 << 4)
+#define PWR_DOWN_LN_3_2_1 (0xe << 4)
+#define PWR_DOWN_LN_3_2 (0xc << 4)
+#define PWR_DOWN_LN_3 (0x8 << 4)
+#define PWR_DOWN_LN_2_1_0 (0x7 << 4)
+#define PWR_DOWN_LN_1_0 (0x3 << 4)
+#define PWR_DOWN_LN_3_1 (0xa << 4)
+#define PWR_DOWN_LN_3_1_0 (0xb << 4)
+#define PWR_DOWN_LN_MASK (0xf << 4)
+#define PWR_DOWN_LN_SHIFT 4
+#define EDP4K2K_MODE_OVRD_EN (1 << 3)
+#define EDP4K2K_MODE_OVRD_OPTIMIZED (1 << 2)
+
+#define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))
+#define ICL_LANE_ENABLE_AUX (1 << 0)
+
+/* ICL Port COMP_DW registers */
+#define _ICL_PORT_COMP 0x100
+#define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
+ _ICL_PORT_COMP + 4 * (dw))
+
+#define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy))
+#define COMP_INIT (1 << 31)
+
+#define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy))
+
+#define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy))
+#define PROCESS_INFO_DOT_0 (0 << 26)
+#define PROCESS_INFO_DOT_1 (1 << 26)
+#define PROCESS_INFO_DOT_4 (2 << 26)
+#define PROCESS_INFO_MASK (7 << 26)
+#define PROCESS_INFO_SHIFT 26
+#define VOLTAGE_INFO_0_85V (0 << 24)
+#define VOLTAGE_INFO_0_95V (1 << 24)
+#define VOLTAGE_INFO_1_05V (2 << 24)
+#define VOLTAGE_INFO_MASK (3 << 24)
+#define VOLTAGE_INFO_SHIFT 24
+
+#define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy))
+#define IREFGEN (1 << 24)
+
+#define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy))
+
+#define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy))
+
+/* ICL Port PCS registers */
+#define _ICL_PORT_PCS_AUX 0x300
+#define _ICL_PORT_PCS_GRP 0x600
+#define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100)
+#define _ICL_PORT_PCS_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
+ _ICL_PORT_PCS_AUX + 4 * (dw))
+#define _ICL_PORT_PCS_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
+ _ICL_PORT_PCS_GRP + 4 * (dw))
+#define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
+ _ICL_PORT_PCS_LN(ln) + 4 * (dw))
+#define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
+#define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
+#define ICL_PORT_PCS_DW1_LN(ln, phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, ln, phy))
+#define DCC_MODE_SELECT_MASK (0x3 << 20)
+#define DCC_MODE_SELECT_CONTINUOSLY (0x3 << 20)
+#define COMMON_KEEPER_EN (1 << 26)
+#define LATENCY_OPTIM_MASK (0x3 << 2)
+#define LATENCY_OPTIM_VAL(x) ((x) << 2)
+
+/* ICL Port TX registers */
+#define _ICL_PORT_TX_AUX 0x380
+#define _ICL_PORT_TX_GRP 0x680
+#define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100)
+
+#define _ICL_PORT_TX_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
+ _ICL_PORT_TX_AUX + 4 * (dw))
+#define _ICL_PORT_TX_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
+ _ICL_PORT_TX_GRP + 4 * (dw))
+#define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
+ _ICL_PORT_TX_LN(ln) + 4 * (dw))
+
+#define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
+#define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
+#define ICL_PORT_TX_DW2_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(2, ln, phy))
+#define SWING_SEL_UPPER(x) (((x) >> 3) << 15)
+#define SWING_SEL_UPPER_MASK (1 << 15)
+#define SWING_SEL_LOWER(x) (((x) & 0x7) << 11)
+#define SWING_SEL_LOWER_MASK (0x7 << 11)
+#define FRC_LATENCY_OPTIM_MASK (0x7 << 8)
+#define FRC_LATENCY_OPTIM_VAL(x) ((x) << 8)
+#define RCOMP_SCALAR(x) ((x) << 0)
+#define RCOMP_SCALAR_MASK (0xFF << 0)
+
+#define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
+#define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
+#define ICL_PORT_TX_DW4_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))
+#define LOADGEN_SELECT (1 << 31)
+#define POST_CURSOR_1(x) ((x) << 12)
+#define POST_CURSOR_1_MASK (0x3F << 12)
+#define POST_CURSOR_2(x) ((x) << 6)
+#define POST_CURSOR_2_MASK (0x3F << 6)
+#define CURSOR_COEFF(x) ((x) << 0)
+#define CURSOR_COEFF_MASK (0x3F << 0)
+
+#define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
+#define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
+#define ICL_PORT_TX_DW5_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(5, ln, phy))
+#define TX_TRAINING_EN (1 << 31)
+#define TAP2_DISABLE (1 << 30)
+#define TAP3_DISABLE (1 << 29)
+#define SCALING_MODE_SEL(x) ((x) << 18)
+#define SCALING_MODE_SEL_MASK (0x7 << 18)
+#define RTERM_SELECT(x) ((x) << 3)
+#define RTERM_SELECT_MASK (0x7 << 3)
+
+#define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
+#define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
+#define ICL_PORT_TX_DW7_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))
+#define N_SCALAR(x) ((x) << 24)
+#define N_SCALAR_MASK (0x7F << 24)
+
+#define ICL_PORT_TX_DW8_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(8, phy))
+#define ICL_PORT_TX_DW8_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(8, phy))
+#define ICL_PORT_TX_DW8_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(8, ln, phy))
+#define ICL_PORT_TX_DW8_ODCC_CLK_SEL REG_BIT(31)
+#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK REG_GENMASK(30, 29)
+#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1)
+
+#define _ICL_DPHY_CHKN_REG 0x194
+#define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
+#define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7)
+
+#endif /* __INTEL_COMBO_PHY_REGS__ */
#include <drm/drm_plane_helper.h>
#include <drm/drm_vblank_work.h>
+#include "i915_irq.h"
#include "i915_vgpu.h"
#include "i9xx_plane.h"
#include "icl_dsi.h"
u32 pos = 0;
if (x < 0) {
- pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
+ pos |= CURSOR_POS_X_SIGN;
x = -x;
}
- pos |= x << CURSOR_X_SHIFT;
+ pos |= CURSOR_POS_X(x);
if (y < 0) {
- pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
+ pos |= CURSOR_POS_Y_SIGN;
y = -y;
}
- pos |= y << CURSOR_Y_SHIFT;
+ pos |= CURSOR_POS_Y(y);
return pos;
}
u32 cntl = 0;
if (crtc_state->gamma_enable)
- cntl |= CURSOR_GAMMA_ENABLE;
+ cntl |= CURSOR_PIPE_GAMMA_ENABLE;
return cntl;
}
cntl = plane_state->ctl |
i845_cursor_ctl_crtc(crtc_state);
- size = (height << 12) | width;
+ size = CURSOR_HEIGHT(height) | CURSOR_WIDTH(width);
base = intel_cursor_base(plane_state);
pos = intel_cursor_position(plane_state);
plane->cursor.cntl != cntl) {
intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);
intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
- intel_de_write_fw(dev_priv, CURSIZE, size);
+ intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size);
intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
return cntl;
if (crtc_state->gamma_enable)
- cntl = MCURSOR_GAMMA_ENABLE;
+ cntl = MCURSOR_PIPE_GAMMA_ENABLE;
if (crtc_state->csc_enable)
cntl |= MCURSOR_PIPE_CSC_ENABLE;
if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
- cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
+ cntl |= MCURSOR_PIPE_SEL(crtc->pipe);
return cntl;
}
i9xx_cursor_ctl_crtc(crtc_state);
if (width != height)
- fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
+ fbc_ctl = CUR_FBC_EN | CUR_FBC_HEIGHT(height - 1);
base = intel_cursor_base(plane_state);
pos = intel_cursor_position(plane_state);
val = intel_de_read(dev_priv, CURCNTR(plane->pipe));
- ret = val & MCURSOR_MODE;
+ ret = val & MCURSOR_MODE_MASK;
if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
*pipe = plane->pipe;
else
- *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
- MCURSOR_PIPE_SELECT_SHIFT;
+ *pipe = REG_FIELD_GET(MCURSOR_PIPE_SEL_MASK, val);
intel_display_power_put(dev_priv, power_domain, wakeref);
#include "intel_audio.h"
#include "intel_backlight.h"
#include "intel_combo_phy.h"
+#include "intel_combo_phy_regs.h"
#include "intel_connector.h"
#include "intel_crtc.h"
#include "intel_ddi.h"
#include "intel_snps_phy.h"
#include "intel_sprite.h"
#include "intel_tc.h"
+#include "intel_tc_phy_regs.h"
#include "intel_vdsc.h"
#include "intel_vrr.h"
#include "skl_scaler.h"
OVERLAP_PIXELS_MASK, dss1);
}
-static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state,
- struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
-{
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
- bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
-
- intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
- crtc_state->lane_count);
-
- /*
- * We only configure what the register value will be here. Actual
- * enabling happens during link training farther down.
- */
- intel_ddi_init_dp_buf_reg(encoder, crtc_state);
-
- /*
- * 1. Enable Power Wells
- *
- * This was handled at the beginning of intel_atomic_commit_tail(),
- * before we called down into this function.
- */
-
- /* 2. Enable Panel Power if PPS is required */
- intel_pps_on(intel_dp);
-
- /*
- * 3. Enable the port PLL.
- */
- intel_ddi_enable_clock(encoder, crtc_state);
-
- /* 4. Enable IO power */
- if (!intel_tc_port_in_tbt_alt_mode(dig_port))
- dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
- dig_port->ddi_io_power_domain);
-
- /*
- * 5. The rest of the below are substeps under the bspec's "Enable and
- * Train Display Port" step. Note that steps that are specific to
- * MST will be handled by intel_mst_pre_enable_dp() before/after it
- * calls into this function. Also intel_mst_pre_enable_dp() only calls
- * us when active_mst_links==0, so any steps designated for "single
- * stream or multi-stream master transcoder" can just be performed
- * unconditionally here.
- */
-
- /*
- * 5.a Configure Transcoder Clock Select to direct the Port clock to the
- * Transcoder.
- */
- intel_ddi_enable_pipe_clock(encoder, crtc_state);
-
- /* 5.b Configure transcoder for DP 2.0 128b/132b */
- intel_ddi_config_transcoder_dp2(encoder, crtc_state);
-
- /*
- * 5.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
- * Transport Select
- */
- intel_ddi_config_transcoder_func(encoder, crtc_state);
-
- /*
- * 5.d Configure & enable DP_TP_CTL with link training pattern 1
- * selected
- *
- * This will be handled by the intel_dp_start_link_train() farther
- * down this function.
- */
-
- /* 5.e Configure voltage swing and related IO settings */
- encoder->set_signal_levels(encoder, crtc_state);
-
- if (!is_mst)
- intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
-
- intel_dp_configure_protocol_converter(intel_dp, crtc_state);
- intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
- /*
- * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
- * in the FEC_CONFIGURATION register to 1 before initiating link
- * training
- */
- intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
- intel_dp_check_frl_training(intel_dp);
- intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
-
- /*
- * 5.h Follow DisplayPort specification training sequence (see notes for
- * failure handling)
- * 5.i If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
- * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
- * (timeout after 800 us)
- */
- intel_dp_start_link_train(intel_dp, crtc_state);
-
- /* 5.j Set DP_TP_CTL link training to Normal */
- if (!is_trans_port_sync_mode(crtc_state))
- intel_dp_stop_link_train(intel_dp, crtc_state);
-
- /* 5.k Configure and enable FEC if needed */
- intel_ddi_enable_fec(encoder, crtc_state);
-
- intel_dsc_dp_pps_write(encoder, crtc_state);
-
- intel_dsc_enable(crtc_state);
-}
-
static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
*/
intel_ddi_enable_pipe_clock(encoder, crtc_state);
+ if (HAS_DP20(dev_priv))
+ intel_ddi_config_transcoder_dp2(encoder, crtc_state);
+
/*
* 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
* Transport Select
intel_ddi_enable_fec(encoder, crtc_state);
intel_dsc_dp_pps_write(encoder, crtc_state);
-
- if (!crtc_state->bigjoiner)
- intel_dsc_enable(crtc_state);
}
static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
intel_ddi_enable_pipe_clock(encoder, crtc_state);
intel_dsc_dp_pps_write(encoder, crtc_state);
-
- if (!crtc_state->bigjoiner)
- intel_dsc_enable(crtc_state);
}
static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- if (IS_DG2(dev_priv))
- dg2_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
- else if (DISPLAY_VER(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
else
hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
const struct intel_link_m_n *m_n_2)
{
return m_n_1->tu == m_n_2->tu &&
- m_n_1->gmch_m == m_n_2->gmch_m &&
- m_n_1->gmch_n == m_n_2->gmch_n &&
+ m_n_1->data_m == m_n_2->data_m &&
+ m_n_1->data_n == m_n_2->data_n &&
m_n_1->link_m == m_n_2->link_m &&
m_n_1->link_n == m_n_2->link_n;
}
};
static const union intel_ddi_buf_trans_entry _dg2_snps_trans[] = {
- { .snps = { 26, 0, 0 } }, /* VS 0, pre-emph 0 */
- { .snps = { 33, 0, 6 } }, /* VS 0, pre-emph 1 */
- { .snps = { 38, 0, 12 } }, /* VS 0, pre-emph 2 */
- { .snps = { 43, 0, 19 } }, /* VS 0, pre-emph 3 */
- { .snps = { 39, 0, 0 } }, /* VS 1, pre-emph 0 */
- { .snps = { 44, 0, 8 } }, /* VS 1, pre-emph 1 */
- { .snps = { 47, 0, 15 } }, /* VS 1, pre-emph 2 */
- { .snps = { 52, 0, 0 } }, /* VS 2, pre-emph 0 */
- { .snps = { 51, 0, 10 } }, /* VS 2, pre-emph 1 */
+ { .snps = { 25, 0, 0 } }, /* VS 0, pre-emph 0 */
+ { .snps = { 32, 0, 6 } }, /* VS 0, pre-emph 1 */
+ { .snps = { 35, 0, 10 } }, /* VS 0, pre-emph 2 */
+ { .snps = { 43, 0, 17 } }, /* VS 0, pre-emph 3 */
+ { .snps = { 35, 0, 0 } }, /* VS 1, pre-emph 0 */
+ { .snps = { 45, 0, 8 } }, /* VS 1, pre-emph 1 */
+ { .snps = { 48, 0, 14 } }, /* VS 1, pre-emph 2 */
+ { .snps = { 47, 0, 0 } }, /* VS 2, pre-emph 0 */
+ { .snps = { 55, 0, 7 } }, /* VS 2, pre-emph 1 */
{ .snps = { 62, 0, 0 } }, /* VS 3, pre-emph 0 */
};
static const union intel_ddi_buf_trans_entry _dg2_snps_trans_uhbr[] = {
{ .snps = { 62, 0, 0 } }, /* preset 0 */
- { .snps = { 56, 0, 6 } }, /* preset 1 */
- { .snps = { 51, 0, 11 } }, /* preset 2 */
- { .snps = { 48, 0, 14 } }, /* preset 3 */
- { .snps = { 43, 0, 19 } }, /* preset 4 */
+ { .snps = { 55, 0, 7 } }, /* preset 1 */
+ { .snps = { 50, 0, 12 } }, /* preset 2 */
+ { .snps = { 44, 0, 18 } }, /* preset 3 */
+ { .snps = { 35, 0, 21 } }, /* preset 4 */
{ .snps = { 59, 3, 0 } }, /* preset 5 */
{ .snps = { 53, 3, 6 } }, /* preset 6 */
- { .snps = { 49, 3, 10 } }, /* preset 7 */
- { .snps = { 45, 3, 14 } }, /* preset 8 */
- { .snps = { 42, 3, 17 } }, /* preset 9 */
+ { .snps = { 48, 3, 11 } }, /* preset 7 */
+ { .snps = { 42, 5, 15 } }, /* preset 8 */
+ { .snps = { 37, 5, 20 } }, /* preset 9 */
{ .snps = { 56, 6, 0 } }, /* preset 10 */
- { .snps = { 50, 6, 6 } }, /* preset 11 */
- { .snps = { 47, 6, 9 } }, /* preset 12 */
- { .snps = { 42, 6, 14 } }, /* preset 13 */
- { .snps = { 46, 8, 8 } }, /* preset 14 */
- { .snps = { 56, 3, 3 } }, /* preset 15 */
+ { .snps = { 48, 7, 7 } }, /* preset 11 */
+ { .snps = { 45, 7, 10 } }, /* preset 12 */
+ { .snps = { 39, 8, 15 } }, /* preset 13 */
+ { .snps = { 48, 14, 0 } }, /* preset 14 */
+ { .snps = { 45, 4, 4 } }, /* preset 15 */
};
static const struct intel_ddi_buf_trans dg2_snps_trans_uhbr = {
{
i915_reg_t reg = PIPEDSL(pipe);
u32 line1, line2;
- u32 line_mask;
- if (DISPLAY_VER(dev_priv) == 2)
- line_mask = DSL_LINEMASK_GEN2;
- else
- line_mask = DSL_LINEMASK_GEN3;
-
- line1 = intel_de_read(dev_priv, reg) & line_mask;
+ line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
msleep(5);
- line2 = intel_de_read(dev_priv, reg) & line_mask;
+ line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
return line1 != line2;
}
if (DISPLAY_VER(dev_priv) >= 4) {
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
- i915_reg_t reg = PIPECONF(cpu_transcoder);
/* Wait for the Pipe State to go off */
- if (intel_de_wait_for_clear(dev_priv, reg,
- I965_PIPECONF_ACTIVE, 100))
- drm_WARN(&dev_priv->drm, 1,
- "pipe_off wait timed out\n");
+ if (intel_de_wait_for_clear(dev_priv, PIPECONF(cpu_transcoder),
+ PIPECONF_STATE_ENABLE, 100))
+ drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n");
} else {
intel_wait_for_pipe_scanline_stopped(crtc);
}
drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
if (IS_BROADWELL(dev_priv)) {
- drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
- IPS_ENABLE | IPS_PCODE_CONTROL));
+ drm_WARN_ON(dev, snb_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
+ IPS_ENABLE | IPS_PCODE_CONTROL));
/* Quoting Art Runyan: "its not safe to expect any particular
* value in IPS_CTL bit 31 after enabling IPS through the
* mailbox." Moreover, the mailbox may return a bogus state,
if (IS_BROADWELL(dev_priv)) {
drm_WARN_ON(dev,
- sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
+ snb_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
/*
* Wait for PCODE to finish disabling IPS. The BSpec specified
* 42ms timeout value leads to occasional timeouts so use 100ms
for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
if (plane->enable_flip_done &&
plane->pipe == crtc->pipe &&
- update_planes & BIT(plane->id))
+ update_planes & BIT(plane->id) &&
+ plane_state->do_async_flip)
plane->enable_flip_done(plane);
}
}
for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
if (plane->disable_flip_done &&
plane->pipe == crtc->pipe &&
- update_planes & BIT(plane->id))
+ update_planes & BIT(plane->id) &&
+ plane_state->do_async_flip)
plane->disable_flip_done(plane);
}
}
intel_encoders_pre_enable(state, crtc);
if (new_crtc_state->has_pch_encoder) {
- /* Note: FDI PLL enabling _must_ be done before we enable the
- * cpu pipes, hence this is separate from all the other fdi/pch
- * enabling. */
- ilk_fdi_pll_enable(new_crtc_state);
+ ilk_pch_pre_enable(state, crtc);
} else {
assert_fdi_tx_disabled(dev_priv, pipe);
assert_fdi_rx_disabled(dev_priv, pipe);
static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *master_crtc_state;
struct intel_crtc *master_crtc;
struct drm_connector_state *conn_state;
if (crtc_state->bigjoiner_slave)
intel_encoders_pre_enable(state, master_crtc);
+}
+
+static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- /* need to enable VDSC, which we skipped in pre-enable */
- intel_dsc_enable(crtc_state);
+ intel_set_transcoder_timings(crtc_state);
- if (DISPLAY_VER(dev_priv) >= 13)
- intel_uncompressed_joiner_enable(crtc_state);
+ if (cpu_transcoder != TRANSCODER_EDP)
+ intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
+ crtc_state->pixel_multiplier - 1);
+
+ if (crtc_state->has_pch_encoder)
+ intel_cpu_transcoder_set_m_n(crtc_state,
+ &crtc_state->fdi_m_n, NULL);
+
+ hsw_set_frame_start_delay(crtc_state);
+
+ hsw_set_transconf(crtc_state);
}
static void hsw_crtc_enable(struct intel_atomic_state *state,
icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
}
+ intel_dsc_enable(new_crtc_state);
+
+ if (DISPLAY_VER(dev_priv) >= 13)
+ intel_uncompressed_joiner_enable(new_crtc_state);
+
intel_set_pipe_src_size(new_crtc_state);
if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
bdw_set_pipemisc(new_crtc_state);
- if (!new_crtc_state->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder)) {
- intel_set_transcoder_timings(new_crtc_state);
-
- if (cpu_transcoder != TRANSCODER_EDP)
- intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
- new_crtc_state->pixel_multiplier - 1);
-
- if (new_crtc_state->has_pch_encoder)
- intel_cpu_transcoder_set_m_n(new_crtc_state,
- &new_crtc_state->fdi_m_n, NULL);
-
- hsw_set_frame_start_delay(new_crtc_state);
-
- hsw_set_transconf(new_crtc_state);
- }
+ if (!new_crtc_state->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder))
+ hsw_configure_cpu_transcoder(new_crtc_state);
crtc->active = true;
m_n->tu = 64;
compute_m_n(data_clock,
link_clock * nlanes * 8,
- &m_n->gmch_m, &m_n->gmch_n,
+ &m_n->data_m, &m_n->data_n,
constant_n);
compute_m_n(pixel_clock, link_clock,
}
}
+static void intel_set_m_n(struct drm_i915_private *i915,
+ const struct intel_link_m_n *m_n,
+ i915_reg_t data_m_reg, i915_reg_t data_n_reg,
+ i915_reg_t link_m_reg, i915_reg_t link_n_reg)
+{
+ intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
+ intel_de_write(i915, data_n_reg, m_n->data_n);
+ intel_de_write(i915, link_m_reg, m_n->link_m);
+ intel_de_write(i915, link_n_reg, m_n->link_n);
+}
+
static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
const struct intel_link_m_n *m_n)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
- intel_de_write(dev_priv, PCH_TRANS_DATA_M1(pipe),
- TU_SIZE(m_n->tu) | m_n->gmch_m);
- intel_de_write(dev_priv, PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
- intel_de_write(dev_priv, PCH_TRANS_LINK_M1(pipe), m_n->link_m);
- intel_de_write(dev_priv, PCH_TRANS_LINK_N1(pipe), m_n->link_n);
+ intel_set_m_n(dev_priv, m_n,
+ PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),
+ PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));
}
static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
enum transcoder transcoder = crtc_state->cpu_transcoder;
if (DISPLAY_VER(dev_priv) >= 5) {
- intel_de_write(dev_priv, PIPE_DATA_M1(transcoder),
- TU_SIZE(m_n->tu) | m_n->gmch_m);
- intel_de_write(dev_priv, PIPE_DATA_N1(transcoder),
- m_n->gmch_n);
- intel_de_write(dev_priv, PIPE_LINK_M1(transcoder),
- m_n->link_m);
- intel_de_write(dev_priv, PIPE_LINK_N1(transcoder),
- m_n->link_n);
+ intel_set_m_n(dev_priv, m_n,
+ PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
+ PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
/*
* M2_N2 registers are set only if DRRS is supported
* (to make sure the registers are not unnecessarily accessed).
*/
if (m2_n2 && crtc_state->has_drrs &&
transcoder_has_m2_n2(dev_priv, transcoder)) {
- intel_de_write(dev_priv, PIPE_DATA_M2(transcoder),
- TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
- intel_de_write(dev_priv, PIPE_DATA_N2(transcoder),
- m2_n2->gmch_n);
- intel_de_write(dev_priv, PIPE_LINK_M2(transcoder),
- m2_n2->link_m);
- intel_de_write(dev_priv, PIPE_LINK_N2(transcoder),
- m2_n2->link_n);
+ intel_set_m_n(dev_priv, m2_n2,
+ PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
+ PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
}
} else {
- intel_de_write(dev_priv, PIPE_DATA_M_G4X(pipe),
- TU_SIZE(m_n->tu) | m_n->gmch_m);
- intel_de_write(dev_priv, PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
- intel_de_write(dev_priv, PIPE_LINK_M_G4X(pipe), m_n->link_m);
- intel_de_write(dev_priv, PIPE_LINK_N_G4X(pipe), m_n->link_n);
+ intel_set_m_n(dev_priv, m_n,
+ PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
+ PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
}
}
* always be the user's requested size.
*/
intel_de_write(dev_priv, PIPESRC(pipe),
- ((crtc_state->pipe_src_w - 1) << 16) | (crtc_state->pipe_src_h - 1));
+ PIPESRC_WIDTH(crtc_state->pipe_src_w - 1) |
+ PIPESRC_HEIGHT(crtc_state->pipe_src_h - 1));
}
static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
u32 tmp;
tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
- pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
- pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
+ pipe_config->pipe_src_w = REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1;
+ pipe_config->pipe_src_h = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1;
}
static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
switch (crtc_state->pipe_bpp) {
case 18:
- pipeconf |= PIPECONF_6BPC;
+ pipeconf |= PIPECONF_BPC_6;
break;
case 24:
- pipeconf |= PIPECONF_8BPC;
+ pipeconf |= PIPECONF_BPC_8;
break;
case 30:
- pipeconf |= PIPECONF_10BPC;
+ pipeconf |= PIPECONF_BPC_10;
break;
default:
/* Case prevented by intel_choose_pipe_bpp_dither. */
else
pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
} else {
- pipeconf |= PIPECONF_PROGRESSIVE;
+ pipeconf |= PIPECONF_INTERLACE_PROGRESSIVE;
}
if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
- if (tmp & DISPPLANE_GAMMA_ENABLE)
+ if (tmp & DISP_PIPE_GAMMA_ENABLE)
crtc_state->gamma_enable = true;
if (!HAS_GMCH(dev_priv) &&
- tmp & DISPPLANE_PIPE_CSC_ENABLE)
+ tmp & DISP_PIPE_CSC_ENABLE)
crtc_state->csc_enable = true;
}
if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
IS_CHERRYVIEW(dev_priv)) {
switch (tmp & PIPECONF_BPC_MASK) {
- case PIPECONF_6BPC:
+ case PIPECONF_BPC_6:
pipe_config->pipe_bpp = 18;
break;
- case PIPECONF_8BPC:
+ case PIPECONF_BPC_8:
pipe_config->pipe_bpp = 24;
break;
- case PIPECONF_10BPC:
+ case PIPECONF_BPC_10:
pipe_config->pipe_bpp = 30;
break;
default:
+ MISSING_CASE(tmp);
break;
}
}
(tmp & PIPECONF_COLOR_RANGE_SELECT))
pipe_config->limited_color_range = true;
- pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
- PIPECONF_GAMMA_MODE_SHIFT;
+ pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_I9XX, tmp);
if (IS_CHERRYVIEW(dev_priv))
pipe_config->cgm_mode = intel_de_read(dev_priv,
switch (crtc_state->pipe_bpp) {
case 18:
- val |= PIPECONF_6BPC;
+ val |= PIPECONF_BPC_6;
break;
case 24:
- val |= PIPECONF_8BPC;
+ val |= PIPECONF_BPC_8;
break;
case 30:
- val |= PIPECONF_10BPC;
+ val |= PIPECONF_BPC_10;
break;
case 36:
- val |= PIPECONF_12BPC;
+ val |= PIPECONF_BPC_12;
break;
default:
/* Case prevented by intel_choose_pipe_bpp_dither. */
}
if (crtc_state->dither)
- val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
+ val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP;
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
- val |= PIPECONF_INTERLACED_ILK;
+ val |= PIPECONF_INTERLACE_IF_ID_ILK;
else
- val |= PIPECONF_PROGRESSIVE;
+ val |= PIPECONF_INTERLACE_PF_PD_ILK;
/*
* This would end up with an odd purple hue over
u32 val = 0;
if (IS_HASWELL(dev_priv) && crtc_state->dither)
- val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
+ val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP;
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
- val |= PIPECONF_INTERLACED_ILK;
+ val |= PIPECONF_INTERLACE_IF_ID_ILK;
else
- val |= PIPECONF_PROGRESSIVE;
+ val |= PIPECONF_INTERLACE_PF_PD_ILK;
if (IS_HASWELL(dev_priv) &&
crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
switch (crtc_state->pipe_bpp) {
case 18:
- val |= PIPEMISC_6_BPC;
+ val |= PIPEMISC_BPC_6;
break;
case 24:
- val |= PIPEMISC_8_BPC;
+ val |= PIPEMISC_BPC_8;
break;
case 30:
- val |= PIPEMISC_10_BPC;
+ val |= PIPEMISC_BPC_10;
break;
case 36:
/* Port output 12BPC defined for ADLP+ */
if (DISPLAY_VER(dev_priv) > 12)
- val |= PIPEMISC_12_BPC_ADLP;
+ val |= PIPEMISC_BPC_12_ADLP;
break;
default:
MISSING_CASE(crtc_state->pipe_bpp);
}
intel_de_rmw(dev_priv, PIPE_MISC2(crtc->pipe),
- PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK,
+ PIPE_MISC2_BUBBLE_COUNTER_MASK,
scaler_in_use ? PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN :
PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS);
}
tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
switch (tmp & PIPEMISC_BPC_MASK) {
- case PIPEMISC_6_BPC:
+ case PIPEMISC_BPC_6:
return 18;
- case PIPEMISC_8_BPC:
+ case PIPEMISC_BPC_8:
return 24;
- case PIPEMISC_10_BPC:
+ case PIPEMISC_BPC_10:
return 30;
/*
* PORT OUTPUT 12 BPC defined for ADLP+.
* on older platforms, need to find a workaround for 12 BPC
* MIPI DSI HW readout.
*/
- case PIPEMISC_12_BPC_ADLP:
+ case PIPEMISC_BPC_12_ADLP:
if (DISPLAY_VER(dev_priv) > 12)
return 36;
fallthrough;
return DIV_ROUND_UP(bps, link_bw * 8);
}
+static void intel_get_m_n(struct drm_i915_private *i915,
+ struct intel_link_m_n *m_n,
+ i915_reg_t data_m_reg, i915_reg_t data_n_reg,
+ i915_reg_t link_m_reg, i915_reg_t link_n_reg)
+{
+ m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK;
+ m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK;
+ m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;
+ m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;
+ m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;
+}
+
static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
struct intel_link_m_n *m_n)
{
struct drm_i915_private *dev_priv = to_i915(dev);
enum pipe pipe = crtc->pipe;
- m_n->link_m = intel_de_read(dev_priv, PCH_TRANS_LINK_M1(pipe));
- m_n->link_n = intel_de_read(dev_priv, PCH_TRANS_LINK_N1(pipe));
- m_n->gmch_m = intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
- & ~TU_SIZE_MASK;
- m_n->gmch_n = intel_de_read(dev_priv, PCH_TRANS_DATA_N1(pipe));
- m_n->tu = ((intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
- & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
+ intel_get_m_n(dev_priv, m_n,
+ PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),
+ PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));
}
static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
enum pipe pipe = crtc->pipe;
if (DISPLAY_VER(dev_priv) >= 5) {
- m_n->link_m = intel_de_read(dev_priv,
- PIPE_LINK_M1(transcoder));
- m_n->link_n = intel_de_read(dev_priv,
- PIPE_LINK_N1(transcoder));
- m_n->gmch_m = intel_de_read(dev_priv,
- PIPE_DATA_M1(transcoder))
- & ~TU_SIZE_MASK;
- m_n->gmch_n = intel_de_read(dev_priv,
- PIPE_DATA_N1(transcoder));
- m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M1(transcoder))
- & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
+ intel_get_m_n(dev_priv, m_n,
+ PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
+ PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
- m2_n2->link_m = intel_de_read(dev_priv,
- PIPE_LINK_M2(transcoder));
- m2_n2->link_n = intel_de_read(dev_priv,
- PIPE_LINK_N2(transcoder));
- m2_n2->gmch_m = intel_de_read(dev_priv,
- PIPE_DATA_M2(transcoder))
- & ~TU_SIZE_MASK;
- m2_n2->gmch_n = intel_de_read(dev_priv,
- PIPE_DATA_N2(transcoder));
- m2_n2->tu = ((intel_de_read(dev_priv, PIPE_DATA_M2(transcoder))
- & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
+ intel_get_m_n(dev_priv, m2_n2,
+ PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
+ PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
}
} else {
- m_n->link_m = intel_de_read(dev_priv, PIPE_LINK_M_G4X(pipe));
- m_n->link_n = intel_de_read(dev_priv, PIPE_LINK_N_G4X(pipe));
- m_n->gmch_m = intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
- & ~TU_SIZE_MASK;
- m_n->gmch_n = intel_de_read(dev_priv, PIPE_DATA_N_G4X(pipe));
- m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
- & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
+ intel_get_m_n(dev_priv, m_n,
+ PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
+ PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
}
}
goto out;
switch (tmp & PIPECONF_BPC_MASK) {
- case PIPECONF_6BPC:
+ case PIPECONF_BPC_6:
pipe_config->pipe_bpp = 18;
break;
- case PIPECONF_8BPC:
+ case PIPECONF_BPC_8:
pipe_config->pipe_bpp = 24;
break;
- case PIPECONF_10BPC:
+ case PIPECONF_BPC_10:
pipe_config->pipe_bpp = 30;
break;
- case PIPECONF_12BPC:
+ case PIPECONF_BPC_12:
pipe_config->pipe_bpp = 36;
break;
default:
break;
}
- pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
- PIPECONF_GAMMA_MODE_SHIFT;
+ pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp);
pipe_config->csc_mode = intel_de_read(dev_priv,
PIPE_CSC_MODE(crtc->pipe));
active = true;
}
+ if (!active)
+ goto out;
+
intel_dsc_get_config(pipe_config);
if (DISPLAY_VER(dev_priv) >= 13 && !pipe_config->dsc.compression_enable)
intel_uncompressed_joiner_get_config(pipe_config);
- if (!active)
- goto out;
-
if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
DISPLAY_VER(dev_priv) >= 11)
intel_get_transcoder_timings(crtc, pipe_config);
return (src_w != dst_w || src_h != dst_h);
}
+static bool intel_plane_do_async_flip(struct intel_plane *plane,
+ const struct intel_crtc_state *old_crtc_state,
+ const struct intel_crtc_state *new_crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+ if (!plane->async_flip)
+ return false;
+
+ if (!new_crtc_state->uapi.async_flip)
+ return false;
+
+ /*
+ * In platforms after DISPLAY13, we might need to override
+ * first async flip in order to change watermark levels
+ * as part of optimization.
+ * So for those, we are checking if this is a first async flip.
+ * For platforms earlier than DISPLAY13 we always do async flip.
+ */
+ return DISPLAY_VER(i915) < 13 || old_crtc_state->uapi.async_flip;
+}
+
int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
struct intel_crtc_state *new_crtc_state,
const struct intel_plane_state *old_plane_state,
needs_scaling(new_plane_state))))
new_crtc_state->disable_lp_wm = true;
+ if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state))
+ new_plane_state->do_async_flip = true;
+
return 0;
}
struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
drm_dbg_kms(&i915->drm,
- "%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
+ "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n",
id, lane_count,
- m_n->gmch_m, m_n->gmch_n,
+ m_n->data_m, m_n->data_n,
m_n->link_m, m_n->link_n, m_n->tu);
}
bool exact)
{
return m_n->tu == m2_n2->tu &&
- intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
- m2_n2->gmch_m, m2_n2->gmch_n, exact) &&
+ intel_compare_m_n(m_n->data_m, m_n->data_n,
+ m2_n2->data_m, m2_n2->data_n, exact) &&
intel_compare_m_n(m_n->link_m, m_n->link_n,
m2_n2->link_m, m2_n2->link_n, exact);
}
&pipe_config->name,\
!fastset)) { \
pipe_config_mismatch(fastset, crtc, __stringify(name), \
- "(expected tu %i gmch %i/%i link %i/%i, " \
- "found tu %i, gmch %i/%i link %i/%i)", \
+ "(expected tu %i data %i/%i link %i/%i, " \
+ "found tu %i, data %i/%i link %i/%i)", \
current_config->name.tu, \
- current_config->name.gmch_m, \
- current_config->name.gmch_n, \
+ current_config->name.data_m, \
+ current_config->name.data_n, \
current_config->name.link_m, \
current_config->name.link_n, \
pipe_config->name.tu, \
- pipe_config->name.gmch_m, \
- pipe_config->name.gmch_n, \
+ pipe_config->name.data_m, \
+ pipe_config->name.data_n, \
pipe_config->name.link_m, \
pipe_config->name.link_n); \
ret = false; \
!intel_compare_link_m_n(¤t_config->alt_name, \
&pipe_config->name, !fastset)) { \
pipe_config_mismatch(fastset, crtc, __stringify(name), \
- "(expected tu %i gmch %i/%i link %i/%i, " \
- "or tu %i gmch %i/%i link %i/%i, " \
- "found tu %i, gmch %i/%i link %i/%i)", \
+ "(expected tu %i data %i/%i link %i/%i, " \
+ "or tu %i data %i/%i link %i/%i, " \
+ "found tu %i, data %i/%i link %i/%i)", \
current_config->name.tu, \
- current_config->name.gmch_m, \
- current_config->name.gmch_n, \
+ current_config->name.data_m, \
+ current_config->name.data_n, \
current_config->name.link_m, \
current_config->name.link_n, \
current_config->alt_name.tu, \
- current_config->alt_name.gmch_m, \
- current_config->alt_name.gmch_n, \
+ current_config->alt_name.data_m, \
+ current_config->alt_name.data_n, \
current_config->alt_name.link_m, \
current_config->alt_name.link_n, \
pipe_config->name.tu, \
- pipe_config->name.gmch_m, \
- pipe_config->name.gmch_n, \
+ pipe_config->name.data_m, \
+ pipe_config->name.data_n, \
pipe_config->name.link_m, \
pipe_config->name.link_n); \
ret = false; \
struct intel_crtc_state *old_crtc_state,
struct intel_crtc_state *new_crtc_state)
{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_crtc_state *slave_crtc_state, *master_crtc_state;
struct intel_crtc *slave_crtc, *master_crtc;
slave_crtc = intel_dsc_get_bigjoiner_secondary(crtc);
if (!slave_crtc) {
- DRM_DEBUG_KMS("[CRTC:%d:%s] Big joiner configuration requires "
- "CRTC + 1 to be used, doesn't exist\n",
- crtc->base.base.id, crtc->base.name);
+ drm_dbg_kms(&i915->drm,
+ "[CRTC:%d:%s] Big joiner configuration requires "
+ "CRTC + 1 to be used, doesn't exist\n",
+ crtc->base.base.id, crtc->base.name);
return -EINVAL;
}
if (slave_crtc_state->uapi.enable)
goto claimed;
- DRM_DEBUG_KMS("[CRTC:%d:%s] Used as slave for big joiner\n",
- slave_crtc->base.base.id, slave_crtc->base.name);
+ drm_dbg_kms(&i915->drm,
+ "[CRTC:%d:%s] Used as slave for big joiner\n",
+ slave_crtc->base.base.id, slave_crtc->base.name);
return copy_bigjoiner_crtc_state(slave_crtc_state, new_crtc_state);
claimed:
- DRM_DEBUG_KMS("[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
- "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
- slave_crtc->base.base.id, slave_crtc->base.name,
- master_crtc->base.base.id, master_crtc->base.name);
+ drm_dbg_kms(&i915->drm,
+ "[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
+ "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
+ slave_crtc->base.base.id, slave_crtc->base.name,
+ master_crtc->base.base.id, master_crtc->base.name);
return -EINVAL;
}
cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state);
intel_update_cdclk(i915);
- intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
+ intel_cdclk_dump_config(i915, &i915->cdclk.hw, "Current CDCLK");
cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
}
udelay(150); /* wait for warmup */
}
- intel_de_write(dev_priv, PIPECONF(pipe),
- PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
+ intel_de_write(dev_priv, PIPECONF(pipe), PIPECONF_ENABLE);
intel_de_posting_read(dev_priv, PIPECONF(pipe));
intel_wait_for_pipe_scanline_moving(crtc);
pipe_name(pipe));
drm_WARN_ON(&dev_priv->drm,
- intel_de_read(dev_priv, DSPCNTR(PLANE_A)) &
- DISPLAY_PLANE_ENABLE);
+ intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE);
drm_WARN_ON(&dev_priv->drm,
- intel_de_read(dev_priv, DSPCNTR(PLANE_B)) &
- DISPLAY_PLANE_ENABLE);
+ intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE);
drm_WARN_ON(&dev_priv->drm,
- intel_de_read(dev_priv, DSPCNTR(PLANE_C)) &
- DISPLAY_PLANE_ENABLE);
+ intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE);
drm_WARN_ON(&dev_priv->drm,
- intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE);
+ intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK);
drm_WARN_ON(&dev_priv->drm,
- intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE);
+ intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK);
intel_de_write(dev_priv, PIPECONF(pipe), 0);
intel_de_posting_read(dev_priv, PIPECONF(pipe));
/* Used by dp and fdi links */
struct intel_link_m_n {
u32 tu;
- u32 gmch_m;
- u32 gmch_n;
+ u32 data_m;
+ u32 data_n;
u32 link_m;
u32 link_n;
};
*/
void intel_crtc_debugfs_add(struct drm_crtc *crtc)
{
- if (crtc->debugfs_entry)
- crtc_updates_add(crtc);
+ if (!crtc->debugfs_entry)
+ return;
+
+ crtc_updates_add(crtc);
+ intel_fbc_crtc_debugfs_add(to_intel_crtc(crtc));
}
#include "i915_irq.h"
#include "intel_cdclk.h"
#include "intel_combo_phy.h"
+#include "intel_combo_phy_regs.h"
#include "intel_crt.h"
#include "intel_de.h"
#include "intel_display_power.h"
int ret, tries = 0;
while (1) {
- ret = sandybridge_pcode_write_timeout(i915,
- ICL_PCODE_EXIT_TCCOLD,
- 0, 250, 1);
+ ret = snb_pcode_write_timeout(i915, ICL_PCODE_EXIT_TCCOLD, 0,
+ 250, 1);
if (ret != -EAGAIN || ++tries == 3)
break;
msleep(1);
* Spec states that we should timeout the request after 200us
* but the function below will timeout after 500us
*/
- ret = sandybridge_pcode_read(i915, TGL_PCODE_TCCOLD, &low_val,
- &high_val);
+ ret = snb_pcode_read(i915, TGL_PCODE_TCCOLD, &low_val, &high_val);
if (ret == 0) {
if (block &&
(low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED))
static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)
{
if (IS_HASWELL(dev_priv)) {
- if (sandybridge_pcode_write(dev_priv,
- GEN6_PCODE_WRITE_D_COMP, val))
+ if (snb_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
drm_dbg_kms(&dev_priv->drm,
"Failed to write to D_COMP\n");
} else {
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
intel_update_cdclk(dev_priv);
- intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
+ intel_cdclk_dump_config(dev_priv, &dev_priv->cdclk.hw, "Current CDCLK");
}
/*
#include <linux/tracepoint.h>
#include "i915_drv.h"
+#include "i915_irq.h"
#include "intel_crtc.h"
#include "intel_display_types.h"
struct intel_fb_view view;
+ /* Indicates if async flip is required */
+ bool do_async_flip;
+
/* Plane pxp decryption state */
bool decrypt;
__stringify(major) "_" \
__stringify(minor) ".bin"
-#define GEN12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE
+#define DISPLAY_VER13_DMC_MAX_FW_SIZE 0x20000
-#define GEN13_DMC_MAX_FW_SIZE 0x20000
+#define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE
#define ADLP_DMC_PATH DMC_PATH(adlp, 2, 14)
#define ADLP_DMC_VERSION_REQUIRED DMC_VERSION(2, 14)
if (IS_ALDERLAKE_P(dev_priv)) {
dmc->fw_path = ADLP_DMC_PATH;
dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
- dmc->max_fw_size = GEN13_DMC_MAX_FW_SIZE;
+ dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
} else if (IS_ALDERLAKE_S(dev_priv)) {
dmc->fw_path = ADLS_DMC_PATH;
dmc->required_version = ADLS_DMC_VERSION_REQUIRED;
- dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
+ dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE;
} else if (IS_DG1(dev_priv)) {
dmc->fw_path = DG1_DMC_PATH;
dmc->required_version = DG1_DMC_VERSION_REQUIRED;
- dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
+ dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE;
} else if (IS_ROCKETLAKE(dev_priv)) {
dmc->fw_path = RKL_DMC_PATH;
dmc->required_version = RKL_DMC_VERSION_REQUIRED;
- dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
+ dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE;
} else if (DISPLAY_VER(dev_priv) >= 12) {
dmc->fw_path = TGL_DMC_PATH;
dmc->required_version = TGL_DMC_VERSION_REQUIRED;
- dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
+ dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE;
} else if (DISPLAY_VER(dev_priv) == 11) {
dmc->fw_path = ICL_DMC_PATH;
dmc->required_version = ICL_DMC_VERSION_REQUIRED;
#include "intel_atomic.h"
#include "intel_audio.h"
#include "intel_backlight.h"
+#include "intel_combo_phy_regs.h"
#include "intel_connector.h"
#include "intel_crtc.h"
#include "intel_ddi.h"
#include "intel_vdsc.h"
#include "intel_vrr.h"
-#define DP_DPRX_ESI_LEN 14
-
/* DP DSC throughput values used for slice count calculations KPixels/s */
#define DP_DSC_PEAK_PIXEL_RATE 2720000
#define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
i915->max_cdclk_freq * 48 /
intel_dp_mode_to_fec_clock(mode_clock);
- DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
+ drm_dbg_kms(&i915->drm, "Max big joiner bpp: %u\n", max_bpp_bigjoiner);
bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
}
return true;
}
-static bool intel_dp_hdmi_deep_color_possible(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state,
- int bpc)
+static bool intel_dp_hdmi_bpc_possible(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ int bpc)
{
- return intel_hdmi_deep_color_possible(crtc_state, bpc,
- intel_dp->has_hdmi_sink,
- intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) &&
+ return intel_hdmi_bpc_possible(crtc_state, bpc, intel_dp->has_hdmi_sink,
+ intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) &&
intel_dp_hdmi_tmds_clock_valid(intel_dp, crtc_state, bpc);
}
if (intel_dp->dfp.min_tmds_clock) {
for (; bpc >= 10; bpc -= 2) {
- if (intel_dp_hdmi_deep_color_possible(intel_dp, crtc_state, bpc))
+ if (intel_dp_hdmi_bpc_possible(intel_dp, crtc_state, bpc))
break;
}
}
/* FIXME: abstract this better */
if (pipe_config->splitter.enable)
- pipe_config->dp_m_n.gmch_m *= pipe_config->splitter.link_count;
+ pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
if (!HAS_DDI(dev_priv))
g4x_dp_set_clock(encoder, pipe_config);
}
static bool
-intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
+intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)
{
- return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
- sink_irq_vector, DP_DPRX_ESI_LEN) ==
- DP_DPRX_ESI_LEN;
+ return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;
+}
+
+static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])
+{
+ int retry;
+
+ for (retry = 0; retry < 3; retry++) {
+ if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,
+ &esi[1], 3) == 3)
+ return true;
+ }
+
+ return false;
}
bool
}
static ssize_t
-intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_infoframe,
+intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
+ const struct hdmi_drm_infoframe *drm_infoframe,
struct dp_sdp *sdp,
size_t size)
{
len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
if (len < 0) {
- DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
+ drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n");
return -ENOSPC;
}
if (len != infoframe_size) {
- DRM_DEBUG_KMS("wrong static hdr metadata size\n");
+ drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
return -ENOSPC;
}
sizeof(sdp));
break;
case HDMI_PACKET_TYPE_GAMUT_METADATA:
- len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state->infoframes.drm.drm,
+ len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,
+ &crtc_state->infoframes.drm.drm,
&sdp, sizeof(sdp));
break;
default:
switch (data->phy_pattern) {
case DP_PHY_TEST_PATTERN_NONE:
- DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
+ drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n");
intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
break;
case DP_PHY_TEST_PATTERN_D10_2:
- DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
+ drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n");
intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
break;
case DP_PHY_TEST_PATTERN_ERROR_COUNT:
- DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
+ drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n");
intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
DDI_DP_COMP_CTL_ENABLE |
DDI_DP_COMP_CTL_SCRAMBLED_0);
break;
case DP_PHY_TEST_PATTERN_PRBS7:
- DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
+ drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n");
intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
break;
* current firmware of DPR-100 could not set it, so hardcoding
* now for complaince test.
*/
- DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
+ drm_dbg_kms(&dev_priv->drm,
+ "Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
pattern_val = 0x3e0f83e0;
intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
pattern_val = 0x0f83e0f8;
* current firmware of DPR-100 could not set it, so hardcoding
* now for complaince test.
*/
- DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
+ drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n");
pattern_val = 0xFB;
intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct drm_dp_phy_test_params *data =
&intel_dp->compliance.test_data.phytest;
u8 link_status[DP_LINK_STATUS_SIZE];
if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
link_status) < 0) {
- DRM_DEBUG_KMS("failed to get link status\n");
+ drm_dbg_kms(&i915->drm, "failed to get link status\n");
return;
}
static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct drm_dp_phy_test_params *data =
&intel_dp->compliance.test_data.phytest;
if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
- DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
+ drm_dbg_kms(&i915->drm, "DP Phy Test pattern AUX read failure\n");
return DP_TEST_NAK;
}
}
static void
-intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, bool *handled)
+intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
{
- drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, handled);
+ bool handled = false;
- if (esi[1] & DP_CP_IRQ) {
- intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
- *handled = true;
- }
+ drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
+ if (handled)
+ ack[1] |= esi[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY);
+
+ if (esi[1] & DP_CP_IRQ) {
+ intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
+ ack[1] |= DP_CP_IRQ;
+ }
+}
+
+static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
+{
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ u8 link_status[DP_LINK_STATUS_SIZE] = {};
+ const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;
+
+ if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,
+ esi_link_status_size) != esi_link_status_size) {
+ drm_err(&i915->drm,
+ "[ENCODER:%d:%s] Failed to read link status\n",
+ encoder->base.base.id, encoder->base.name);
+ return false;
+ }
+
+ if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
+ drm_dbg_kms(&i915->drm,
+ "[ENCODER:%d:%s] channel EQ not ok, retraining\n",
+ encoder->base.base.id, encoder->base.name);
+ return false;
+ }
+
+ return true;
}
/**
drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
for (;;) {
- /*
- * The +2 is because DP_DPRX_ESI_LEN is 14, but we then
- * pass in "esi+10" to drm_dp_channel_eq_ok(), which
- * takes a 6-byte array. So we actually need 16 bytes
- * here.
- *
- * Somebody who knows what the limits actually are
- * should check this, but for now this is at least
- * harmless and avoids a valid compiler warning about
- * using more of the array than we have allocated.
- */
- u8 esi[DP_DPRX_ESI_LEN+2] = {};
- bool handled;
- int retry;
+ u8 esi[4] = {};
+ u8 ack[4] = {};
if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
drm_dbg_kms(&i915->drm,
break;
}
- /* check link status - esi[10] = 0x200c */
+ drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi);
+
if (intel_dp->active_mst_links > 0 && link_ok &&
- !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
- drm_dbg_kms(&i915->drm,
- "channel EQ not ok, retraining\n");
- link_ok = false;
+ esi[3] & LINK_STATUS_CHANGED) {
+ if (!intel_dp_mst_link_status(intel_dp))
+ link_ok = false;
+ ack[3] |= LINK_STATUS_CHANGED;
}
- drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
+ intel_dp_mst_hpd_irq(intel_dp, esi, ack);
- intel_dp_mst_hpd_irq(intel_dp, esi, &handled);
-
- if (!handled)
+ if (!memchr_inv(ack, 0, sizeof(ack)))
break;
- for (retry = 0; retry < 3; retry++) {
- int wret;
-
- wret = drm_dp_dpcd_write(&intel_dp->aux,
- DP_SINK_COUNT_ESI+1,
- &esi[1], 3);
- if (wret == 3)
- break;
- }
+ if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
+ drm_dbg_kms(&i915->drm, "Failed to ack ESI\n");
}
return link_ok;
mutex_lock(&dev->mode_config.mutex);
edid = drm_get_edid(connector, &intel_dp->aux.ddc);
+ if (!edid) {
+ /* Fallback to EDID from ACPI OpRegion, if any */
+ edid = intel_opregion_get_edid(intel_connector);
+ if (edid)
+ drm_dbg_kms(&dev_priv->drm,
+ "[CONNECTOR:%d:%s] Using OpRegion EDID\n",
+ connector->base.id, connector->name);
+ }
if (edid) {
if (drm_add_edid_modes(connector, edid)) {
drm_connector_update_edid_property(connector, edid);
intel_connector = container_of(work, typeof(*intel_connector),
modeset_retry_work);
connector = &intel_connector->base;
- DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
- connector->name);
+ drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id,
+ connector->name);
/* Grab the locks before changing connector property*/
mutex_lock(&connector->dev->mode_config.mutex);
#include "intel_pps.h"
#include "intel_tc.h"
-u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
+static u32 intel_dp_aux_pack(const u8 *src, int src_bytes)
{
int i;
u32 v = 0;
return v;
}
-static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
+static void intel_dp_aux_unpack(u32 src, u8 *dst, int dst_bytes)
{
int i;
for (i = 0; i < send_bytes; i += 4)
intel_uncore_write(uncore,
ch_data[i >> 2],
- intel_dp_pack_aux(send + i,
+ intel_dp_aux_pack(send + i,
send_bytes - i));
/* Send the command and wait for it to complete */
recv_bytes = recv_size;
for (i = 0; i < recv_bytes; i += 4)
- intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
+ intel_dp_aux_unpack(intel_uncore_read(uncore, ch_data[i >> 2]),
recv + i, recv_bytes - i);
ret = recv_bytes;
#ifndef __INTEL_DP_AUX_H__
#define __INTEL_DP_AUX_H__
-#include <linux/types.h>
-
struct intel_dp;
-u32 intel_dp_pack_aux(const u8 *src, int src_bytes);
-
void intel_dp_aux_fini(struct intel_dp *intel_dp);
void intel_dp_aux_init(struct intel_dp *intel_dp);
#include "intel_dpll_mgr.h"
#include "intel_pch_refclk.h"
#include "intel_tc.h"
+#include "intel_tc_phy_regs.h"
/**
* DOC: Display PLLs
* commit phase.
*/
+/* platform specific hooks for managing DPLLs */
+struct intel_shared_dpll_funcs {
+ /*
+ * Hook for enabling the pll, called from intel_enable_shared_dpll() if
+ * the pll is not already enabled.
+ */
+ void (*enable)(struct drm_i915_private *i915,
+ struct intel_shared_dpll *pll);
+
+ /*
+ * Hook for disabling the pll, called from intel_disable_shared_dpll()
+ * only when it is safe to disable the pll, i.e., there are no more
+ * tracked users for it.
+ */
+ void (*disable)(struct drm_i915_private *i915,
+ struct intel_shared_dpll *pll);
+
+ /*
+ * Hook for reading the values currently programmed to the DPLL
+ * registers. This is used for initial hw state readout and state
+ * verification after a mode set.
+ */
+ bool (*get_hw_state)(struct drm_i915_private *i915,
+ struct intel_shared_dpll *pll,
+ struct intel_dpll_hw_state *hw_state);
+
+ /*
+ * Hook for calculating the pll's output frequency based on its passed
+ * in state.
+ */
+ int (*get_freq)(struct drm_i915_private *i915,
+ const struct intel_shared_dpll *pll,
+ const struct intel_dpll_hw_state *pll_state);
+};
+
struct intel_dpll_mgr {
const struct dpll_info *dpll_info;
struct intel_crtc_state;
struct intel_encoder;
struct intel_shared_dpll;
+struct intel_shared_dpll_funcs;
/**
* enum intel_dpll_id - possible DPLL ids
};
/**
- * struct intel_shared_dpll_funcs - platform specific hooks for managing DPLLs
- */
-struct intel_shared_dpll_funcs {
- /**
- * @enable:
- *
- * Hook for enabling the pll, called from intel_enable_shared_dpll()
- * if the pll is not already enabled.
- */
- void (*enable)(struct drm_i915_private *dev_priv,
- struct intel_shared_dpll *pll);
-
- /**
- * @disable:
- *
- * Hook for disabling the pll, called from intel_disable_shared_dpll()
- * only when it is safe to disable the pll, i.e., there are no more
- * tracked users for it.
- */
- void (*disable)(struct drm_i915_private *dev_priv,
- struct intel_shared_dpll *pll);
-
- /**
- * @get_hw_state:
- *
- * Hook for reading the values currently programmed to the DPLL
- * registers. This is used for initial hw state readout and state
- * verification after a mode set.
- */
- bool (*get_hw_state)(struct drm_i915_private *dev_priv,
- struct intel_shared_dpll *pll,
- struct intel_dpll_hw_state *hw_state);
-
- /**
- * @get_freq:
- *
- * Hook for calculating the pll's output frequency based on its
- * passed in state.
- */
- int (*get_freq)(struct drm_i915_private *i915,
- const struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *pll_state);
-};
-
-/**
* struct dpll_info - display PLL platform specific info
*/
struct dpll_info {
/* FIXME: abstract this better */
if (pipe_config->splitter.enable)
- pipe_config->dp_m2_n2.gmch_m *= pipe_config->splitter.link_count;
+ pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
+}
+
+static void
+intel_drrs_set_refresh_rate_pipeconf(const struct intel_crtc_state *crtc_state,
+ enum drrs_refresh_rate_type refresh_type)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 val, bit;
+
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+ bit = PIPECONF_EDP_RR_MODE_SWITCH_VLV;
+ else
+ bit = PIPECONF_EDP_RR_MODE_SWITCH;
+
+ val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
+
+ if (refresh_type == DRRS_LOW_RR)
+ val |= bit;
+ else
+ val &= ~bit;
+
+ intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
+}
+
+static void
+intel_drrs_set_refresh_rate_m_n(const struct intel_crtc_state *crtc_state,
+ enum drrs_refresh_rate_type refresh_type)
+{
+ intel_dp_set_m_n(crtc_state,
+ refresh_type == DRRS_LOW_RR ? M2_N2 : M1_N1);
}
static void intel_drrs_set_state(struct drm_i915_private *dev_priv,
return;
}
- if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
- switch (refresh_type) {
- case DRRS_HIGH_RR:
- intel_dp_set_m_n(crtc_state, M1_N1);
- break;
- case DRRS_LOW_RR:
- intel_dp_set_m_n(crtc_state, M2_N2);
- break;
- case DRRS_MAX_RR:
- default:
- drm_err(&dev_priv->drm,
- "Unsupported refreshrate type\n");
- }
- } else if (DISPLAY_VER(dev_priv) > 6) {
- i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
- u32 val;
-
- val = intel_de_read(dev_priv, reg);
- if (refresh_type == DRRS_LOW_RR) {
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
- else
- val |= PIPECONF_EDP_RR_MODE_SWITCH;
- } else {
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
- else
- val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
- }
- intel_de_write(dev_priv, reg, val);
- }
+ if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv))
+ intel_drrs_set_refresh_rate_m_n(crtc_state, refresh_type);
+ else if (DISPLAY_VER(dev_priv) > 6)
+ intel_drrs_set_refresh_rate_pipeconf(crtc_state, refresh_type);
dev_priv->drrs.refresh_rate_type = refresh_type;
const u16 slave_addr)
{
struct drm_device *drm_dev = intel_dsi->base.base.dev;
- struct device *dev = drm_dev->dev;
- struct acpi_device *acpi_dev;
- struct list_head resource_list;
- struct i2c_adapter_lookup lookup;
-
- acpi_dev = ACPI_COMPANION(dev);
- if (acpi_dev) {
- memset(&lookup, 0, sizeof(lookup));
- lookup.slave_addr = slave_addr;
- lookup.intel_dsi = intel_dsi;
- lookup.dev_handle = acpi_device_handle(acpi_dev);
-
- INIT_LIST_HEAD(&resource_list);
- acpi_dev_get_resources(acpi_dev, &resource_list,
- i2c_adapter_lookup,
- &lookup);
- acpi_dev_free_resource_list(&resource_list);
- }
+ struct acpi_device *adev = ACPI_COMPANION(drm_dev->dev);
+ struct i2c_adapter_lookup lookup = {
+ .slave_addr = slave_addr,
+ .intel_dsi = intel_dsi,
+ .dev_handle = acpi_device_handle(adev),
+ };
+ LIST_HEAD(resource_list);
+
+ acpi_dev_get_resources(adev, &resource_list, i2c_adapter_lookup, &lookup);
+ acpi_dev_free_resource_list(&resource_list);
}
#else
static inline void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi,
#include "intel_fbc.h"
#include "intel_frontbuffer.h"
+#define for_each_fbc_id(__dev_priv, __fbc_id) \
+ for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++) \
+ for_each_if(INTEL_INFO(__dev_priv)->display.fbc_mask & BIT(__fbc_id))
+
+#define for_each_intel_fbc(__dev_priv, __fbc, __fbc_id) \
+ for_each_fbc_id((__dev_priv), (__fbc_id)) \
+ for_each_if((__fbc) = (__dev_priv)->fbc[(__fbc_id)])
+
struct intel_fbc_funcs {
void (*activate)(struct intel_fbc *fbc);
void (*deactivate)(struct intel_fbc *fbc);
struct drm_mm_node compressed_fb;
struct drm_mm_node compressed_llb;
+ enum intel_fbc_id id;
+
u8 limit;
bool false_color;
struct intel_fbc_state *fbc_state = &fbc->state;
struct drm_i915_private *i915 = fbc->i915;
- intel_de_write(i915, ILK_DPFC_FENCE_YOFF,
+ intel_de_write(i915, ILK_DPFC_FENCE_YOFF(fbc->id),
fbc_state->fence_y_offset);
- intel_de_write(i915, ILK_DPFC_CONTROL,
+ intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
}
u32 dpfc_ctl;
/* Disable compression */
- dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL);
+ dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL(fbc->id));
if (dpfc_ctl & DPFC_CTL_EN) {
dpfc_ctl &= ~DPFC_CTL_EN;
- intel_de_write(i915, ILK_DPFC_CONTROL, dpfc_ctl);
+ intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
}
}
static bool ilk_fbc_is_active(struct intel_fbc *fbc)
{
- return intel_de_read(fbc->i915, ILK_DPFC_CONTROL) & DPFC_CTL_EN;
+ return intel_de_read(fbc->i915, ILK_DPFC_CONTROL(fbc->id)) & DPFC_CTL_EN;
}
static bool ilk_fbc_is_compressing(struct intel_fbc *fbc)
{
- return intel_de_read(fbc->i915, ILK_DPFC_STATUS) & DPFC_COMP_SEG_MASK;
+ return intel_de_read(fbc->i915, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK;
}
static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
{
struct drm_i915_private *i915 = fbc->i915;
- intel_de_write(i915, ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
+ intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id), fbc->compressed_fb.start);
}
static const struct intel_fbc_funcs ilk_fbc_funcs = {
{
struct drm_i915_private *i915 = fbc->i915;
- intel_de_write(i915, MSG_FBC_REND_STATE, FBC_REND_NUKE);
- intel_de_posting_read(i915, MSG_FBC_REND_STATE);
+ intel_de_write(i915, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE);
+ intel_de_posting_read(i915, MSG_FBC_REND_STATE(fbc->id));
}
static const struct intel_fbc_funcs snb_fbc_funcs = {
val |= FBC_STRIDE_OVERRIDE |
FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit);
- intel_de_write(i915, GLK_FBC_STRIDE, val);
+ intel_de_write(i915, GLK_FBC_STRIDE(fbc->id), val);
}
static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc)
if (i915->ggtt.num_fences)
snb_fbc_program_fence(fbc);
- intel_de_write(i915, ILK_DPFC_CONTROL,
+ intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
DPFC_CTL_EN | ivb_dpfc_ctl(fbc));
}
static bool ivb_fbc_is_compressing(struct intel_fbc *fbc)
{
- return intel_de_read(fbc->i915, ILK_DPFC_STATUS2) & DPFC_COMP_SEG_MASK_IVB;
+ return intel_de_read(fbc->i915, ILK_DPFC_STATUS2(fbc->id)) & DPFC_COMP_SEG_MASK_IVB;
}
static void ivb_fbc_set_false_color(struct intel_fbc *fbc,
bool enable)
{
- intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL,
+ intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL(fbc->id),
DPFC_CTL_FALSE_COLOR, enable ? DPFC_CTL_FALSE_COLOR : 0);
}
void intel_fbc_cleanup(struct drm_i915_private *i915)
{
- struct intel_fbc *fbc = i915->fbc;
-
- if (!fbc)
- return;
+ struct intel_fbc *fbc;
+ enum intel_fbc_id fbc_id;
- mutex_lock(&fbc->lock);
- __intel_fbc_cleanup_cfb(fbc);
- mutex_unlock(&fbc->lock);
+ for_each_intel_fbc(i915, fbc, fbc_id) {
+ mutex_lock(&fbc->lock);
+ __intel_fbc_cleanup_cfb(fbc);
+ mutex_unlock(&fbc->lock);
- kfree(fbc);
+ kfree(fbc);
+ }
}
static bool stride_is_valid(const struct intel_plane_state *plane_state)
return fbc->possible_framebuffer_bits;
}
-void intel_fbc_invalidate(struct drm_i915_private *i915,
- unsigned int frontbuffer_bits,
- enum fb_op_origin origin)
+static void __intel_fbc_invalidate(struct intel_fbc *fbc,
+ unsigned int frontbuffer_bits,
+ enum fb_op_origin origin)
{
- struct intel_fbc *fbc = i915->fbc;
-
- if (!fbc)
- return;
-
if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE)
return;
mutex_unlock(&fbc->lock);
}
-void intel_fbc_flush(struct drm_i915_private *i915,
- unsigned int frontbuffer_bits, enum fb_op_origin origin)
+void intel_fbc_invalidate(struct drm_i915_private *i915,
+ unsigned int frontbuffer_bits,
+ enum fb_op_origin origin)
{
- struct intel_fbc *fbc = i915->fbc;
+ struct intel_fbc *fbc;
+ enum intel_fbc_id fbc_id;
- if (!fbc)
- return;
+ for_each_intel_fbc(i915, fbc, fbc_id)
+ __intel_fbc_invalidate(fbc, frontbuffer_bits, origin);
+
+}
+static void __intel_fbc_flush(struct intel_fbc *fbc,
+ unsigned int frontbuffer_bits,
+ enum fb_op_origin origin)
+{
mutex_lock(&fbc->lock);
fbc->busy_bits &= ~frontbuffer_bits;
mutex_unlock(&fbc->lock);
}
+void intel_fbc_flush(struct drm_i915_private *i915,
+ unsigned int frontbuffer_bits,
+ enum fb_op_origin origin)
+{
+ struct intel_fbc *fbc;
+ enum intel_fbc_id fbc_id;
+
+ for_each_intel_fbc(i915, fbc, fbc_id)
+ __intel_fbc_flush(fbc, frontbuffer_bits, origin);
+}
+
int intel_fbc_atomic_check(struct intel_atomic_state *state)
{
struct intel_plane_state *plane_state;
*/
void intel_fbc_global_disable(struct drm_i915_private *i915)
{
- struct intel_fbc *fbc = i915->fbc;
-
- if (!fbc)
- return;
+ struct intel_fbc *fbc;
+ enum intel_fbc_id fbc_id;
- mutex_lock(&fbc->lock);
- if (fbc->state.plane)
- __intel_fbc_disable(fbc);
- mutex_unlock(&fbc->lock);
+ for_each_intel_fbc(i915, fbc, fbc_id) {
+ mutex_lock(&fbc->lock);
+ if (fbc->state.plane)
+ __intel_fbc_disable(fbc);
+ mutex_unlock(&fbc->lock);
+ }
}
static void intel_fbc_underrun_work_fn(struct work_struct *work)
mutex_unlock(&fbc->lock);
}
-/*
- * intel_fbc_reset_underrun - reset FBC fifo underrun status.
- * @i915: the i915 device
- *
- * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
- * want to re-enable FBC after an underrun to increase test coverage.
- */
-void intel_fbc_reset_underrun(struct drm_i915_private *i915)
+static void __intel_fbc_reset_underrun(struct intel_fbc *fbc)
{
- struct intel_fbc *fbc = i915->fbc;
-
- if (!fbc)
- return;
+ struct drm_i915_private *i915 = fbc->i915;
cancel_work_sync(&fbc->underrun_work);
mutex_unlock(&fbc->lock);
}
+/*
+ * intel_fbc_reset_underrun - reset FBC fifo underrun status.
+ * @i915: the i915 device
+ *
+ * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
+ * want to re-enable FBC after an underrun to increase test coverage.
+ */
+void intel_fbc_reset_underrun(struct drm_i915_private *i915)
+{
+ struct intel_fbc *fbc;
+ enum intel_fbc_id fbc_id;
+
+ for_each_intel_fbc(i915, fbc, fbc_id)
+ __intel_fbc_reset_underrun(fbc);
+}
+
+static void __intel_fbc_handle_fifo_underrun_irq(struct intel_fbc *fbc)
+{
+ /*
+ * There's no guarantee that underrun_detected won't be set to true
+ * right after this check and before the work is scheduled, but that's
+ * not a problem since we'll check it again under the work function
+ * while FBC is locked. This check here is just to prevent us from
+ * unnecessarily scheduling the work, and it relies on the fact that we
+ * never switch underrun_detect back to false after it's true.
+ */
+ if (READ_ONCE(fbc->underrun_detected))
+ return;
+
+ schedule_work(&fbc->underrun_work);
+}
+
/**
* intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
* @i915: i915 device
*/
void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *i915)
{
- struct intel_fbc *fbc = i915->fbc;
-
- if (!fbc)
- return;
-
- /* There's no guarantee that underrun_detected won't be set to true
- * right after this check and before the work is scheduled, but that's
- * not a problem since we'll check it again under the work function
- * while FBC is locked. This check here is just to prevent us from
- * unnecessarily scheduling the work, and it relies on the fact that we
- * never switch underrun_detect back to false after it's true. */
- if (READ_ONCE(fbc->underrun_detected))
- return;
+ struct intel_fbc *fbc;
+ enum intel_fbc_id fbc_id;
- schedule_work(&fbc->underrun_work);
+ for_each_intel_fbc(i915, fbc, fbc_id)
+ __intel_fbc_handle_fifo_underrun_irq(fbc);
}
/*
fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
}
-static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915)
+static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915,
+ enum intel_fbc_id fbc_id)
{
struct intel_fbc *fbc;
if (!fbc)
return NULL;
+ fbc->id = fbc_id;
fbc->i915 = i915;
INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
mutex_init(&fbc->lock);
*/
void intel_fbc_init(struct drm_i915_private *i915)
{
- struct intel_fbc *fbc;
+ enum intel_fbc_id fbc_id;
if (!drm_mm_initialized(&i915->mm.stolen))
- mkwrite_device_info(i915)->display.has_fbc = false;
+ mkwrite_device_info(i915)->display.fbc_mask = 0;
if (need_fbc_vtd_wa(i915))
- mkwrite_device_info(i915)->display.has_fbc = false;
+ mkwrite_device_info(i915)->display.fbc_mask = 0;
i915->params.enable_fbc = intel_sanitize_fbc_option(i915);
drm_dbg_kms(&i915->drm, "Sanitized enable_fbc value: %d\n",
i915->params.enable_fbc);
- if (!HAS_FBC(i915))
- return;
+ for_each_fbc_id(i915, fbc_id) {
+ struct intel_fbc *fbc;
- fbc = intel_fbc_create(i915);
- if (!fbc)
- return;
+ fbc = intel_fbc_create(i915, fbc_id);
+ if (!fbc)
+ continue;
- /* We still don't have any sort of hardware state readout for FBC, so
- * deactivate it in case the BIOS activated it to make sure software
- * matches the hardware state. */
- if (intel_fbc_hw_is_active(fbc))
- intel_fbc_hw_deactivate(fbc);
+ /*
+ * We still don't have any sort of hardware state readout
+ * for FBC, so deactivate it in case the BIOS activated it
+ * to make sure software matches the hardware state.
+ */
+ if (intel_fbc_hw_is_active(fbc))
+ intel_fbc_hw_deactivate(fbc);
- i915->fbc = fbc;
+ i915->fbc[fbc->id] = fbc;
+ }
}
static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
intel_fbc_debugfs_false_color_set,
"%llu\n");
-static void intel_fbc_debugfs_add(struct intel_fbc *fbc)
+static void intel_fbc_debugfs_add(struct intel_fbc *fbc,
+ struct dentry *parent)
{
- struct drm_i915_private *i915 = fbc->i915;
- struct drm_minor *minor = i915->drm.primary;
-
- debugfs_create_file("i915_fbc_status", 0444,
- minor->debugfs_root, fbc,
- &intel_fbc_debugfs_status_fops);
+ debugfs_create_file("i915_fbc_status", 0444, parent,
+ fbc, &intel_fbc_debugfs_status_fops);
if (fbc->funcs->set_false_color)
- debugfs_create_file("i915_fbc_false_color", 0644,
- minor->debugfs_root, fbc,
- &intel_fbc_debugfs_false_color_fops);
+ debugfs_create_file("i915_fbc_false_color", 0644, parent,
+ fbc, &intel_fbc_debugfs_false_color_fops);
}
+void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc)
+{
+ struct intel_plane *plane = to_intel_plane(crtc->base.primary);
+
+ if (plane->fbc)
+ intel_fbc_debugfs_add(plane->fbc, crtc->base.debugfs_entry);
+}
+
+/* FIXME: remove this once igt is on board with per-crtc stuff */
void intel_fbc_debugfs_register(struct drm_i915_private *i915)
{
- struct intel_fbc *fbc = i915->fbc;
+ struct drm_minor *minor = i915->drm.primary;
+ struct intel_fbc *fbc;
+ fbc = i915->fbc[INTEL_FBC_A];
if (fbc)
- intel_fbc_debugfs_add(fbc);
+ intel_fbc_debugfs_add(fbc, minor->debugfs_root);
}
struct intel_plane;
struct intel_plane_state;
+enum intel_fbc_id {
+ INTEL_FBC_A,
+
+ I915_MAX_FBCS,
+};
+
int intel_fbc_atomic_check(struct intel_atomic_state *state);
bool intel_fbc_pre_update(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane);
void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *i915);
void intel_fbc_reset_underrun(struct drm_i915_private *i915);
+void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc);
void intel_fbc_debugfs_register(struct drm_i915_private *i915);
#endif /* __INTEL_FBC_H__ */
return &dev_priv->gmbus[pin].adapter;
}
-void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
-{
- struct intel_gmbus *bus = to_intel_gmbus(adapter);
-
- bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
-}
-
void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
{
struct intel_gmbus *bus = to_intel_gmbus(adapter);
struct i2c_adapter *
intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
-void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter);
void intel_gmbus_reset(struct drm_i915_private *dev_priv);
* Mailbox interface.
*/
if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
- ret = sandybridge_pcode_write(dev_priv,
- SKL_PCODE_LOAD_HDCP_KEYS, 1);
+ ret = snb_pcode_write(dev_priv, SKL_PCODE_LOAD_HDCP_KEYS, 1);
if (ret) {
drm_err(&dev_priv->drm,
"Failed to initiate HDCP key load (%d)\n",
return intel_mode_valid_max_plane_size(dev_priv, mode, false);
}
-bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
- int bpc, bool has_hdmi_sink, bool ycbcr420_output)
+bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
+ int bpc, bool has_hdmi_sink, bool ycbcr420_output)
{
struct drm_atomic_state *state = crtc_state->uapi.state;
struct drm_connector_state *connector_state;
struct drm_connector *connector;
int i;
- if (crtc_state->pipe_bpp < bpc * 3)
- return false;
-
for_each_new_connector_in_state(state, connector, connector_state, i) {
if (connector_state->crtc != crtc_state->uapi.crtc)
continue;
return true;
}
-static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
- int bpc)
+static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc)
{
struct drm_i915_private *dev_priv =
to_i915(crtc_state->uapi.crtc->dev);
* HDMI deep color affects the clocks, so it's only possible
* when not cloning with other encoder types.
*/
- if (crtc_state->output_types != BIT(INTEL_OUTPUT_HDMI))
+ if (bpc > 8 && crtc_state->output_types != BIT(INTEL_OUTPUT_HDMI))
return false;
/* Display Wa_1405510057:icl,ehl */
adjusted_mode->crtc_hblank_start) % 8 == 2)
return false;
- return intel_hdmi_deep_color_possible(crtc_state, bpc,
- crtc_state->has_hdmi_sink,
- intel_hdmi_is_ycbcr420(crtc_state));
+ return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink,
+ intel_hdmi_is_ycbcr420(crtc_state));
}
static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
- int clock)
+ int clock, bool respect_downstream_limits)
{
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
bool ycbcr420_output = intel_hdmi_is_ycbcr420(crtc_state);
int bpc;
- for (bpc = 12; bpc >= 10; bpc -= 2) {
- if (hdmi_deep_color_possible(crtc_state, bpc) &&
- hdmi_port_clock_valid(intel_hdmi,
- intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output),
- true, crtc_state->has_hdmi_sink) == MODE_OK)
+ /*
+ * pipe_bpp could already be below 8bpc due to FDI
+ * bandwidth constraints. HDMI minimum is 8bpc however.
+ */
+ bpc = max(crtc_state->pipe_bpp / 3, 8);
+
+ /*
+ * We will never exceed downstream TMDS clock limits while
+ * attempting deep color. If the user insists on forcing an
+ * out of spec mode they will have to be satisfied with 8bpc.
+ */
+ if (!respect_downstream_limits)
+ bpc = 8;
+
+ for (; bpc >= 8; bpc -= 2) {
+ int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
+
+ if (hdmi_bpc_possible(crtc_state, bpc) &&
+ hdmi_port_clock_valid(intel_hdmi, tmds_clock,
+ respect_downstream_limits,
+ crtc_state->has_hdmi_sink) == MODE_OK)
return bpc;
}
- return 8;
+ return -EINVAL;
}
static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc_state *crtc_state,
+ bool respect_downstream_limits)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
int bpc, clock = adjusted_mode->crtc_clock;
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
clock *= 2;
- bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock);
+ bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock,
+ respect_downstream_limits);
+ if (bpc < 0)
+ return bpc;
- crtc_state->port_clock = intel_hdmi_tmds_clock(clock, bpc,
- intel_hdmi_is_ycbcr420(crtc_state));
+ crtc_state->port_clock =
+ intel_hdmi_tmds_clock(clock, bpc, intel_hdmi_is_ycbcr420(crtc_state));
/*
* pipe_bpp could already be below 8bpc due to
* FDI bandwidth constraints. We shouldn't bump it
- * back up to 8bpc in that case.
+ * back up to the HDMI minimum 8bpc in that case.
*/
- if (crtc_state->pipe_bpp > bpc * 3)
- crtc_state->pipe_bpp = bpc * 3;
+ crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3);
drm_dbg_kms(&i915->drm,
"picking %d bpc for HDMI output (pipe bpp: %d)\n",
bpc, crtc_state->pipe_bpp);
- if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock,
- false, crtc_state->has_hdmi_sink) != MODE_OK) {
- drm_dbg_kms(&i915->drm,
- "unsupported HDMI clock (%d kHz), rejecting mode\n",
- crtc_state->port_clock);
- return -EINVAL;
- }
-
return 0;
}
static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
+ const struct drm_connector_state *conn_state,
+ bool respect_downstream_limits)
{
struct intel_connector *connector = to_intel_connector(conn_state->connector);
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
}
- ret = intel_hdmi_compute_clock(encoder, crtc_state);
+ ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
if (ret) {
if (intel_hdmi_is_ycbcr420(crtc_state) ||
!connector->base.ycbcr_420_allowed ||
return ret;
crtc_state->output_format = intel_hdmi_output_format(connector, true);
- ret = intel_hdmi_compute_clock(encoder, crtc_state);
+ ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
}
return ret;
pipe_config->has_audio =
intel_hdmi_has_audio(encoder, pipe_config, conn_state);
- ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state);
+ /*
+ * Try to respect downstream TMDS clock limits first, if
+ * that fails assume the user might know something we don't.
+ */
+ ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true);
if (ret)
+ ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false);
+ if (ret) {
+ drm_dbg_kms(&dev_priv->drm,
+ "unsupported HDMI clock (%d kHz), rejecting mode\n",
+ pipe_config->hw.adjusted_mode.crtc_clock);
return ret;
+ }
if (intel_hdmi_is_ycbcr420(pipe_config)) {
ret = intel_panel_fitting(pipe_config, conn_state);
"DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
drm_dp_get_dual_mode_type_name(type),
hdmi->dp_dual_mode.max_tmds_clock);
+
+ /* Older VBTs are often buggy and can't be trusted :( Play it safe. */
+ if ((DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) &&
+ !intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n");
+ hdmi->dp_dual_mode.max_tmds_clock = 0;
+ }
}
static bool
union hdmi_infoframe *frame);
bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
-bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, int bpc,
- bool has_hdmi_sink, bool ycbcr420_output);
+bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
+ int bpc, bool has_hdmi_sink, bool ycbcr420_output);
int intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width,
int num_slices, int output_format, bool hdmi_all_bpp,
int hdmi_max_chunk_bytes);
ret = true;
if (ret) {
- DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s (epoch counter %llu->%llu)\n",
- connector->base.base.id,
- connector->base.name,
- drm_get_connector_status_name(old_status),
- drm_get_connector_status_name(connector->base.status),
- old_epoch_counter,
- connector->base.epoch_counter);
+ drm_dbg_kms(dev, "[CONNECTOR:%d:%s] status updated from %s to %s (epoch counter %llu->%llu)\n",
+ connector->base.base.id,
+ connector->base.name,
+ drm_get_connector_status_name(old_status),
+ drm_get_connector_status_name(connector->base.status),
+ old_epoch_counter,
+ connector->base.epoch_counter);
return INTEL_HOTPLUG_CHANGED;
}
return INTEL_HOTPLUG_UNCHANGED;
static bool lspcon_detect_vendor(struct intel_lspcon *lspcon)
{
struct intel_dp *dp = lspcon_to_intel_dp(lspcon);
+ struct drm_i915_private *i915 = dp_to_i915(dp);
struct drm_dp_dpcd_ident *ident;
u32 vendor_oui;
if (drm_dp_read_desc(&dp->aux, &dp->desc, drm_dp_is_branch(dp->dpcd))) {
- DRM_ERROR("Can't read description\n");
+ drm_err(&i915->drm, "Can't read description\n");
return false;
}
switch (vendor_oui) {
case LSPCON_VENDOR_MCA_OUI:
lspcon->vendor = LSPCON_VENDOR_MCA;
- DRM_DEBUG_KMS("Vendor: Mega Chips\n");
+ drm_dbg_kms(&i915->drm, "Vendor: Mega Chips\n");
break;
case LSPCON_VENDOR_PARADE_OUI:
lspcon->vendor = LSPCON_VENDOR_PARADE;
- DRM_DEBUG_KMS("Vendor: Parade Tech\n");
+ drm_dbg_kms(&i915->drm, "Vendor: Parade Tech\n");
break;
default:
- DRM_ERROR("Invalid/Unknown vendor OUI\n");
+ drm_err(&i915->drm, "Invalid/Unknown vendor OUI\n");
return false;
}
void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon)
{
- struct intel_digital_port *dig_port =
- container_of(lspcon, struct intel_digital_port, lspcon);
- struct drm_device *dev = dig_port->base.base.dev;
- struct intel_dp *dp = lspcon_to_intel_dp(lspcon);
+ struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u8 hdr_caps;
int ret;
- ret = drm_dp_dpcd_read(&dp->aux, get_hdr_status_reg(lspcon),
+ ret = drm_dp_dpcd_read(&intel_dp->aux, get_hdr_status_reg(lspcon),
&hdr_caps, 1);
if (ret < 0) {
- drm_dbg_kms(dev, "HDR capability detection failed\n");
+ drm_dbg_kms(&i915->drm, "HDR capability detection failed\n");
lspcon->hdr_supported = false;
} else if (hdr_caps & 0x1) {
- drm_dbg_kms(dev, "LSPCON capable of HDR\n");
+ drm_dbg_kms(&i915->drm, "LSPCON capable of HDR\n");
lspcon->hdr_supported = true;
}
}
static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon *lspcon)
{
struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
enum drm_lspcon_mode current_mode;
struct i2c_adapter *adapter = &intel_dp->aux.ddc;
if (drm_lspcon_get_mode(intel_dp->aux.drm_dev, adapter, ¤t_mode)) {
- DRM_DEBUG_KMS("Error reading LSPCON mode\n");
+ drm_dbg_kms(&i915->drm, "Error reading LSPCON mode\n");
return DRM_LSPCON_MODE_INVALID;
}
return current_mode;
static enum drm_lspcon_mode lspcon_wait_mode(struct intel_lspcon *lspcon,
enum drm_lspcon_mode mode)
{
+ struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
enum drm_lspcon_mode current_mode;
current_mode = lspcon_get_current_mode(lspcon);
if (current_mode == mode)
goto out;
- DRM_DEBUG_KMS("Waiting for LSPCON mode %s to settle\n",
- lspcon_mode_name(mode));
+ drm_dbg_kms(&i915->drm, "Waiting for LSPCON mode %s to settle\n",
+ lspcon_mode_name(mode));
wait_for((current_mode = lspcon_get_current_mode(lspcon)) == mode, 400);
if (current_mode != mode)
- DRM_ERROR("LSPCON mode hasn't settled\n");
+ drm_err(&i915->drm, "LSPCON mode hasn't settled\n");
out:
- DRM_DEBUG_KMS("Current LSPCON mode %s\n",
- lspcon_mode_name(current_mode));
+ drm_dbg_kms(&i915->drm, "Current LSPCON mode %s\n",
+ lspcon_mode_name(current_mode));
return current_mode;
}
enum drm_lspcon_mode mode)
{
struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int err;
enum drm_lspcon_mode current_mode;
struct i2c_adapter *adapter = &intel_dp->aux.ddc;
err = drm_lspcon_get_mode(intel_dp->aux.drm_dev, adapter, ¤t_mode);
if (err) {
- DRM_ERROR("Error reading LSPCON mode\n");
+ drm_err(&i915->drm, "Error reading LSPCON mode\n");
return err;
}
if (current_mode == mode) {
- DRM_DEBUG_KMS("Current mode = desired LSPCON mode\n");
+ drm_dbg_kms(&i915->drm, "Current mode = desired LSPCON mode\n");
return 0;
}
err = drm_lspcon_set_mode(intel_dp->aux.drm_dev, adapter, mode);
if (err < 0) {
- DRM_ERROR("LSPCON mode change failed\n");
+ drm_err(&i915->drm, "LSPCON mode change failed\n");
return err;
}
lspcon->mode = mode;
- DRM_DEBUG_KMS("LSPCON mode changed done\n");
+ drm_dbg_kms(&i915->drm, "LSPCON mode changed done\n");
return 0;
}
static bool lspcon_wake_native_aux_ch(struct intel_lspcon *lspcon)
{
+ struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u8 rev;
if (drm_dp_dpcd_readb(&lspcon_to_intel_dp(lspcon)->aux, DP_DPCD_REV,
&rev) != 1) {
- DRM_DEBUG_KMS("Native AUX CH down\n");
+ drm_dbg_kms(&i915->drm, "Native AUX CH down\n");
return false;
}
- DRM_DEBUG_KMS("Native AUX CH up, DPCD version: %d.%d\n",
- rev >> 4, rev & 0xf);
+ drm_dbg_kms(&i915->drm, "Native AUX CH up, DPCD version: %d.%d\n",
+ rev >> 4, rev & 0xf);
return true;
}
int retry;
enum drm_dp_dual_mode_type adaptor_type;
struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct i2c_adapter *adapter = &intel_dp->aux.ddc;
enum drm_lspcon_mode expected_mode;
}
if (adaptor_type != DRM_DP_DUAL_MODE_LSPCON) {
- DRM_DEBUG_KMS("No LSPCON detected, found %s\n",
- drm_dp_get_dual_mode_type_name(adaptor_type));
+ drm_dbg_kms(&i915->drm, "No LSPCON detected, found %s\n",
+ drm_dp_get_dual_mode_type_name(adaptor_type));
return false;
}
/* Yay ... got a LSPCON device */
- DRM_DEBUG_KMS("LSPCON detected\n");
+ drm_dbg_kms(&i915->drm, "LSPCON detected\n");
lspcon->mode = lspcon_wait_mode(lspcon, expected_mode);
/*
*/
if (lspcon->mode != DRM_LSPCON_MODE_PCON) {
if (lspcon_change_mode(lspcon, DRM_LSPCON_MODE_PCON) < 0) {
- DRM_ERROR("LSPCON mode change to PCON failed\n");
+ drm_err(&i915->drm, "LSPCON mode change to PCON failed\n");
return false;
}
}
static void lspcon_resume_in_pcon_wa(struct intel_lspcon *lspcon)
{
struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
unsigned long start = jiffies;
while (1) {
if (intel_digital_port_connected(&dig_port->base)) {
- DRM_DEBUG_KMS("LSPCON recovering in PCON mode after %u ms\n",
- jiffies_to_msecs(jiffies - start));
+ drm_dbg_kms(&i915->drm, "LSPCON recovering in PCON mode after %u ms\n",
+ jiffies_to_msecs(jiffies - start));
return;
}
usleep_range(10000, 15000);
}
- DRM_DEBUG_KMS("LSPCON DP descriptor mismatch after resume\n");
+ drm_dbg_kms(&i915->drm, "LSPCON DP descriptor mismatch after resume\n");
}
static bool lspcon_parade_fw_ready(struct drm_dp_aux *aux)
ret = drm_dp_dpcd_read(aux, LSPCON_PARADE_AVI_IF_CTRL,
&avi_if_ctrl, 1);
if (ret < 0) {
- DRM_ERROR("Failed to read AVI IF control\n");
+ drm_err(aux->drm_dev, "Failed to read AVI IF control\n");
return false;
}
return true;
}
- DRM_ERROR("Parade FW not ready to accept AVI IF\n");
+ drm_err(aux->drm_dev, "Parade FW not ready to accept AVI IF\n");
return false;
}
while (block_count < 4) {
if (!lspcon_parade_fw_ready(aux)) {
- DRM_DEBUG_KMS("LSPCON FW not ready, block %d\n",
- block_count);
+ drm_dbg_kms(aux->drm_dev, "LSPCON FW not ready, block %d\n",
+ block_count);
return false;
}
data = avi_buf + block_count * 8;
ret = drm_dp_dpcd_write(aux, reg, data, 8);
if (ret < 0) {
- DRM_ERROR("Failed to write AVI IF block %d\n",
- block_count);
+ drm_err(aux->drm_dev, "Failed to write AVI IF block %d\n",
+ block_count);
return false;
}
avi_if_ctrl = LSPCON_PARADE_AVI_IF_KICKOFF | block_count;
ret = drm_dp_dpcd_write(aux, reg, &avi_if_ctrl, 1);
if (ret < 0) {
- DRM_ERROR("Failed to update (0x%x), block %d\n",
- reg, block_count);
+ drm_err(aux->drm_dev, "Failed to update (0x%x), block %d\n",
+ reg, block_count);
return false;
}
block_count++;
}
- DRM_DEBUG_KMS("Wrote AVI IF blocks successfully\n");
+ drm_dbg_kms(aux->drm_dev, "Wrote AVI IF blocks successfully\n");
return true;
}
*/
if (len > LSPCON_PARADE_AVI_IF_DATA_SIZE - 1) {
- DRM_ERROR("Invalid length of infoframes\n");
+ drm_err(aux->drm_dev, "Invalid length of infoframes\n");
return false;
}
memcpy(&avi_if[1], frame, len);
if (!_lspcon_parade_write_infoframe_blocks(aux, avi_if)) {
- DRM_DEBUG_KMS("Failed to write infoframe blocks\n");
+ drm_dbg_kms(aux->drm_dev, "Failed to write infoframe blocks\n");
return false;
}
mdelay(50);
continue;
} else {
- DRM_ERROR("DPCD write failed at:0x%x\n", reg);
+ drm_err(aux->drm_dev, "DPCD write failed at:0x%x\n", reg);
return false;
}
}
reg = LSPCON_MCA_AVI_IF_CTRL;
ret = drm_dp_dpcd_read(aux, reg, &val, 1);
if (ret < 0) {
- DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
+ drm_err(aux->drm_dev, "DPCD read failed, address 0x%x\n", reg);
return false;
}
ret = drm_dp_dpcd_write(aux, reg, &val, 1);
if (ret < 0) {
- DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
+ drm_err(aux->drm_dev, "DPCD read failed, address 0x%x\n", reg);
return false;
}
val = 0;
ret = drm_dp_dpcd_read(aux, reg, &val, 1);
if (ret < 0) {
- DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
+ drm_err(aux->drm_dev, "DPCD read failed, address 0x%x\n", reg);
return false;
}
if (val == LSPCON_MCA_AVI_IF_HANDLED)
- DRM_DEBUG_KMS("AVI IF handled by FW\n");
+ drm_dbg_kms(aux->drm_dev, "AVI IF handled by FW\n");
return true;
}
{
bool ret = true;
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
switch (type) {
frame, len);
break;
case HDMI_PACKET_TYPE_GAMUT_METADATA:
- drm_dbg_kms(encoder->base.dev, "Update HDR metadata for lspcon\n");
+ drm_dbg_kms(&i915->drm, "Update HDR metadata for lspcon\n");
/* It uses the legacy hsw implementation for the same */
hsw_write_infoframe(encoder, crtc_state, type, frame, len);
break;
}
if (!ret) {
- DRM_ERROR("Failed to write infoframes\n");
+ drm_err(&i915->drm, "Failed to write infoframes\n");
return;
}
}
u8 buf[VIDEO_DIP_DATA_SIZE];
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
struct intel_lspcon *lspcon = &dig_port->lspcon;
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
if (!lspcon->active) {
- DRM_ERROR("Writing infoframes while LSPCON disabled ?\n");
+ drm_err(&i915->drm, "Writing infoframes while LSPCON disabled ?\n");
return;
}
conn_state->connector,
adjusted_mode);
if (ret < 0) {
- DRM_ERROR("couldn't fill AVI infoframe\n");
+ drm_err(&i915->drm, "couldn't fill AVI infoframe\n");
return;
}
ret = hdmi_infoframe_pack(&frame, buf, sizeof(buf));
if (ret < 0) {
- DRM_ERROR("Failed to pack AVI IF\n");
+ drm_err(&i915->drm, "Failed to pack AVI IF\n");
return;
}
ret = drm_dp_dpcd_read(aux, reg, &val, 1);
if (ret < 0) {
- DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
+ drm_err(aux->drm_dev, "DPCD read failed, address 0x%x\n", reg);
return false;
}
ret = drm_dp_dpcd_read(aux, reg, &val, 1);
if (ret < 0) {
- DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
+ drm_err(aux->drm_dev, "DPCD read failed, address 0x%x\n", reg);
return false;
}
bool lspcon_init(struct intel_digital_port *dig_port)
{
- struct intel_dp *dp = &dig_port->dp;
+ struct intel_dp *intel_dp = &dig_port->dp;
struct intel_lspcon *lspcon = &dig_port->lspcon;
- struct drm_connector *connector = &dp->attached_connector->base;
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ struct drm_connector *connector = &intel_dp->attached_connector->base;
lspcon->active = false;
lspcon->mode = DRM_LSPCON_MODE_INVALID;
if (!lspcon_probe(lspcon)) {
- DRM_ERROR("Failed to probe lspcon\n");
+ drm_err(&i915->drm, "Failed to probe lspcon\n");
return false;
}
- if (drm_dp_read_dpcd_caps(&dp->aux, dp->dpcd) != 0) {
- DRM_ERROR("LSPCON DPCD read failed\n");
+ if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0) {
+ drm_err(&i915->drm, "LSPCON DPCD read failed\n");
return false;
}
if (!lspcon_detect_vendor(lspcon)) {
- DRM_ERROR("LSPCON vendor detection failed\n");
+ drm_err(&i915->drm, "LSPCON vendor detection failed\n");
return false;
}
connector->ycbcr_420_allowed = true;
lspcon->active = true;
- DRM_DEBUG_KMS("Success: LSPCON init\n");
+ drm_dbg_kms(&i915->drm, "Success: LSPCON init\n");
return true;
}
{
struct intel_lspcon *lspcon = &dig_port->lspcon;
struct drm_device *dev = dig_port->base.base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_i915_private *i915 = to_i915(dev);
enum drm_lspcon_mode expected_mode;
- if (!intel_bios_is_lspcon_present(dev_priv, dig_port->base.port))
+ if (!intel_bios_is_lspcon_present(i915, dig_port->base.port))
return;
if (!lspcon->active) {
if (!lspcon_init(dig_port)) {
- DRM_ERROR("LSPCON init failed on port %c\n",
- port_name(dig_port->base.port));
+ drm_err(&i915->drm, "LSPCON init failed on port %c\n",
+ port_name(dig_port->base.port));
return;
}
}
return;
if (lspcon_change_mode(lspcon, DRM_LSPCON_MODE_PCON))
- DRM_ERROR("LSPCON resume failed\n");
+ drm_err(&i915->drm, "LSPCON resume failed\n");
else
- DRM_DEBUG_KMS("LSPCON resume success\n");
+ drm_dbg_kms(&i915->drm, "LSPCON resume success\n");
}
#include "intel_backlight.h"
#include "intel_display_types.h"
#include "intel_opregion.h"
+#include "intel_pci_config.h"
#define OPREGION_HEADER_OFFSET 0
#define OPREGION_ACPI_OFFSET 0x100
#define ASLE_IUER_WINDOWS_BTN (1 << 1)
#define ASLE_IUER_POWER_BTN (1 << 0)
+#define ASLE_PHED_EDID_VALID_MASK 0x3
+
/* Software System Control Interrupt (SWSCI) */
#define SWSCI_SCIC_INDICATOR (1 << 0)
#define SWSCI_SCIC_MAIN_FUNCTION_SHIFT 1
opregion->asle->ardy = ASLE_ARDY_NOT_READY;
}
- if (mboxes & MBOX_ASLE_EXT)
+ if (mboxes & MBOX_ASLE_EXT) {
drm_dbg(&dev_priv->drm, "ASLE extension supported\n");
+ opregion->asle_ext = base + OPREGION_ASLE_EXT_OFFSET;
+ }
if (intel_load_vbt_firmware(dev_priv) == 0)
goto out;
return ret - 1;
}
+/**
+ * intel_opregion_get_edid - Fetch EDID from ACPI OpRegion mailbox #5
+ * @intel_connector: eDP connector
+ *
+ * This reads the ACPI Opregion mailbox #5 to extract the EDID that is passed
+ * to it.
+ *
+ * Returns:
+ * The EDID in the OpRegion, or NULL if there is none or it's invalid.
+ *
+ */
+struct edid *intel_opregion_get_edid(struct intel_connector *intel_connector)
+{
+ struct drm_connector *connector = &intel_connector->base;
+ struct drm_i915_private *i915 = to_i915(connector->dev);
+ struct intel_opregion *opregion = &i915->opregion;
+ const void *in_edid;
+ const struct edid *edid;
+ struct edid *new_edid;
+ int len;
+
+ if (!opregion->asle_ext)
+ return NULL;
+
+ in_edid = opregion->asle_ext->bddc;
+
+ /* Validity corresponds to number of 128-byte blocks */
+ len = (opregion->asle_ext->phed & ASLE_PHED_EDID_VALID_MASK) * 128;
+ if (!len || !memchr_inv(in_edid, 0, len))
+ return NULL;
+
+ edid = in_edid;
+
+ if (len < EDID_LENGTH * (1 + edid->extensions)) {
+ drm_dbg_kms(&i915->drm, "Invalid EDID in ACPI OpRegion (Mailbox #5): too short\n");
+ return NULL;
+ }
+ new_edid = drm_edid_duplicate(edid);
+ if (!new_edid)
+ return NULL;
+ if (!drm_edid_is_valid(new_edid)) {
+ kfree(new_edid);
+ drm_dbg_kms(&i915->drm, "Invalid EDID in ACPI OpRegion (Mailbox #5)\n");
+ return NULL;
+ }
+ return new_edid;
+}
+
void intel_opregion_register(struct drm_i915_private *i915)
{
struct intel_opregion *opregion = &i915->opregion;
opregion->acpi = NULL;
opregion->swsci = NULL;
opregion->asle = NULL;
+ opregion->asle_ext = NULL;
opregion->vbt = NULL;
opregion->lid_state = NULL;
}
#include <linux/pci.h>
struct drm_i915_private;
+struct intel_connector;
struct intel_encoder;
struct opregion_header;
struct opregion_acpi;
struct opregion_swsci;
struct opregion_asle;
+struct opregion_asle_ext;
struct intel_opregion {
struct opregion_header *header;
u32 swsci_gbda_sub_functions;
u32 swsci_sbcb_sub_functions;
struct opregion_asle *asle;
+ struct opregion_asle_ext *asle_ext;
void *rvda;
void *vbt_firmware;
const void *vbt;
int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
pci_power_t state);
int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
+struct edid *intel_opregion_get_edid(struct intel_connector *connector);
#else /* CONFIG_ACPI*/
return -ENODEV;
}
+static inline struct edid *
+intel_opregion_get_edid(struct intel_connector *connector)
+{
+ return NULL;
+}
+
#endif /* CONFIG_ACPI */
#endif
#include "intel_display_types.h"
#include "intel_frontbuffer.h"
#include "intel_overlay.h"
+#include "intel_pci_config.h"
/* Limits for overlay size. According to intel doc, the real limits are:
* Y width: 4095, UV width (planar): 2047, Y height: 2047,
const struct intel_crtc_state *pipe_config =
overlay->crtc->config;
+ if (rec->dst_height == 0 || rec->dst_width == 0)
+ return -EINVAL;
+
if (rec->dst_x < pipe_config->pipe_src_w &&
rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w &&
rec->dst_y < pipe_config->pipe_src_h &&
*/
val &= ~PIPECONF_BPC_MASK;
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
- val |= PIPECONF_8BPC;
+ val |= PIPECONF_BPC_8;
else
val |= pipeconf_val & PIPECONF_BPC_MASK;
}
val &= ~TRANS_INTERLACE_MASK;
- if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
+ if ((pipeconf_val & PIPECONF_INTERLACE_MASK_ILK) == PIPECONF_INTERLACE_IF_ID_ILK) {
if (HAS_PCH_IBX(dev_priv) &&
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
- val |= TRANS_LEGACY_INTERLACED_ILK;
+ val |= TRANS_INTERLACE_LEGACY_VSYNC_IBX;
else
- val |= TRANS_INTERLACED;
+ val |= TRANS_INTERLACE_INTERLACED;
} else {
- val |= TRANS_PROGRESSIVE;
+ val |= TRANS_INTERLACE_PROGRESSIVE;
}
intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
}
}
+void ilk_pch_pre_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+
+ /*
+ * Note: FDI PLL enabling _must_ be done before we enable the
+ * cpu pipes, hence this is separate from all the other fdi/pch
+ * enabling.
+ */
+ ilk_fdi_pll_enable(crtc_state);
+}
+
/*
* Enable PCH resources required for PCH ports:
* - PCH PLLs
temp = intel_de_read(dev_priv, reg);
temp &= ~(TRANS_DP_PORT_SEL_MASK |
- TRANS_DP_SYNC_MASK |
+ TRANS_DP_VSYNC_ACTIVE_HIGH |
+ TRANS_DP_HSYNC_ACTIVE_HIGH |
TRANS_DP_BPC_MASK);
temp |= TRANS_DP_OUTPUT_ENABLE;
temp |= bpc << 9; /* same format but at 11:9 */
val = TRANS_ENABLE;
pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
- if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
- PIPECONF_INTERLACED_ILK)
- val |= TRANS_INTERLACED;
+ if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == PIPECONF_INTERLACE_IF_ID_ILK)
+ val |= TRANS_INTERLACE_INTERLACED;
else
- val |= TRANS_PROGRESSIVE;
+ val |= TRANS_INTERLACE_PROGRESSIVE;
intel_de_write(dev_priv, LPT_TRANSCONF, val);
if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
struct intel_crtc;
struct intel_crtc_state;
+void ilk_pch_pre_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
void ilk_pch_enable(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void ilk_pch_disable(struct intel_atomic_state *state,
}
static void
-intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
+intel_pps_dump_state(struct intel_dp *intel_dp, const char *state_name,
+ const struct edp_power_seq *seq)
{
- DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
- state_name,
- seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+ drm_dbg_kms(&i915->drm, "%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
+ state_name,
+ seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
}
static void
intel_pps_verify_state(struct intel_dp *intel_dp)
{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct edp_power_seq hw;
struct edp_power_seq *sw = &intel_dp->pps.pps_delays;
if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
- DRM_ERROR("PPS state mismatch\n");
- intel_pps_dump_state("sw", sw);
- intel_pps_dump_state("hw", &hw);
+ drm_err(&i915->drm, "PPS state mismatch\n");
+ intel_pps_dump_state(intel_dp, "sw", sw);
+ intel_pps_dump_state(intel_dp, "hw", &hw);
}
}
intel_pps_readout_hw_state(intel_dp, &cur);
- intel_pps_dump_state("cur", &cur);
+ intel_pps_dump_state(intel_dp, "cur", &cur);
vbt = dev_priv->vbt.edp.pps;
/* On Toshiba Satellite P50-C-18C system the VBT T12 delay
* too. */
spec.t11_t12 = (510 + 100) * 10;
- intel_pps_dump_state("vbt", &vbt);
+ intel_pps_dump_state(intel_dp, "vbt", &vbt);
/* Use the max of the register settings and vbt. If both are
* unset, fall back to the spec limits. */
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_snps_phy.h"
+#include "intel_snps_phy_regs.h"
/**
* DOC: Synopsis PHY support
* since it is not handled by the shared DPLL framework as on other platforms.
*/
-void intel_snps_phy_wait_for_calibration(struct drm_i915_private *dev_priv)
+void intel_snps_phy_wait_for_calibration(struct drm_i915_private *i915)
{
enum phy phy;
for_each_phy_masked(phy, ~0) {
- if (!intel_phy_is_snps(dev_priv, phy))
+ if (!intel_phy_is_snps(i915, phy))
continue;
- if (intel_de_wait_for_clear(dev_priv, ICL_PHY_MISC(phy),
+ if (intel_de_wait_for_clear(i915, ICL_PHY_MISC(phy),
DG2_PHY_DP_TX_ACK_MASK, 25))
- DRM_ERROR("SNPS PHY %c failed to calibrate after 25ms.\n",
- phy);
+ drm_err(&i915->drm, "SNPS PHY %c failed to calibrate after 25ms.\n",
+ phy);
}
}
int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
const struct intel_mpllb_state * const *tables;
int i;
* until we have a proper algorithm under a valid
* license.
*/
- DRM_DEBUG_KMS("Can't support HDMI link rate %d\n",
- crtc_state->port_clock);
+ drm_dbg_kms(&i915->drm, "Can't support HDMI link rate %d\n",
+ crtc_state->port_clock);
return -EINVAL;
}
}
* dp_mpllb_state interface signal.
*/
if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_LOCK, 5))
- DRM_ERROR("Port %c PLL not locked\n", phy_name(phy));
+ drm_dbg_kms(&dev_priv->drm, "Port %c PLL not locked\n", phy_name(phy));
/*
* 11. If the frequency will result in a change to the voltage
void intel_mpllb_disable(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
i915_reg_t enable_reg = (phy <= PHY_D ?
DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0));
*/
/* 2. Software programs DPLL_ENABLE [PLL Enable] to "0" */
- intel_uncore_rmw(&dev_priv->uncore, enable_reg, PLL_ENABLE, 0);
+ intel_uncore_rmw(&i915->uncore, enable_reg, PLL_ENABLE, 0);
/*
* 4. Software programs SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "0".
* This will allow the PLL to stop running.
*/
- intel_uncore_rmw(&dev_priv->uncore, SNPS_PHY_MPLLB_DIV(phy),
+ intel_uncore_rmw(&i915->uncore, SNPS_PHY_MPLLB_DIV(phy),
SNPS_PHY_MPLLB_FORCE_EN, 0);
/*
* 5. Software polls DPLL_ENABLE [PLL Lock] for PHY acknowledgment
* (dp_txX_ack) that the new transmitter setting request is completed.
*/
- if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_LOCK, 5))
- DRM_ERROR("Port %c PLL not locked\n", phy_name(phy));
+ if (intel_de_wait_for_clear(i915, enable_reg, PLL_LOCK, 5))
+ drm_err(&i915->drm, "Port %c PLL not locked\n", phy_name(phy));
/*
* 6. If the frequency will result in a change to the voltage
--- /dev/null
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_SNPS_PHY_REGS__
+#define __INTEL_SNPS_PHY_REGS__
+
+#include "i915_reg_defs.h"
+
+#define _SNPS_PHY_A_BASE 0x168000
+#define _SNPS_PHY_B_BASE 0x169000
+#define _SNPS_PHY(phy) _PHY(phy, \
+ _SNPS_PHY_A_BASE, \
+ _SNPS_PHY_B_BASE)
+#define _SNPS2(phy, reg) (_SNPS_PHY(phy) - \
+ _SNPS_PHY_A_BASE + (reg))
+#define _MMIO_SNPS(phy, reg) _MMIO(_SNPS2(phy, reg))
+#define _MMIO_SNPS_LN(ln, phy, reg) _MMIO(_SNPS2(phy, \
+ (reg) + (ln) * 0x10))
+
+#define SNPS_PHY_MPLLB_CP(phy) _MMIO_SNPS(phy, 0x168000)
+#define SNPS_PHY_MPLLB_CP_INT REG_GENMASK(31, 25)
+#define SNPS_PHY_MPLLB_CP_INT_GS REG_GENMASK(23, 17)
+#define SNPS_PHY_MPLLB_CP_PROP REG_GENMASK(15, 9)
+#define SNPS_PHY_MPLLB_CP_PROP_GS REG_GENMASK(7, 1)
+
+#define SNPS_PHY_MPLLB_DIV(phy) _MMIO_SNPS(phy, 0x168004)
+#define SNPS_PHY_MPLLB_FORCE_EN REG_BIT(31)
+#define SNPS_PHY_MPLLB_DIV_CLK_EN REG_BIT(30)
+#define SNPS_PHY_MPLLB_DIV5_CLK_EN REG_BIT(29)
+#define SNPS_PHY_MPLLB_V2I REG_GENMASK(27, 26)
+#define SNPS_PHY_MPLLB_FREQ_VCO REG_GENMASK(25, 24)
+#define SNPS_PHY_MPLLB_DIV_MULTIPLIER REG_GENMASK(23, 16)
+#define SNPS_PHY_MPLLB_PMIX_EN REG_BIT(10)
+#define SNPS_PHY_MPLLB_DP2_MODE REG_BIT(9)
+#define SNPS_PHY_MPLLB_WORD_DIV2_EN REG_BIT(8)
+#define SNPS_PHY_MPLLB_TX_CLK_DIV REG_GENMASK(7, 5)
+#define SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL REG_BIT(0)
+
+#define SNPS_PHY_MPLLB_FRACN1(phy) _MMIO_SNPS(phy, 0x168008)
+#define SNPS_PHY_MPLLB_FRACN_EN REG_BIT(31)
+#define SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN REG_BIT(30)
+#define SNPS_PHY_MPLLB_FRACN_DEN REG_GENMASK(15, 0)
+
+#define SNPS_PHY_MPLLB_FRACN2(phy) _MMIO_SNPS(phy, 0x16800C)
+#define SNPS_PHY_MPLLB_FRACN_REM REG_GENMASK(31, 16)
+#define SNPS_PHY_MPLLB_FRACN_QUOT REG_GENMASK(15, 0)
+
+#define SNPS_PHY_MPLLB_SSCEN(phy) _MMIO_SNPS(phy, 0x168014)
+#define SNPS_PHY_MPLLB_SSC_EN REG_BIT(31)
+#define SNPS_PHY_MPLLB_SSC_UP_SPREAD REG_BIT(30)
+#define SNPS_PHY_MPLLB_SSC_PEAK REG_GENMASK(29, 10)
+
+#define SNPS_PHY_MPLLB_SSCSTEP(phy) _MMIO_SNPS(phy, 0x168018)
+#define SNPS_PHY_MPLLB_SSC_STEPSIZE REG_GENMASK(31, 11)
+
+#define SNPS_PHY_MPLLB_DIV2(phy) _MMIO_SNPS(phy, 0x16801C)
+#define SNPS_PHY_MPLLB_HDMI_PIXEL_CLK_DIV REG_GENMASK(19, 18)
+#define SNPS_PHY_MPLLB_HDMI_DIV REG_GENMASK(17, 15)
+#define SNPS_PHY_MPLLB_REF_CLK_DIV REG_GENMASK(14, 12)
+#define SNPS_PHY_MPLLB_MULTIPLIER REG_GENMASK(11, 0)
+
+#define SNPS_PHY_REF_CONTROL(phy) _MMIO_SNPS(phy, 0x168188)
+#define SNPS_PHY_REF_CONTROL_REF_RANGE REG_GENMASK(31, 27)
+
+#define SNPS_PHY_TX_REQ(phy) _MMIO_SNPS(phy, 0x168200)
+#define SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR REG_GENMASK(31, 30)
+
+#define SNPS_PHY_TX_EQ(ln, phy) _MMIO_SNPS_LN(ln, phy, 0x168300)
+#define SNPS_PHY_TX_EQ_MAIN REG_GENMASK(23, 18)
+#define SNPS_PHY_TX_EQ_POST REG_GENMASK(15, 10)
+#define SNPS_PHY_TX_EQ_PRE REG_GENMASK(7, 2)
+
+#endif /* __INTEL_SNPS_PHY_REGS__ */
int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
{
+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
const struct drm_framebuffer *fb = plane_state->hw.fb;
struct drm_rect *src = &plane_state->uapi.src;
u32 src_x, src_y, src_w, src_h, hsub, vsub;
hsub = vsub = max(hsub, vsub);
if (src_x % hsub || src_w % hsub) {
- DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of %u (rotated: %s)\n",
- src_x, src_w, hsub, yesno(rotated));
+ drm_dbg_kms(&i915->drm, "src x/w (%u, %u) must be a multiple of %u (rotated: %s)\n",
+ src_x, src_w, hsub, yesno(rotated));
return -EINVAL;
}
if (src_y % vsub || src_h % vsub) {
- DRM_DEBUG_KMS("src y/h (%u, %u) must be a multiple of %u (rotated: %s)\n",
- src_y, src_h, vsub, yesno(rotated));
+ drm_dbg_kms(&i915->drm, "src y/h (%u, %u) must be a multiple of %u (rotated: %s)\n",
+ src_y, src_h, vsub, yesno(rotated));
return -EINVAL;
}
u32 sprctl = 0;
if (crtc_state->gamma_enable)
- sprctl |= SP_GAMMA_ENABLE;
+ sprctl |= SP_PIPE_GAMMA_ENABLE;
return sprctl;
}
intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id),
plane_state->view.color_plane[0].mapping_stride);
intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id),
- (crtc_y << 16) | crtc_x);
+ SP_POS_Y(crtc_y) | SP_POS_X(crtc_x));
intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id),
- ((crtc_h - 1) << 16) | (crtc_w - 1));
+ SP_HEIGHT(crtc_h - 1) | SP_WIDTH(crtc_w - 1));
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
intel_de_write_fw(dev_priv, SPCONSTALPHA(pipe, plane_id), 0);
intel_de_write_fw(dev_priv, SPLINOFF(pipe, plane_id), linear_offset);
- intel_de_write_fw(dev_priv, SPTILEOFF(pipe, plane_id), (y << 16) | x);
+ intel_de_write_fw(dev_priv, SPTILEOFF(pipe, plane_id),
+ SP_OFFSET_Y(y) | SP_OFFSET_X(x));
/*
* The control register self-arms if the plane was previously
u32 sprctl = 0;
if (crtc_state->gamma_enable)
- sprctl |= SPRITE_GAMMA_ENABLE;
+ sprctl |= SPRITE_PIPE_GAMMA_ENABLE;
if (crtc_state->csc_enable)
sprctl |= SPRITE_PIPE_CSC_ENABLE;
}
if (!ivb_need_sprite_gamma(plane_state))
- sprctl |= SPRITE_INT_GAMMA_DISABLE;
+ sprctl |= SPRITE_PLANE_GAMMA_DISABLE;
if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709;
unsigned long irqflags;
if (crtc_w != src_w || crtc_h != src_h)
- sprscale = SPRITE_SCALE_ENABLE | ((src_w - 1) << 16) | (src_h - 1);
+ sprscale = SPRITE_SCALE_ENABLE |
+ SPRITE_SRC_WIDTH(src_w - 1) |
+ SPRITE_SRC_HEIGHT(src_h - 1);
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, SPRSTRIDE(pipe),
plane_state->view.color_plane[0].mapping_stride);
- intel_de_write_fw(dev_priv, SPRPOS(pipe), (crtc_y << 16) | crtc_x);
- intel_de_write_fw(dev_priv, SPRSIZE(pipe), ((crtc_h - 1) << 16) | (crtc_w - 1));
+ intel_de_write_fw(dev_priv, SPRPOS(pipe),
+ SPRITE_POS_Y(crtc_y) | SPRITE_POS_X(crtc_x));
+ intel_de_write_fw(dev_priv, SPRSIZE(pipe),
+ SPRITE_HEIGHT(crtc_h - 1) | SPRITE_WIDTH(crtc_w - 1));
if (IS_IVYBRIDGE(dev_priv))
intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale);
/* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
* register */
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
- intel_de_write_fw(dev_priv, SPROFFSET(pipe), (y << 16) | x);
+ intel_de_write_fw(dev_priv, SPROFFSET(pipe),
+ SPRITE_OFFSET_Y(y) | SPRITE_OFFSET_X(x));
} else {
intel_de_write_fw(dev_priv, SPRLINOFF(pipe), linear_offset);
- intel_de_write_fw(dev_priv, SPRTILEOFF(pipe), (y << 16) | x);
+ intel_de_write_fw(dev_priv, SPRTILEOFF(pipe),
+ SPRITE_OFFSET_Y(y) | SPRITE_OFFSET_X(x));
}
/*
u32 dvscntr = 0;
if (crtc_state->gamma_enable)
- dvscntr |= DVS_GAMMA_ENABLE;
+ dvscntr |= DVS_PIPE_GAMMA_ENABLE;
if (crtc_state->csc_enable)
dvscntr |= DVS_PIPE_CSC_ENABLE;
unsigned long irqflags;
if (crtc_w != src_w || crtc_h != src_h)
- dvsscale = DVS_SCALE_ENABLE | ((src_w - 1) << 16) | (src_h - 1);
+ dvsscale = DVS_SCALE_ENABLE |
+ DVS_SRC_WIDTH(src_w - 1) |
+ DVS_SRC_HEIGHT(src_h - 1);
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, DVSSTRIDE(pipe),
plane_state->view.color_plane[0].mapping_stride);
- intel_de_write_fw(dev_priv, DVSPOS(pipe), (crtc_y << 16) | crtc_x);
- intel_de_write_fw(dev_priv, DVSSIZE(pipe), ((crtc_h - 1) << 16) | (crtc_w - 1));
+ intel_de_write_fw(dev_priv, DVSPOS(pipe),
+ DVS_POS_Y(crtc_y) | DVS_POS_X(crtc_x));
+ intel_de_write_fw(dev_priv, DVSSIZE(pipe),
+ DVS_HEIGHT(crtc_h - 1) | DVS_WIDTH(crtc_w - 1));
intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale);
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state)
{
+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
const struct drm_framebuffer *fb = plane_state->hw.fb;
const struct drm_rect *src = &plane_state->uapi.src;
const struct drm_rect *dst = &plane_state->uapi.dst;
if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
if (src_h & 1) {
- DRM_DEBUG_KMS("Source height must be even with interlaced modes\n");
+ drm_dbg_kms(&i915->drm, "Source height must be even with interlaced modes\n");
return -EINVAL;
}
min_height = 6;
if (src_w < min_width || src_h < min_height ||
src_w > 2048 || src_h > 2048) {
- DRM_DEBUG_KMS("Source dimensions (%dx%d) exceed hardware limits (%dx%d - %dx%d)\n",
- src_w, src_h, min_width, min_height, 2048, 2048);
+ drm_dbg_kms(&i915->drm, "Source dimensions (%dx%d) exceed hardware limits (%dx%d - %dx%d)\n",
+ src_w, src_h, min_width, min_height, 2048, 2048);
return -EINVAL;
}
if (width_bytes > 4096) {
- DRM_DEBUG_KMS("Fetch width (%d) exceeds hardware max with scaling (%u)\n",
- width_bytes, 4096);
+ drm_dbg_kms(&i915->drm, "Fetch width (%d) exceeds hardware max with scaling (%u)\n",
+ width_bytes, 4096);
return -EINVAL;
}
if (stride > 4096) {
- DRM_DEBUG_KMS("Stride (%u) exceeds hardware max with scaling (%u)\n",
- stride, 4096);
+ drm_dbg_kms(&i915->drm, "Stride (%u) exceeds hardware max with scaling (%u)\n",
+ stride, 4096);
return -EINVAL;
}
#include "intel_display_types.h"
#include "intel_dp_mst.h"
#include "intel_tc.h"
+#include "intel_tc_phy_regs.h"
static const char *tc_port_mode_name(enum tc_port_mode mode)
{
static bool adl_tc_phy_status_complete(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
struct intel_uncore *uncore = &i915->uncore;
u32 val;
- val = intel_uncore_read(uncore, TCSS_DDI_STATUS(dig_port->tc_phy_fia_idx));
+ val = intel_uncore_read(uncore, TCSS_DDI_STATUS(tc_port));
if (val == 0xffffffff) {
drm_dbg_kms(&i915->drm,
"Port %s: PHY in TCCOLD, assuming not complete\n",
--- /dev/null
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_TC_PHY_REGS__
+#define __INTEL_TC_PHY_REGS__
+
+#include "i915_reg_defs.h"
+
+#define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \
+ _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
+
+#define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
+#define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
+#define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
+#define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
+#define MG_TX1_LINK_PARAMS(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
+ MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
+ MG_TX_LINK_PARAMS_TX1LN1_PORT1)
+
+#define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
+#define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
+#define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
+#define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
+#define MG_TX2_LINK_PARAMS(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
+ MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
+ MG_TX_LINK_PARAMS_TX2LN1_PORT1)
+#define CRI_USE_FS32 (1 << 5)
+
+#define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
+#define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
+#define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
+#define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
+#define MG_TX1_PISO_READLOAD(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
+ MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
+ MG_TX_PISO_READLOAD_TX1LN1_PORT1)
+
+#define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
+#define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
+#define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
+#define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
+#define MG_TX2_PISO_READLOAD(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
+ MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
+ MG_TX_PISO_READLOAD_TX2LN1_PORT1)
+#define CRI_CALCINIT (1 << 1)
+
+#define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
+#define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
+#define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
+#define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
+#define MG_TX1_SWINGCTRL(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
+ MG_TX_SWINGCTRL_TX1LN0_PORT2, \
+ MG_TX_SWINGCTRL_TX1LN1_PORT1)
+
+#define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
+#define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
+#define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
+#define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
+#define MG_TX2_SWINGCTRL(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
+ MG_TX_SWINGCTRL_TX2LN0_PORT2, \
+ MG_TX_SWINGCTRL_TX2LN1_PORT1)
+#define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
+#define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
+
+#define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144
+#define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544
+#define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144
+#define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544
+#define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144
+#define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544
+#define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144
+#define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544
+#define MG_TX1_DRVCTRL(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
+ MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
+ MG_TX_DRVCTRL_TX1LN1_TXPORT1)
+
+#define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
+#define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
+#define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
+#define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
+#define MG_TX2_DRVCTRL(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
+ MG_TX_DRVCTRL_TX2LN0_PORT2, \
+ MG_TX_DRVCTRL_TX2LN1_PORT1)
+#define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
+#define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)
+#define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
+#define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
+#define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
+#define CRI_LOADGEN_SEL(x) ((x) << 12)
+#define CRI_LOADGEN_SEL_MASK (0x3 << 12)
+
+#define MG_CLKHUB_LN0_PORT1 0x16839C
+#define MG_CLKHUB_LN1_PORT1 0x16879C
+#define MG_CLKHUB_LN0_PORT2 0x16939C
+#define MG_CLKHUB_LN1_PORT2 0x16979C
+#define MG_CLKHUB(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \
+ MG_CLKHUB_LN0_PORT2, \
+ MG_CLKHUB_LN1_PORT1)
+#define CFG_LOW_RATE_LKREN_EN (1 << 11)
+
+#define MG_TX_DCC_TX1LN0_PORT1 0x168110
+#define MG_TX_DCC_TX1LN1_PORT1 0x168510
+#define MG_TX_DCC_TX1LN0_PORT2 0x169110
+#define MG_TX_DCC_TX1LN1_PORT2 0x169510
+#define MG_TX1_DCC(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \
+ MG_TX_DCC_TX1LN0_PORT2, \
+ MG_TX_DCC_TX1LN1_PORT1)
+#define MG_TX_DCC_TX2LN0_PORT1 0x168090
+#define MG_TX_DCC_TX2LN1_PORT1 0x168490
+#define MG_TX_DCC_TX2LN0_PORT2 0x169090
+#define MG_TX_DCC_TX2LN1_PORT2 0x169490
+#define MG_TX2_DCC(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \
+ MG_TX_DCC_TX2LN0_PORT2, \
+ MG_TX_DCC_TX2LN1_PORT1)
+#define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)
+#define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)
+#define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)
+
+#define MG_DP_MODE_LN0_ACU_PORT1 0x1683A0
+#define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0
+#define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0
+#define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0
+#define MG_DP_MODE(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \
+ MG_DP_MODE_LN0_ACU_PORT2, \
+ MG_DP_MODE_LN1_ACU_PORT1)
+#define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
+#define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
+
+#define FIA1_BASE 0x163000
+#define FIA2_BASE 0x16E000
+#define FIA3_BASE 0x16F000
+#define _FIA(fia) _PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
+#define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off))
+
+/* ICL PHY DFLEX registers */
+#define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0)
+#define DFLEXDPMLE1_DPMLETC_MASK(idx) (0xf << (4 * (idx)))
+#define DFLEXDPMLE1_DPMLETC_ML0(idx) (1 << (4 * (idx)))
+#define DFLEXDPMLE1_DPMLETC_ML1_0(idx) (3 << (4 * (idx)))
+#define DFLEXDPMLE1_DPMLETC_ML3(idx) (8 << (4 * (idx)))
+#define DFLEXDPMLE1_DPMLETC_ML3_2(idx) (12 << (4 * (idx)))
+#define DFLEXDPMLE1_DPMLETC_ML3_0(idx) (15 << (4 * (idx)))
+
+#define _MG_REFCLKIN_CTL_PORT1 0x16892C
+#define _MG_REFCLKIN_CTL_PORT2 0x16992C
+#define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8)
+#define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8)
+#define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
+ _MG_REFCLKIN_CTL_PORT1, \
+ _MG_REFCLKIN_CTL_PORT2)
+
+#define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8
+#define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8
+#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16)
+#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16)
+#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8)
+#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8)
+#define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \
+ _MG_CLKTOP2_CORECLKCTL1_PORT1, \
+ _MG_CLKTOP2_CORECLKCTL1_PORT2)
+
+#define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4
+#define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4
+#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16)
+#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16)
+#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14)
+#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14)
+#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << 12)
+#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 (0 << 12)
+#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 (1 << 12)
+#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12)
+#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12)
+#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8)
+#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8
+#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8)
+#define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \
+ _MG_CLKTOP2_HSCLKCTL_PORT1, \
+ _MG_CLKTOP2_HSCLKCTL_PORT2)
+
+#define _MG_PLL_DIV0_PORT1 0x168A00
+#define _MG_PLL_DIV0_PORT2 0x169A00
+#define MG_PLL_DIV0_FRACNEN_H (1 << 30)
+#define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fffff << 8)
+#define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8
+#define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8)
+#define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0)
+#define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
+#define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \
+ _MG_PLL_DIV0_PORT2)
+
+#define _MG_PLL_DIV1_PORT1 0x168A04
+#define _MG_PLL_DIV1_PORT2 0x169A04
+#define MG_PLL_DIV1_IREF_NDIVRATIO(x) ((x) << 16)
+#define MG_PLL_DIV1_DITHER_DIV_1 (0 << 12)
+#define MG_PLL_DIV1_DITHER_DIV_2 (1 << 12)
+#define MG_PLL_DIV1_DITHER_DIV_4 (2 << 12)
+#define MG_PLL_DIV1_DITHER_DIV_8 (3 << 12)
+#define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4)
+#define MG_PLL_DIV1_FBPREDIV_MASK (0xf << 0)
+#define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0)
+#define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \
+ _MG_PLL_DIV1_PORT2)
+
+#define _MG_PLL_LF_PORT1 0x168A08
+#define _MG_PLL_LF_PORT2 0x169A08
+#define MG_PLL_LF_TDCTARGETCNT(x) ((x) << 24)
+#define MG_PLL_LF_AFCCNTSEL_256 (0 << 20)
+#define MG_PLL_LF_AFCCNTSEL_512 (1 << 20)
+#define MG_PLL_LF_GAINCTRL(x) ((x) << 16)
+#define MG_PLL_LF_INT_COEFF(x) ((x) << 8)
+#define MG_PLL_LF_PROP_COEFF(x) ((x) << 0)
+#define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \
+ _MG_PLL_LF_PORT2)
+
+#define _MG_PLL_FRAC_LOCK_PORT1 0x168A0C
+#define _MG_PLL_FRAC_LOCK_PORT2 0x169A0C
+#define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 (1 << 18)
+#define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 (1 << 16)
+#define MG_PLL_FRAC_LOCK_LOCKTHRESH(x) ((x) << 11)
+#define MG_PLL_FRAC_LOCK_DCODITHEREN (1 << 10)
+#define MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN (1 << 8)
+#define MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x) ((x) << 0)
+#define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \
+ _MG_PLL_FRAC_LOCK_PORT1, \
+ _MG_PLL_FRAC_LOCK_PORT2)
+
+#define _MG_PLL_SSC_PORT1 0x168A10
+#define _MG_PLL_SSC_PORT2 0x169A10
+#define MG_PLL_SSC_EN (1 << 28)
+#define MG_PLL_SSC_TYPE(x) ((x) << 26)
+#define MG_PLL_SSC_STEPLENGTH(x) ((x) << 16)
+#define MG_PLL_SSC_STEPNUM(x) ((x) << 10)
+#define MG_PLL_SSC_FLLEN (1 << 9)
+#define MG_PLL_SSC_STEPSIZE(x) ((x) << 0)
+#define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \
+ _MG_PLL_SSC_PORT2)
+
+#define _MG_PLL_BIAS_PORT1 0x168A14
+#define _MG_PLL_BIAS_PORT2 0x169A14
+#define MG_PLL_BIAS_BIAS_GB_SEL(x) ((x) << 30)
+#define MG_PLL_BIAS_BIAS_GB_SEL_MASK (0x3 << 30)
+#define MG_PLL_BIAS_INIT_DCOAMP(x) ((x) << 24)
+#define MG_PLL_BIAS_INIT_DCOAMP_MASK (0x3f << 24)
+#define MG_PLL_BIAS_BIAS_BONUS(x) ((x) << 16)
+#define MG_PLL_BIAS_BIAS_BONUS_MASK (0xff << 16)
+#define MG_PLL_BIAS_BIASCAL_EN (1 << 15)
+#define MG_PLL_BIAS_CTRIM(x) ((x) << 8)
+#define MG_PLL_BIAS_CTRIM_MASK (0x1f << 8)
+#define MG_PLL_BIAS_VREF_RDAC(x) ((x) << 5)
+#define MG_PLL_BIAS_VREF_RDAC_MASK (0x7 << 5)
+#define MG_PLL_BIAS_IREFTRIM(x) ((x) << 0)
+#define MG_PLL_BIAS_IREFTRIM_MASK (0x1f << 0)
+#define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \
+ _MG_PLL_BIAS_PORT2)
+
+#define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168A18
+#define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169A18
+#define MG_PLL_TDC_COLDST_IREFINT_EN (1 << 27)
+#define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x) ((x) << 17)
+#define MG_PLL_TDC_COLDST_COLDSTART (1 << 16)
+#define MG_PLL_TDC_TDCOVCCORR_EN (1 << 2)
+#define MG_PLL_TDC_TDCSEL(x) ((x) << 0)
+#define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \
+ _MG_PLL_TDC_COLDST_BIAS_PORT1, \
+ _MG_PLL_TDC_COLDST_BIAS_PORT2)
+
+#endif /* __INTEL_TC_PHY_REGS__ */
#define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1)
#define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0)
-/*
- * Bits we care about when checking for DEVICE_TYPE_eDP. Depending on the
- * system, the other bits may or may not be set for eDP outputs.
- */
-#define DEVICE_TYPE_eDP_BITS \
- (DEVICE_TYPE_INTERNAL_CONNECTOR | \
- DEVICE_TYPE_MIPI_OUTPUT | \
- DEVICE_TYPE_COMPOSITE_OUTPUT | \
- DEVICE_TYPE_DUAL_CHANNEL | \
- DEVICE_TYPE_LVDS_SIGNALING | \
- DEVICE_TYPE_TMDS_DVI_SIGNALING | \
- DEVICE_TYPE_VIDEO_SIGNALING | \
- DEVICE_TYPE_DISPLAYPORT_OUTPUT | \
- DEVICE_TYPE_ANALOG_OUTPUT)
-
-#define DEVICE_TYPE_DP_DUAL_MODE_BITS \
- (DEVICE_TYPE_INTERNAL_CONNECTOR | \
- DEVICE_TYPE_MIPI_OUTPUT | \
- DEVICE_TYPE_COMPOSITE_OUTPUT | \
- DEVICE_TYPE_LVDS_SIGNALING | \
- DEVICE_TYPE_TMDS_DVI_SIGNALING | \
- DEVICE_TYPE_VIDEO_SIGNALING | \
- DEVICE_TYPE_DISPLAYPORT_OUTPUT | \
- DEVICE_TYPE_DIGITAL_OUTPUT | \
- DEVICE_TYPE_ANALOG_OUTPUT)
-
#define DEVICE_CFG_NONE 0x00
#define DEVICE_CFG_12BIT_DVOB 0x01
#define DEVICE_CFG_12BIT_DVOC 0x02
const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- enum pipe pipe = crtc->pipe;
if (!INTEL_INFO(i915)->display.has_dsc)
return false;
- /* On TGL, DSC is supported on all Pipes */
if (DISPLAY_VER(i915) >= 12)
return true;
- if (DISPLAY_VER(i915) >= 11 &&
- (pipe != PIPE_A || cpu_transcoder == TRANSCODER_EDP ||
- cpu_transcoder == TRANSCODER_DSI_0 ||
- cpu_transcoder == TRANSCODER_DSI_1))
+ if (DISPLAY_VER(i915) >= 11 && cpu_transcoder != TRANSCODER_A)
return true;
return false;
static u32 skl_surf_address(const struct intel_plane_state *plane_state,
int color_plane)
{
+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
const struct drm_framebuffer *fb = plane_state->hw.fb;
u32 offset = plane_state->view.color_plane[color_plane].offset;
* The DPT object contains only one vma, so the VMA's offset
* within the DPT is always 0.
*/
- WARN_ON(plane_state->dpt_vma->node.start);
- WARN_ON(offset & 0x1fffff);
+ drm_WARN_ON(&i915->drm, plane_state->dpt_vma->node.start);
+ drm_WARN_ON(&i915->drm, offset & 0x1fffff);
return offset >> 9;
} else {
- WARN_ON(offset & 0xfff);
+ drm_WARN_ON(&i915->drm, offset & 0xfff);
return offset;
}
}
return plane_surf;
}
+static u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state,
+ int color_plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ int aux_plane = skl_main_to_aux_plane(fb, color_plane);
+ u32 aux_dist;
+
+ if (!aux_plane)
+ return 0;
+
+ aux_dist = skl_surf_address(plane_state, aux_plane) -
+ skl_surf_address(plane_state, color_plane);
+
+ if (DISPLAY_VER(i915) < 12)
+ aux_dist |= PLANE_AUX_STRIDE(skl_plane_stride(plane_state, aux_plane));
+
+ return aux_dist;
+}
+
+static u32 skl_plane_keyval(const struct intel_plane_state *plane_state)
+{
+ const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
+
+ return key->min_value;
+}
+
+static u32 skl_plane_keymax(const struct intel_plane_state *plane_state)
+{
+ const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
+ u8 alpha = plane_state->hw.alpha >> 8;
+
+ return (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
+}
+
+static u32 skl_plane_keymsk(const struct intel_plane_state *plane_state)
+{
+ const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
+ u8 alpha = plane_state->hw.alpha >> 8;
+ u32 keymsk;
+
+ keymsk = key->channel_mask & 0x7ffffff;
+ if (alpha < 0xff)
+ keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
+
+ return keymsk;
+}
+
static void icl_plane_csc_load_black(struct intel_plane *plane)
{
struct drm_i915_private *i915 = to_i915(plane->base.dev);
intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 2), 0);
}
+static int skl_plane_color_plane(const struct intel_plane_state *plane_state)
+{
+ /* Program the UV plane on planar master */
+ if (plane_state->planar_linked_plane && !plane_state->planar_slave)
+ return 1;
+ else
+ return 0;
+}
+
static void
-skl_program_plane_noarm(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state,
- int color_plane)
+skl_plane_update_noarm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum plane_id plane_id = plane->id;
enum pipe pipe = plane->pipe;
+ int color_plane = skl_plane_color_plane(plane_state);
u32 stride = skl_plane_stride(plane_state, color_plane);
const struct drm_framebuffer *fb = plane_state->hw.fb;
int crtc_x = plane_state->uapi.dst.x1;
if (plane_state->force_black)
icl_plane_csc_load_black(plane);
- intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id), stride);
+ intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id),
+ PLANE_STRIDE_(stride));
intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
- (crtc_y << 16) | crtc_x);
+ PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x));
intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
- ((src_h - 1) << 16) | (src_w - 1));
+ PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1));
if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) {
intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0),
}
static void
-skl_program_plane_arm(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state,
- int color_plane)
+skl_plane_update_arm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum plane_id plane_id = plane->id;
enum pipe pipe = plane->pipe;
- const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
- const struct drm_framebuffer *fb = plane_state->hw.fb;
- int aux_plane = skl_main_to_aux_plane(fb, color_plane);
+ int color_plane = skl_plane_color_plane(plane_state);
u32 x = plane_state->view.color_plane[color_plane].x;
u32 y = plane_state->view.color_plane[color_plane].y;
- u32 keymsk, keymax, aux_dist = 0, plane_color_ctl = 0;
- u8 alpha = plane_state->hw.alpha >> 8;
+ u32 plane_color_ctl = 0;
u32 plane_ctl = plane_state->ctl;
unsigned long irqflags;
plane_color_ctl = plane_state->color_ctl |
glk_plane_color_ctl_crtc(crtc_state);
- keymax = (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
-
- keymsk = key->channel_mask & 0x7ffffff;
- if (alpha < 0xff)
- keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
-
- if (aux_plane) {
- aux_dist = skl_surf_address(plane_state, aux_plane) -
- skl_surf_address(plane_state, color_plane);
-
- if (DISPLAY_VER(dev_priv) < 12)
- aux_dist |= skl_plane_stride(plane_state, aux_plane);
- }
-
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
- intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id),
- key->min_value);
- intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), keymsk);
- intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), keymax);
+ intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), skl_plane_keyval(plane_state));
+ intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), skl_plane_keymsk(plane_state));
+ intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), skl_plane_keymax(plane_state));
intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
- (y << 16) | x);
+ PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
- intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist);
+ intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
+ skl_plane_aux_dist(plane_state, color_plane));
if (DISPLAY_VER(dev_priv) < 11)
intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),
- (plane_state->view.color_plane[1].y << 16) |
- plane_state->view.color_plane[1].x);
+ PLANE_OFFSET_Y(plane_state->view.color_plane[1].y) |
+ PLANE_OFFSET_X(plane_state->view.color_plane[1].x));
if (DISPLAY_VER(dev_priv) >= 10)
intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
-static void
-skl_plane_update_noarm(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
-{
- int color_plane = 0;
-
- if (plane_state->planar_linked_plane && !plane_state->planar_slave)
- /* Program the UV plane on planar master */
- color_plane = 1;
-
- skl_program_plane_noarm(plane, crtc_state, plane_state, color_plane);
-}
-
-static void
-skl_plane_update_arm(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
-{
- int color_plane = 0;
-
- if (plane_state->planar_linked_plane && !plane_state->planar_slave)
- /* Program the UV plane on planar master */
- color_plane = 1;
-
- skl_program_plane_arm(plane, crtc_state, plane_state, color_plane);
-}
-
static bool intel_format_is_p01x(u32 format)
{
switch (format) {
static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_state)
{
+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
const struct drm_framebuffer *fb = plane_state->hw.fb;
unsigned int rotation = plane_state->hw.rotation;
int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
src_w & 3 &&
(rotation == DRM_MODE_ROTATE_270 ||
rotation == (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90))) {
- DRM_DEBUG_KMS("src width must be multiple of 4 for rotated planar YUV\n");
+ drm_dbg_kms(&i915->drm, "src width must be multiple of 4 for rotated planar YUV\n");
return -EINVAL;
}
return 0;
}
+static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe)
+{
+ return pipe - PIPE_A + INTEL_FBC_A;
+}
+
static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
- enum pipe pipe, enum plane_id plane_id)
+ enum intel_fbc_id fbc_id, enum plane_id plane_id)
{
- if (!HAS_FBC(dev_priv))
+ if ((INTEL_INFO(dev_priv)->display.fbc_mask & BIT(fbc_id)) == 0)
return false;
- return pipe == PIPE_A && plane_id == PLANE_PRIMARY;
+ return plane_id == PLANE_PRIMARY;
}
static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv,
enum pipe pipe, enum plane_id plane_id)
{
- if (skl_plane_has_fbc(dev_priv, pipe, plane_id))
- return dev_priv->fbc;
+ enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(pipe);
+
+ if (skl_plane_has_fbc(dev_priv, fbc_id, plane_id))
+ return dev_priv->fbc[fbc_id];
else
return NULL;
}
val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id));
if (DISPLAY_VER(dev_priv) >= 11)
- pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
+ pixel_format = val & PLANE_CTL_FORMAT_MASK_ICL;
else
- pixel_format = val & PLANE_CTL_FORMAT_MASK;
+ pixel_format = val & PLANE_CTL_FORMAT_MASK_SKL;
if (DISPLAY_VER(dev_priv) >= 10) {
- alpha = intel_de_read(dev_priv,
- PLANE_COLOR_CTL(pipe, plane_id));
- alpha &= PLANE_COLOR_ALPHA_MASK;
+ u32 color_ctl;
+
+ color_ctl = intel_de_read(dev_priv, PLANE_COLOR_CTL(pipe, plane_id));
+ alpha = REG_FIELD_GET(PLANE_COLOR_ALPHA_MASK, color_ctl);
} else {
- alpha = val & PLANE_CTL_ALPHA_MASK;
+ alpha = REG_FIELD_GET(PLANE_CTL_ALPHA_MASK, val);
}
fourcc = skl_format_to_fourcc(pixel_format,
if (drm_rotation_90_or_270(plane_config->rotation))
goto error;
- base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000;
+ base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & PLANE_SURF_ADDR_MASK;
plane_config->base = base;
offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id));
val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id));
- fb->height = ((val >> 16) & 0xffff) + 1;
- fb->width = ((val >> 0) & 0xffff) + 1;
+ fb->height = REG_FIELD_GET(PLANE_HEIGHT_MASK, val) + 1;
+ fb->width = REG_FIELD_GET(PLANE_WIDTH_MASK, val) + 1;
val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
- if (DISPLAY_VER(dev_priv) >= 13)
- fb->pitches[0] = (val & PLANE_STRIDE_MASK_XELPD) * stride_mult;
- else
- fb->pitches[0] = (val & PLANE_STRIDE_MASK) * stride_mult;
+ fb->pitches[0] = REG_FIELD_GET(PLANE_STRIDE__MASK, val) * stride_mult;
aligned_height = intel_fb_align_height(fb, 0, fb->height);
#include "pxp/intel_pxp.h"
+#include "i915_cmd_parser.h"
#include "i915_drv.h"
#include "i915_gem_clflush.h"
#include "i915_gem_context.h"
+#include "i915_gem_evict.h"
#include "i915_gem_ioctls.h"
#include "i915_trace.h"
#include "i915_user_extensions.h"
#include "i915_gem_ioctls.h"
#include "i915_gem_mman.h"
#include "i915_gem_object.h"
+#include "i915_gem_tiling.h"
/**
* DOC: buffer object tiling
--- /dev/null
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __I915_GEM_TILING_H__
+#define __I915_GEM_TILING_H__
+
+#include <linux/types.h>
+
+struct drm_i915_private;
+
+u32 i915_gem_fence_size(struct drm_i915_private *i915, u32 size,
+ unsigned int tiling, unsigned int stride);
+u32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size,
+ unsigned int tiling, unsigned int stride);
+
+#endif /* __I915_GEM_TILING_H__ */
#include "i915_drv.h"
#include "i915_gem_ioctls.h"
#include "i915_gem_object.h"
+#include "i915_gem_userptr.h"
#include "i915_scatterlist.h"
#ifdef CONFIG_MMU_NOTIFIER
--- /dev/null
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef __I915_GEM_USERPTR_H__
+#define __I915_GEM_USERPTR_H__
+
+struct drm_i915_private;
+
+int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
+void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
+
+#endif /* __I915_GEM_USERPTR_H__ */
#include "gen2_engine_cs.h"
#include "i915_drv.h"
#include "intel_engine.h"
+#include "intel_engine_regs.h"
#include "intel_gpu_commands.h"
#include "intel_gt.h"
#include "intel_gt_irq.h"
#include "gen6_engine_cs.h"
#include "intel_engine.h"
+#include "intel_engine_regs.h"
#include "intel_gpu_commands.h"
#include "intel_gt.h"
#include "intel_gt_irq.h"
#include "i915_scatterlist.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
+#include "intel_engine_regs.h"
#include "intel_gt.h"
/* Write pde (index) from the page directory @pd to the page table @pt */
#include "gem/i915_gem_context.h"
+#include "i915_cmd_parser.h"
#include "i915_drv.h"
-
#include "intel_breadcrumbs.h"
#include "intel_context.h"
#include "intel_engine.h"
#include "intel_engine_pm.h"
+#include "intel_engine_regs.h"
#include "intel_engine_user.h"
#include "intel_execlists_submission.h"
#include "intel_gt.h"
--- /dev/null
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_ENGINE_REGS__
+#define __INTEL_ENGINE_REGS__
+
+#include "i915_reg_defs.h"
+
+#define RING_TAIL(base) _MMIO((base) + 0x30)
+#define TAIL_ADDR 0x001FFFF8
+#define RING_HEAD(base) _MMIO((base) + 0x34)
+#define HEAD_WRAP_COUNT 0xFFE00000
+#define HEAD_WRAP_ONE 0x00200000
+#define HEAD_ADDR 0x001FFFFC
+#define RING_START(base) _MMIO((base) + 0x38)
+#define RING_CTL(base) _MMIO((base) + 0x3c)
+#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
+#define RING_NR_PAGES 0x001FF000
+#define RING_REPORT_MASK 0x00000006
+#define RING_REPORT_64K 0x00000002
+#define RING_REPORT_128K 0x00000004
+#define RING_NO_REPORT 0x00000000
+#define RING_VALID_MASK 0x00000001
+#define RING_VALID 0x00000001
+#define RING_INVALID 0x00000000
+#define RING_WAIT_I8XX (1 << 0) /* gen2, PRBx_HEAD */
+#define RING_WAIT (1 << 11) /* gen3+, PRBx_CTL */
+#define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */
+#define RING_SYNC_0(base) _MMIO((base) + 0x40)
+#define RING_SYNC_1(base) _MMIO((base) + 0x44)
+#define RING_SYNC_2(base) _MMIO((base) + 0x48)
+#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
+#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
+#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
+#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
+#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
+#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
+#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
+#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
+#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
+#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
+#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
+#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
+#define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
+#define GEN8_RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
+#define GEN8_FF_DOP_CLOCK_GATE_DISABLE REG_BIT(10)
+#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
+#define GEN6_BSD_GO_INDICATOR REG_BIT(4)
+#define GEN6_BSD_SLEEP_INDICATOR REG_BIT(3)
+#define GEN6_BSD_SLEEP_FLUSH_DISABLE REG_BIT(2)
+#define GEN6_PSMI_SLEEP_MSG_DISABLE REG_BIT(0)
+#define RING_MAX_IDLE(base) _MMIO((base) + 0x54)
+#define PWRCTX_MAXCNT(base) _MMIO((base) + 0x54)
+#define IDLE_TIME_MASK 0xFFFFF
+#define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c)
+#define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */
+#define RING_IPEIR(base) _MMIO((base) + 0x64)
+#define RING_IPEHR(base) _MMIO((base) + 0x68)
+#define RING_INSTDONE(base) _MMIO((base) + 0x6c)
+#define RING_INSTPS(base) _MMIO((base) + 0x70)
+#define RING_DMA_FADD(base) _MMIO((base) + 0x78)
+#define RING_ACTHD(base) _MMIO((base) + 0x74)
+#define RING_HWS_PGA(base) _MMIO((base) + 0x80)
+#define RING_CMD_BUF_CCTL(base) _MMIO((base) + 0x84)
+#define IPEIR(base) _MMIO((base) + 0x88)
+#define IPEHR(base) _MMIO((base) + 0x8c)
+#define RING_ID(base) _MMIO((base) + 0x8c)
+#define RING_NOPID(base) _MMIO((base) + 0x94)
+#define RING_HWSTAM(base) _MMIO((base) + 0x98)
+#define RING_MI_MODE(base) _MMIO((base) + 0x9c)
+#define RING_IMR(base) _MMIO((base) + 0xa8)
+#define RING_EIR(base) _MMIO((base) + 0xb0)
+#define RING_EMR(base) _MMIO((base) + 0xb4)
+#define RING_ESR(base) _MMIO((base) + 0xb8)
+#define RING_INSTPM(base) _MMIO((base) + 0xc0)
+#define RING_CMD_CCTL(base) _MMIO((base) + 0xc4)
+#define ACTHD(base) _MMIO((base) + 0xc8)
+#define RING_RESET_CTL(base) _MMIO((base) + 0xd0)
+#define RESET_CTL_CAT_ERROR REG_BIT(2)
+#define RESET_CTL_READY_TO_RESET REG_BIT(1)
+#define RESET_CTL_REQUEST_RESET REG_BIT(0)
+#define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0)
+#define RING_BBSTATE(base) _MMIO((base) + 0x110)
+#define RING_BB_PPGTT (1 << 5)
+#define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */
+#define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */
+#define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */
+#define RING_BBADDR(base) _MMIO((base) + 0x140)
+#define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */
+#define CCID(base) _MMIO((base) + 0x180)
+#define CCID_EN BIT(0)
+#define CCID_EXTENDED_STATE_RESTORE BIT(2)
+#define CCID_EXTENDED_STATE_SAVE BIT(3)
+#define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */
+#define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */
+#define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */
+#define ECOSKPD(base) _MMIO((base) + 0x1d0)
+#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
+#define ECO_GATING_CX_ONLY REG_BIT(3)
+#define GEN6_BLITTER_FBC_NOTIFY REG_BIT(3)
+#define ECO_FLIP_DONE REG_BIT(0)
+#define GEN6_BLITTER_LOCK_SHIFT 16
+
+#define BLIT_CCTL(base) _MMIO((base) + 0x204)
+#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8)
+#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0)
+#define BLIT_CCTL_MASK (BLIT_CCTL_DST_MOCS_MASK | \
+ BLIT_CCTL_SRC_MOCS_MASK)
+#define BLIT_CCTL_MOCS(dst, src) \
+ (REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (dst) << 1) | \
+ REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (src) << 1))
+
+/*
+ * CMD_CCTL read/write fields take a MOCS value and _not_ a table index.
+ * The lsb of each can be considered a separate enabling bit for encryption.
+ * 6:0 == default MOCS value for reads => 6:1 == table index for reads.
+ * 13:7 == default MOCS value for writes => 13:8 == table index for writes.
+ * 15:14 == Reserved => 31:30 are set to 0.
+ */
+#define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 7)
+#define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 0)
+#define CMD_CCTL_MOCS_MASK (CMD_CCTL_WRITE_OVERRIDE_MASK | \
+ CMD_CCTL_READ_OVERRIDE_MASK)
+#define CMD_CCTL_MOCS_OVERRIDE(write, read) \
+ (REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \
+ REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))
+
+#define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220)
+#define PP_DIR_DCLV_2G 0xffffffff
+#define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228)
+#define RING_ELSP(base) _MMIO((base) + 0x230)
+#define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234)
+#define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4)
+#define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244)
+#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0)
+#define CTX_CTRL_RS_CTX_ENABLE REG_BIT(1)
+#define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT REG_BIT(2)
+#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3)
+#define GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE REG_BIT(8)
+#define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
+#define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4)
+#define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8)
+#define RING_MODE_GEN7(base) _MMIO((base) + 0x29c)
+#define GFX_RUN_LIST_ENABLE (1 << 15)
+#define GFX_INTERRUPT_STEERING (1 << 14)
+#define GFX_TLB_INVALIDATE_EXPLICIT (1 << 13)
+#define GFX_SURFACE_FAULT_ENABLE (1 << 12)
+#define GFX_REPLAY_MODE (1 << 11)
+#define GFX_PSMI_GRANULARITY (1 << 10)
+#define GFX_PPGTT_ENABLE (1 << 9)
+#define GEN8_GFX_PPGTT_48B (1 << 7)
+#define GFX_FORWARD_VBLANK_MASK (3 << 5)
+#define GFX_FORWARD_VBLANK_NEVER (0 << 5)
+#define GFX_FORWARD_VBLANK_ALWAYS (1 << 5)
+#define GFX_FORWARD_VBLANK_COND (2 << 5)
+#define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3)
+#define RING_TIMESTAMP(base) _MMIO((base) + 0x358)
+#define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4)
+#define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0)
+#define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */
+#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
+#define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2)
+#define RING_FORCE_TO_NONPRIV_ACCESS_RW (0 << 28) /* CFL+ & Gen11+ */
+#define RING_FORCE_TO_NONPRIV_ACCESS_RD (1 << 28)
+#define RING_FORCE_TO_NONPRIV_ACCESS_WR (2 << 28)
+#define RING_FORCE_TO_NONPRIV_ACCESS_INVALID (3 << 28)
+#define RING_FORCE_TO_NONPRIV_ACCESS_MASK (3 << 28)
+#define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0) /* CFL+ & Gen11+ */
+#define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0)
+#define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0)
+#define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0)
+#define RING_FORCE_TO_NONPRIV_RANGE_MASK (3 << 0)
+#define RING_FORCE_TO_NONPRIV_MASK_VALID \
+ (RING_FORCE_TO_NONPRIV_RANGE_MASK | RING_FORCE_TO_NONPRIV_ACCESS_MASK)
+#define RING_MAX_NONPRIV_SLOTS 12
+
+#define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510)
+#define RING_PP_DIR_BASE_READ(base) _MMIO((base) + 0x518)
+#define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550)
+#define EL_CTRL_LOAD REG_BIT(0)
+
+/* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */
+#define GEN8_RING_CS_GPR(base, n) _MMIO((base) + 0x600 + (n) * 8)
+#define GEN8_RING_CS_GPR_UDW(base, n) _MMIO((base) + 0x600 + (n) * 8 + 4)
+
+#define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)
+
+#define VDBOX_CGCTL3F10(base) _MMIO((base) + 0x3f10)
+#define IECPUNIT_CLKGATE_DIS REG_BIT(22)
+
+#define VDBOX_CGCTL3F18(base) _MMIO((base) + 0x3f18)
+#define ALNUNIT_CLKGATE_DIS REG_BIT(13)
+
+
+#endif /* __INTEL_ENGINE_REGS__ */
#include "intel_context.h"
#include "intel_engine_heartbeat.h"
#include "intel_engine_pm.h"
+#include "intel_engine_regs.h"
#include "intel_engine_stats.h"
#include "intel_execlists_submission.h"
#include "intel_gt.h"
#include "gem/i915_gem_lmem.h"
#include "i915_drv.h"
#include "intel_context.h"
+#include "intel_engine_regs.h"
#include "intel_gt.h"
#include "intel_gt_buffer_pool.h"
#include "intel_gt_clock_utils.h"
}
if (GRAPHICS_VER(i915) <= 7)
- sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
- &rc6vids, NULL);
+ snb_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
seq_printf(m, "RC1e Enabled: %s\n",
yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
wakeref = intel_runtime_pm_get(gt->uncore->rpm);
for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
ia_freq = gpu_freq;
- sandybridge_pcode_read(i915,
- GEN6_PCODE_READ_MIN_FREQ_TABLE,
- &ia_freq, NULL);
+ snb_pcode_read(i915, GEN6_PCODE_READ_MIN_FREQ_TABLE,
+ &ia_freq, NULL);
seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
intel_gpu_freq(rps,
(gpu_freq *
unsigned int ia_freq, ring_freq;
calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq);
- sandybridge_pcode_write(i915,
- GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
- ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
- ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
- gpu_freq);
+ snb_pcode_write(i915, GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
+ ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
+ ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
+ gpu_freq);
}
}
#include "i915_drv.h"
#include "i915_perf.h"
#include "intel_engine.h"
+#include "intel_engine_regs.h"
#include "intel_gpu_commands.h"
#include "intel_gt.h"
#include "intel_lrc.h"
#define GEN8_EXECLISTS_STATUS_BUF 0x370
#define GEN11_EXECLISTS_STATUS_BUF2 0x3c0
-/* Execlists regs */
-#define RING_ELSP(base) _MMIO((base) + 0x230)
-#define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234)
-#define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4)
-#define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244)
-#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0)
-#define CTX_CTRL_RS_CTX_ENABLE REG_BIT(1)
-#define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT REG_BIT(2)
-#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3)
-#define GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE REG_BIT(8)
-#define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0)
-#define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510)
-#define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550)
-#define EL_CTRL_LOAD REG_BIT(0)
-
/*
* The docs specify that the write pointer wraps around after 5h, "After status
* is written out to the last available status QW at offset 5h, this pointer
#include "i915_drv.h"
#include "i915_vgpu.h"
+#include "intel_engine_regs.h"
#include "intel_gt.h"
#include "intel_gt_pm.h"
#include "intel_pcode.h"
GEN6_RC_CTL_HW_ENABLE;
rc6vids = 0;
- ret = sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
- &rc6vids, NULL);
+ ret = snb_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
if (GRAPHICS_VER(i915) == 6 && ret) {
drm_dbg(&i915->drm, "Couldn't check for BIOS workaround\n");
} else if (GRAPHICS_VER(i915) == 6 &&
GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
rc6vids &= 0xffff00;
rc6vids |= GEN6_ENCODE_RC6_VID(450);
- ret = sandybridge_pcode_write(i915, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
+ ret = snb_pcode_write(i915, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
if (ret)
drm_err(&i915->drm,
"Couldn't fix incorrect rc6 voltage\n");
enable_rc6 = false;
}
- if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1 &&
- (intel_uncore_read(uncore, PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1 &&
- (intel_uncore_read(uncore, PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1 &&
- (intel_uncore_read(uncore, PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1)) {
+ if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT(RENDER_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
+ (intel_uncore_read(uncore, PWRCTX_MAXCNT(GEN6_BSD_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
+ (intel_uncore_read(uncore, PWRCTX_MAXCNT(BLT_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
+ (intel_uncore_read(uncore, PWRCTX_MAXCNT(VEBOX_RING_BASE)) & IDLE_TIME_MASK) > 1)) {
drm_dbg(&i915->drm,
"Engine Idle wait time not set properly.\n");
enable_rc6 = false;
#include "i915_irq.h"
#include "intel_breadcrumbs.h"
#include "intel_engine_pm.h"
+#include "intel_engine_regs.h"
#include "intel_gt.h"
#include "intel_gt_pm.h"
#include "intel_gt_requests.h"
+#include "intel_pci_config.h"
#include "intel_reset.h"
#include "uc/intel_guc.h"
#include "i915_drv.h"
#include "i915_vma.h"
#include "intel_engine.h"
+#include "intel_engine_regs.h"
#include "intel_gpu_commands.h"
#include "intel_ring.h"
#include "intel_timeline.h"
#include "i915_mitigations.h"
#include "intel_breadcrumbs.h"
#include "intel_context.h"
+#include "intel_engine_regs.h"
#include "intel_gt.h"
#include "intel_gt_irq.h"
#include "intel_reset.h"
/* Disable notification that the ring is IDLE. The GT
* will then assume that it is busy and bring it out of rc6.
*/
- intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL,
- _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
+ intel_uncore_write_fw(uncore, RING_PSMI_CTL(GEN6_BSD_RING_BASE),
+ _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
/* Clear the context id. Here be magic! */
intel_uncore_write64_fw(uncore, GEN6_BSD_RNCID, 0x0);
/* Wait for the ring not to be idle, i.e. for it to wake up. */
if (__intel_wait_for_register_fw(uncore,
- GEN6_BSD_SLEEP_PSMI_CONTROL,
+ RING_PSMI_CTL(GEN6_BSD_RING_BASE),
GEN6_BSD_SLEEP_INDICATOR,
0,
1000, 0, NULL))
/* Let the ring send IDLE messages to the GT again,
* and so let it sleep to conserve power when idle.
*/
- intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL,
- _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
+ intel_uncore_write_fw(uncore, RING_PSMI_CTL(GEN6_BSD_RING_BASE),
+ _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
}
#include <drm/i915_drm.h>
#include "i915_drv.h"
+#include "i915_irq.h"
#include "intel_breadcrumbs.h"
#include "intel_gt.h"
#include "intel_gt_clock_utils.h"
IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) {
u32 ddcc_status = 0;
- if (sandybridge_pcode_read(i915,
- HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
- &ddcc_status, NULL) == 0)
+ if (snb_pcode_read(i915, HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
+ &ddcc_status, NULL) == 0)
rps->efficient_freq =
clamp_t(u8,
(ddcc_status >> 8) & 0xff,
if (GRAPHICS_VER(i915) == 6 || IS_IVYBRIDGE(i915) || IS_HASWELL(i915)) {
u32 params = 0;
- sandybridge_pcode_read(i915, GEN6_READ_OC_PARAMS,
- ¶ms, NULL);
+ snb_pcode_read(i915, GEN6_READ_OC_PARAMS, ¶ms, NULL);
if (params & BIT(31)) { /* OC supported */
drm_dbg(&i915->drm,
"Overclocking supported, max: %dMHz, overclock: %dMHz\n",
#include "i915_drv.h"
#include "intel_context.h"
#include "intel_engine_pm.h"
+#include "intel_engine_regs.h"
#include "intel_gpu_commands.h"
#include "intel_gt.h"
#include "intel_ring.h"
* For DG1 this only applies to A0.
*/
wa_masked_en(wal,
- GEN6_RC_SLEEP_PSMI_CONTROL,
+ RING_PSMI_CTL(RENDER_RING_BASE),
GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
GEN8_RC_SEMA_IDLE_MSG_DISABLE);
}
if (GRAPHICS_VER(i915) == 7) {
/* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
wa_masked_en(wal,
- GFX_MODE_GEN7,
+ RING_MODE_GEN7(RENDER_RING_BASE),
GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE);
/* WaDisable_RenderCache_OperationalFlush:ivb,vlv,hsw */
* they are already accustomed to from before contexts were
* enabled.
*/
- wa_add(wal, ECOSKPD,
+ wa_add(wal, ECOSKPD(RENDER_RING_BASE),
0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE),
0 /* XXX bit doesn't stick on Broadwater */,
true);
#include <linux/sort.h>
#include "i915_selftest.h"
+#include "intel_engine_regs.h"
#include "intel_gpu_commands.h"
#include "intel_gt_clock_utils.h"
#include "selftest_engine.h"
#include <linux/sort.h>
+#include "intel_engine_regs.h"
#include "intel_gt_clock_utils.h"
#include "selftest_llc.h"
#include "gem/i915_gem_context.h"
+#include "i915_gem_evict.h"
#include "intel_gt.h"
#include "intel_engine_heartbeat.h"
#include "intel_engine_pm.h"
calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq);
val = gpu_freq;
- if (sandybridge_pcode_read(i915,
- GEN6_PCODE_READ_MIN_FREQ_TABLE,
- &val, NULL)) {
+ if (snb_pcode_read(i915, GEN6_PCODE_READ_MIN_FREQ_TABLE,
+ &val, NULL)) {
pr_err("Failed to read freq table[%d], range [%d, %d]\n",
gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq);
err = -ENXIO;
#include "intel_engine_heartbeat.h"
#include "intel_engine_pm.h"
+#include "intel_engine_regs.h"
#include "intel_gpu_commands.h"
#include "intel_gt_clock_utils.h"
#include "intel_gt_pm.h"
for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
int ia_freq = gpu_freq;
- sandybridge_pcode_read(i915,
- GEN6_PCODE_READ_MIN_FREQ_TABLE,
- &ia_freq, NULL);
+ snb_pcode_read(i915, GEN6_PCODE_READ_MIN_FREQ_TABLE,
+ &ia_freq, NULL);
pr_info("%5d %5d %5d\n",
gpu_freq * 50,
#include "intel_context.h"
#include "intel_engine_heartbeat.h"
#include "intel_engine_pm.h"
+#include "intel_engine_regs.h"
#include "intel_gpu_commands.h"
#include "intel_gt.h"
#include "intel_gt_requests.h"
#include "intel_guc_ads.h"
#include "intel_guc_submission.h"
#include "i915_drv.h"
+#include "i915_irq.h"
/**
* DOC: GuC
#include <linux/bsearch.h>
+#include "gt/intel_engine_regs.h"
#include "gt/intel_gt.h"
#include "gt/intel_lrc.h"
#include "gt/shmem_utils.h"
#include "gt/intel_gt.h"
#include "i915_drv.h"
+#include "i915_irq.h"
#include "i915_memcpy.h"
#include "intel_guc_log.h"
#include "gt/gen8_engine_cs.h"
#include "gt/intel_breadcrumbs.h"
#include "gt/intel_context.h"
-#include "gt/intel_engine_pm.h"
#include "gt/intel_engine_heartbeat.h"
+#include "gt/intel_engine_pm.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_gpu_commands.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_clock_utils.h"
#include <linux/slab.h>
#include "i915_drv.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_gpu_commands.h"
#include "gt/intel_lrc.h"
#include "gt/intel_ring.h"
int mi_user_interrupt;
};
-static struct cmd_interrupt_event cmd_interrupt_events[] = {
+static const struct cmd_interrupt_event cmd_interrupt_events[] = {
[RCS0] = {
.pipe_control_notify = RCS_PIPE_CONTROL,
.mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
for_each_pipe(dev_priv, pipe) {
vgpu_vreg_t(vgpu, PIPECONF(pipe)) &=
- ~(PIPECONF_ENABLE | I965_PIPECONF_ACTIVE);
- vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
+ ~(PIPECONF_ENABLE | PIPECONF_STATE_ENABLE);
+ vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE;
vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
- vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;
+ vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK;
vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
}
* setup_virtual_dp_monitor.
*/
vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
- vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= I965_PIPECONF_ACTIVE;
+ vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_STATE_ENABLE;
/*
* Golden M/N are calculated based on:
* DP link clk 1620 MHz and non-constant_n.
* TODO: calculate DP link symbol clk and stream clk m/n.
*/
- vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
+ vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = TU_SIZE(64);
vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
* DP link clk 1620 MHz and non-constant_n.
* TODO: calculate DP link symbol clk and stream clk m/n.
*/
- vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
+ vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = TU_SIZE(64);
vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
/* Disable Primary/Sprite/Cursor plane */
for_each_pipe(dev_priv, pipe) {
- vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
+ vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE;
vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
- vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;
+ vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK;
vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
}
if (vgpu && vgpu->active && !list_empty(&vgpu->dmabuf_obj_list_head)) {
list_for_each(pos, &vgpu->dmabuf_obj_list_head) {
- dmabuf_obj = container_of(pos,
- struct intel_vgpu_dmabuf_obj, list);
+ dmabuf_obj = list_entry(pos, struct intel_vgpu_dmabuf_obj, list);
if (dmabuf_obj == obj) {
list_del(pos);
intel_gvt_hypervisor_put_vfio_device(vgpu);
struct intel_vgpu_dmabuf_obj *ret = NULL;
list_for_each(pos, &vgpu->dmabuf_obj_list_head) {
- dmabuf_obj = container_of(pos, struct intel_vgpu_dmabuf_obj,
- list);
- if ((dmabuf_obj == NULL) ||
- (dmabuf_obj->info == NULL))
+ dmabuf_obj = list_entry(pos, struct intel_vgpu_dmabuf_obj, list);
+ if (!dmabuf_obj->info)
continue;
fb_info = (struct intel_vgpu_fb_info *)dmabuf_obj->info;
struct intel_vgpu_dmabuf_obj *ret = NULL;
list_for_each(pos, &vgpu->dmabuf_obj_list_head) {
- dmabuf_obj = container_of(pos, struct intel_vgpu_dmabuf_obj,
- list);
- if (!dmabuf_obj)
- continue;
-
+ dmabuf_obj = list_entry(pos, struct intel_vgpu_dmabuf_obj, list);
if (dmabuf_obj->dmabuf_id == id) {
ret = dmabuf_obj;
break;
mutex_lock(&vgpu->dmabuf_lock);
list_for_each_safe(pos, n, &vgpu->dmabuf_obj_list_head) {
- dmabuf_obj = container_of(pos, struct intel_vgpu_dmabuf_obj,
- list);
+ dmabuf_obj = list_entry(pos, struct intel_vgpu_dmabuf_obj, list);
dmabuf_obj->vgpu = NULL;
idr_remove(&vgpu->object_idr, dmabuf_obj->dmabuf_id);
#define PRIMARY_FORMAT_NUM 16
struct pixel_format {
- int drm_format; /* Pixel format in DRM definition */
- int bpp; /* Bits per pixel, 0 indicates invalid */
- char *desc; /* The description */
+ int drm_format; /* Pixel format in DRM definition */
+ int bpp; /* Bits per pixel, 0 indicates invalid */
+ const char *desc; /* The description */
};
-static struct pixel_format bdw_pixel_formats[] = {
+static const struct pixel_format bdw_pixel_formats[] = {
{DRM_FORMAT_C8, 8, "8-bit Indexed"},
{DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
{DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
{0, 0, NULL},
};
-static struct pixel_format skl_pixel_formats[] = {
+static const struct pixel_format skl_pixel_formats[] = {
{DRM_FORMAT_YUYV, 16, "16-bit packed YUYV (8:8:8:8 MSB-V:Y2:U:Y1)"},
{DRM_FORMAT_UYVY, 16, "16-bit packed UYVY (8:8:8:8 MSB-Y2:V:Y1:U)"},
{DRM_FORMAT_YVYU, 16, "16-bit packed YVYU (8:8:8:8 MSB-U:Y2:V:Y1)"},
int bdw_pixel_formats_index = 6;
switch (format) {
- case DISPPLANE_8BPP:
+ case DISP_FORMAT_8BPP:
bdw_pixel_formats_index = 0;
break;
- case DISPPLANE_BGRX565:
+ case DISP_FORMAT_BGRX565:
bdw_pixel_formats_index = 1;
break;
- case DISPPLANE_BGRX888:
+ case DISP_FORMAT_BGRX888:
bdw_pixel_formats_index = 2;
break;
- case DISPPLANE_RGBX101010:
+ case DISP_FORMAT_RGBX101010:
bdw_pixel_formats_index = 3;
break;
- case DISPPLANE_BGRX101010:
+ case DISP_FORMAT_BGRX101010:
bdw_pixel_formats_index = 4;
break;
- case DISPPLANE_RGBX888:
+ case DISP_FORMAT_RGBX888:
bdw_pixel_formats_index = 5;
break;
return -ENODEV;
val = vgpu_vreg_t(vgpu, DSPCNTR(pipe));
- plane->enabled = !!(val & DISPLAY_PLANE_ENABLE);
+ plane->enabled = !!(val & DISP_ENABLE);
if (!plane->enabled)
return -ENODEV;
if (GRAPHICS_VER(dev_priv) >= 9) {
plane->tiled = val & PLANE_CTL_TILED_MASK;
fmt = skl_format_to_drm(
- val & PLANE_CTL_FORMAT_MASK,
+ val & PLANE_CTL_FORMAT_MASK_SKL,
val & PLANE_CTL_ORDER_RGBX,
val & PLANE_CTL_ALPHA_MASK,
val & PLANE_CTL_YUV422_ORDER_MASK);
plane->bpp = skl_pixel_formats[fmt].bpp;
plane->drm_format = skl_pixel_formats[fmt].drm_format;
} else {
- plane->tiled = val & DISPPLANE_TILED;
- fmt = bdw_format_to_drm(val & DISPPLANE_PIXFORMAT_MASK);
+ plane->tiled = val & DISP_TILED;
+ fmt = bdw_format_to_drm(val & DISP_FORMAT_MASK);
plane->bpp = bdw_pixel_formats[fmt].bpp;
plane->drm_format = bdw_pixel_formats[fmt].drm_format;
}
#define CURSOR_FORMAT_NUM (1 << 6)
struct cursor_mode_format {
- int drm_format; /* Pixel format in DRM definition */
- u8 bpp; /* Bits per pixel; 0 indicates invalid */
- u32 width; /* In pixel */
- u32 height; /* In lines */
- char *desc; /* The description */
+ int drm_format; /* Pixel format in DRM definition */
+ u8 bpp; /* Bits per pixel; 0 indicates invalid */
+ u32 width; /* In pixel */
+ u32 height; /* In lines */
+ const char *desc; /* The description */
};
-static struct cursor_mode_format cursor_pixel_formats[] = {
+static const struct cursor_mode_format cursor_pixel_formats[] = {
{DRM_FORMAT_ARGB8888, 32, 128, 128, "128x128 32bpp ARGB"},
{DRM_FORMAT_ARGB8888, 32, 256, 256, "256x256 32bpp ARGB"},
{DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
return -ENODEV;
val = vgpu_vreg_t(vgpu, CURCNTR(pipe));
- mode = val & MCURSOR_MODE;
+ mode = val & MCURSOR_MODE_MASK;
plane->enabled = (mode != MCURSOR_MODE_DISABLE);
if (!plane->enabled)
return -ENODEV;
#define SPRITE_FORMAT_NUM (1 << 3)
-static struct pixel_format sprite_pixel_formats[SPRITE_FORMAT_NUM] = {
+static const struct pixel_format sprite_pixel_formats[SPRITE_FORMAT_NUM] = {
[0x0] = {DRM_FORMAT_YUV422, 16, "YUV 16-bit 4:2:2 packed"},
[0x1] = {DRM_FORMAT_XRGB2101010, 32, "RGB 32-bit 2:10:10:10"},
[0x2] = {DRM_FORMAT_XRGB8888, 32, "RGB 32-bit 8:8:8:8"},
yuv_order = (val & SPRITE_YUV_ORDER_MASK) >>
_SPRITE_YUV_ORDER_SHIFT;
- fmt = (val & SPRITE_PIXFORMAT_MASK) >> _SPRITE_FMT_SHIFT;
+ fmt = (val & SPRITE_FORMAT_MASK) >> _SPRITE_FMT_SHIFT;
if (!sprite_pixel_formats[fmt].bpp) {
gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
return -EINVAL;
.pse_entry_type = pse_type, \
}
-static struct gtt_type_table_entry gtt_type_table[] = {
+static const struct gtt_type_table_entry gtt_type_table[] = {
GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
GTT_TYPE_INVALID,
DEFINE_PPGTT_GMA_TO_INDEX(gen8, l4_pdp, (gma >> 30 & 0x1ff));
DEFINE_PPGTT_GMA_TO_INDEX(gen8, pml4, (gma >> 39 & 0x1ff));
-static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
+static const struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
.get_entry = gtt_get_entry64,
.set_entry = gtt_set_entry64,
.clear_present = gtt_entry_clear_present,
.set_pfn = gen8_gtt_set_pfn,
};
-static struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops = {
+static const struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops = {
.gma_to_ggtt_pte_index = gma_to_ggtt_pte_index,
.gma_to_pte_index = gen8_gma_to_pte_index,
.gma_to_pde_index = gen8_gma_to_pde_index,
};
/* Update entry type per pse and ips bit. */
-static void update_entry_type_for_real(struct intel_gvt_gtt_pte_ops *pte_ops,
+static void update_entry_type_for_real(const struct intel_gvt_gtt_pte_ops *pte_ops,
struct intel_gvt_gtt_entry *entry, bool ips)
{
switch (entry->type) {
struct intel_gvt_gtt_entry *entry, unsigned long index,
bool guest)
{
- struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
GEM_BUG_ON(mm->type != INTEL_GVT_MM_PPGTT);
struct intel_gvt_gtt_entry *entry, unsigned long index,
bool guest)
{
- struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
pte_ops->set_entry(guest ? mm->ppgtt_mm.guest_pdps :
mm->ppgtt_mm.shadow_pdps,
static void ggtt_get_guest_entry(struct intel_vgpu_mm *mm,
struct intel_gvt_gtt_entry *entry, unsigned long index)
{
- struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
static void ggtt_set_guest_entry(struct intel_vgpu_mm *mm,
struct intel_gvt_gtt_entry *entry, unsigned long index)
{
- struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
static void ggtt_get_host_entry(struct intel_vgpu_mm *mm,
struct intel_gvt_gtt_entry *entry, unsigned long index)
{
- struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
static void ggtt_set_host_entry(struct intel_vgpu_mm *mm,
struct intel_gvt_gtt_entry *entry, unsigned long index)
{
- struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
unsigned long offset = index;
GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
bool guest)
{
struct intel_gvt *gvt = spt->vgpu->gvt;
- struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
int ret;
e->type = get_entry_type(type);
bool guest)
{
struct intel_gvt *gvt = spt->vgpu->gvt;
- struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
return -EINVAL;
struct intel_gvt_gtt_entry *e)
{
struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
- struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
struct intel_vgpu_ppgtt_spt *s;
enum intel_gvt_gtt_type cur_pt_type;
struct intel_gvt_gtt_entry *entry)
{
struct intel_vgpu *vgpu = spt->vgpu;
- struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
unsigned long pfn;
int type;
static struct intel_vgpu_ppgtt_spt *ppgtt_populate_spt_by_guest_entry(
struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *we)
{
- struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
struct intel_vgpu_ppgtt_spt *spt = NULL;
bool ips = false;
int ret;
static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se,
struct intel_vgpu_ppgtt_spt *s, struct intel_gvt_gtt_entry *ge)
{
- struct intel_gvt_gtt_pte_ops *ops = s->vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = s->vgpu->gvt->gtt.pte_ops;
se->type = ge->type;
se->val64 = ge->val64;
static int is_2MB_gtt_possible(struct intel_vgpu *vgpu,
struct intel_gvt_gtt_entry *entry)
{
- struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
unsigned long pfn;
if (!HAS_PAGE_SIZES(vgpu->gvt->gt->i915, I915_GTT_PAGE_SIZE_2M))
struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
struct intel_gvt_gtt_entry *se)
{
- struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
struct intel_vgpu_ppgtt_spt *sub_spt;
struct intel_gvt_gtt_entry sub_se;
unsigned long start_gfn;
struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
struct intel_gvt_gtt_entry *se)
{
- struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
struct intel_gvt_gtt_entry entry = *se;
unsigned long start_gfn;
dma_addr_t dma_addr;
struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
struct intel_gvt_gtt_entry *ge)
{
- struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
struct intel_gvt_gtt_entry se = *ge;
unsigned long gfn, page_size = PAGE_SIZE;
dma_addr_t dma_addr;
{
struct intel_vgpu *vgpu = spt->vgpu;
struct intel_gvt *gvt = vgpu->gvt;
- struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
struct intel_vgpu_ppgtt_spt *s;
struct intel_gvt_gtt_entry se, ge;
unsigned long gfn, i;
struct intel_gvt_gtt_entry *se, unsigned long index)
{
struct intel_vgpu *vgpu = spt->vgpu;
- struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
int ret;
trace_spt_guest_change(spt->vgpu->id, "remove", spt,
{
const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
struct intel_gvt *gvt = vgpu->gvt;
- struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
struct intel_vgpu_ppgtt_spt *spt = oos_page->spt;
struct intel_gvt_gtt_entry old, new;
int index;
{
struct intel_vgpu *vgpu = spt->vgpu;
int type = spt->shadow_page.type;
- struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
struct intel_gvt_gtt_entry old_se;
int new_present;
int i, ret;
u64 pa, void *p_data, int bytes)
{
struct intel_vgpu *vgpu = spt->vgpu;
- struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
struct intel_gvt_gtt_entry we, se;
unsigned long index;
struct intel_vgpu *vgpu = mm->vgpu;
struct intel_gvt *gvt = vgpu->gvt;
struct intel_gvt_gtt *gtt = &gvt->gtt;
- struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
struct intel_gvt_gtt_entry se;
int index;
struct intel_vgpu *vgpu = mm->vgpu;
struct intel_gvt *gvt = vgpu->gvt;
struct intel_gvt_gtt *gtt = &gvt->gtt;
- struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
struct intel_vgpu_ppgtt_spt *spt;
struct intel_gvt_gtt_entry ge, se;
int index, ret;
struct intel_gvt_gtt_entry *e, unsigned long index, bool guest)
{
struct intel_vgpu *vgpu = mm->vgpu;
- struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
struct intel_vgpu_ppgtt_spt *s;
s = intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(e));
{
struct intel_vgpu *vgpu = mm->vgpu;
struct intel_gvt *gvt = vgpu->gvt;
- struct intel_gvt_gtt_pte_ops *pte_ops = gvt->gtt.pte_ops;
- struct intel_gvt_gtt_gma_ops *gma_ops = gvt->gtt.gma_ops;
+ const struct intel_gvt_gtt_pte_ops *pte_ops = gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_gma_ops *gma_ops = gvt->gtt.gma_ops;
unsigned long gpa = INTEL_GVT_INVALID_ADDR;
unsigned long gma_index[4];
struct intel_gvt_gtt_entry e;
static void ggtt_invalidate_pte(struct intel_vgpu *vgpu,
struct intel_gvt_gtt_entry *entry)
{
- struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
unsigned long pfn;
pfn = pte_ops->get_pfn(entry);
struct intel_gvt *gvt = vgpu->gvt;
const struct intel_gvt_device_info *info = &gvt->device_info;
struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm;
- struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
unsigned long g_gtt_index = off >> info->gtt_entry_size_shift;
unsigned long gma, gfn;
struct intel_gvt_gtt_entry e = {.val64 = 0, .type = GTT_TYPE_GGTT_PTE};
{
struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
struct intel_vgpu_gtt *gtt = &vgpu->gtt;
- struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
int page_entry_num = I915_GTT_PAGE_SIZE >>
vgpu->gvt->device_info.gtt_entry_size_shift;
void *scratch_pt;
void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old)
{
struct intel_gvt *gvt = vgpu->gvt;
- struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
struct intel_gvt_gtt_entry entry = {.type = GTT_TYPE_GGTT_PTE};
struct intel_gvt_gtt_entry old_entry;
u32 index;
};
struct intel_gvt_gtt {
- struct intel_gvt_gtt_pte_ops *pte_ops;
- struct intel_gvt_gtt_gma_ops *gma_ops;
+ const struct intel_gvt_gtt_pte_ops *pte_ops;
+ const struct intel_gvt_gtt_gma_ops *gma_ops;
int (*mm_alloc_page_table)(struct intel_vgpu_mm *mm);
void (*mm_free_page_table)(struct intel_vgpu_mm *mm);
struct list_head oos_page_use_list_head;
/* Value of command write of this reg needs to be patched */
#define F_CMD_WRITE_PATCH (1 << 8)
- struct gvt_mmio_block *mmio_block;
+ const struct gvt_mmio_block *mmio_block;
unsigned int num_mmio_block;
DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS);
#include "gvt.h"
#include "i915_pvinfo.h"
#include "display/intel_display_types.h"
+#include "display/intel_fbc.h"
/* XXX FIXME i915 has changed PP_XXX definition */
#define PCH_PP_STATUS _MMIO(0xc7200)
data = vgpu_vreg(vgpu, offset);
if (data & PIPECONF_ENABLE) {
- vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE;
+ vgpu_vreg(vgpu, offset) |= PIPECONF_STATE_ENABLE;
vgpu_update_refresh_rate(vgpu);
vgpu_update_vblank_emulation(vgpu, true);
} else {
- vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE;
+ vgpu_vreg(vgpu, offset) &= ~PIPECONF_STATE_ENABLE;
vgpu_update_vblank_emulation(vgpu, false);
}
return 0;
MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
- MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
- MMIO_D(ILK_DPFC_CONTROL, D_ALL);
- MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
- MMIO_D(ILK_DPFC_STATUS, D_ALL);
- MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
- MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
+ MMIO_D(ILK_DPFC_CB_BASE(INTEL_FBC_A), D_ALL);
+ MMIO_D(ILK_DPFC_CONTROL(INTEL_FBC_A), D_ALL);
+ MMIO_D(ILK_DPFC_RECOMP_CTL(INTEL_FBC_A), D_ALL);
+ MMIO_D(ILK_DPFC_STATUS(INTEL_FBC_A), D_ALL);
+ MMIO_D(ILK_DPFC_FENCE_YOFF(INTEL_FBC_A), D_ALL);
+ MMIO_D(ILK_DPFC_CHICKEN(INTEL_FBC_A), D_ALL);
MMIO_D(ILK_FBC_RT_BASE, D_ALL);
MMIO_D(IPS_CTL, D_ALL);
MMIO_D(_MMIO(0x3c), D_ALL);
MMIO_D(_MMIO(0x860), D_ALL);
- MMIO_D(ECOSKPD, D_ALL);
+ MMIO_D(ECOSKPD(RENDER_RING_BASE), D_ALL);
MMIO_D(_MMIO(0x121d0), D_ALL);
- MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
+ MMIO_D(ECOSKPD(BLT_RING_BASE), D_ALL);
MMIO_D(_MMIO(0x41d0), D_ALL);
MMIO_D(GAC_ECO_BITS, D_ALL);
MMIO_D(_MMIO(0x6200), D_ALL);
MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
+ MMIO_DFH(_MMIO(0xe4cc), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
return 0;
}
return 0;
}
-static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
- unsigned int offset)
+static const struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
+ unsigned int offset)
{
unsigned long device = intel_gvt_get_device_type(gvt);
- struct gvt_mmio_block *block = gvt->mmio.mmio_block;
+ const struct gvt_mmio_block *block = gvt->mmio.mmio_block;
int num = gvt->mmio.num_mmio_block;
int i;
* accessible (should have no F_CMD_ACCESS flag).
* otherwise, need to update cmd_reg_handler in cmd_parser.c
*/
-static struct gvt_mmio_block mmio_blocks[] = {
+static const struct gvt_mmio_block mmio_blocks[] = {
{D_SKL_PLUS, _MMIO(DMC_MMIO_START_RANGE), 0x3000, NULL, NULL},
{D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL},
{D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE,
int (*handler)(struct intel_gvt *gvt, u32 offset, void *data),
void *data)
{
- struct gvt_mmio_block *block = gvt->mmio.mmio_block;
+ const struct gvt_mmio_block *block = gvt->mmio.mmio_block;
struct intel_gvt_mmio_info *e;
int i, j, ret;
struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
struct intel_gvt *gvt = vgpu->gvt;
struct intel_gvt_mmio_info *mmio_info;
- struct gvt_mmio_block *mmio_block;
+ const struct gvt_mmio_block *mmio_block;
gvt_mmio_func func;
int ret;
unsigned int reg, void *p_data, unsigned int bytes)
{
struct intel_gvt *gvt = vgpu->gvt;
- struct intel_gvt_irq_ops *ops = gvt->irq.ops;
+ const struct intel_gvt_irq_ops *ops = gvt->irq.ops;
u32 imr = *(u32 *)p_data;
trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg),
unsigned int reg, void *p_data, unsigned int bytes)
{
struct intel_gvt *gvt = vgpu->gvt;
- struct intel_gvt_irq_ops *ops = gvt->irq.ops;
+ const struct intel_gvt_irq_ops *ops = gvt->irq.ops;
u32 ier = *(u32 *)p_data;
u32 virtual_ier = vgpu_vreg(vgpu, reg);
{
struct intel_gvt *gvt = vgpu->gvt;
struct drm_i915_private *i915 = gvt->gt->i915;
- struct intel_gvt_irq_ops *ops = gvt->irq.ops;
+ const struct intel_gvt_irq_ops *ops = gvt->irq.ops;
struct intel_gvt_irq_info *info;
u32 ier = *(u32 *)p_data;
SET_BIT_INFO(irq, 25, PCU_PCODE2DRIVER_MAILBOX, INTEL_GVT_IRQ_INFO_PCU);
}
-static struct intel_gvt_irq_ops gen8_irq_ops = {
+static const struct intel_gvt_irq_ops gen8_irq_ops = {
.init_irq = gen8_init_irq,
.check_pending_irq = gen8_check_pending_irq,
};
struct intel_gvt *gvt = vgpu->gvt;
struct intel_gvt_irq *irq = &gvt->irq;
gvt_event_virt_handler_t handler;
- struct intel_gvt_irq_ops *ops = gvt->irq.ops;
+ const struct intel_gvt_irq_ops *ops = gvt->irq.ops;
handler = get_event_virt_handler(irq, event);
drm_WARN_ON(&i915->drm, !handler);
/* structure containing device specific IRQ state */
struct intel_gvt_irq {
- struct intel_gvt_irq_ops *ops;
+ const struct intel_gvt_irq_ops *ops;
struct intel_gvt_irq_info *info[INTEL_GVT_IRQ_INFO_MAX];
DECLARE_BITMAP(irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX);
struct intel_gvt_event_info events[INTEL_GVT_EVENT_MAX];
#include "i915_drv.h"
#include "gt/intel_context.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_gpu_commands.h"
#include "gt/intel_ring.h"
#include "gvt.h"
/* Raw offset is appened to each line for convenience. */
static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
- {RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
+ {RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */
{RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
{RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
{RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
};
static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
- {RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
+ {RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */
{RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
{RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
{RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
#include <linux/types.h>
+#include "gt/intel_engine_regs.h"
#include "gt/intel_engine_types.h"
#include "gt/intel_lrc_reg.h"
#include "i915_reg.h"
#define SKL_FLIP_EVENT(pipe, plane) (PRIMARY_A_FLIP_DONE + (plane) * 3 + (pipe))
-#define PLANE_CTL_ASYNC_FLIP (1 << 9)
#define REG50080_FLIP_TYPE_MASK 0x3
#define REG50080_FLIP_TYPE_ASYNC 0x1
vgpu_data->active = false;
}
-static struct intel_gvt_sched_policy_ops tbs_schedule_ops = {
+static const struct intel_gvt_sched_policy_ops tbs_schedule_ops = {
.init = tbs_sched_init,
.clean = tbs_sched_clean,
.init_vgpu = tbs_sched_init_vgpu,
wait_queue_head_t waitq[I915_NUM_ENGINES];
void *sched_data;
- struct intel_gvt_sched_policy_ops *sched_ops;
+ const struct intel_gvt_sched_policy_ops *sched_ops;
};
#define INDIRECT_CTX_ADDR_MASK 0xffffffc0
#define VGPU_WEIGHT(vgpu_num) \
(VGPU_MAX_WEIGHT / (vgpu_num))
-static struct {
+static const struct {
unsigned int low_mm;
unsigned int high_mm;
unsigned int fence;
*/
unsigned int weight;
enum intel_vgpu_edid edid;
- char *name;
+ const char *name;
} vgpu_types[] = {
/* Fixed vGPU type table */
{ MB_TO_BYTES(64), MB_TO_BYTES(384), 4, VGPU_WEIGHT(8), GVT_EDID_1024_768, "8" },
*/
#include "gt/intel_engine.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_gpu_commands.h"
+#include "i915_cmd_parser.h"
#include "i915_drv.h"
#include "i915_memcpy.h"
{ .addr = _reg(idx) }, \
{ .addr = _reg ## _UDW(idx) }
+#define REG64_BASE_IDX(_reg, base, idx) \
+ { .addr = _reg(base, idx) }, \
+ { .addr = _reg ## _UDW(base, idx) }
+
static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
REG64(GPGPU_THREADS_DISPATCHED),
REG64(HS_INVOCATION_COUNT),
};
static const struct drm_i915_reg_descriptor hsw_render_regs[] = {
- REG64_IDX(HSW_CS_GPR, 0),
- REG64_IDX(HSW_CS_GPR, 1),
- REG64_IDX(HSW_CS_GPR, 2),
- REG64_IDX(HSW_CS_GPR, 3),
- REG64_IDX(HSW_CS_GPR, 4),
- REG64_IDX(HSW_CS_GPR, 5),
- REG64_IDX(HSW_CS_GPR, 6),
- REG64_IDX(HSW_CS_GPR, 7),
- REG64_IDX(HSW_CS_GPR, 8),
- REG64_IDX(HSW_CS_GPR, 9),
- REG64_IDX(HSW_CS_GPR, 10),
- REG64_IDX(HSW_CS_GPR, 11),
- REG64_IDX(HSW_CS_GPR, 12),
- REG64_IDX(HSW_CS_GPR, 13),
- REG64_IDX(HSW_CS_GPR, 14),
- REG64_IDX(HSW_CS_GPR, 15),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 0),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 1),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 2),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 3),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 4),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 5),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 6),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 7),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 8),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 9),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 10),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 11),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 12),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 13),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 14),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 15),
REG32(HSW_SCRATCH1,
.mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,
.value = 0),
REG32(BCS_SWCTRL),
REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
REG32_IDX(RING_CTX_TIMESTAMP, BLT_RING_BASE),
- REG64_IDX(BCS_GPR, 0),
- REG64_IDX(BCS_GPR, 1),
- REG64_IDX(BCS_GPR, 2),
- REG64_IDX(BCS_GPR, 3),
- REG64_IDX(BCS_GPR, 4),
- REG64_IDX(BCS_GPR, 5),
- REG64_IDX(BCS_GPR, 6),
- REG64_IDX(BCS_GPR, 7),
- REG64_IDX(BCS_GPR, 8),
- REG64_IDX(BCS_GPR, 9),
- REG64_IDX(BCS_GPR, 10),
- REG64_IDX(BCS_GPR, 11),
- REG64_IDX(BCS_GPR, 12),
- REG64_IDX(BCS_GPR, 13),
- REG64_IDX(BCS_GPR, 14),
- REG64_IDX(BCS_GPR, 15),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 0),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 1),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 2),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 3),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 4),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 5),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 6),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 7),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 8),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 9),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 10),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 11),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 12),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 13),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 14),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 15),
};
#undef REG64
--- /dev/null
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef __I915_CMD_PARSER_H__
+#define __I915_CMD_PARSER_H__
+
+#include <linux/types.h>
+
+struct drm_i915_private;
+struct intel_engine_cs;
+struct i915_vma;
+
+int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
+int intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
+void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
+int intel_engine_cmd_parser(struct intel_engine_cs *engine,
+ struct i915_vma *batch,
+ unsigned long batch_offset,
+ unsigned long batch_length,
+ struct i915_vma *shadow,
+ bool trampoline);
+#define I915_CMD_PARSER_TRAMPOLINE_SIZE 8
+
+#endif /* __I915_CMD_PARSER_H__ */
#include "i915_debugfs.h"
#include "i915_driver.h"
#include "i915_drv.h"
+#include "i915_getparam.h"
#include "i915_ioc32.h"
+#include "i915_ioctl.h"
#include "i915_irq.h"
#include "i915_memcpy.h"
#include "i915_perf.h"
#include "intel_dram.h"
#include "intel_gvt.h"
#include "intel_memory_region.h"
+#include "intel_pci_config.h"
#include "intel_pcode.h"
#include "intel_pm.h"
#include "intel_region_ttm.h"
#include "i915_utils.h"
#include "display/intel_bios.h"
+#include "display/intel_cdclk.h"
#include "display/intel_display.h"
#include "display/intel_display_power.h"
#include "display/intel_dmc.h"
#include "display/intel_dpll_mgr.h"
#include "display/intel_dsb.h"
+#include "display/intel_fbc.h"
#include "display/intel_frontbuffer.h"
#include "display/intel_global_state.h"
#include "display/intel_gmbus.h"
#include "i915_scheduler.h"
#include "gt/intel_timeline.h"
#include "i915_vma.h"
-#include "i915_irq.h"
/* General customization:
struct intel_encoder;
struct intel_atomic_state;
struct intel_cdclk_config;
+struct intel_cdclk_funcs;
struct intel_cdclk_state;
struct intel_cdclk_vals;
struct intel_initial_plane_config;
void (*read_luts)(struct intel_crtc_state *crtc_state);
};
-struct intel_cdclk_funcs {
- void (*get_cdclk)(struct drm_i915_private *dev_priv,
- struct intel_cdclk_config *cdclk_config);
- void (*set_cdclk)(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_config *cdclk_config,
- enum pipe pipe);
- int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
- int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
- u8 (*calc_voltage_level)(int cdclk);
-};
-
struct intel_hotplug_funcs {
void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
};
/* Amount of PSF GV points, BSpec precisely defines this */
#define I915_NUM_PSF_GV_POINTS 3
-enum psr_lines_to_wait {
- PSR_0_LINES_TO_WAIT = 0,
- PSR_1_LINE_TO_WAIT,
- PSR_4_LINES_TO_WAIT,
- PSR_8_LINES_TO_WAIT
-};
-
struct intel_vbt_data {
/* bdb version */
u16 version;
bool full_link;
bool require_aux_wakeup;
int idle_frames;
- enum psr_lines_to_wait lines_to_wait;
int tp1_wakeup_time_us;
int tp2_tp3_wakeup_time_us;
int psr2_tp2_tp3_wakeup_time_us;
u32 caps;
};
-struct intel_cdclk_config {
- unsigned int cdclk, vco, ref, bypass;
- u8 voltage_level;
-};
-
struct i915_selftest_stash {
atomic_t counter;
struct ida mock_region_instances;
u32 pipestat_irq_mask[I915_MAX_PIPES];
struct i915_hotplug hotplug;
- struct intel_fbc *fbc;
+ struct intel_fbc *fbc[I915_MAX_FBCS];
struct i915_drrs drrs;
struct intel_opregion opregion;
struct intel_vbt_data vbt;
IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
#define IS_ADLS_RPLS(dev_priv) \
IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL_S)
+#define IS_ADLP_N(dev_priv) \
+ IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv) \
#define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
#define HAS_FW_BLC(dev_priv) (GRAPHICS_VER(dev_priv) > 2)
-#define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
+#define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.fbc_mask != 0)
#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && GRAPHICS_VER(dev_priv) >= 7)
#define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
return IS_CHERRYVIEW(i915) || intel_ggtt_update_needs_vtd_wa(i915);
}
-/* i915_getparam.c */
-int i915_getparam_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv);
-
/* i915_gem.c */
-int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
-void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
void i915_gem_init_early(struct drm_i915_private *dev_priv);
void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
return vm;
}
-/* i915_gem_evict.c */
-int __must_check i915_gem_evict_something(struct i915_address_space *vm,
- u64 min_size, u64 alignment,
- unsigned long color,
- u64 start, u64 end,
- unsigned flags);
-int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
- struct drm_mm_node *node,
- unsigned int flags);
-int i915_gem_evict_vm(struct i915_address_space *vm);
-
/* i915_gem_internal.c */
struct drm_i915_gem_object *
i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
i915_gem_object_is_tiled(obj);
}
-u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
- unsigned int tiling, unsigned int stride);
-u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
- unsigned int tiling, unsigned int stride);
-
const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
-/* i915_cmd_parser.c */
-int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
-int intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
-void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
-int intel_engine_cmd_parser(struct intel_engine_cs *engine,
- struct i915_vma *batch,
- unsigned long batch_offset,
- unsigned long batch_length,
- struct i915_vma *shadow,
- bool trampoline);
-#define I915_CMD_PARSER_TRAMPOLINE_SIZE 8
-
/* intel_device_info.c */
static inline struct intel_device_info *
mkwrite_device_info(struct drm_i915_private *dev_priv)
return (struct intel_device_info *)INTEL_INFO(dev_priv);
}
-int i915_reg_read_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file);
-
static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
{
if (GRAPHICS_VER(i915) >= 11)
#include "gem/i915_gem_ioctls.h"
#include "gem/i915_gem_mman.h"
#include "gem/i915_gem_region.h"
+#include "gem/i915_gem_userptr.h"
#include "gt/intel_engine_user.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
#include "gt/intel_gt_requests.h"
#include "i915_drv.h"
+#include "i915_gem_evict.h"
#include "i915_trace.h"
I915_SELFTEST_DECLARE(static struct igt_evict_ctl {
--- /dev/null
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef __I915_GEM_EVICT_H__
+#define __I915_GEM_EVICT_H__
+
+#include <linux/types.h>
+
+struct drm_mm_node;
+struct i915_address_space;
+
+int __must_check i915_gem_evict_something(struct i915_address_space *vm,
+ u64 min_size, u64 alignment,
+ unsigned long color,
+ u64 start, u64 end,
+ unsigned flags);
+int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
+ struct drm_mm_node *node,
+ unsigned int flags);
+int i915_gem_evict_vm(struct i915_address_space *vm);
+
+#endif /* __I915_GEM_EVICT_H__ */
#include "gt/intel_gt_requests.h"
#include "i915_drv.h"
+#include "i915_gem_evict.h"
#include "i915_scatterlist.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
#include "gem/i915_gem_mman.h"
#include "gt/intel_engine_user.h"
+#include "i915_cmd_parser.h"
#include "i915_drv.h"
+#include "i915_getparam.h"
#include "i915_perf.h"
int i915_getparam_ioctl(struct drm_device *dev, void *data,
--- /dev/null
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef __I915_GETPARAM_H__
+#define __I915_GETPARAM_H__
+
+struct drm_device;
+struct drm_file;
+
+int i915_getparam_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file_priv);
+
+#endif /* __I915_GETPARAM_H__ */
#include "gem/i915_gem_context.h"
#include "gem/i915_gem_lmem.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
#include <drm/drm_ioctl.h>
#include "i915_drv.h"
+#include "i915_getparam.h"
#include "i915_ioc32.h"
struct drm_i915_getparam32 {
--- /dev/null
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include "gt/intel_engine_regs.h"
+
+#include "i915_drv.h"
+#include "i915_gem.h"
+#include "i915_ioctl.h"
+#include "i915_reg.h"
+#include "intel_runtime_pm.h"
+#include "intel_uncore.h"
+
+/*
+ * This file is for small ioctl functions that are out of place everywhere else,
+ * and not big enough to warrant a file of their own.
+ *
+ * This is not the dumping ground for random ioctls.
+ */
+
+struct reg_whitelist {
+ i915_reg_t offset_ldw;
+ i915_reg_t offset_udw;
+ u8 min_graphics_ver;
+ u8 max_graphics_ver;
+ u8 size;
+};
+
+static const struct reg_whitelist reg_read_whitelist[] = {
+ {
+ .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
+ .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
+ .min_graphics_ver = 4,
+ .max_graphics_ver = 12,
+ .size = 8
+ }
+};
+
+int i915_reg_read_ioctl(struct drm_device *dev,
+ void *data, struct drm_file *unused)
+{
+ struct drm_i915_private *i915 = to_i915(dev);
+ struct intel_uncore *uncore = &i915->uncore;
+ struct drm_i915_reg_read *reg = data;
+ struct reg_whitelist const *entry;
+ intel_wakeref_t wakeref;
+ unsigned int flags;
+ int remain;
+ int ret = 0;
+
+ entry = reg_read_whitelist;
+ remain = ARRAY_SIZE(reg_read_whitelist);
+ while (remain) {
+ u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);
+
+ GEM_BUG_ON(!is_power_of_2(entry->size));
+ GEM_BUG_ON(entry->size > 8);
+ GEM_BUG_ON(entry_offset & (entry->size - 1));
+
+ if (IS_GRAPHICS_VER(i915, entry->min_graphics_ver, entry->max_graphics_ver) &&
+ entry_offset == (reg->offset & -entry->size))
+ break;
+ entry++;
+ remain--;
+ }
+
+ if (!remain)
+ return -EINVAL;
+
+ flags = reg->offset & (entry->size - 1);
+
+ with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
+ if (entry->size == 8 && flags == I915_REG_READ_8B_WA)
+ reg->val = intel_uncore_read64_2x32(uncore,
+ entry->offset_ldw,
+ entry->offset_udw);
+ else if (entry->size == 8 && flags == 0)
+ reg->val = intel_uncore_read64(uncore,
+ entry->offset_ldw);
+ else if (entry->size == 4 && flags == 0)
+ reg->val = intel_uncore_read(uncore, entry->offset_ldw);
+ else if (entry->size == 2 && flags == 0)
+ reg->val = intel_uncore_read16(uncore,
+ entry->offset_ldw);
+ else if (entry->size == 1 && flags == 0)
+ reg->val = intel_uncore_read8(uncore,
+ entry->offset_ldw);
+ else
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
--- /dev/null
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __I915_IOCTL_H__
+#define __I915_IOCTL_H__
+
+struct drm_device;
+struct drm_file;
+
+int i915_reg_read_ioctl(struct drm_device *dev, void *data, struct drm_file *file);
+
+#endif /* __I915_IOCTL_H__ */
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
vtotal /= 2;
- if (DISPLAY_VER(dev_priv) == 2)
- position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
- else
- position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
+ position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & PIPEDSL_LINE_MASK;
/*
* On HSW, the DSL reg (0x70000) appears to return 0 if we
for (i = 0; i < 100; i++) {
udelay(1);
- temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
+ temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & PIPEDSL_LINE_MASK;
if (temp != position) {
position = temp;
break;
static const struct intel_device_info i85x_info = {
I830_FEATURES,
PLATFORM(INTEL_I85X),
- .display.has_fbc = 1,
+ .display.fbc_mask = BIT(INTEL_FBC_A),
};
static const struct intel_device_info i865g_info = {
I845_FEATURES,
PLATFORM(INTEL_I865G),
- .display.has_fbc = 1,
+ .display.fbc_mask = BIT(INTEL_FBC_A),
};
#define GEN3_FEATURES \
.display.has_overlay = 1,
.display.overlay_needs_physical = 1,
.display.supports_tv = 1,
- .display.has_fbc = 1,
+ .display.fbc_mask = BIT(INTEL_FBC_A),
.hws_needs_physical = 1,
.unfenced_needs_alignment = 1,
};
.display.has_overlay = 1,
.display.overlay_needs_physical = 1,
.display.supports_tv = 1,
- .display.has_fbc = 1,
+ .display.fbc_mask = BIT(INTEL_FBC_A),
.hws_needs_physical = 1,
.unfenced_needs_alignment = 1,
};
GEN4_FEATURES,
PLATFORM(INTEL_I965GM),
.is_mobile = 1,
- .display.has_fbc = 1,
+ .display.fbc_mask = BIT(INTEL_FBC_A),
.display.has_overlay = 1,
.display.supports_tv = 1,
.hws_needs_physical = 1,
GEN4_FEATURES,
PLATFORM(INTEL_GM45),
.is_mobile = 1,
- .display.has_fbc = 1,
+ .display.fbc_mask = BIT(INTEL_FBC_A),
.display.supports_tv = 1,
.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
.gpu_reset_clobbers_display = false,
PLATFORM(INTEL_IRONLAKE),
.is_mobile = 1,
.has_rps = true,
- .display.has_fbc = 1,
+ .display.fbc_mask = BIT(INTEL_FBC_A),
};
#define GEN6_FEATURES \
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
.display.has_hotplug = 1, \
- .display.has_fbc = 1, \
+ .display.fbc_mask = BIT(INTEL_FBC_A), \
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
.has_coherent_ggtt = true, \
.has_llc = 1, \
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
.display.has_hotplug = 1, \
- .display.has_fbc = 1, \
+ .display.fbc_mask = BIT(INTEL_FBC_A), \
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
.has_coherent_ggtt = true, \
.has_llc = 1, \
.has_64bit_reloc = 1, \
.display.has_ddi = 1, \
.display.has_fpga_dbg = 1, \
- .display.has_fbc = 1, \
+ .display.fbc_mask = BIT(INTEL_FBC_A), \
.display.has_hdcp = 1, \
.display.has_psr = 1, \
.display.has_psr_hw_tracking = 1, \
.display.has_dp_mst = 1, \
.display.has_dsb = 1, \
.display.has_dsc = 1, \
- .display.has_fbc = 1, \
+ .display.fbc_mask = BIT(INTEL_FBC_A), \
.display.has_fpga_dbg = 1, \
.display.has_hdcp = 1, \
.display.has_hotplug = 1, \
INTEL_RKL_IDS(&rkl_info),
INTEL_ADLS_IDS(&adl_s_info),
INTEL_ADLP_IDS(&adl_p_info),
+ INTEL_ADLN_IDS(&adl_p_info),
INTEL_DG1_IDS(&dg1_info),
INTEL_RPLS_IDS(&adl_s_info),
{0, 0, 0}
#include "gem/i915_gem_context.h"
#include "gt/intel_engine_pm.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_engine_user.h"
#include "gt/intel_execlists_submission.h"
#include "gt/intel_gpu_commands.h"
#include "gt/intel_engine.h"
#include "gt/intel_engine_pm.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_engine_user.h"
#include "gt/intel_gt_pm.h"
#include "gt/intel_rc6.h"
#ifndef _I915_REG_H_
#define _I915_REG_H_
-#include <linux/bitfield.h>
-#include <linux/bits.h>
+#include "i915_reg_defs.h"
/**
* DOC: The i915 register macro definition style guide
* #define GEN8_BAR _MMIO(0xb888)
*/
-/**
- * REG_BIT() - Prepare a u32 bit value
- * @__n: 0-based bit number
- *
- * Local wrapper for BIT() to force u32, with compile time checks.
- *
- * @return: Value with bit @__n set.
- */
-#define REG_BIT(__n) \
- ((u32)(BIT(__n) + \
- BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
- ((__n) < 0 || (__n) > 31))))
-
-/**
- * REG_GENMASK() - Prepare a continuous u32 bitmask
- * @__high: 0-based high bit
- * @__low: 0-based low bit
- *
- * Local wrapper for GENMASK() to force u32, with compile time checks.
- *
- * @return: Continuous bitmask from @__high to @__low, inclusive.
- */
-#define REG_GENMASK(__high, __low) \
- ((u32)(GENMASK(__high, __low) + \
- BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
- __is_constexpr(__low) && \
- ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
-
-/*
- * Local integer constant expression version of is_power_of_2().
- */
-#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
-
-/**
- * REG_FIELD_PREP() - Prepare a u32 bitfield value
- * @__mask: shifted mask defining the field's length and position
- * @__val: value to put in the field
- *
- * Local copy of FIELD_PREP() to generate an integer constant expression, force
- * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
- *
- * @return: @__val masked and shifted into the field defined by @__mask.
- */
-#define REG_FIELD_PREP(__mask, __val) \
- ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
- BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
- BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
- BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
- BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
-
-/**
- * REG_FIELD_GET() - Extract a u32 bitfield value
- * @__mask: shifted mask defining the field's length and position
- * @__val: value to extract the bitfield value from
- *
- * Local wrapper for FIELD_GET() to force u32 and for consistency with
- * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
- *
- * @return: Masked and shifted value of the field defined by @__mask in @__val.
- */
-#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
-
-typedef struct {
- u32 reg;
-} i915_reg_t;
-
-#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
-
-#define INVALID_MMIO_REG _MMIO(0)
-
-static __always_inline u32 i915_mmio_reg_offset(i915_reg_t reg)
-{
- return reg.reg;
-}
-
-static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
-{
- return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
-}
-
-static inline bool i915_mmio_reg_valid(i915_reg_t reg)
-{
- return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
-}
-
#define VLV_DISPLAY_BASE 0x180000
#define VLV_MIPI_BASE VLV_DISPLAY_BASE
#define BXT_MIPI_BASE 0x60000
#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
-/* PCI config space */
-
-#define MCHBAR_I915 0x44
-#define MCHBAR_I965 0x48
-#define MCHBAR_SIZE (4 * 4096)
-
-#define DEVEN 0x54
-#define DEVEN_MCHBAR_EN (1 << 28)
-
-/* BSM in include/drm/i915_drm.h */
-
-#define HPLLCC 0xc0 /* 85x only */
-#define GC_CLOCK_CONTROL_MASK (0x7 << 0)
-#define GC_CLOCK_133_200 (0 << 0)
-#define GC_CLOCK_100_200 (1 << 0)
-#define GC_CLOCK_100_133 (2 << 0)
-#define GC_CLOCK_133_266 (3 << 0)
-#define GC_CLOCK_133_200_2 (4 << 0)
-#define GC_CLOCK_133_266_2 (5 << 0)
-#define GC_CLOCK_166_266 (6 << 0)
-#define GC_CLOCK_166_250 (7 << 0)
-
-#define I915_GDRST 0xc0 /* PCI config register */
-#define GRDOM_FULL (0 << 2)
-#define GRDOM_RENDER (1 << 2)
-#define GRDOM_MEDIA (3 << 2)
-#define GRDOM_MASK (3 << 2)
-#define GRDOM_RESET_STATUS (1 << 1)
-#define GRDOM_RESET_ENABLE (1 << 0)
-
-/* BSpec only has register offset, PCI device and bit found empirically */
-#define I830_CLOCK_GATE 0xc8 /* device 0 */
-#define I830_L2_CACHE_CLOCK_GATE_DISABLE (1 << 2)
-
-#define GCDGMBUS 0xcc
-
-#define GCFGC2 0xda
-#define GCFGC 0xf0 /* 915+ only */
-#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
-#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
-#define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4)
-#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
-#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
-#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
-#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
-#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
-#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
-#define GC_DISPLAY_CLOCK_MASK (7 << 4)
-#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
-#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
-#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
-#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
-#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
-#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
-#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
-#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
-#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
-#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
-#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
-#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
-#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
-#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
-#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
-#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
-#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
-#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
-#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
-
-#define ASLE 0xe4
-#define ASLS 0xfc
-
-#define SWSCI 0xe8
-#define SWSCI_SCISEL (1 << 15)
-#define SWSCI_GSSCIE (1 << 0)
-
-#define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
-
-
#define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
#define ILK_GRDOM_FULL (0 << 1)
#define ILK_GRDOM_RENDER (1 << 1)
#define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
#define GEN12_SFC_DONE_MAX 4
-#define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228)
-#define RING_PP_DIR_BASE_READ(base) _MMIO((base) + 0x518)
-#define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220)
-#define PP_DIR_DCLV_2G 0xffffffff
-
-#define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4)
-#define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8)
-
#define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
#define GEN8_RPCS_ENABLE (1 << 31)
#define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
#define BCS_SRC_Y REG_BIT(0)
#define BCS_DST_Y REG_BIT(1)
-/* There are 16 GPR registers */
-#define BCS_GPR(n) _MMIO(0x22600 + (n) * 8)
-#define BCS_GPR_UDW(n) _MMIO(0x22600 + (n) * 8 + 4)
-
#define GPGPU_THREADS_DISPATCHED _MMIO(0x2290)
#define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4)
#define HS_INVOCATION_COUNT _MMIO(0x2300)
#define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504)
#define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508)
-/* There are the 16 64-bit CS General Purpose Registers */
-#define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8)
-#define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4)
-
#define GEN7_OACONTROL _MMIO(0x2360)
#define GEN7_OACONTROL_CTX_MASK 0xFFFFF000
#define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F
#define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
#define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
-/* See configdb bunit SB addr map */
-#define BUNIT_REG_BISOC 0x11
-
-/* PUNIT_REG_*SSPM0 */
-#define _SSPM0_SSC(val) ((val) << 0)
-#define SSPM0_SSC_MASK _SSPM0_SSC(0x3)
-#define SSPM0_SSC_PWR_ON _SSPM0_SSC(0x0)
-#define SSPM0_SSC_CLK_GATE _SSPM0_SSC(0x1)
-#define SSPM0_SSC_RESET _SSPM0_SSC(0x2)
-#define SSPM0_SSC_PWR_GATE _SSPM0_SSC(0x3)
-#define _SSPM0_SSS(val) ((val) << 24)
-#define SSPM0_SSS_MASK _SSPM0_SSS(0x3)
-#define SSPM0_SSS_PWR_ON _SSPM0_SSS(0x0)
-#define SSPM0_SSS_CLK_GATE _SSPM0_SSS(0x1)
-#define SSPM0_SSS_RESET _SSPM0_SSS(0x2)
-#define SSPM0_SSS_PWR_GATE _SSPM0_SSS(0x3)
-
-/* PUNIT_REG_*SSPM1 */
-#define SSPM1_FREQSTAT_SHIFT 24
-#define SSPM1_FREQSTAT_MASK (0x1f << SSPM1_FREQSTAT_SHIFT)
-#define SSPM1_FREQGUAR_SHIFT 8
-#define SSPM1_FREQGUAR_MASK (0x1f << SSPM1_FREQGUAR_SHIFT)
-#define SSPM1_FREQ_SHIFT 0
-#define SSPM1_FREQ_MASK (0x1f << SSPM1_FREQ_SHIFT)
-
-#define PUNIT_REG_VEDSSPM0 0x32
-#define PUNIT_REG_VEDSSPM1 0x33
-
-#define PUNIT_REG_DSPSSPM 0x36
-#define DSPFREQSTAT_SHIFT_CHV 24
-#define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
-#define DSPFREQGUAR_SHIFT_CHV 8
-#define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
-#define DSPFREQSTAT_SHIFT 30
-#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
-#define DSPFREQGUAR_SHIFT 14
-#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
-#define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */
-#define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */
-#define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */
-#define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
-#define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
-#define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
-#define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
-#define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
-#define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
-#define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
-#define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
-#define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
-#define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
-#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
-#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
-
-#define PUNIT_REG_ISPSSPM0 0x39
-#define PUNIT_REG_ISPSSPM1 0x3a
-
-#define PUNIT_REG_PWRGT_CTRL 0x60
-#define PUNIT_REG_PWRGT_STATUS 0x61
-#define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2))
-#define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2))
-#define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2))
-#define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2))
-#define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2))
-
-#define PUNIT_PWGT_IDX_RENDER 0
-#define PUNIT_PWGT_IDX_MEDIA 1
-#define PUNIT_PWGT_IDX_DISP2D 3
-#define PUNIT_PWGT_IDX_DPIO_CMN_BC 5
-#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6
-#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7
-#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8
-#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9
-#define PUNIT_PWGT_IDX_DPIO_RX0 10
-#define PUNIT_PWGT_IDX_DPIO_RX1 11
-#define PUNIT_PWGT_IDX_DPIO_CMN_D 12
-
-#define PUNIT_REG_GPU_LFM 0xd3
-#define PUNIT_REG_GPU_FREQ_REQ 0xd4
-#define PUNIT_REG_GPU_FREQ_STS 0xd8
-#define GPLLENABLE (1 << 4)
-#define GENFREQSTATUS (1 << 0)
-#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
-#define PUNIT_REG_CZ_TIMESTAMP 0xce
-
-#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
-#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
-
-#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
-#define FB_GFX_FREQ_FUSE_MASK 0xff
-#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
-#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
-#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
-
-#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
-#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
-
-#define PUNIT_REG_DDR_SETUP2 0x139
-#define FORCE_DDR_FREQ_REQ_ACK (1 << 8)
-#define FORCE_DDR_LOW_FREQ (1 << 1)
-#define FORCE_DDR_HIGH_FREQ (1 << 0)
-
-#define PUNIT_GPU_STATUS_REG 0xdb
-#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
-#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
-#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
-#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
-
-#define PUNIT_GPU_DUTYCYCLE_REG 0xdf
-#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
-#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
-
-#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
-#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
-#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
-#define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
-#define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
-#define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
-#define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
-#define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
-#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
-#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
-
-#define VLV_TURBO_SOC_OVERRIDE 0x04
-#define VLV_OVERRIDE_EN 1
-#define VLV_SOC_TDP_EN (1 << 1)
-#define VLV_BIAS_CPU_125_SOC_875 (6 << 2)
-#define CHV_BIAS_CPU_50_SOC_50 (3 << 2)
-
-/* vlv2 north clock has */
-#define CCK_FUSE_REG 0x8
-#define CCK_FUSE_HPLL_FREQ_MASK 0x3
-#define CCK_REG_DSI_PLL_FUSE 0x44
-#define CCK_REG_DSI_PLL_CONTROL 0x48
-#define DSI_PLL_VCO_EN (1 << 31)
-#define DSI_PLL_LDO_GATE (1 << 30)
-#define DSI_PLL_P1_POST_DIV_SHIFT 17
-#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
-#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
-#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
-#define DSI_PLL_MUX_MASK (3 << 9)
-#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
-#define DSI_PLL_MUX_DSI0_CCK (1 << 10)
-#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
-#define DSI_PLL_MUX_DSI1_CCK (1 << 9)
-#define DSI_PLL_CLK_GATE_MASK (0xf << 5)
-#define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
-#define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
-#define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
-#define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
-#define DSI_PLL_LOCK (1 << 0)
-#define CCK_REG_DSI_PLL_DIVIDER 0x4c
-#define DSI_PLL_LFSR (1 << 31)
-#define DSI_PLL_FRACTION_EN (1 << 30)
-#define DSI_PLL_FRAC_COUNTER_SHIFT 27
-#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
-#define DSI_PLL_USYNC_CNT_SHIFT 18
-#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
-#define DSI_PLL_N1_DIV_SHIFT 16
-#define DSI_PLL_N1_DIV_MASK (3 << 16)
-#define DSI_PLL_M1_DIV_SHIFT 0
-#define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
-#define CCK_CZ_CLOCK_CONTROL 0x62
-#define CCK_GPLL_CLOCK_CONTROL 0x67
-#define CCK_DISPLAY_CLOCK_CONTROL 0x6b
-#define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c
-#define CCK_TRUNK_FORCE_ON (1 << 17)
-#define CCK_TRUNK_FORCE_OFF (1 << 16)
-#define CCK_FREQUENCY_STATUS (0x1f << 8)
-#define CCK_FREQUENCY_STATUS_SHIFT 8
-#define CCK_FREQUENCY_VALUES (0x1f << 0)
-
/* DPIO registers */
#define DPIO_DEVFN 0
#define OCL2_LDOFUSE_PWR_DIS (1 << 6)
#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
-/*
- * ICL Port/COMBO-PHY Registers
- */
-#define _ICL_COMBOPHY_A 0x162000
-#define _ICL_COMBOPHY_B 0x6C000
-#define _EHL_COMBOPHY_C 0x160000
-#define _RKL_COMBOPHY_D 0x161000
-#define _ADL_COMBOPHY_E 0x16B000
-
-#define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \
- _ICL_COMBOPHY_B, \
- _EHL_COMBOPHY_C, \
- _RKL_COMBOPHY_D, \
- _ADL_COMBOPHY_E)
-
-/* ICL Port CL_DW registers */
-#define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
- 4 * (dw))
-
-#define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy))
-#define CL_POWER_DOWN_ENABLE (1 << 4)
-#define SUS_CLOCK_CONFIG (3 << 0)
-
-#define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy))
-#define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25)
-#define PG_SEQ_DELAY_OVERRIDE_SHIFT 25
-#define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24)
-#define PWR_UP_ALL_LANES (0x0 << 4)
-#define PWR_DOWN_LN_3_2_1 (0xe << 4)
-#define PWR_DOWN_LN_3_2 (0xc << 4)
-#define PWR_DOWN_LN_3 (0x8 << 4)
-#define PWR_DOWN_LN_2_1_0 (0x7 << 4)
-#define PWR_DOWN_LN_1_0 (0x3 << 4)
-#define PWR_DOWN_LN_3_1 (0xa << 4)
-#define PWR_DOWN_LN_3_1_0 (0xb << 4)
-#define PWR_DOWN_LN_MASK (0xf << 4)
-#define PWR_DOWN_LN_SHIFT 4
-#define EDP4K2K_MODE_OVRD_EN (1 << 3)
-#define EDP4K2K_MODE_OVRD_OPTIMIZED (1 << 2)
-
-#define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))
-#define ICL_LANE_ENABLE_AUX (1 << 0)
-
-/* ICL Port COMP_DW registers */
-#define _ICL_PORT_COMP 0x100
-#define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
- _ICL_PORT_COMP + 4 * (dw))
-
-#define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy))
-#define COMP_INIT (1 << 31)
-
-#define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy))
-
-#define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy))
-#define PROCESS_INFO_DOT_0 (0 << 26)
-#define PROCESS_INFO_DOT_1 (1 << 26)
-#define PROCESS_INFO_DOT_4 (2 << 26)
-#define PROCESS_INFO_MASK (7 << 26)
-#define PROCESS_INFO_SHIFT 26
-#define VOLTAGE_INFO_0_85V (0 << 24)
-#define VOLTAGE_INFO_0_95V (1 << 24)
-#define VOLTAGE_INFO_1_05V (2 << 24)
-#define VOLTAGE_INFO_MASK (3 << 24)
-#define VOLTAGE_INFO_SHIFT 24
-
-#define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy))
-#define IREFGEN (1 << 24)
-
-#define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy))
-
-#define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy))
-
-/* ICL Port PCS registers */
-#define _ICL_PORT_PCS_AUX 0x300
-#define _ICL_PORT_PCS_GRP 0x600
-#define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100)
-#define _ICL_PORT_PCS_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
- _ICL_PORT_PCS_AUX + 4 * (dw))
-#define _ICL_PORT_PCS_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
- _ICL_PORT_PCS_GRP + 4 * (dw))
-#define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
- _ICL_PORT_PCS_LN(ln) + 4 * (dw))
-#define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
-#define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
-#define ICL_PORT_PCS_DW1_LN(ln, phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, ln, phy))
-#define DCC_MODE_SELECT_MASK (0x3 << 20)
-#define DCC_MODE_SELECT_CONTINUOSLY (0x3 << 20)
-#define COMMON_KEEPER_EN (1 << 26)
-#define LATENCY_OPTIM_MASK (0x3 << 2)
-#define LATENCY_OPTIM_VAL(x) ((x) << 2)
-
-/* ICL Port TX registers */
-#define _ICL_PORT_TX_AUX 0x380
-#define _ICL_PORT_TX_GRP 0x680
-#define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100)
-
-#define _ICL_PORT_TX_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
- _ICL_PORT_TX_AUX + 4 * (dw))
-#define _ICL_PORT_TX_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
- _ICL_PORT_TX_GRP + 4 * (dw))
-#define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
- _ICL_PORT_TX_LN(ln) + 4 * (dw))
-
-#define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
-#define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
-#define ICL_PORT_TX_DW2_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(2, ln, phy))
-#define SWING_SEL_UPPER(x) (((x) >> 3) << 15)
-#define SWING_SEL_UPPER_MASK (1 << 15)
-#define SWING_SEL_LOWER(x) (((x) & 0x7) << 11)
-#define SWING_SEL_LOWER_MASK (0x7 << 11)
-#define FRC_LATENCY_OPTIM_MASK (0x7 << 8)
-#define FRC_LATENCY_OPTIM_VAL(x) ((x) << 8)
-#define RCOMP_SCALAR(x) ((x) << 0)
-#define RCOMP_SCALAR_MASK (0xFF << 0)
-
-#define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
-#define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
-#define ICL_PORT_TX_DW4_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))
-#define LOADGEN_SELECT (1 << 31)
-#define POST_CURSOR_1(x) ((x) << 12)
-#define POST_CURSOR_1_MASK (0x3F << 12)
-#define POST_CURSOR_2(x) ((x) << 6)
-#define POST_CURSOR_2_MASK (0x3F << 6)
-#define CURSOR_COEFF(x) ((x) << 0)
-#define CURSOR_COEFF_MASK (0x3F << 0)
-
-#define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
-#define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
-#define ICL_PORT_TX_DW5_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(5, ln, phy))
-#define TX_TRAINING_EN (1 << 31)
-#define TAP2_DISABLE (1 << 30)
-#define TAP3_DISABLE (1 << 29)
-#define SCALING_MODE_SEL(x) ((x) << 18)
-#define SCALING_MODE_SEL_MASK (0x7 << 18)
-#define RTERM_SELECT(x) ((x) << 3)
-#define RTERM_SELECT_MASK (0x7 << 3)
-
-#define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
-#define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
-#define ICL_PORT_TX_DW7_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))
-#define N_SCALAR(x) ((x) << 24)
-#define N_SCALAR_MASK (0x7F << 24)
-
-#define ICL_PORT_TX_DW8_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(8, phy))
-#define ICL_PORT_TX_DW8_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(8, phy))
-#define ICL_PORT_TX_DW8_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(8, ln, phy))
-#define ICL_PORT_TX_DW8_ODCC_CLK_SEL REG_BIT(31)
-#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK REG_GENMASK(30, 29)
-#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1)
-
-#define _ICL_DPHY_CHKN_REG 0x194
-#define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
-#define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7)
-
-#define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \
- _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
-
-#define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
-#define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
-#define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
-#define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
-#define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
-#define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
-#define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
-#define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
-#define MG_TX1_LINK_PARAMS(ln, tc_port) \
- MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
- MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
- MG_TX_LINK_PARAMS_TX1LN1_PORT1)
-
-#define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
-#define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
-#define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
-#define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
-#define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
-#define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
-#define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
-#define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
-#define MG_TX2_LINK_PARAMS(ln, tc_port) \
- MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
- MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
- MG_TX_LINK_PARAMS_TX2LN1_PORT1)
-#define CRI_USE_FS32 (1 << 5)
-
-#define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
-#define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
-#define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
-#define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
-#define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
-#define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
-#define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
-#define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
-#define MG_TX1_PISO_READLOAD(ln, tc_port) \
- MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
- MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
- MG_TX_PISO_READLOAD_TX1LN1_PORT1)
-
-#define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
-#define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
-#define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
-#define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
-#define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
-#define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
-#define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
-#define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
-#define MG_TX2_PISO_READLOAD(ln, tc_port) \
- MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
- MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
- MG_TX_PISO_READLOAD_TX2LN1_PORT1)
-#define CRI_CALCINIT (1 << 1)
-
-#define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
-#define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
-#define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
-#define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
-#define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
-#define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
-#define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
-#define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
-#define MG_TX1_SWINGCTRL(ln, tc_port) \
- MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
- MG_TX_SWINGCTRL_TX1LN0_PORT2, \
- MG_TX_SWINGCTRL_TX1LN1_PORT1)
-
-#define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
-#define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
-#define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
-#define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
-#define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
-#define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
-#define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
-#define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
-#define MG_TX2_SWINGCTRL(ln, tc_port) \
- MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
- MG_TX_SWINGCTRL_TX2LN0_PORT2, \
- MG_TX_SWINGCTRL_TX2LN1_PORT1)
-#define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
-#define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
-
-#define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144
-#define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544
-#define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144
-#define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544
-#define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144
-#define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544
-#define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144
-#define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544
-#define MG_TX1_DRVCTRL(ln, tc_port) \
- MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
- MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
- MG_TX_DRVCTRL_TX1LN1_TXPORT1)
-
-#define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
-#define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
-#define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
-#define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
-#define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
-#define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
-#define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
-#define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
-#define MG_TX2_DRVCTRL(ln, tc_port) \
- MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
- MG_TX_DRVCTRL_TX2LN0_PORT2, \
- MG_TX_DRVCTRL_TX2LN1_PORT1)
-#define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
-#define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)
-#define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
-#define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
-#define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
-#define CRI_LOADGEN_SEL(x) ((x) << 12)
-#define CRI_LOADGEN_SEL_MASK (0x3 << 12)
-
-#define MG_CLKHUB_LN0_PORT1 0x16839C
-#define MG_CLKHUB_LN1_PORT1 0x16879C
-#define MG_CLKHUB_LN0_PORT2 0x16939C
-#define MG_CLKHUB_LN1_PORT2 0x16979C
-#define MG_CLKHUB_LN0_PORT3 0x16A39C
-#define MG_CLKHUB_LN1_PORT3 0x16A79C
-#define MG_CLKHUB_LN0_PORT4 0x16B39C
-#define MG_CLKHUB_LN1_PORT4 0x16B79C
-#define MG_CLKHUB(ln, tc_port) \
- MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \
- MG_CLKHUB_LN0_PORT2, \
- MG_CLKHUB_LN1_PORT1)
-#define CFG_LOW_RATE_LKREN_EN (1 << 11)
-
-#define MG_TX_DCC_TX1LN0_PORT1 0x168110
-#define MG_TX_DCC_TX1LN1_PORT1 0x168510
-#define MG_TX_DCC_TX1LN0_PORT2 0x169110
-#define MG_TX_DCC_TX1LN1_PORT2 0x169510
-#define MG_TX_DCC_TX1LN0_PORT3 0x16A110
-#define MG_TX_DCC_TX1LN1_PORT3 0x16A510
-#define MG_TX_DCC_TX1LN0_PORT4 0x16B110
-#define MG_TX_DCC_TX1LN1_PORT4 0x16B510
-#define MG_TX1_DCC(ln, tc_port) \
- MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \
- MG_TX_DCC_TX1LN0_PORT2, \
- MG_TX_DCC_TX1LN1_PORT1)
-#define MG_TX_DCC_TX2LN0_PORT1 0x168090
-#define MG_TX_DCC_TX2LN1_PORT1 0x168490
-#define MG_TX_DCC_TX2LN0_PORT2 0x169090
-#define MG_TX_DCC_TX2LN1_PORT2 0x169490
-#define MG_TX_DCC_TX2LN0_PORT3 0x16A090
-#define MG_TX_DCC_TX2LN1_PORT3 0x16A490
-#define MG_TX_DCC_TX2LN0_PORT4 0x16B090
-#define MG_TX_DCC_TX2LN1_PORT4 0x16B490
-#define MG_TX2_DCC(ln, tc_port) \
- MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \
- MG_TX_DCC_TX2LN0_PORT2, \
- MG_TX_DCC_TX2LN1_PORT1)
-#define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)
-#define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)
-#define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)
-
-#define MG_DP_MODE_LN0_ACU_PORT1 0x1683A0
-#define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0
-#define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0
-#define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0
-#define MG_DP_MODE_LN0_ACU_PORT3 0x16A3A0
-#define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0
-#define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0
-#define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0
-#define MG_DP_MODE(ln, tc_port) \
- MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \
- MG_DP_MODE_LN0_ACU_PORT2, \
- MG_DP_MODE_LN1_ACU_PORT1)
-#define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
-#define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
-
-/*
- * DG2 SNPS PHY registers (TC1 = PHY_E)
- */
-#define _SNPS_PHY_A_BASE 0x168000
-#define _SNPS_PHY_B_BASE 0x169000
-#define _SNPS_PHY(phy) _PHY(phy, \
- _SNPS_PHY_A_BASE, \
- _SNPS_PHY_B_BASE)
-#define _SNPS2(phy, reg) (_SNPS_PHY(phy) - \
- _SNPS_PHY_A_BASE + (reg))
-#define _MMIO_SNPS(phy, reg) _MMIO(_SNPS2(phy, reg))
-#define _MMIO_SNPS_LN(ln, phy, reg) _MMIO(_SNPS2(phy, \
- (reg) + (ln) * 0x10))
-
-#define SNPS_PHY_MPLLB_CP(phy) _MMIO_SNPS(phy, 0x168000)
-#define SNPS_PHY_MPLLB_CP_INT REG_GENMASK(31, 25)
-#define SNPS_PHY_MPLLB_CP_INT_GS REG_GENMASK(23, 17)
-#define SNPS_PHY_MPLLB_CP_PROP REG_GENMASK(15, 9)
-#define SNPS_PHY_MPLLB_CP_PROP_GS REG_GENMASK(7, 1)
-
-#define SNPS_PHY_MPLLB_DIV(phy) _MMIO_SNPS(phy, 0x168004)
-#define SNPS_PHY_MPLLB_FORCE_EN REG_BIT(31)
-#define SNPS_PHY_MPLLB_DIV_CLK_EN REG_BIT(30)
-#define SNPS_PHY_MPLLB_DIV5_CLK_EN REG_BIT(29)
-#define SNPS_PHY_MPLLB_V2I REG_GENMASK(27, 26)
-#define SNPS_PHY_MPLLB_FREQ_VCO REG_GENMASK(25, 24)
-#define SNPS_PHY_MPLLB_DIV_MULTIPLIER REG_GENMASK(23, 16)
-#define SNPS_PHY_MPLLB_PMIX_EN REG_BIT(10)
-#define SNPS_PHY_MPLLB_DP2_MODE REG_BIT(9)
-#define SNPS_PHY_MPLLB_WORD_DIV2_EN REG_BIT(8)
-#define SNPS_PHY_MPLLB_TX_CLK_DIV REG_GENMASK(7, 5)
-#define SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL REG_BIT(0)
-
-#define SNPS_PHY_MPLLB_FRACN1(phy) _MMIO_SNPS(phy, 0x168008)
-#define SNPS_PHY_MPLLB_FRACN_EN REG_BIT(31)
-#define SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN REG_BIT(30)
-#define SNPS_PHY_MPLLB_FRACN_DEN REG_GENMASK(15, 0)
-
-#define SNPS_PHY_MPLLB_FRACN2(phy) _MMIO_SNPS(phy, 0x16800C)
-#define SNPS_PHY_MPLLB_FRACN_REM REG_GENMASK(31, 16)
-#define SNPS_PHY_MPLLB_FRACN_QUOT REG_GENMASK(15, 0)
-
-#define SNPS_PHY_MPLLB_SSCEN(phy) _MMIO_SNPS(phy, 0x168014)
-#define SNPS_PHY_MPLLB_SSC_EN REG_BIT(31)
-#define SNPS_PHY_MPLLB_SSC_UP_SPREAD REG_BIT(30)
-#define SNPS_PHY_MPLLB_SSC_PEAK REG_GENMASK(29, 10)
-
-#define SNPS_PHY_MPLLB_SSCSTEP(phy) _MMIO_SNPS(phy, 0x168018)
-#define SNPS_PHY_MPLLB_SSC_STEPSIZE REG_GENMASK(31, 11)
-
-#define SNPS_PHY_MPLLB_DIV2(phy) _MMIO_SNPS(phy, 0x16801C)
-#define SNPS_PHY_MPLLB_HDMI_PIXEL_CLK_DIV REG_GENMASK(19, 18)
-#define SNPS_PHY_MPLLB_HDMI_DIV REG_GENMASK(17, 15)
-#define SNPS_PHY_MPLLB_REF_CLK_DIV REG_GENMASK(14, 12)
-#define SNPS_PHY_MPLLB_MULTIPLIER REG_GENMASK(11, 0)
-
-#define SNPS_PHY_REF_CONTROL(phy) _MMIO_SNPS(phy, 0x168188)
-#define SNPS_PHY_REF_CONTROL_REF_RANGE REG_GENMASK(31, 27)
-
-#define SNPS_PHY_TX_REQ(phy) _MMIO_SNPS(phy, 0x168200)
-#define SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR REG_GENMASK(31, 30)
-
-#define SNPS_PHY_TX_EQ(ln, phy) _MMIO_SNPS_LN(ln, phy, 0x168300)
-#define SNPS_PHY_TX_EQ_MAIN REG_GENMASK(23, 18)
-#define SNPS_PHY_TX_EQ_POST REG_GENMASK(15, 10)
-#define SNPS_PHY_TX_EQ_PRE REG_GENMASK(7, 2)
-
/* The spec defines this only for BXT PHY0, but lets assume that this
* would exist for PHY1 too if it had a second channel.
*/
#define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
-#define FIA1_BASE 0x163000
-#define FIA2_BASE 0x16E000
-#define FIA3_BASE 0x16F000
-#define _FIA(fia) _PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
-#define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off))
-
-/* ICL PHY DFLEX registers */
-#define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0)
-#define DFLEXDPMLE1_DPMLETC_MASK(idx) (0xf << (4 * (idx)))
-#define DFLEXDPMLE1_DPMLETC_ML0(idx) (1 << (4 * (idx)))
-#define DFLEXDPMLE1_DPMLETC_ML1_0(idx) (3 << (4 * (idx)))
-#define DFLEXDPMLE1_DPMLETC_ML3(idx) (8 << (4 * (idx)))
-#define DFLEXDPMLE1_DPMLETC_ML3_2(idx) (12 << (4 * (idx)))
-#define DFLEXDPMLE1_DPMLETC_ML3_0(idx) (15 << (4 * (idx)))
-
/* BXT PHY Ref registers */
#define _PORT_REF_DW3_A 0x16218C
#define _PORT_REF_DW3_BC 0x6C18C
#define XEHP_VEBOX3_RING_BASE 0x1e8000
#define XEHP_VEBOX4_RING_BASE 0x1f8000
#define BLT_RING_BASE 0x22000
-#define RING_TAIL(base) _MMIO((base) + 0x30)
-#define RING_HEAD(base) _MMIO((base) + 0x34)
-#define RING_START(base) _MMIO((base) + 0x38)
-#define RING_CTL(base) _MMIO((base) + 0x3c)
-#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
-#define RING_SYNC_0(base) _MMIO((base) + 0x40)
-#define RING_SYNC_1(base) _MMIO((base) + 0x44)
-#define RING_SYNC_2(base) _MMIO((base) + 0x48)
-#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
-#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
-#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
-#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
-#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
-#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
-#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
-#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
-#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
-#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
-#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
-#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
-#define GEN6_NOSYNC INVALID_MMIO_REG
-#define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
-#define RING_MAX_IDLE(base) _MMIO((base) + 0x54)
-#define RING_HWS_PGA(base) _MMIO((base) + 0x80)
-#define RING_ID(base) _MMIO((base) + 0x8c)
-#define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)
-
-#define RING_CMD_CCTL(base) _MMIO((base) + 0xc4)
-/*
- * CMD_CCTL read/write fields take a MOCS value and _not_ a table index.
- * The lsb of each can be considered a separate enabling bit for encryption.
- * 6:0 == default MOCS value for reads => 6:1 == table index for reads.
- * 13:7 == default MOCS value for writes => 13:8 == table index for writes.
- * 15:14 == Reserved => 31:30 are set to 0.
- */
-#define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 7)
-#define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 0)
-#define CMD_CCTL_MOCS_MASK (CMD_CCTL_WRITE_OVERRIDE_MASK | \
- CMD_CCTL_READ_OVERRIDE_MASK)
-#define CMD_CCTL_MOCS_OVERRIDE(write, read) \
- (REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \
- REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))
-
-#define BLIT_CCTL(base) _MMIO((base) + 0x204)
-#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8)
-#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0)
-#define BLIT_CCTL_MASK (BLIT_CCTL_DST_MOCS_MASK | \
- BLIT_CCTL_SRC_MOCS_MASK)
-#define BLIT_CCTL_MOCS(dst, src) \
- (REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (dst) << 1) | \
- REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (src) << 1))
-
-#define RING_RESET_CTL(base) _MMIO((base) + 0xd0)
-#define RESET_CTL_CAT_ERROR REG_BIT(2)
-#define RESET_CTL_READY_TO_RESET REG_BIT(1)
-#define RESET_CTL_REQUEST_RESET REG_BIT(0)
-
-#define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
+
+
#define HSW_GTT_CACHE_EN _MMIO(0x4024)
#define GTT_CACHE_EN_ALL 0xF0007FFF
#define AUX_INV REG_BIT(0)
#define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
#define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)
-#define RING_ACTHD(base) _MMIO((base) + 0x74)
-#define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c)
-#define RING_NOPID(base) _MMIO((base) + 0x94)
-#define RING_IMR(base) _MMIO((base) + 0xa8)
-#define RING_HWSTAM(base) _MMIO((base) + 0x98)
-#define RING_TIMESTAMP(base) _MMIO((base) + 0x358)
-#define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4)
-#define TAIL_ADDR 0x001FFFF8
-#define HEAD_WRAP_COUNT 0xFFE00000
-#define HEAD_WRAP_ONE 0x00200000
-#define HEAD_ADDR 0x001FFFFC
-#define RING_NR_PAGES 0x001FF000
-#define RING_REPORT_MASK 0x00000006
-#define RING_REPORT_64K 0x00000002
-#define RING_REPORT_128K 0x00000004
-#define RING_NO_REPORT 0x00000000
-#define RING_VALID_MASK 0x00000001
-#define RING_VALID 0x00000001
-#define RING_INVALID 0x00000000
-#define RING_WAIT_I8XX (1 << 0) /* gen2, PRBx_HEAD */
-#define RING_WAIT (1 << 11) /* gen3+, PRBx_CTL */
-#define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */
#define GUCPMTIMESTAMP _MMIO(0xC3E8)
-/* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */
-#define GEN8_RING_CS_GPR(base, n) _MMIO((base) + 0x600 + (n) * 8)
-#define GEN8_RING_CS_GPR_UDW(base, n) _MMIO((base) + 0x600 + (n) * 8 + 4)
-
-#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
-#define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2)
-#define RING_FORCE_TO_NONPRIV_ACCESS_RW (0 << 28) /* CFL+ & Gen11+ */
-#define RING_FORCE_TO_NONPRIV_ACCESS_RD (1 << 28)
-#define RING_FORCE_TO_NONPRIV_ACCESS_WR (2 << 28)
-#define RING_FORCE_TO_NONPRIV_ACCESS_INVALID (3 << 28)
-#define RING_FORCE_TO_NONPRIV_ACCESS_MASK (3 << 28)
-#define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0) /* CFL+ & Gen11+ */
-#define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0)
-#define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0)
-#define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0)
-#define RING_FORCE_TO_NONPRIV_RANGE_MASK (3 << 0)
-#define RING_FORCE_TO_NONPRIV_MASK_VALID \
- (RING_FORCE_TO_NONPRIV_RANGE_MASK \
- | RING_FORCE_TO_NONPRIV_ACCESS_MASK)
-#define RING_MAX_NONPRIV_SLOTS 12
-
#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
#define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
#define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf)
#define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
#define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7)
-#define RING_IPEIR(base) _MMIO((base) + 0x64)
-#define RING_IPEHR(base) _MMIO((base) + 0x68)
-#define RING_EIR(base) _MMIO((base) + 0xb0)
-#define RING_EMR(base) _MMIO((base) + 0xb4)
-#define RING_ESR(base) _MMIO((base) + 0xb8)
/*
* On GEN4, only the render ring INSTDONE exists and has a different
* layout than the GEN7+ version.
* The GEN2 counterpart of this register is GEN2_INSTDONE.
*/
-#define RING_INSTDONE(base) _MMIO((base) + 0x6c)
-#define RING_INSTPS(base) _MMIO((base) + 0x70)
-#define RING_DMA_FADD(base) _MMIO((base) + 0x78)
-#define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */
-#define RING_INSTPM(base) _MMIO((base) + 0xc0)
-#define RING_MI_MODE(base) _MMIO((base) + 0x9c)
-#define RING_CMD_BUF_CCTL(base) _MMIO((base) + 0x84)
#define INSTPS _MMIO(0x2070) /* 965+ only */
#define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
#define ACTHD_I965 _MMIO(0x2074)
#define HWS_START_ADDRESS_SHIFT 4
#define PWRCTXA _MMIO(0x2088) /* 965GM+ only */
#define PWRCTX_EN (1 << 0)
-#define IPEIR(base) _MMIO((base) + 0x88)
-#define IPEHR(base) _MMIO((base) + 0x8c)
#define GEN2_INSTDONE _MMIO(0x2090)
#define NOPID _MMIO(0x2094)
#define HWSTAM _MMIO(0x2098)
-#define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0)
-#define RING_BBSTATE(base) _MMIO((base) + 0x110)
-#define RING_BB_PPGTT (1 << 5)
-#define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */
-#define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */
-#define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */
-#define RING_BBADDR(base) _MMIO((base) + 0x140)
-#define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */
-#define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */
-#define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */
-#define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */
-#define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */
-
-#define VDBOX_CGCTL3F10(base) _MMIO((base) + 0x3f10)
-#define IECPUNIT_CLKGATE_DIS REG_BIT(22)
#define VDBOX_CGCTL3F18(base) _MMIO((base) + 0x3f18)
#define ALNUNIT_CLKGATE_DIS REG_BIT(13)
GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
#define GFX_MODE _MMIO(0x2520)
-#define GFX_MODE_GEN7 _MMIO(0x229c)
-#define RING_MODE_GEN7(base) _MMIO((base) + 0x29c)
-#define GFX_RUN_LIST_ENABLE (1 << 15)
-#define GFX_INTERRUPT_STEERING (1 << 14)
-#define GFX_TLB_INVALIDATE_EXPLICIT (1 << 13)
-#define GFX_SURFACE_FAULT_ENABLE (1 << 12)
-#define GFX_REPLAY_MODE (1 << 11)
-#define GFX_PSMI_GRANULARITY (1 << 10)
-#define GFX_PPGTT_ENABLE (1 << 9)
-#define GEN8_GFX_PPGTT_48B (1 << 7)
-
-#define GFX_FORWARD_VBLANK_MASK (3 << 5)
-#define GFX_FORWARD_VBLANK_NEVER (0 << 5)
-#define GFX_FORWARD_VBLANK_ALWAYS (1 << 5)
-#define GFX_FORWARD_VBLANK_COND (2 << 5)
-
-#define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3)
#define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
#define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
#define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
#define INSTPM_TLB_INVALIDATE (1 << 9)
#define INSTPM_SYNC_FLUSH (1 << 5)
-#define ACTHD(base) _MMIO((base) + 0xc8)
#define MEM_MODE _MMIO(0x20cc)
#define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
#define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
#define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */
#define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
#define GFX_FLSH_CNTL_EN (1 << 0)
-#define ECOSKPD _MMIO(0x21d0)
-#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
-#define ECO_GATING_CX_ONLY (1 << 3)
-#define ECO_FLIP_DONE (1 << 0)
#define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */
#define RC_OP_FLUSH_ENABLE (1 << 0)
#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6)
#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1)
-#define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)
-#define GEN6_BLITTER_LOCK_SHIFT 16
-#define GEN6_BLITTER_FBC_NOTIFY (1 << 3)
-
-#define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
-#define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
-#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
-#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
-#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1 << 10)
-
#define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
#define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
#define XEHP_EU_ENABLE _MMIO(0x9134)
#define XEHP_EU_ENA_MASK 0xFF
-#define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
-#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
-#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
-#define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
-#define GEN6_BSD_GO_INDICATOR (1 << 4)
-
/* On modern GEN architectures interrupt control consists of two sets
* of registers. The first set pertains to the ring generating the
* interrupt. The second control is for the functional block generating the
#define FBC_LL_SIZE (1536)
/* Framebuffer compression for GM45+ */
-#define DPFC_CB_BASE _MMIO(0x3200)
-#define ILK_DPFC_CB_BASE _MMIO(0x43200)
-#define DPFC_CONTROL _MMIO(0x3208)
-#define ILK_DPFC_CONTROL _MMIO(0x43208)
+#define DPFC_CB_BASE _MMIO(0x3200)
+#define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240)
+#define DPFC_CONTROL _MMIO(0x3208)
+#define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248)
#define DPFC_CTL_EN REG_BIT(31)
#define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */
#define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane))
#define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2)
#define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
#define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence))
-#define DPFC_RECOMP_CTL _MMIO(0x320c)
-#define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c)
+#define DPFC_RECOMP_CTL _MMIO(0x320c)
+#define ILK_DPFC_RECOMP_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c)
#define DPFC_RECOMP_STALL_EN REG_BIT(27)
#define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16)
#define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0)
-#define DPFC_STATUS _MMIO(0x3210)
-#define ILK_DPFC_STATUS _MMIO(0x43210)
+#define DPFC_STATUS _MMIO(0x3210)
+#define ILK_DPFC_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43210, 0x43250)
#define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16)
#define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0)
-#define DPFC_STATUS2 _MMIO(0x3214)
-#define ILK_DPFC_STATUS2 _MMIO(0x43214)
+#define DPFC_STATUS2 _MMIO(0x3214)
+#define ILK_DPFC_STATUS2(fbc_id) _MMIO_PIPE((fbc_id), 0x43214, 0x43254)
#define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0)
-#define DPFC_FENCE_YOFF _MMIO(0x3218)
-#define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
-#define DPFC_CHICKEN _MMIO(0x3224)
-#define ILK_DPFC_CHICKEN _MMIO(0x43224)
+#define DPFC_FENCE_YOFF _MMIO(0x3218)
+#define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258)
+#define DPFC_CHICKEN _MMIO(0x3224)
+#define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264)
#define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */
#define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */
#define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */
#define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */
-#define GLK_FBC_STRIDE _MMIO(0x43228)
+#define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268)
#define FBC_STRIDE_OVERRIDE REG_BIT(15)
#define FBC_STRIDE_MASK REG_GENMASK(14, 0)
#define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x))
#define IPS_CTL _MMIO(0x43408)
#define IPS_ENABLE (1 << 31)
-#define MSG_FBC_REND_STATE _MMIO(0x50380)
+#define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384)
#define FBC_REND_NUKE REG_BIT(2)
-#define FBC_REND_CACHE_CLEAN REG_BIT(1)
+#define FBC_REND_CACHE_CLEAN REG_BIT(1)
/*
* GPIO regs
/*
* Logical Context regs
*/
-#define CCID(base) _MMIO((base) + 0x180)
-#define CCID_EN BIT(0)
-#define CCID_EXTENDED_STATE_RESTORE BIT(2)
-#define CCID_EXTENDED_STATE_SAVE BIT(3)
/*
* Notes on SNB/IVB/VLV context size:
* - Power context is saved elsewhere (LLC or stolen)
#define _VSYNC_A 0x60014
#define _EXITLINE_A 0x60018
#define _PIPEASRC 0x6001c
+#define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16)
+#define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w))
+#define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0)
+#define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h))
#define _BCLRPAT_A 0x60020
#define _VSYNCSHIFT_A 0x60028
#define _PIPE_MULT_A 0x6002c
#define _PIPEB_DATA_M_G4X 0x71050
/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
-#define TU_SIZE(x) (((x) - 1) << 25) /* default size 64 */
-#define TU_SIZE_SHIFT 25
-#define TU_SIZE_MASK (0x3f << 25)
+#define TU_SIZE_MASK REG_GENMASK(30, 25)
+#define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */
-#define DATA_LINK_M_N_MASK (0xffffff)
+#define DATA_LINK_M_N_MASK REG_GENMASK(23, 0)
#define DATA_LINK_N_MAX (0x800000)
#define _PIPEA_DATA_N_G4X 0x70054
#define _PIPEB_DATA_N_G4X 0x71054
-#define PIPE_GMCH_DATA_N_MASK (0xffffff)
/*
* Computing Link M and N values for the Display Port link
#define _PIPEA_LINK_M_G4X 0x70060
#define _PIPEB_LINK_M_G4X 0x71060
-#define PIPEA_DP_LINK_M_MASK (0xffffff)
-
#define _PIPEA_LINK_N_G4X 0x70064
#define _PIPEB_LINK_N_G4X 0x71064
-#define PIPEA_DP_LINK_N_MASK (0xffffff)
#define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
#define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
/* Pipe A */
#define _PIPEADSL 0x70000
-#define DSL_LINEMASK_GEN2 0x00000fff
-#define DSL_LINEMASK_GEN3 0x00001fff
+#define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */
+#define PIPEDSL_LINE_MASK REG_GENMASK(19, 0)
#define _PIPEACONF 0x70008
-#define PIPECONF_ENABLE (1 << 31)
-#define PIPECONF_DISABLE 0
-#define PIPECONF_DOUBLE_WIDE (1 << 30)
-#define I965_PIPECONF_ACTIVE (1 << 30)
-#define PIPECONF_DSI_PLL_LOCKED (1 << 29) /* vlv & pipe A only */
-#define PIPECONF_FRAME_START_DELAY_MASK (3 << 27) /* pre-hsw */
-#define PIPECONF_FRAME_START_DELAY(x) ((x) << 27) /* pre-hsw: 0-3 */
-#define PIPECONF_SINGLE_WIDE 0
-#define PIPECONF_PIPE_UNLOCKED 0
-#define PIPECONF_PIPE_LOCKED (1 << 25)
-#define PIPECONF_FORCE_BORDER (1 << 25)
-#define PIPECONF_GAMMA_MODE_MASK_I9XX (1 << 24) /* gmch */
-#define PIPECONF_GAMMA_MODE_MASK_ILK (3 << 24) /* ilk-ivb */
-#define PIPECONF_GAMMA_MODE_8BIT (0 << 24) /* gmch,ilk-ivb */
-#define PIPECONF_GAMMA_MODE_10BIT (1 << 24) /* gmch,ilk-ivb */
-#define PIPECONF_GAMMA_MODE_12BIT (2 << 24) /* ilk-ivb */
-#define PIPECONF_GAMMA_MODE_SPLIT (3 << 24) /* ivb */
-#define PIPECONF_GAMMA_MODE(x) ((x) << 24) /* pass in GAMMA_MODE_MODE_* */
-#define PIPECONF_GAMMA_MODE_SHIFT 24
-#define PIPECONF_INTERLACE_MASK (7 << 21)
-#define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
-/* Note that pre-gen3 does not support interlaced display directly. Panel
- * fitting must be disabled on pre-ilk for interlaced. */
-#define PIPECONF_PROGRESSIVE (0 << 21)
-#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
-#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
-#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
-#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
-/* Ironlake and later have a complete new set of values for interlaced. PFIT
- * means panel fitter required, PF means progressive fetch, DBL means power
- * saving pixel doubling. */
-#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
-#define PIPECONF_INTERLACED_ILK (3 << 21)
-#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
-#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
-#define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
-#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
-#define PIPECONF_CXSR_DOWNCLOCK (1 << 16)
-#define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
-#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
-#define PIPECONF_OUTPUT_COLORSPACE_MASK (3 << 11) /* ilk-ivb */
-#define PIPECONF_OUTPUT_COLORSPACE_RGB (0 << 11) /* ilk-ivb */
-#define PIPECONF_OUTPUT_COLORSPACE_YUV601 (1 << 11) /* ilk-ivb */
-#define PIPECONF_OUTPUT_COLORSPACE_YUV709 (2 << 11) /* ilk-ivb */
-#define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW (1 << 11) /* hsw only */
-#define PIPECONF_BPC_MASK (0x7 << 5)
-#define PIPECONF_8BPC (0 << 5)
-#define PIPECONF_10BPC (1 << 5)
-#define PIPECONF_6BPC (2 << 5)
-#define PIPECONF_12BPC (3 << 5)
-#define PIPECONF_DITHER_EN (1 << 4)
-#define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
-#define PIPECONF_DITHER_TYPE_SP (0 << 2)
-#define PIPECONF_DITHER_TYPE_ST1 (1 << 2)
-#define PIPECONF_DITHER_TYPE_ST2 (2 << 2)
-#define PIPECONF_DITHER_TYPE_TEMP (3 << 2)
+#define PIPECONF_ENABLE REG_BIT(31)
+#define PIPECONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */
+#define PIPECONF_STATE_ENABLE REG_BIT(30) /* i965+ */
+#define PIPECONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */
+#define PIPECONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */
+#define PIPECONF_FRAME_START_DELAY(x) REG_FIELD_PREP(PIPECONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
+#define PIPECONF_PIPE_LOCKED REG_BIT(25)
+#define PIPECONF_FORCE_BORDER REG_BIT(25)
+#define PIPECONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */
+#define PIPECONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */
+#define PIPECONF_GAMMA_MODE_8BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 0)
+#define PIPECONF_GAMMA_MODE_10BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 1)
+#define PIPECONF_GAMMA_MODE_12BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */
+#define PIPECONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */
+#define PIPECONF_GAMMA_MODE(x) REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */
+#define PIPECONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */
+#define PIPECONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 0)
+#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 4) /* gen4 only */
+#define PIPECONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 5) /* gen4 only */
+#define PIPECONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 6)
+#define PIPECONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 7) /* gen3 only */
+/*
+ * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display,
+ * DBL=power saving pixel doubling, PF-ID* requires panel fitter
+ */
+#define PIPECONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */
+#define PIPECONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */
+#define PIPECONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 0)
+#define PIPECONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 1)
+#define PIPECONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 3)
+#define PIPECONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */
+#define PIPECONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */
+#define PIPECONF_EDP_RR_MODE_SWITCH REG_BIT(20)
+#define PIPECONF_CXSR_DOWNCLOCK REG_BIT(16)
+#define PIPECONF_EDP_RR_MODE_SWITCH_VLV REG_BIT(14)
+#define PIPECONF_COLOR_RANGE_SELECT REG_BIT(13)
+#define PIPECONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */
+#define PIPECONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */
+#define PIPECONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */
+#define PIPECONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */
+#define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */
+#define PIPECONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */
+#define PIPECONF_BPC_8 REG_FIELD_PREP(PIPECONF_BPC_MASK, 0)
+#define PIPECONF_BPC_10 REG_FIELD_PREP(PIPECONF_BPC_MASK, 1)
+#define PIPECONF_BPC_6 REG_FIELD_PREP(PIPECONF_BPC_MASK, 2)
+#define PIPECONF_BPC_12 REG_FIELD_PREP(PIPECONF_BPC_MASK, 3)
+#define PIPECONF_DITHER_EN REG_BIT(4)
+#define PIPECONF_DITHER_TYPE_MASK REG_GENMASK(3, 2)
+#define PIPECONF_DITHER_TYPE_SP REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 0)
+#define PIPECONF_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 1)
+#define PIPECONF_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 2)
+#define PIPECONF_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 3)
#define _PIPEASTAT 0x70024
#define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31)
#define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30)
#define _PIPE_MISC_A 0x70030
#define _PIPE_MISC_B 0x71030
-#define PIPEMISC_YUV420_ENABLE (1 << 27) /* glk+ */
-#define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26) /* glk+ */
-#define PIPEMISC_HDR_MODE_PRECISION (1 << 23) /* icl+ */
-#define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11)
-#define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
+#define PIPEMISC_YUV420_ENABLE REG_BIT(27) /* glk+ */
+#define PIPEMISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */
+#define PIPEMISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */
+#define PIPEMISC_OUTPUT_COLORSPACE_YUV REG_BIT(11)
+#define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
/*
* For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
* valid values of: 6, 8, 10 BPC.
* ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
* 6, 8, 10, 12 BPC.
*/
-#define PIPEMISC_BPC_MASK (7 << 5)
-#define PIPEMISC_8_BPC (0 << 5)
-#define PIPEMISC_10_BPC (1 << 5)
-#define PIPEMISC_6_BPC (2 << 5)
-#define PIPEMISC_12_BPC_ADLP (4 << 5) /* adlp+ */
-#define PIPEMISC_DITHER_ENABLE (1 << 4)
-#define PIPEMISC_DITHER_TYPE_MASK (3 << 2)
-#define PIPEMISC_DITHER_TYPE_SP (0 << 2)
+#define PIPEMISC_BPC_MASK REG_GENMASK(7, 5)
+#define PIPEMISC_BPC_8 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 0)
+#define PIPEMISC_BPC_10 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 1)
+#define PIPEMISC_BPC_6 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 2)
+#define PIPEMISC_BPC_12_ADLP REG_FIELD_PREP(PIPEMISC_BPC_MASK, 4) /* adlp+ */
+#define PIPEMISC_DITHER_ENABLE REG_BIT(4)
+#define PIPEMISC_DITHER_TYPE_MASK REG_GENMASK(3, 2)
+#define PIPEMISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 0)
+#define PIPEMISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 1)
+#define PIPEMISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 2)
+#define PIPEMISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 3)
#define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A)
#define _PIPE_MISC2_A 0x7002C
#define _PIPE_MISC2_B 0x7102C
-#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN (0x50 << 24)
-#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS (0x14 << 24)
-#define PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK (0xff << 24)
+#define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24)
+#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80)
+#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20)
#define PIPE_MISC2(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC2_A)
/* Skylake+ pipe bottom (background) color */
#define _SKL_BOTTOM_COLOR_A 0x70034
-#define SKL_BOTTOM_COLOR_GAMMA_ENABLE (1 << 31)
-#define SKL_BOTTOM_COLOR_CSC_ENABLE (1 << 30)
+#define SKL_BOTTOM_COLOR_GAMMA_ENABLE REG_BIT(31)
+#define SKL_BOTTOM_COLOR_CSC_ENABLE REG_BIT(30)
#define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A)
#define _ICL_PIPE_A_STATUS 0x70058
/* Cursor A & B regs */
#define _CURACNTR 0x70080
/* Old style CUR*CNTR flags (desktop 8xx) */
-#define CURSOR_ENABLE 0x80000000
-#define CURSOR_GAMMA_ENABLE 0x40000000
-#define CURSOR_STRIDE_SHIFT 28
-#define CURSOR_STRIDE(x) ((ffs(x) - 9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
-#define CURSOR_FORMAT_SHIFT 24
-#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
-#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
-#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
-#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
-#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
-#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
+#define CURSOR_ENABLE REG_BIT(31)
+#define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30)
+#define CURSOR_STRIDE_MASK REG_GENMASK(29, 28)
+#define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */
+#define CURSOR_FORMAT_MASK REG_GENMASK(26, 24)
+#define CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0)
+#define CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1)
+#define CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2)
+#define CURSOR_FORMAT_ARGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4)
+#define CURSOR_FORMAT_XRGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5)
/* New style CUR*CNTR flags */
-#define MCURSOR_MODE 0x27
-#define MCURSOR_MODE_DISABLE 0x00
-#define MCURSOR_MODE_128_32B_AX 0x02
-#define MCURSOR_MODE_256_32B_AX 0x03
-#define MCURSOR_MODE_64_32B_AX 0x07
-#define MCURSOR_MODE_128_ARGB_AX ((1 << 5) | MCURSOR_MODE_128_32B_AX)
-#define MCURSOR_MODE_256_ARGB_AX ((1 << 5) | MCURSOR_MODE_256_32B_AX)
-#define MCURSOR_MODE_64_ARGB_AX ((1 << 5) | MCURSOR_MODE_64_32B_AX)
#define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
#define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */
-#define MCURSOR_PIPE_SELECT_MASK (0x3 << 28)
-#define MCURSOR_PIPE_SELECT_SHIFT 28
-#define MCURSOR_PIPE_SELECT(pipe) ((pipe) << 28)
-#define MCURSOR_GAMMA_ENABLE (1 << 26)
-#define MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
-#define MCURSOR_ROTATE_180 (1 << 15)
-#define MCURSOR_TRICKLE_FEED_DISABLE (1 << 14)
+#define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28)
+#define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe))
+#define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26)
+#define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
+#define MCURSOR_ROTATE_180 REG_BIT(15)
+#define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14)
+#define MCURSOR_MODE_MASK 0x27
+#define MCURSOR_MODE_DISABLE 0x00
+#define MCURSOR_MODE_128_32B_AX 0x02
+#define MCURSOR_MODE_256_32B_AX 0x03
+#define MCURSOR_MODE_64_32B_AX 0x07
+#define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX)
+#define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX)
+#define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX)
#define _CURABASE 0x70084
#define _CURAPOS 0x70088
-#define CURSOR_POS_MASK 0x007FF
-#define CURSOR_POS_SIGN 0x8000
-#define CURSOR_X_SHIFT 0
-#define CURSOR_Y_SHIFT 16
-#define CURSIZE _MMIO(0x700a0) /* 845/865 */
+#define CURSOR_POS_Y_SIGN REG_BIT(31)
+#define CURSOR_POS_Y_MASK REG_GENMASK(30, 16)
+#define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y))
+#define CURSOR_POS_X_SIGN REG_BIT(15)
+#define CURSOR_POS_X_MASK REG_GENMASK(14, 0)
+#define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x))
+#define _CURASIZE 0x700a0 /* 845/865 */
+#define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12)
+#define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h))
+#define CURSOR_WIDTH_MASK REG_GENMASK(9, 0)
+#define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w))
#define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */
-#define CUR_FBC_CTL_EN (1 << 31)
+#define CUR_FBC_EN REG_BIT(31)
+#define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0)
+#define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h))
#define _CURASURFLIVE 0x700ac /* g4x+ */
#define _CURBCNTR 0x700c0
#define _CURBBASE 0x700c4
#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
+#define CURSIZE(pipe) _CURSOR2(pipe, _CURASIZE)
#define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)
#define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE)
/* Display A control */
#define _DSPAADDR_VLV 0x7017C /* vlv/chv */
#define _DSPACNTR 0x70180
-#define DISPLAY_PLANE_ENABLE (1 << 31)
-#define DISPLAY_PLANE_DISABLE 0
-#define DISPPLANE_GAMMA_ENABLE (1 << 30)
-#define DISPPLANE_GAMMA_DISABLE 0
-#define DISPPLANE_PIXFORMAT_MASK (0xf << 26)
-#define DISPPLANE_YUV422 (0x0 << 26)
-#define DISPPLANE_8BPP (0x2 << 26)
-#define DISPPLANE_BGRA555 (0x3 << 26)
-#define DISPPLANE_BGRX555 (0x4 << 26)
-#define DISPPLANE_BGRX565 (0x5 << 26)
-#define DISPPLANE_BGRX888 (0x6 << 26)
-#define DISPPLANE_BGRA888 (0x7 << 26)
-#define DISPPLANE_RGBX101010 (0x8 << 26)
-#define DISPPLANE_RGBA101010 (0x9 << 26)
-#define DISPPLANE_BGRX101010 (0xa << 26)
-#define DISPPLANE_BGRA101010 (0xb << 26)
-#define DISPPLANE_RGBX161616 (0xc << 26)
-#define DISPPLANE_RGBX888 (0xe << 26)
-#define DISPPLANE_RGBA888 (0xf << 26)
-#define DISPPLANE_STEREO_ENABLE (1 << 25)
-#define DISPPLANE_STEREO_DISABLE 0
-#define DISPPLANE_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
-#define DISPPLANE_SEL_PIPE_SHIFT 24
-#define DISPPLANE_SEL_PIPE_MASK (3 << DISPPLANE_SEL_PIPE_SHIFT)
-#define DISPPLANE_SEL_PIPE(pipe) ((pipe) << DISPPLANE_SEL_PIPE_SHIFT)
-#define DISPPLANE_SRC_KEY_ENABLE (1 << 22)
-#define DISPPLANE_SRC_KEY_DISABLE 0
-#define DISPPLANE_LINE_DOUBLE (1 << 20)
-#define DISPPLANE_NO_LINE_DOUBLE 0
-#define DISPPLANE_STEREO_POLARITY_FIRST 0
-#define DISPPLANE_STEREO_POLARITY_SECOND (1 << 18)
-#define DISPPLANE_ALPHA_PREMULTIPLY (1 << 16) /* CHV pipe B */
-#define DISPPLANE_ROTATE_180 (1 << 15)
-#define DISPPLANE_TRICKLE_FEED_DISABLE (1 << 14) /* Ironlake */
-#define DISPPLANE_TILED (1 << 10)
-#define DISPPLANE_ASYNC_FLIP (1 << 9) /* g4x+ */
-#define DISPPLANE_MIRROR (1 << 8) /* CHV pipe B */
+#define DISP_ENABLE REG_BIT(31)
+#define DISP_PIPE_GAMMA_ENABLE REG_BIT(30)
+#define DISP_FORMAT_MASK REG_GENMASK(29, 26)
+#define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2)
+#define DISP_FORMAT_BGRA555 REG_FIELD_PREP(DISP_FORMAT_MASK, 3)
+#define DISP_FORMAT_BGRX555 REG_FIELD_PREP(DISP_FORMAT_MASK, 4)
+#define DISP_FORMAT_BGRX565 REG_FIELD_PREP(DISP_FORMAT_MASK, 5)
+#define DISP_FORMAT_BGRX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 6)
+#define DISP_FORMAT_BGRA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 7)
+#define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8)
+#define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9)
+#define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10)
+#define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11)
+#define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12)
+#define DISP_FORMAT_RGBX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 14)
+#define DISP_FORMAT_RGBA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 15)
+#define DISP_STEREO_ENABLE REG_BIT(25)
+#define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
+#define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24)
+#define DISP_PIPE_SEL(pipe) REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe))
+#define DISP_SRC_KEY_ENABLE REG_BIT(22)
+#define DISP_LINE_DOUBLE REG_BIT(20)
+#define DISP_STEREO_POLARITY_SECOND REG_BIT(18)
+#define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */
+#define DISP_ROTATE_180 REG_BIT(15)
+#define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */
+#define DISP_TILED REG_BIT(10)
+#define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */
+#define DISP_MIRROR REG_BIT(8) /* CHV pipe B */
#define _DSPAADDR 0x70184
#define _DSPASTRIDE 0x70188
#define _DSPAPOS 0x7018C /* reserved */
+#define DISP_POS_Y_MASK REG_GENMASK(31, 0)
+#define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y))
+#define DISP_POS_X_MASK REG_GENMASK(15, 0)
+#define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x))
#define _DSPASIZE 0x70190
+#define DISP_HEIGHT_MASK REG_GENMASK(31, 0)
+#define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h))
+#define DISP_WIDTH_MASK REG_GENMASK(15, 0)
+#define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w))
#define _DSPASURF 0x7019C /* 965+ only */
+#define DISP_ADDR_MASK REG_GENMASK(31, 12)
#define _DSPATILEOFF 0x701A4 /* 965+ only */
+#define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16)
+#define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y))
+#define DISP_OFFSET_X_MASK REG_GENMASK(15, 0)
+#define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x))
#define _DSPAOFFSET 0x701A4 /* HSW */
#define _DSPASURFLIVE 0x701AC
#define _DSPAGAMC 0x701E0
/* CHV pipe B blender and primary plane */
#define _CHV_BLEND_A 0x60a00
-#define CHV_BLEND_LEGACY (0 << 30)
-#define CHV_BLEND_ANDROID (1 << 30)
-#define CHV_BLEND_MPO (2 << 30)
-#define CHV_BLEND_MASK (3 << 30)
+#define CHV_BLEND_MASK REG_GENMASK(31, 30)
+#define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0)
+#define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK, 1)
+#define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2)
#define _CHV_CANVAS_A 0x60a04
+#define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20)
+#define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10)
+#define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0)
#define _PRIMPOS_A 0x60a08
+#define PRIM_POS_Y_MASK REG_GENMASK(31, 16)
+#define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y))
+#define PRIM_POS_X_MASK REG_GENMASK(15, 0)
+#define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x))
#define _PRIMSIZE_A 0x60a0c
+#define PRIM_HEIGHT_MASK REG_GENMASK(31, 16)
+#define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h))
+#define PRIM_WIDTH_MASK REG_GENMASK(15, 0)
+#define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w))
#define _PRIMCNSTALPHA_A 0x60a10
-#define PRIM_CONST_ALPHA_ENABLE (1 << 31)
+#define PRIM_CONST_ALPHA_ENABLE REG_BIT(31)
+#define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0)
+#define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha))
#define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A)
#define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A)
/* Display B control */
#define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
-#define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15)
-#define DISPPLANE_ALPHA_TRANS_DISABLE 0
-#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
-#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
+#define DISP_ALPHA_TRANS_ENABLE REG_BIT(15)
+#define DISP_SPRITE_ABOVE_OVERLAY REG_BIT(0)
#define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
#define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
#define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
/* Sprite A control */
#define _DVSACNTR 0x72180
-#define DVS_ENABLE (1 << 31)
-#define DVS_GAMMA_ENABLE (1 << 30)
-#define DVS_YUV_RANGE_CORRECTION_DISABLE (1 << 27)
-#define DVS_PIXFORMAT_MASK (3 << 25)
-#define DVS_FORMAT_YUV422 (0 << 25)
-#define DVS_FORMAT_RGBX101010 (1 << 25)
-#define DVS_FORMAT_RGBX888 (2 << 25)
-#define DVS_FORMAT_RGBX161616 (3 << 25)
-#define DVS_PIPE_CSC_ENABLE (1 << 24)
-#define DVS_SOURCE_KEY (1 << 22)
-#define DVS_RGB_ORDER_XBGR (1 << 20)
-#define DVS_YUV_FORMAT_BT709 (1 << 18)
-#define DVS_YUV_ORDER_MASK (3 << 16)
-#define DVS_YUV_ORDER_YUYV (0 << 16)
-#define DVS_YUV_ORDER_UYVY (1 << 16)
-#define DVS_YUV_ORDER_YVYU (2 << 16)
-#define DVS_YUV_ORDER_VYUY (3 << 16)
-#define DVS_ROTATE_180 (1 << 15)
-#define DVS_DEST_KEY (1 << 2)
-#define DVS_TRICKLE_FEED_DISABLE (1 << 14)
-#define DVS_TILED (1 << 10)
+#define DVS_ENABLE REG_BIT(31)
+#define DVS_PIPE_GAMMA_ENABLE REG_BIT(30)
+#define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27)
+#define DVS_FORMAT_MASK REG_GENMASK(26, 25)
+#define DVS_FORMAT_YUV422 REG_FIELD_PREP(DVS_FORMAT_MASK, 0)
+#define DVS_FORMAT_RGBX101010 REG_FIELD_PREP(DVS_FORMAT_MASK, 1)
+#define DVS_FORMAT_RGBX888 REG_FIELD_PREP(DVS_FORMAT_MASK, 2)
+#define DVS_FORMAT_RGBX161616 REG_FIELD_PREP(DVS_FORMAT_MASK, 3)
+#define DVS_PIPE_CSC_ENABLE REG_BIT(24)
+#define DVS_SOURCE_KEY REG_BIT(22)
+#define DVS_RGB_ORDER_XBGR REG_BIT(20)
+#define DVS_YUV_FORMAT_BT709 REG_BIT(18)
+#define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16)
+#define DVS_YUV_ORDER_YUYV REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0)
+#define DVS_YUV_ORDER_UYVY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1)
+#define DVS_YUV_ORDER_YVYU REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2)
+#define DVS_YUV_ORDER_VYUY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3)
+#define DVS_ROTATE_180 REG_BIT(15)
+#define DVS_TRICKLE_FEED_DISABLE REG_BIT(14)
+#define DVS_TILED REG_BIT(10)
+#define DVS_DEST_KEY REG_BIT(2)
#define _DVSALINOFF 0x72184
#define _DVSASTRIDE 0x72188
#define _DVSAPOS 0x7218c
+#define DVS_POS_Y_MASK REG_GENMASK(31, 16)
+#define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y))
+#define DVS_POS_X_MASK REG_GENMASK(15, 0)
+#define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x))
#define _DVSASIZE 0x72190
+#define DVS_HEIGHT_MASK REG_GENMASK(31, 16)
+#define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h))
+#define DVS_WIDTH_MASK REG_GENMASK(15, 0)
+#define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w))
#define _DVSAKEYVAL 0x72194
#define _DVSAKEYMSK 0x72198
#define _DVSASURF 0x7219c
+#define DVS_ADDR_MASK REG_GENMASK(31, 12)
#define _DVSAKEYMAXVAL 0x721a0
#define _DVSATILEOFF 0x721a4
+#define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16)
+#define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y))
+#define DVS_OFFSET_X_MASK REG_GENMASK(15, 0)
+#define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x))
#define _DVSASURFLIVE 0x721ac
#define _DVSAGAMC_G4X 0x721e0 /* g4x */
#define _DVSASCALE 0x72204
-#define DVS_SCALE_ENABLE (1 << 31)
-#define DVS_FILTER_MASK (3 << 29)
-#define DVS_FILTER_MEDIUM (0 << 29)
-#define DVS_FILTER_ENHANCING (1 << 29)
-#define DVS_FILTER_SOFTENING (2 << 29)
-#define DVS_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
-#define DVS_VERTICAL_OFFSET_ENABLE (1 << 27)
+#define DVS_SCALE_ENABLE REG_BIT(31)
+#define DVS_FILTER_MASK REG_GENMASK(30, 29)
+#define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0)
+#define DVS_FILTER_ENHANCING REG_FIELD_PREP(DVS_FILTER_MASK, 1)
+#define DVS_FILTER_SOFTENING REG_FIELD_PREP(DVS_FILTER_MASK, 2)
+#define DVS_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
+#define DVS_VERTICAL_OFFSET_ENABLE REG_BIT(27)
+#define DVS_SRC_WIDTH_MASK REG_GENMASK(26, 16)
+#define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w))
+#define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
+#define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h))
#define _DVSAGAMC_ILK 0x72300 /* ilk/snb */
#define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */
#define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
#define _SPRA_CTL 0x70280
-#define SPRITE_ENABLE (1 << 31)
-#define SPRITE_GAMMA_ENABLE (1 << 30)
-#define SPRITE_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
-#define SPRITE_PIXFORMAT_MASK (7 << 25)
-#define SPRITE_FORMAT_YUV422 (0 << 25)
-#define SPRITE_FORMAT_RGBX101010 (1 << 25)
-#define SPRITE_FORMAT_RGBX888 (2 << 25)
-#define SPRITE_FORMAT_RGBX161616 (3 << 25)
-#define SPRITE_FORMAT_YUV444 (4 << 25)
-#define SPRITE_FORMAT_XR_BGR101010 (5 << 25) /* Extended range */
-#define SPRITE_PIPE_CSC_ENABLE (1 << 24)
-#define SPRITE_SOURCE_KEY (1 << 22)
-#define SPRITE_RGB_ORDER_RGBX (1 << 20) /* only for 888 and 161616 */
-#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1 << 19)
-#define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18) /* 0 is BT601 */
-#define SPRITE_YUV_ORDER_MASK (3 << 16)
-#define SPRITE_YUV_ORDER_YUYV (0 << 16)
-#define SPRITE_YUV_ORDER_UYVY (1 << 16)
-#define SPRITE_YUV_ORDER_YVYU (2 << 16)
-#define SPRITE_YUV_ORDER_VYUY (3 << 16)
-#define SPRITE_ROTATE_180 (1 << 15)
-#define SPRITE_TRICKLE_FEED_DISABLE (1 << 14)
-#define SPRITE_INT_GAMMA_DISABLE (1 << 13)
-#define SPRITE_TILED (1 << 10)
-#define SPRITE_DEST_KEY (1 << 2)
+#define SPRITE_ENABLE REG_BIT(31)
+#define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30)
+#define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
+#define SPRITE_FORMAT_MASK REG_GENMASK(27, 25)
+#define SPRITE_FORMAT_YUV422 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0)
+#define SPRITE_FORMAT_RGBX101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 1)
+#define SPRITE_FORMAT_RGBX888 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 2)
+#define SPRITE_FORMAT_RGBX161616 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 3)
+#define SPRITE_FORMAT_YUV444 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 4)
+#define SPRITE_FORMAT_XR_BGR101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */
+#define SPRITE_PIPE_CSC_ENABLE REG_BIT(24)
+#define SPRITE_SOURCE_KEY REG_BIT(22)
+#define SPRITE_RGB_ORDER_RGBX REG_BIT(20) /* only for 888 and 161616 */
+#define SPRITE_YUV_TO_RGB_CSC_DISABLE REG_BIT(19)
+#define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) /* 0 is BT601 */
+#define SPRITE_YUV_ORDER_MASK REG_GENMASK(17, 16)
+#define SPRITE_YUV_ORDER_YUYV REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0)
+#define SPRITE_YUV_ORDER_UYVY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1)
+#define SPRITE_YUV_ORDER_YVYU REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2)
+#define SPRITE_YUV_ORDER_VYUY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3)
+#define SPRITE_ROTATE_180 REG_BIT(15)
+#define SPRITE_TRICKLE_FEED_DISABLE REG_BIT(14)
+#define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13)
+#define SPRITE_TILED REG_BIT(10)
+#define SPRITE_DEST_KEY REG_BIT(2)
#define _SPRA_LINOFF 0x70284
#define _SPRA_STRIDE 0x70288
#define _SPRA_POS 0x7028c
+#define SPRITE_POS_Y_MASK REG_GENMASK(31, 16)
+#define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y))
+#define SPRITE_POS_X_MASK REG_GENMASK(15, 0)
+#define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x))
#define _SPRA_SIZE 0x70290
+#define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16)
+#define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h))
+#define SPRITE_WIDTH_MASK REG_GENMASK(15, 0)
+#define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w))
#define _SPRA_KEYVAL 0x70294
#define _SPRA_KEYMSK 0x70298
#define _SPRA_SURF 0x7029c
+#define SPRITE_ADDR_MASK REG_GENMASK(31, 12)
#define _SPRA_KEYMAX 0x702a0
#define _SPRA_TILEOFF 0x702a4
+#define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16)
+#define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y))
+#define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0)
+#define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x))
#define _SPRA_OFFSET 0x702a4
#define _SPRA_SURFLIVE 0x702ac
#define _SPRA_SCALE 0x70304
-#define SPRITE_SCALE_ENABLE (1 << 31)
-#define SPRITE_FILTER_MASK (3 << 29)
-#define SPRITE_FILTER_MEDIUM (0 << 29)
-#define SPRITE_FILTER_ENHANCING (1 << 29)
-#define SPRITE_FILTER_SOFTENING (2 << 29)
-#define SPRITE_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
-#define SPRITE_VERTICAL_OFFSET_ENABLE (1 << 27)
+#define SPRITE_SCALE_ENABLE REG_BIT(31)
+#define SPRITE_FILTER_MASK REG_GENMASK(30, 29)
+#define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0)
+#define SPRITE_FILTER_ENHANCING REG_FIELD_PREP(SPRITE_FILTER_MASK, 1)
+#define SPRITE_FILTER_SOFTENING REG_FIELD_PREP(SPRITE_FILTER_MASK, 2)
+#define SPRITE_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
+#define SPRITE_VERTICAL_OFFSET_ENABLE REG_BIT(27)
+#define SPRITE_SRC_WIDTH_MASK REG_GENMASK(26, 16)
+#define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w))
+#define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
+#define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h))
#define _SPRA_GAMC 0x70400
#define _SPRA_GAMC16 0x70440
#define _SPRA_GAMC17 0x7044c
#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
-#define SP_ENABLE (1 << 31)
-#define SP_GAMMA_ENABLE (1 << 30)
-#define SP_PIXFORMAT_MASK (0xf << 26)
-#define SP_FORMAT_YUV422 (0x0 << 26)
-#define SP_FORMAT_8BPP (0x2 << 26)
-#define SP_FORMAT_BGR565 (0x5 << 26)
-#define SP_FORMAT_BGRX8888 (0x6 << 26)
-#define SP_FORMAT_BGRA8888 (0x7 << 26)
-#define SP_FORMAT_RGBX1010102 (0x8 << 26)
-#define SP_FORMAT_RGBA1010102 (0x9 << 26)
-#define SP_FORMAT_BGRX1010102 (0xa << 26) /* CHV pipe B */
-#define SP_FORMAT_BGRA1010102 (0xb << 26) /* CHV pipe B */
-#define SP_FORMAT_RGBX8888 (0xe << 26)
-#define SP_FORMAT_RGBA8888 (0xf << 26)
-#define SP_ALPHA_PREMULTIPLY (1 << 23) /* CHV pipe B */
-#define SP_SOURCE_KEY (1 << 22)
-#define SP_YUV_FORMAT_BT709 (1 << 18)
-#define SP_YUV_ORDER_MASK (3 << 16)
-#define SP_YUV_ORDER_YUYV (0 << 16)
-#define SP_YUV_ORDER_UYVY (1 << 16)
-#define SP_YUV_ORDER_YVYU (2 << 16)
-#define SP_YUV_ORDER_VYUY (3 << 16)
-#define SP_ROTATE_180 (1 << 15)
-#define SP_TILED (1 << 10)
-#define SP_MIRROR (1 << 8) /* CHV pipe B */
+#define SP_ENABLE REG_BIT(31)
+#define SP_PIPE_GAMMA_ENABLE REG_BIT(30)
+#define SP_FORMAT_MASK REG_GENMASK(29, 26)
+#define SP_FORMAT_YUV422 REG_FIELD_PREP(SP_FORMAT_MASK, 0)
+#define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2)
+#define SP_FORMAT_BGR565 REG_FIELD_PREP(SP_FORMAT_MASK, 5)
+#define SP_FORMAT_BGRX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 6)
+#define SP_FORMAT_BGRA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 7)
+#define SP_FORMAT_RGBX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 8)
+#define SP_FORMAT_RGBA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 9)
+#define SP_FORMAT_BGRX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */
+#define SP_FORMAT_BGRA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */
+#define SP_FORMAT_RGBX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 14)
+#define SP_FORMAT_RGBA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 15)
+#define SP_ALPHA_PREMULTIPLY REG_BIT(23) /* CHV pipe B */
+#define SP_SOURCE_KEY REG_BIT(22)
+#define SP_YUV_FORMAT_BT709 REG_BIT(18)
+#define SP_YUV_ORDER_MASK REG_GENMASK(17, 16)
+#define SP_YUV_ORDER_YUYV REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0)
+#define SP_YUV_ORDER_UYVY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 1)
+#define SP_YUV_ORDER_YVYU REG_FIELD_PREP(SP_YUV_ORDER_MASK, 2)
+#define SP_YUV_ORDER_VYUY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 3)
+#define SP_ROTATE_180 REG_BIT(15)
+#define SP_TILED REG_BIT(10)
+#define SP_MIRROR REG_BIT(8) /* CHV pipe B */
#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
+#define SP_POS_Y_MASK REG_GENMASK(31, 16)
+#define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y))
+#define SP_POS_X_MASK REG_GENMASK(15, 0)
+#define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x))
#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
+#define SP_HEIGHT_MASK REG_GENMASK(31, 16)
+#define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h))
+#define SP_WIDTH_MASK REG_GENMASK(15, 0)
+#define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w))
#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
+#define SP_ADDR_MASK REG_GENMASK(31, 12)
#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
+#define SP_OFFSET_Y_MASK REG_GENMASK(31, 16)
+#define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y))
+#define SP_OFFSET_X_MASK REG_GENMASK(15, 0)
+#define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x))
#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
-#define SP_CONST_ALPHA_ENABLE (1 << 31)
+#define SP_CONST_ALPHA_ENABLE REG_BIT(31)
+#define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0)
+#define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha))
#define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
-#define SP_CONTRAST(x) ((x) << 18) /* u3.6 */
-#define SP_BRIGHTNESS(x) ((x) & 0xff) /* s8 */
+#define SP_CONTRAST_MASK REG_GENMASK(26, 18)
+#define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */
+#define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0)
+#define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */
#define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)
-#define SP_SH_SIN(x) (((x) & 0x7ff) << 16) /* s4.7 */
-#define SP_SH_COS(x) (x) /* u3.7 */
+#define SP_SH_SIN_MASK REG_GENMASK(26, 16)
+#define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */
+#define SP_SH_COS_MASK REG_GENMASK(9, 0)
+#define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */
#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0)
#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
#define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900)
#define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904)
#define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908)
-#define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */
-#define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */
+#define SPCSC_OOFF_MASK REG_GENMASK(26, 16)
+#define SPCSC_OOFF(x) REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */
+#define SPCSC_IOFF_MASK REG_GENMASK(10, 0)
+#define SPCSC_IOFF(x) REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */
#define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c)
#define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910)
#define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914)
#define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918)
#define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c)
-#define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */
-#define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */
+#define SPCSC_C1_MASK REG_GENMASK(30, 16)
+#define SPCSC_C1(x) REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */
+#define SPCSC_C0_MASK REG_GENMASK(14, 0)
+#define SPCSC_C0(x) REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */
#define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)
#define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)
#define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)
-#define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */
-#define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */
+#define SPCSC_IMAX_MASK REG_GENMASK(26, 16)
+#define SPCSC_IMAX(x) REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */
+#define SPCSC_IMIN_MASK REG_GENMASK(10, 0)
+#define SPCSC_IMIN(x) REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */
#define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)
#define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)
#define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)
-#define SPCSC_OMAX(x) ((x) << 16) /* u10 */
-#define SPCSC_OMIN(x) ((x) << 0) /* u10 */
+#define SPCSC_OMAX_MASK REG_GENMASK(25, 16)
+#define SPCSC_OMAX(x) REG_FIELD_PREP(SPCSC_OMAX_MASK, (x)) /* u10 */
+#define SPCSC_OMIN_MASK REG_GENMASK(9, 0)
+#define SPCSC_OMIN(x) REG_FIELD_PREP(SPCSC_OMIN_MASK, (x)) /* u10 */
/* Skylake plane registers */
#define _PLANE_CTL_1_A 0x70180
#define _PLANE_CTL_2_A 0x70280
#define _PLANE_CTL_3_A 0x70380
-#define PLANE_CTL_ENABLE (1 << 31)
+#define PLANE_CTL_ENABLE REG_BIT(31)
#define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
#define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
-#define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-GLK */
-#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
+#define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */
+#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
/*
* ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
* expanded to include bit 23 as well. However, the shift-24 based values
* correctly map to the same formats in ICL, as long as bit 23 is set to 0
*/
-#define PLANE_CTL_FORMAT_MASK (0xf << 24)
-#define PLANE_CTL_FORMAT_YUV422 (0 << 24)
-#define PLANE_CTL_FORMAT_NV12 (1 << 24)
-#define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24)
-#define PLANE_CTL_FORMAT_P010 (3 << 24)
-#define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24)
-#define PLANE_CTL_FORMAT_P012 (5 << 24)
-#define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
-#define PLANE_CTL_FORMAT_P016 (7 << 24)
-#define PLANE_CTL_FORMAT_XYUV (8 << 24)
-#define PLANE_CTL_FORMAT_INDEXED (12 << 24)
-#define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
-#define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
-#define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */
-#define PLANE_CTL_FORMAT_Y210 (1 << 23)
-#define PLANE_CTL_FORMAT_Y212 (3 << 23)
-#define PLANE_CTL_FORMAT_Y216 (5 << 23)
-#define PLANE_CTL_FORMAT_Y410 (7 << 23)
-#define PLANE_CTL_FORMAT_Y412 (9 << 23)
-#define PLANE_CTL_FORMAT_Y416 (0xb << 23)
-#define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
-#define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21)
-#define PLANE_CTL_KEY_ENABLE_DESTINATION (2 << 21)
-#define PLANE_CTL_ORDER_BGRX (0 << 20)
-#define PLANE_CTL_ORDER_RGBX (1 << 20)
-#define PLANE_CTL_YUV420_Y_PLANE (1 << 19)
-#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18)
-#define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
-#define PLANE_CTL_YUV422_ORDER_YUYV (0 << 16)
-#define PLANE_CTL_YUV422_ORDER_UYVY (1 << 16)
-#define PLANE_CTL_YUV422_ORDER_YVYU (2 << 16)
-#define PLANE_CTL_YUV422_ORDER_VYUY (3 << 16)
-#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
-#define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
-#define PLANE_CTL_CLEAR_COLOR_DISABLE (1 << 13) /* TGL+ */
-#define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */
-#define PLANE_CTL_TILED_MASK (0x7 << 10)
-#define PLANE_CTL_TILED_LINEAR (0 << 10)
-#define PLANE_CTL_TILED_X (1 << 10)
-#define PLANE_CTL_TILED_Y (4 << 10)
-#define PLANE_CTL_TILED_YF (5 << 10)
-#define PLANE_CTL_ASYNC_FLIP (1 << 9)
-#define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
-#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
-#define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
-#define PLANE_CTL_ALPHA_DISABLE (0 << 4)
-#define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4)
-#define PLANE_CTL_ALPHA_HW_PREMULTIPLY (3 << 4)
-#define PLANE_CTL_ROTATE_MASK 0x3
-#define PLANE_CTL_ROTATE_0 0x0
-#define PLANE_CTL_ROTATE_90 0x1
-#define PLANE_CTL_ROTATE_180 0x2
-#define PLANE_CTL_ROTATE_270 0x3
+#define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */
+#define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */
+#define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0)
+#define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1)
+#define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2)
+#define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3)
+#define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4)
+#define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5)
+#define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6)
+#define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7)
+#define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8)
+#define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12)
+#define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14)
+#define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1)
+#define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3)
+#define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5)
+#define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7)
+#define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9)
+#define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11)
+#define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */
+#define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21)
+#define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1)
+#define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2)
+#define PLANE_CTL_ORDER_RGBX REG_BIT(20)
+#define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19)
+#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18)
+#define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16)
+#define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0)
+#define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1)
+#define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2)
+#define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3)
+#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15)
+#define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14)
+#define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */
+#define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */
+#define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10)
+#define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0)
+#define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1)
+#define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4)
+#define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)
+#define PLANE_CTL_ASYNC_FLIP REG_BIT(9)
+#define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8)
+#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */
+#define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */
+#define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0)
+#define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2)
+#define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3)
+#define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0)
+#define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0)
+#define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1)
+#define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2)
+#define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3)
#define _PLANE_STRIDE_1_A 0x70188
#define _PLANE_STRIDE_2_A 0x70288
#define _PLANE_STRIDE_3_A 0x70388
+#define PLANE_STRIDE__MASK REG_GENMASK(11, 0)
+#define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride))
#define _PLANE_POS_1_A 0x7018c
#define _PLANE_POS_2_A 0x7028c
#define _PLANE_POS_3_A 0x7038c
+#define PLANE_POS_Y_MASK REG_GENMASK(31, 16)
+#define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y))
+#define PLANE_POS_X_MASK REG_GENMASK(15, 0)
+#define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x))
#define _PLANE_SIZE_1_A 0x70190
#define _PLANE_SIZE_2_A 0x70290
#define _PLANE_SIZE_3_A 0x70390
+#define PLANE_HEIGHT_MASK REG_GENMASK(31, 16)
+#define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h))
+#define PLANE_WIDTH_MASK REG_GENMASK(15, 0)
+#define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w))
#define _PLANE_SURF_1_A 0x7019c
#define _PLANE_SURF_2_A 0x7029c
#define _PLANE_SURF_3_A 0x7039c
+#define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12)
+#define PLANE_SURF_DECRYPT REG_BIT(2)
#define _PLANE_OFFSET_1_A 0x701a4
#define _PLANE_OFFSET_2_A 0x702a4
#define _PLANE_OFFSET_3_A 0x703a4
+#define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16)
+#define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y))
+#define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0)
+#define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x))
#define _PLANE_KEYVAL_1_A 0x70194
#define _PLANE_KEYVAL_2_A 0x70294
#define _PLANE_KEYMSK_1_A 0x70198
#define _PLANE_CC_VAL_1_A 0x701b4
#define _PLANE_CC_VAL_2_A 0x702b4
#define _PLANE_AUX_DIST_1_A 0x701c0
+#define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12)
+#define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0)
+#define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride))
#define _PLANE_AUX_DIST_2_A 0x702c0
#define _PLANE_AUX_OFFSET_1_A 0x701c4
#define _PLANE_AUX_OFFSET_2_A 0x702c4
#define _PLANE_CUS_CTL_1_A 0x701c8
#define _PLANE_CUS_CTL_2_A 0x702c8
-#define PLANE_CUS_ENABLE (1 << 31)
-#define PLANE_CUS_Y_PLANE_4_RKL (0 << 30)
-#define PLANE_CUS_Y_PLANE_5_RKL (1 << 30)
-#define PLANE_CUS_Y_PLANE_6_ICL (0 << 30)
-#define PLANE_CUS_Y_PLANE_7_ICL (1 << 30)
-#define PLANE_CUS_HPHASE_SIGN_NEGATIVE (1 << 19)
-#define PLANE_CUS_HPHASE_0 (0 << 16)
-#define PLANE_CUS_HPHASE_0_25 (1 << 16)
-#define PLANE_CUS_HPHASE_0_5 (2 << 16)
-#define PLANE_CUS_VPHASE_SIGN_NEGATIVE (1 << 15)
-#define PLANE_CUS_VPHASE_0 (0 << 12)
-#define PLANE_CUS_VPHASE_0_25 (1 << 12)
-#define PLANE_CUS_VPHASE_0_5 (2 << 12)
+#define PLANE_CUS_ENABLE REG_BIT(31)
+#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30)
+#define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
+#define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
+#define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
+#define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
+#define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19)
+#define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16)
+#define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0)
+#define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1)
+#define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2)
+#define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15)
+#define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12)
+#define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0)
+#define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1)
+#define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2)
#define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
#define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
-#define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */
-#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
+#define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */
+#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
+#define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
#define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */
-#define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
-#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
-#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
-#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 (1 << 17)
-#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17)
-#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17)
-#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17)
-#define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13)
-#define PLANE_COLOR_ALPHA_MASK (0x3 << 4)
-#define PLANE_COLOR_ALPHA_DISABLE (0 << 4)
-#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
-#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
+#define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */
+#define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17)
+#define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0)
+#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1)
+#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2)
+#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3)
+#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4)
+#define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13)
+#define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4)
+#define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0)
+#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2)
+#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3)
#define _PLANE_BUF_CFG_1_A 0x7027c
#define _PLANE_BUF_CFG_2_A 0x7037c
#define _PLANE_NV12_BUF_CFG_1_A 0x70278
_PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
#define PLANE_STRIDE(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
-#define PLANE_STRIDE_MASK REG_GENMASK(10, 0)
-#define PLANE_STRIDE_MASK_XELPD REG_GENMASK(11, 0)
#define _PLANE_POS_1_B 0x7118c
#define _PLANE_POS_2_B 0x7128c
#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
#define PLANE_SURF(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
-#define PLANE_SURF_DECRYPT REG_BIT(2)
#define _PLANE_OFFSET_1_B 0x711a4
#define _PLANE_OFFSET_2_B 0x712a4
#define _PLANE_BUF_CFG_1_B 0x7127c
#define _PLANE_BUF_CFG_2_B 0x7137c
-#define DDB_ENTRY_MASK 0xFFF /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
-#define DDB_ENTRY_END_SHIFT 16
+/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
+#define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
+#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
+#define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
+#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
#define _PLANE_BUF_CFG_1(pipe) \
_PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
#define _PLANE_BUF_CFG_2(pipe) \
#define _PIPEA_DATA_M1 0x60030
-#define PIPE_DATA_M1_OFFSET 0
#define _PIPEA_DATA_N1 0x60034
-#define PIPE_DATA_N1_OFFSET 0
-
#define _PIPEA_DATA_M2 0x60038
-#define PIPE_DATA_M2_OFFSET 0
#define _PIPEA_DATA_N2 0x6003c
-#define PIPE_DATA_N2_OFFSET 0
-
#define _PIPEA_LINK_M1 0x60040
-#define PIPE_LINK_M1_OFFSET 0
#define _PIPEA_LINK_N1 0x60044
-#define PIPE_LINK_N1_OFFSET 0
-
#define _PIPEA_LINK_M2 0x60048
-#define PIPE_LINK_M2_OFFSET 0
#define _PIPEA_LINK_N2 0x6004c
-#define PIPE_LINK_N2_OFFSET 0
/* PIPEB timing regs are same start from 0x61000 */
#define _PCH_TRANSBCONF 0xf1008
#define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
#define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
-#define TRANS_DISABLE (0 << 31)
-#define TRANS_ENABLE (1 << 31)
-#define TRANS_STATE_MASK (1 << 30)
-#define TRANS_STATE_DISABLE (0 << 30)
-#define TRANS_STATE_ENABLE (1 << 30)
-#define TRANS_FRAME_START_DELAY_MASK (3 << 27) /* ibx */
-#define TRANS_FRAME_START_DELAY(x) ((x) << 27) /* ibx: 0-3 */
-#define TRANS_INTERLACE_MASK (7 << 21)
-#define TRANS_PROGRESSIVE (0 << 21)
-#define TRANS_INTERLACED (3 << 21)
-#define TRANS_LEGACY_INTERLACED_ILK (2 << 21)
-#define TRANS_8BPC (0 << 5)
-#define TRANS_10BPC (1 << 5)
-#define TRANS_6BPC (2 << 5)
-#define TRANS_12BPC (3 << 5)
-
+#define TRANS_ENABLE REG_BIT(31)
+#define TRANS_STATE_ENABLE REG_BIT(30)
+#define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */
+#define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */
+#define TRANS_INTERLACE_MASK REG_GENMASK(23, 21)
+#define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0)
+#define TRANS_INTERLACE_LEGACY_VSYNC_IBX REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */
+#define TRANS_INTERLACE_INTERLACED REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3)
+#define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */
+#define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0)
+#define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1)
+#define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2)
+#define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3)
#define _TRANSA_CHICKEN1 0xf0060
#define _TRANSB_CHICKEN1 0xf1060
#define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
#define _TRANS_DP_CTL_B 0xe1300
#define _TRANS_DP_CTL_C 0xe2300
#define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
-#define TRANS_DP_OUTPUT_ENABLE (1 << 31)
-#define TRANS_DP_PORT_SEL_MASK (3 << 29)
-#define TRANS_DP_PORT_SEL_NONE (3 << 29)
-#define TRANS_DP_PORT_SEL(port) (((port) - PORT_B) << 29)
-#define TRANS_DP_AUDIO_ONLY (1 << 26)
-#define TRANS_DP_ENH_FRAMING (1 << 18)
-#define TRANS_DP_8BPC (0 << 9)
-#define TRANS_DP_10BPC (1 << 9)
-#define TRANS_DP_6BPC (2 << 9)
-#define TRANS_DP_12BPC (3 << 9)
-#define TRANS_DP_BPC_MASK (3 << 9)
-#define TRANS_DP_VSYNC_ACTIVE_HIGH (1 << 4)
-#define TRANS_DP_VSYNC_ACTIVE_LOW 0
-#define TRANS_DP_HSYNC_ACTIVE_HIGH (1 << 3)
-#define TRANS_DP_HSYNC_ACTIVE_LOW 0
-#define TRANS_DP_SYNC_MASK (3 << 3)
+#define TRANS_DP_OUTPUT_ENABLE REG_BIT(31)
+#define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29)
+#define TRANS_DP_PORT_SEL_NONE REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3)
+#define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B)
+#define TRANS_DP_AUDIO_ONLY REG_BIT(26)
+#define TRANS_DP_ENH_FRAMING REG_BIT(18)
+#define TRANS_DP_BPC_MASK REG_GENMASK(10, 9)
+#define TRANS_DP_BPC_8 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0)
+#define TRANS_DP_BPC_10 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1)
+#define TRANS_DP_BPC_6 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2)
+#define TRANS_DP_BPC_12 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3)
+#define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4)
+#define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3)
#define _TRANS_DP2_CTL_A 0x600a0
#define _TRANS_DP2_CTL_B 0x610a0
#define RC6_CTX_IN_DRAM (1 << 0)
#define RC6_CTX_BASE _MMIO(0xD48)
#define RC6_CTX_BASE_MASK 0xFFFFFFF0
-#define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054)
-#define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054)
-#define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054)
-#define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054)
-#define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054)
-#define IDLE_TIME_MASK 0xFFFFF
#define FORCEWAKE _MMIO(0xA18C)
#define FORCEWAKE_VLV _MMIO(0x1300b0)
#define FORCEWAKE_ACK_VLV _MMIO(0x1300b4)
PORTTC1_PLL_ENABLE, \
PORTTC2_PLL_ENABLE)
-#define _MG_REFCLKIN_CTL_PORT1 0x16892C
-#define _MG_REFCLKIN_CTL_PORT2 0x16992C
-#define _MG_REFCLKIN_CTL_PORT3 0x16A92C
-#define _MG_REFCLKIN_CTL_PORT4 0x16B92C
-#define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8)
-#define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8)
-#define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
- _MG_REFCLKIN_CTL_PORT1, \
- _MG_REFCLKIN_CTL_PORT2)
-
-#define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8
-#define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8
-#define _MG_CLKTOP2_CORECLKCTL1_PORT3 0x16A8D8
-#define _MG_CLKTOP2_CORECLKCTL1_PORT4 0x16B8D8
-#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16)
-#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16)
-#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8)
-#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8)
-#define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \
- _MG_CLKTOP2_CORECLKCTL1_PORT1, \
- _MG_CLKTOP2_CORECLKCTL1_PORT2)
-
-#define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4
-#define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4
-#define _MG_CLKTOP2_HSCLKCTL_PORT3 0x16A8D4
-#define _MG_CLKTOP2_HSCLKCTL_PORT4 0x16B8D4
-#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16)
-#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16)
-#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14)
-#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14)
-#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << 12)
-#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 (0 << 12)
-#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 (1 << 12)
-#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12)
-#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12)
-#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8)
-#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8
-#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8)
-#define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \
- _MG_CLKTOP2_HSCLKCTL_PORT1, \
- _MG_CLKTOP2_HSCLKCTL_PORT2)
-
-#define _MG_PLL_DIV0_PORT1 0x168A00
-#define _MG_PLL_DIV0_PORT2 0x169A00
-#define _MG_PLL_DIV0_PORT3 0x16AA00
-#define _MG_PLL_DIV0_PORT4 0x16BA00
-#define MG_PLL_DIV0_FRACNEN_H (1 << 30)
-#define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fffff << 8)
-#define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8
-#define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8)
-#define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0)
-#define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
-#define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \
- _MG_PLL_DIV0_PORT2)
-
-#define _MG_PLL_DIV1_PORT1 0x168A04
-#define _MG_PLL_DIV1_PORT2 0x169A04
-#define _MG_PLL_DIV1_PORT3 0x16AA04
-#define _MG_PLL_DIV1_PORT4 0x16BA04
-#define MG_PLL_DIV1_IREF_NDIVRATIO(x) ((x) << 16)
-#define MG_PLL_DIV1_DITHER_DIV_1 (0 << 12)
-#define MG_PLL_DIV1_DITHER_DIV_2 (1 << 12)
-#define MG_PLL_DIV1_DITHER_DIV_4 (2 << 12)
-#define MG_PLL_DIV1_DITHER_DIV_8 (3 << 12)
-#define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4)
-#define MG_PLL_DIV1_FBPREDIV_MASK (0xf << 0)
-#define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0)
-#define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \
- _MG_PLL_DIV1_PORT2)
-
-#define _MG_PLL_LF_PORT1 0x168A08
-#define _MG_PLL_LF_PORT2 0x169A08
-#define _MG_PLL_LF_PORT3 0x16AA08
-#define _MG_PLL_LF_PORT4 0x16BA08
-#define MG_PLL_LF_TDCTARGETCNT(x) ((x) << 24)
-#define MG_PLL_LF_AFCCNTSEL_256 (0 << 20)
-#define MG_PLL_LF_AFCCNTSEL_512 (1 << 20)
-#define MG_PLL_LF_GAINCTRL(x) ((x) << 16)
-#define MG_PLL_LF_INT_COEFF(x) ((x) << 8)
-#define MG_PLL_LF_PROP_COEFF(x) ((x) << 0)
-#define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \
- _MG_PLL_LF_PORT2)
-
-#define _MG_PLL_FRAC_LOCK_PORT1 0x168A0C
-#define _MG_PLL_FRAC_LOCK_PORT2 0x169A0C
-#define _MG_PLL_FRAC_LOCK_PORT3 0x16AA0C
-#define _MG_PLL_FRAC_LOCK_PORT4 0x16BA0C
-#define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 (1 << 18)
-#define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 (1 << 16)
-#define MG_PLL_FRAC_LOCK_LOCKTHRESH(x) ((x) << 11)
-#define MG_PLL_FRAC_LOCK_DCODITHEREN (1 << 10)
-#define MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN (1 << 8)
-#define MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x) ((x) << 0)
-#define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \
- _MG_PLL_FRAC_LOCK_PORT1, \
- _MG_PLL_FRAC_LOCK_PORT2)
-
-#define _MG_PLL_SSC_PORT1 0x168A10
-#define _MG_PLL_SSC_PORT2 0x169A10
-#define _MG_PLL_SSC_PORT3 0x16AA10
-#define _MG_PLL_SSC_PORT4 0x16BA10
-#define MG_PLL_SSC_EN (1 << 28)
-#define MG_PLL_SSC_TYPE(x) ((x) << 26)
-#define MG_PLL_SSC_STEPLENGTH(x) ((x) << 16)
-#define MG_PLL_SSC_STEPNUM(x) ((x) << 10)
-#define MG_PLL_SSC_FLLEN (1 << 9)
-#define MG_PLL_SSC_STEPSIZE(x) ((x) << 0)
-#define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \
- _MG_PLL_SSC_PORT2)
-
-#define _MG_PLL_BIAS_PORT1 0x168A14
-#define _MG_PLL_BIAS_PORT2 0x169A14
-#define _MG_PLL_BIAS_PORT3 0x16AA14
-#define _MG_PLL_BIAS_PORT4 0x16BA14
-#define MG_PLL_BIAS_BIAS_GB_SEL(x) ((x) << 30)
-#define MG_PLL_BIAS_BIAS_GB_SEL_MASK (0x3 << 30)
-#define MG_PLL_BIAS_INIT_DCOAMP(x) ((x) << 24)
-#define MG_PLL_BIAS_INIT_DCOAMP_MASK (0x3f << 24)
-#define MG_PLL_BIAS_BIAS_BONUS(x) ((x) << 16)
-#define MG_PLL_BIAS_BIAS_BONUS_MASK (0xff << 16)
-#define MG_PLL_BIAS_BIASCAL_EN (1 << 15)
-#define MG_PLL_BIAS_CTRIM(x) ((x) << 8)
-#define MG_PLL_BIAS_CTRIM_MASK (0x1f << 8)
-#define MG_PLL_BIAS_VREF_RDAC(x) ((x) << 5)
-#define MG_PLL_BIAS_VREF_RDAC_MASK (0x7 << 5)
-#define MG_PLL_BIAS_IREFTRIM(x) ((x) << 0)
-#define MG_PLL_BIAS_IREFTRIM_MASK (0x1f << 0)
-#define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \
- _MG_PLL_BIAS_PORT2)
-
-#define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168A18
-#define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169A18
-#define _MG_PLL_TDC_COLDST_BIAS_PORT3 0x16AA18
-#define _MG_PLL_TDC_COLDST_BIAS_PORT4 0x16BA18
-#define MG_PLL_TDC_COLDST_IREFINT_EN (1 << 27)
-#define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x) ((x) << 17)
-#define MG_PLL_TDC_COLDST_COLDSTART (1 << 16)
-#define MG_PLL_TDC_TDCOVCCORR_EN (1 << 2)
-#define MG_PLL_TDC_TDCSEL(x) ((x) << 0)
-#define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \
- _MG_PLL_TDC_COLDST_BIAS_PORT1, \
- _MG_PLL_TDC_COLDST_BIAS_PORT2)
-
#define _ICL_DPLL0_CFGCR0 0x164000
#define _ICL_DPLL1_CFGCR0 0x164080
#define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
+#define PRIMARY_SPI_TRIGGER _MMIO(0x102040)
+#define PRIMARY_SPI_ADDRESS _MMIO(0x102080)
+#define PRIMARY_SPI_REGIONID _MMIO(0x102084)
+#define SPI_STATIC_REGIONS _MMIO(0x102090)
+#define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0)
+#define OROM_OFFSET _MMIO(0x1020c0)
+#define OROM_OFFSET_MASK REG_GENMASK(20, 16)
+
/* This register controls the Display State Buffer (DSB) engines. */
#define _DSBSL_INSTANCE_BASE 0x70B00
#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
--- /dev/null
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __I915_REG_DEFS__
+#define __I915_REG_DEFS__
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+
+/**
+ * REG_BIT() - Prepare a u32 bit value
+ * @__n: 0-based bit number
+ *
+ * Local wrapper for BIT() to force u32, with compile time checks.
+ *
+ * @return: Value with bit @__n set.
+ */
+#define REG_BIT(__n) \
+ ((u32)(BIT(__n) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
+ ((__n) < 0 || (__n) > 31))))
+
+/**
+ * REG_GENMASK() - Prepare a continuous u32 bitmask
+ * @__high: 0-based high bit
+ * @__low: 0-based low bit
+ *
+ * Local wrapper for GENMASK() to force u32, with compile time checks.
+ *
+ * @return: Continuous bitmask from @__high to @__low, inclusive.
+ */
+#define REG_GENMASK(__high, __low) \
+ ((u32)(GENMASK(__high, __low) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
+ __is_constexpr(__low) && \
+ ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
+
+/*
+ * Local integer constant expression version of is_power_of_2().
+ */
+#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
+
+/**
+ * REG_FIELD_PREP() - Prepare a u32 bitfield value
+ * @__mask: shifted mask defining the field's length and position
+ * @__val: value to put in the field
+ *
+ * Local copy of FIELD_PREP() to generate an integer constant expression, force
+ * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
+ *
+ * @return: @__val masked and shifted into the field defined by @__mask.
+ */
+#define REG_FIELD_PREP(__mask, __val) \
+ ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
+ BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
+ BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
+ BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
+
+/**
+ * REG_FIELD_GET() - Extract a u32 bitfield value
+ * @__mask: shifted mask defining the field's length and position
+ * @__val: value to extract the bitfield value from
+ *
+ * Local wrapper for FIELD_GET() to force u32 and for consistency with
+ * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
+ *
+ * @return: Masked and shifted value of the field defined by @__mask in @__val.
+ */
+#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
+
+typedef struct {
+ u32 reg;
+} i915_reg_t;
+
+#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
+
+#define INVALID_MMIO_REG _MMIO(0)
+
+static __always_inline u32 i915_mmio_reg_offset(i915_reg_t reg)
+{
+ return reg.reg;
+}
+
+static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
+{
+ return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
+}
+
+static inline bool i915_mmio_reg_valid(i915_reg_t reg)
+{
+ return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
+}
+
+#endif /* __I915_REG_DEFS__ */
#include "gt/intel_context.h"
#include "gt/intel_engine.h"
#include "gt/intel_engine_heartbeat.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_gpu_commands.h"
#include "gt/intel_reset.h"
#include "gt/intel_ring.h"
#include "i915_drv.h"
#include "i915_reg.h"
#include "i915_suspend.h"
+#include "intel_pci_config.h"
static void intel_save_swf(struct drm_i915_private *dev_priv)
{
#define FDO_BUG_URL "https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs"
-#undef WARN_ON
-/* Many gcc seem to no see through this and fall over :( */
-#if 0
-#define WARN_ON(x) ({ \
- bool __i915_warn_cond = (x); \
- if (__builtin_constant_p(__i915_warn_cond)) \
- BUILD_BUG_ON(__i915_warn_cond); \
- WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
-#else
-#define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
-#endif
-
-#undef WARN_ON_ONCE
-#define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
-
#define MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \
__stringify(x), (long)(x))
#include <drm/drm_gem.h>
#include "display/intel_frontbuffer.h"
-
#include "gem/i915_gem_lmem.h"
+#include "gem/i915_gem_tiling.h"
#include "gt/intel_engine.h"
#include "gt/intel_engine_heartbeat.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_requests.h"
#include "i915_drv.h"
+#include "i915_gem_evict.h"
#include "i915_sw_fence_work.h"
#include "i915_trace.h"
#include "i915_vma.h"
INTEL_ICL_PORT_F_IDS(0),
};
+static const u16 subplatform_n_ids[] = {
+ INTEL_ADLN_IDS(0),
+};
+
static const u16 subplatform_rpls_ids[] = {
INTEL_RPLS_IDS(0),
};
} else if (find_devid(devid, subplatform_portf_ids,
ARRAY_SIZE(subplatform_portf_ids))) {
mask = BIT(INTEL_SUBPLATFORM_PORTF);
+ } else if (find_devid(devid, subplatform_n_ids,
+ ARRAY_SIZE(subplatform_n_ids))) {
+ mask = BIT(INTEL_SUBPLATFORM_N);
} else if (find_devid(devid, subplatform_rpls_ids,
ARRAY_SIZE(subplatform_rpls_ids))) {
mask = BIT(INTEL_SUBPLATFORM_RPL_S);
"Display fused off, disabling\n");
info->display.pipe_mask = 0;
info->display.cpu_transcoder_mask = 0;
+ info->display.fbc_mask = 0;
} else if (fuse_strap & IVB_PIPE_C_DISABLE) {
drm_info(&dev_priv->drm, "PipeC fused off\n");
info->display.pipe_mask &= ~BIT(PIPE_C);
if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
info->display.pipe_mask &= ~BIT(PIPE_A);
info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
+ info->display.fbc_mask &= ~BIT(INTEL_FBC_A);
}
if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
info->display.pipe_mask &= ~BIT(PIPE_B);
info->display.has_hdcp = 0;
if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
- info->display.has_fbc = 0;
+ info->display.fbc_mask = 0;
if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
info->display.has_dmc = 0;
/* ADL-S */
#define INTEL_SUBPLATFORM_RPL_S 0
+/* ADL-P */
+#define INTEL_SUBPLATFORM_N 0
+
enum intel_ppgtt_type {
INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
func(has_dp_mst); \
func(has_dsb); \
func(has_dsc); \
- func(has_fbc); \
func(has_fpga_dbg); \
func(has_gmch); \
func(has_hdcp); \
u8 pipe_mask;
u8 cpu_transcoder_mask;
+ u8 fbc_mask;
u8 abox_mask;
#define DEFINE_FLAG(name) u8 name:1
u32 val = 0;
int ret;
- ret = sandybridge_pcode_read(dev_priv,
- ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
- ICL_PCODE_MEM_SS_READ_GLOBAL_INFO,
- &val, NULL);
+ ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
+ ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, &val, NULL);
if (ret)
return ret;
--- /dev/null
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_PCI_CONFIG_H__
+#define __INTEL_PCI_CONFIG_H__
+
+/* BSM in include/drm/i915_drm.h */
+
+#define MCHBAR_I915 0x44
+#define MCHBAR_I965 0x48
+#define MCHBAR_SIZE (4 * 4096)
+
+#define DEVEN 0x54
+#define DEVEN_MCHBAR_EN (1 << 28)
+
+#define HPLLCC 0xc0 /* 85x only */
+#define GC_CLOCK_CONTROL_MASK (0x7 << 0)
+#define GC_CLOCK_133_200 (0 << 0)
+#define GC_CLOCK_100_200 (1 << 0)
+#define GC_CLOCK_100_133 (2 << 0)
+#define GC_CLOCK_133_266 (3 << 0)
+#define GC_CLOCK_133_200_2 (4 << 0)
+#define GC_CLOCK_133_266_2 (5 << 0)
+#define GC_CLOCK_166_266 (6 << 0)
+#define GC_CLOCK_166_250 (7 << 0)
+
+#define I915_GDRST 0xc0
+#define GRDOM_FULL (0 << 2)
+#define GRDOM_RENDER (1 << 2)
+#define GRDOM_MEDIA (3 << 2)
+#define GRDOM_MASK (3 << 2)
+#define GRDOM_RESET_STATUS (1 << 1)
+#define GRDOM_RESET_ENABLE (1 << 0)
+
+/* BSpec only has register offset, PCI device and bit found empirically */
+#define I830_CLOCK_GATE 0xc8 /* device 0 */
+#define I830_L2_CACHE_CLOCK_GATE_DISABLE (1 << 2)
+
+#define GCDGMBUS 0xcc
+
+#define GCFGC2 0xda
+#define GCFGC 0xf0 /* 915+ only */
+#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
+#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
+#define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4)
+#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
+#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
+#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
+#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
+#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
+#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
+#define GC_DISPLAY_CLOCK_MASK (7 << 4)
+#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
+#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
+#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
+#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
+#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
+#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
+#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
+#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
+#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
+#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
+#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
+#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
+#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
+#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
+#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
+#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
+#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
+#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
+#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
+
+#define ASLE 0xe4
+#define ASLS 0xfc
+
+#define SWSCI 0xe8
+#define SWSCI_SCISEL (1 << 15)
+#define SWSCI_GSSCIE (1 << 0)
+
+/* legacy/combination backlight modes, also called LBB */
+#define LBPC 0xf4
+
+#endif /* __INTEL_PCI_CONFIG_H__ */
}
}
-static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
- u32 mbox, u32 *val, u32 *val1,
- int fast_timeout_us,
- int slow_timeout_ms,
- bool is_read)
+static int __snb_pcode_rw(struct drm_i915_private *i915, u32 mbox,
+ u32 *val, u32 *val1,
+ int fast_timeout_us, int slow_timeout_ms,
+ bool is_read)
{
struct intel_uncore *uncore = &i915->uncore;
return gen6_check_mailbox_status(mbox);
}
-int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox,
- u32 *val, u32 *val1)
+int snb_pcode_read(struct drm_i915_private *i915, u32 mbox, u32 *val, u32 *val1)
{
int err;
mutex_lock(&i915->sb_lock);
- err = __sandybridge_pcode_rw(i915, mbox, val, val1,
- 500, 20,
- true);
+ err = __snb_pcode_rw(i915, mbox, val, val1, 500, 20, true);
mutex_unlock(&i915->sb_lock);
if (err) {
return err;
}
-int sandybridge_pcode_write_timeout(struct drm_i915_private *i915,
- u32 mbox, u32 val,
- int fast_timeout_us,
- int slow_timeout_ms)
+int snb_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox, u32 val,
+ int fast_timeout_us, int slow_timeout_ms)
{
int err;
mutex_lock(&i915->sb_lock);
- err = __sandybridge_pcode_rw(i915, mbox, &val, NULL,
- fast_timeout_us, slow_timeout_ms,
- false);
+ err = __snb_pcode_rw(i915, mbox, &val, NULL,
+ fast_timeout_us, slow_timeout_ms, false);
mutex_unlock(&i915->sb_lock);
if (err) {
u32 request, u32 reply_mask, u32 reply,
u32 *status)
{
- *status = __sandybridge_pcode_rw(i915, mbox, &request, NULL,
- 500, 0,
- true);
+ *status = __snb_pcode_rw(i915, mbox, &request, NULL, 500, 0, true);
return *status || ((request & reply_mask) == reply);
}
struct drm_i915_private;
-int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox,
- u32 *val, u32 *val1);
-int sandybridge_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox,
- u32 val, int fast_timeout_us,
- int slow_timeout_ms);
-#define sandybridge_pcode_write(i915, mbox, val) \
- sandybridge_pcode_write_timeout(i915, mbox, val, 500, 0)
+int snb_pcode_read(struct drm_i915_private *i915, u32 mbox, u32 *val, u32 *val1);
+int snb_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox, u32 val,
+ int fast_timeout_us, int slow_timeout_ms);
+#define snb_pcode_write(i915, mbox, val) \
+ snb_pcode_write_timeout(i915, mbox, val, 500, 0)
int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
u32 reply_mask, u32 reply, int timeout_base_ms);
#include "display/intel_sprite.h"
#include "display/skl_universal_plane.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_llc.h"
#include "i915_drv.h"
static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
{
- enum pipe pipe;
-
if (HAS_LLC(dev_priv)) {
/*
* WaCompressedResourceDisplayNewHashMode:skl,kbl
SKL_DE_COMPRESSED_HASH_MODE);
}
- for_each_pipe(dev_priv, pipe) {
- /*
- * "Plane N strech max must be programmed to 11b (x1)
- * when Async flips are enabled on that plane."
- */
- if (!IS_GEMINILAKE(dev_priv) && intel_vtd_active(dev_priv))
- intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe),
- SKL_PLANE1_STRETCH_MAX_MASK, SKL_PLANE1_STRETCH_MAX_X1);
- }
-
/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1,
intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
* WaFbcHighMemBwCorruptionAvoidance:bxt
* Display WA #0883: bxt
*/
- intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
- DPFC_DISABLE_DUMMY0);
+ intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
+ intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A)) |
+ DPFC_DISABLE_DUMMY0);
}
static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
* crtc->state->active once we have proper CRTC states wired up
* for atomic.
*/
- return crtc->active && crtc->base.primary->state->fb &&
+ return crtc && crtc->active && crtc->base.primary->state->fb &&
crtc->config->hw.adjusted_mode.crtc_clock;
}
crtc = single_enabled_crtc(dev_priv);
if (crtc) {
- const struct drm_display_mode *pipe_mode =
- &crtc->config->hw.pipe_mode;
const struct drm_framebuffer *fb =
crtc->base.primary->state->fb;
+ int pixel_rate = crtc->config->pixel_rate;
int cpp = fb->format->cpp[0];
- int clock = pipe_mode->crtc_clock;
/* Display SR */
- wm = intel_calculate_wm(clock, &pnv_display_wm,
+ wm = intel_calculate_wm(pixel_rate, &pnv_display_wm,
pnv_display_wm.fifo_size,
cpp, latency->display_sr);
reg = intel_uncore_read(&dev_priv->uncore, DSPFW1);
drm_dbg_kms(&dev_priv->drm, "DSPFW1 register is %x\n", reg);
/* cursor SR */
- wm = intel_calculate_wm(clock, &pnv_cursor_wm,
+ wm = intel_calculate_wm(pixel_rate, &pnv_cursor_wm,
pnv_display_wm.fifo_size,
4, latency->cursor_sr);
reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
/* Display HPLL off SR */
- wm = intel_calculate_wm(clock, &pnv_display_hplloff_wm,
+ wm = intel_calculate_wm(pixel_rate, &pnv_display_hplloff_wm,
pnv_display_hplloff_wm.fifo_size,
cpp, latency->display_hpll_disable);
reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
/* cursor HPLL off SR */
- wm = intel_calculate_wm(clock, &pnv_cursor_hplloff_wm,
+ wm = intel_calculate_wm(pixel_rate, &pnv_cursor_hplloff_wm,
pnv_display_hplloff_wm.fifo_size,
4, latency->cursor_hpll_disable);
reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
const struct drm_display_mode *pipe_mode =
&crtc_state->hw.pipe_mode;
unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
- unsigned int clock, htotal, cpp, width, wm;
+ unsigned int pixel_rate, htotal, cpp, width, wm;
if (latency == 0)
return USHRT_MAX;
level != G4X_WM_LEVEL_NORMAL)
cpp = max(cpp, 4u);
- clock = pipe_mode->crtc_clock;
+ pixel_rate = crtc_state->pixel_rate;
htotal = pipe_mode->crtc_htotal;
-
- width = drm_rect_width(&plane_state->uapi.dst);
+ width = drm_rect_width(&plane_state->uapi.src) >> 16;
if (plane->id == PLANE_CURSOR) {
- wm = intel_wm_method2(clock, htotal, width, cpp, latency);
+ wm = intel_wm_method2(pixel_rate, htotal, width, cpp, latency);
} else if (plane->id == PLANE_PRIMARY &&
level == G4X_WM_LEVEL_NORMAL) {
- wm = intel_wm_method1(clock, cpp, latency);
+ wm = intel_wm_method1(pixel_rate, cpp, latency);
} else {
unsigned int small, large;
- small = intel_wm_method1(clock, cpp, latency);
- large = intel_wm_method2(clock, htotal, width, cpp, latency);
+ small = intel_wm_method1(pixel_rate, cpp, latency);
+ large = intel_wm_method2(pixel_rate, htotal, width, cpp, latency);
wm = min(small, large);
}
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
const struct drm_display_mode *pipe_mode =
&crtc_state->hw.pipe_mode;
- unsigned int clock, htotal, cpp, width, wm;
+ unsigned int pixel_rate, htotal, cpp, width, wm;
if (dev_priv->wm.pri_latency[level] == 0)
return USHRT_MAX;
return 0;
cpp = plane_state->hw.fb->format->cpp[0];
- clock = pipe_mode->crtc_clock;
+ pixel_rate = crtc_state->pixel_rate;
htotal = pipe_mode->crtc_htotal;
- width = crtc_state->pipe_src_w;
+ width = drm_rect_width(&plane_state->uapi.src) >> 16;
if (plane->id == PLANE_CURSOR) {
/*
*/
wm = 63;
} else {
- wm = vlv_wm_method2(clock, htotal, width, cpp,
+ wm = vlv_wm_method2(pixel_rate, htotal, width, cpp,
dev_priv->wm.pri_latency[level] * 10);
}
&crtc->config->hw.pipe_mode;
const struct drm_framebuffer *fb =
crtc->base.primary->state->fb;
- int clock = pipe_mode->crtc_clock;
+ int pixel_rate = crtc->config->pixel_rate;
int htotal = pipe_mode->crtc_htotal;
- int hdisplay = crtc->config->pipe_src_w;
+ int width = drm_rect_width(&crtc->base.primary->state->src) >> 16;
int cpp = fb->format->cpp[0];
int entries;
- entries = intel_wm_method2(clock, htotal,
- hdisplay, cpp, sr_latency_ns / 100);
+ entries = intel_wm_method2(pixel_rate, htotal,
+ width, cpp, sr_latency_ns / 100);
entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
srwm = I965_FIFO_SIZE - entries;
if (srwm < 0)
"self-refresh entries: %d, wm: %d\n",
entries, srwm);
- entries = intel_wm_method2(clock, htotal,
+ entries = intel_wm_method2(pixel_rate, htotal,
crtc->base.cursor->state->crtc_w, 4,
sr_latency_ns / 100);
entries = DIV_ROUND_UP(entries,
int cwm, srwm = 1;
int fifo_size;
int planea_wm, planeb_wm;
- struct intel_crtc *crtc, *enabled = NULL;
+ struct intel_crtc *crtc;
if (IS_I945GM(dev_priv))
wm_info = &i945_wm_info;
fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_A);
crtc = intel_crtc_for_plane(dev_priv, PLANE_A);
if (intel_crtc_active(crtc)) {
- const struct drm_display_mode *pipe_mode =
- &crtc->config->hw.pipe_mode;
const struct drm_framebuffer *fb =
crtc->base.primary->state->fb;
int cpp;
else
cpp = fb->format->cpp[0];
- planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
+ planea_wm = intel_calculate_wm(crtc->config->pixel_rate,
wm_info, fifo_size, cpp,
pessimal_latency_ns);
- enabled = crtc;
} else {
planea_wm = fifo_size - wm_info->guard_size;
if (planea_wm > (long)wm_info->max_wm)
fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_B);
crtc = intel_crtc_for_plane(dev_priv, PLANE_B);
if (intel_crtc_active(crtc)) {
- const struct drm_display_mode *pipe_mode =
- &crtc->config->hw.pipe_mode;
const struct drm_framebuffer *fb =
crtc->base.primary->state->fb;
int cpp;
else
cpp = fb->format->cpp[0];
- planeb_wm = intel_calculate_wm(pipe_mode->crtc_clock,
+ planeb_wm = intel_calculate_wm(crtc->config->pixel_rate,
wm_info, fifo_size, cpp,
pessimal_latency_ns);
- if (enabled == NULL)
- enabled = crtc;
- else
- enabled = NULL;
} else {
planeb_wm = fifo_size - wm_info->guard_size;
if (planeb_wm > (long)wm_info->max_wm)
drm_dbg_kms(&dev_priv->drm,
"FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
- if (IS_I915GM(dev_priv) && enabled) {
+ crtc = single_enabled_crtc(dev_priv);
+ if (IS_I915GM(dev_priv) && crtc) {
struct drm_i915_gem_object *obj;
- obj = intel_fb_obj(enabled->base.primary->state->fb);
+ obj = intel_fb_obj(crtc->base.primary->state->fb);
/* self-refresh seems busted with untiled */
if (!i915_gem_object_is_tiled(obj))
- enabled = NULL;
+ crtc = NULL;
}
/*
intel_set_memory_cxsr(dev_priv, false);
/* Calc sr entries for one plane configs */
- if (HAS_FW_BLC(dev_priv) && enabled) {
+ if (HAS_FW_BLC(dev_priv) && crtc) {
/* self-refresh has much higher latency */
static const int sr_latency_ns = 6000;
const struct drm_display_mode *pipe_mode =
- &enabled->config->hw.pipe_mode;
+ &crtc->config->hw.pipe_mode;
const struct drm_framebuffer *fb =
- enabled->base.primary->state->fb;
- int clock = pipe_mode->crtc_clock;
+ crtc->base.primary->state->fb;
+ int pixel_rate = crtc->config->pixel_rate;
int htotal = pipe_mode->crtc_htotal;
- int hdisplay = enabled->config->pipe_src_w;
+ int width = drm_rect_width(&crtc->base.primary->state->src) >> 16;
int cpp;
int entries;
else
cpp = fb->format->cpp[0];
- entries = intel_wm_method2(clock, htotal, hdisplay, cpp,
+ entries = intel_wm_method2(pixel_rate, htotal, width, cpp,
sr_latency_ns / 100);
entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
drm_dbg_kms(&dev_priv->drm,
intel_uncore_write(&dev_priv->uncore, FW_BLC, fwater_lo);
intel_uncore_write(&dev_priv->uncore, FW_BLC2, fwater_hi);
- if (enabled)
+ if (crtc)
intel_set_memory_cxsr(dev_priv, true);
}
static void i845_update_wm(struct drm_i915_private *dev_priv)
{
struct intel_crtc *crtc;
- const struct drm_display_mode *pipe_mode;
u32 fwater_lo;
int planea_wm;
if (crtc == NULL)
return;
- pipe_mode = &crtc->config->hw.pipe_mode;
- planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
+ planea_wm = intel_calculate_wm(crtc->config->pixel_rate,
&i845_wm_info,
i845_get_fifo_size(dev_priv, PLANE_A),
4, pessimal_latency_ns);
method2 = ilk_wm_method2(crtc_state->pixel_rate,
crtc_state->hw.pipe_mode.crtc_htotal,
- drm_rect_width(&plane_state->uapi.dst),
+ drm_rect_width(&plane_state->uapi.src) >> 16,
cpp, mem_value);
return min(method1, method2);
method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
method2 = ilk_wm_method2(crtc_state->pixel_rate,
crtc_state->hw.pipe_mode.crtc_htotal,
- drm_rect_width(&plane_state->uapi.dst),
+ drm_rect_width(&plane_state->uapi.src) >> 16,
cpp, mem_value);
return min(method1, method2);
}
return ilk_wm_method2(crtc_state->pixel_rate,
crtc_state->hw.pipe_mode.crtc_htotal,
- drm_rect_width(&plane_state->uapi.dst),
+ drm_rect_width(&plane_state->uapi.src) >> 16,
cpp, mem_value);
}
cpp = plane_state->hw.fb->format->cpp[0];
- return ilk_wm_fbc(pri_val, drm_rect_width(&plane_state->uapi.dst),
+ return ilk_wm_fbc(pri_val, drm_rect_width(&plane_state->uapi.src) >> 16,
cpp);
}
/* read the first set of memory latencies[0:3] */
val = 0; /* data0 to be programmed to 0 for first set */
- ret = sandybridge_pcode_read(dev_priv,
- GEN9_PCODE_READ_MEM_LATENCY,
- &val, NULL);
+ ret = snb_pcode_read(dev_priv, GEN9_PCODE_READ_MEM_LATENCY,
+ &val, NULL);
if (ret) {
drm_err(&dev_priv->drm,
/* read the second set of memory latencies[4:7] */
val = 1; /* data0 to be programmed to 1 for second set */
- ret = sandybridge_pcode_read(dev_priv,
- GEN9_PCODE_READ_MEM_LATENCY,
- &val, NULL);
+ ret = snb_pcode_read(dev_priv, GEN9_PCODE_READ_MEM_LATENCY,
+ &val, NULL);
if (ret) {
drm_err(&dev_priv->drm,
"SKL Mailbox read error = %d\n", ret);
u32 val = 0;
int ret;
- ret = sandybridge_pcode_read(dev_priv,
- GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
- &val, NULL);
+ ret = snb_pcode_read(dev_priv,
+ GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
+ &val, NULL);
if (!ret) {
dev_priv->sagv_block_time_us = val;
return;
return 0;
drm_dbg_kms(&dev_priv->drm, "Enabling SAGV\n");
- ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
- GEN9_SAGV_ENABLE);
+ ret = snb_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
+ GEN9_SAGV_ENABLE);
/* We don't need to wait for SAGV when enabling */
u64 modifier, unsigned int rotation,
u32 plane_pixel_rate, struct skl_wm_params *wp,
int color_plane);
+
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
+ struct intel_plane *plane,
int level,
unsigned int latency,
const struct skl_wm_params *wp,
skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
int num_active)
{
+ struct intel_plane *plane = to_intel_plane(crtc_state->uapi.crtc->cursor);
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
int level, max_level = ilk_wm_max_level(dev_priv);
struct skl_wm_level wm = {};
for (level = 0; level <= max_level; level++) {
unsigned int latency = dev_priv->wm.skl_latency[level];
- skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
+ skl_compute_plane_wm(crtc_state, plane, level, latency, &wp, &wm, &wm);
if (wm.min_ddb_alloc == U16_MAX)
break;
static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
struct skl_ddb_entry *entry, u32 reg)
{
- entry->start = reg & DDB_ENTRY_MASK;
- entry->end = (reg >> DDB_ENTRY_END_SHIFT) & DDB_ENTRY_MASK;
-
+ entry->start = REG_FIELD_GET(PLANE_BUF_START_MASK, reg);
+ entry->end = REG_FIELD_GET(PLANE_BUF_END_MASK, reg);
if (entry->end)
- entry->end += 1;
+ entry->end++;
}
static void
/* No DDB allocated for disabled planes */
if (val & PLANE_CTL_ENABLE)
- fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK,
+ fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK_SKL,
val & PLANE_CTL_ORDER_RGBX,
val & PLANE_CTL_ALPHA_MASK);
return active_pipes & BIT(pipe) ? BIT(DBUF_S1) : 0;
}
+static bool
+use_min_ddb(const struct intel_crtc_state *crtc_state,
+ struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+ return DISPLAY_VER(i915) >= 13 &&
+ crtc_state->uapi.async_flip &&
+ plane->async_flip;
+}
+
+static bool
+use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
+ struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+ return DISPLAY_VER(i915) >= 13 &&
+ crtc_state->uapi.async_flip &&
+ plane->async_flip;
+}
+
static u64
skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state,
if (plane->id == PLANE_CURSOR)
return 0;
+ /*
+ * We calculate extra ddb based on ratio plane rate/total data rate
+ * in case, in some cases we should not allocate extra ddb for the plane,
+ * so do not count its data rate, if this is the case.
+ */
+ if (use_min_ddb(crtc_state, plane))
+ return 0;
+
if (color_plane == 1 &&
!intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
return 0;
}
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
+ struct intel_plane *plane,
int level,
unsigned int latency,
const struct skl_wm_params *wp,
uint_fixed_16_16_t selected_result;
u32 blocks, lines, min_ddb_alloc = 0;
- if (latency == 0) {
+ if (latency == 0 ||
+ (use_minimal_wm0_only(crtc_state, plane) && level > 0)) {
/* reject it */
result->min_ddb_alloc = U16_MAX;
return;
static void
skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
+ struct intel_plane *plane,
const struct skl_wm_params *wm_params,
struct skl_wm_level *levels)
{
struct skl_wm_level *result = &levels[level];
unsigned int latency = dev_priv->wm.skl_latency[level];
- skl_compute_plane_wm(crtc_state, level, latency,
+ skl_compute_plane_wm(crtc_state, plane, level, latency,
wm_params, result_prev, result);
result_prev = result;
}
static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
+ struct intel_plane *plane,
const struct skl_wm_params *wm_params,
struct skl_plane_wm *plane_wm)
{
struct skl_wm_level *levels = plane_wm->wm;
unsigned int latency = dev_priv->wm.skl_latency[0] + dev_priv->sagv_block_time_us;
- skl_compute_plane_wm(crtc_state, 0, latency,
+ skl_compute_plane_wm(crtc_state, plane, 0, latency,
wm_params, &levels[0],
sagv_wm);
}
static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state,
- enum plane_id plane_id, int color_plane)
+ struct intel_plane *plane, int color_plane)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
+ struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id];
struct skl_wm_params wm_params;
int ret;
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
+ skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->wm);
skl_compute_transition_wm(dev_priv, &wm->trans_wm,
&wm->wm[0], &wm_params);
if (DISPLAY_VER(dev_priv) >= 12) {
- tgl_compute_sagv_wm(crtc_state, &wm_params, wm);
+ tgl_compute_sagv_wm(crtc_state, plane, &wm_params, wm);
skl_compute_transition_wm(dev_priv, &wm->sagv.trans_wm,
&wm->sagv.wm0, &wm_params);
static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state,
- enum plane_id plane_id)
+ struct intel_plane *plane)
{
- struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
+ struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id];
struct skl_wm_params wm_params;
int ret;
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
+ skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->uv_wm);
return 0;
}
return 0;
ret = skl_build_plane_wm_single(crtc_state, plane_state,
- plane_id, 0);
+ plane, 0);
if (ret)
return ret;
if (fb->format->is_yuv && fb->format->num_planes > 1) {
ret = skl_build_plane_wm_uv(crtc_state, plane_state,
- plane_id);
+ plane);
if (ret)
return ret;
}
if (plane_state->planar_linked_plane) {
const struct drm_framebuffer *fb = plane_state->hw.fb;
- enum plane_id y_plane_id = plane_state->planar_linked_plane->id;
drm_WARN_ON(&dev_priv->drm,
!intel_wm_plane_visible(crtc_state, plane_state));
fb->format->num_planes == 1);
ret = skl_build_plane_wm_single(crtc_state, plane_state,
- y_plane_id, 0);
+ plane_state->planar_linked_plane, 0);
if (ret)
return ret;
ret = skl_build_plane_wm_single(crtc_state, plane_state,
- plane_id, 1);
+ plane, 1);
if (ret)
return ret;
} else if (intel_wm_plane_visible(crtc_state, plane_state)) {
ret = skl_build_plane_wm_single(crtc_state, plane_state,
- plane_id, 0);
+ plane, 0);
if (ret)
return ret;
}
{
if (entry->end)
intel_de_write_fw(dev_priv, reg,
- (entry->end - 1) << 16 | entry->start);
+ PLANE_BUF_END(entry->end - 1) |
+ PLANE_BUF_START(entry->start));
else
intel_de_write_fw(dev_priv, reg, 0);
}
for_each_pipe(dev_priv, pipe) {
intel_uncore_write(&dev_priv->uncore, DSPCNTR(pipe),
intel_uncore_read(&dev_priv->uncore, DSPCNTR(pipe)) |
- DISPPLANE_TRICKLE_FEED_DISABLE);
+ DISP_TRICKLE_FEED_DISABLE);
intel_uncore_write(&dev_priv->uncore, DSPSURF(pipe), intel_uncore_read(&dev_priv->uncore, DSPSURF(pipe)));
intel_uncore_posting_read(&dev_priv->uncore, DSPSURF(pipe));
static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
{
/* Wa_1409120013:icl,ehl */
- intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
- DPFC_CHICKEN_COMP_DUMMY_PIXEL);
+ intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
+ DPFC_CHICKEN_COMP_DUMMY_PIXEL);
/*Wa_14010594013:icl, ehl */
intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
/* Wa_1409120013:tgl,rkl,adl-s,dg1,dg2 */
if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv) || IS_DG2(dev_priv))
- intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
+ intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
DPFC_CHICKEN_COMP_DUMMY_PIXEL);
/* Wa_1409825376:tgl (pre-prod)*/
* WaFbcNukeOnHostModify:cfl
* Display WA #0873: cfl
*/
- intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
- DPFC_NUKE_ON_ANY_MODIFICATION);
+ intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
+ intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A)) |
+ DPFC_NUKE_ON_ANY_MODIFICATION);
}
static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
* WaFbcNukeOnHostModify:kbl
* Display WA #0873: kbl
*/
- intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
- DPFC_NUKE_ON_ANY_MODIFICATION);
+ intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
+ intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A)) |
+ DPFC_NUKE_ON_ANY_MODIFICATION);
}
static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
* WaFbcNukeOnHostModify:skl
* Display WA #0873: skl
*/
- intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
- DPFC_NUKE_ON_ANY_MODIFICATION);
+ intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
+ intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A)) |
+ DPFC_NUKE_ON_ANY_MODIFICATION);
/*
* WaFbcHighMemBwCorruptionAvoidance:skl
* Display WA #0883: skl
*/
- intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
- DPFC_DISABLE_DUMMY0);
+ intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
+ intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A)) |
+ DPFC_DISABLE_DUMMY0);
}
static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
intel_uncore_read(&dev_priv->uncore, GEN7_FF_THREAD_MODE) &
~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
- intel_uncore_write(&dev_priv->uncore, GEN6_RC_SLEEP_PSMI_CONTROL,
+ intel_uncore_write(&dev_priv->uncore, RING_PSMI_CTL(RENDER_RING_BASE),
_MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
/* WaDisableSDEUnitClockGating:bdw */
~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
/* WaDisableSemaphoreAndSyncFlipWait:chv */
- intel_uncore_write(&dev_priv->uncore, GEN6_RC_SLEEP_PSMI_CONTROL,
+ intel_uncore_write(&dev_priv->uncore, RING_PSMI_CTL(RENDER_RING_BASE),
_MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
/* WaDisableCSUnitClockGating:chv */
intel_uncore_write(&dev_priv->uncore, D_STATE, dstate);
if (IS_PINEVIEW(dev_priv))
- intel_uncore_write(&dev_priv->uncore, ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
+ intel_uncore_write(&dev_priv->uncore, ECOSKPD(RENDER_RING_BASE),
+ _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
/* IIR "flip pending" means done if this bit is set */
- intel_uncore_write(&dev_priv->uncore, ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
+ intel_uncore_write(&dev_priv->uncore, ECOSKPD(RENDER_RING_BASE),
+ _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
/* interrupts should cause a wake up from C3 */
intel_uncore_write(&dev_priv->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
#include <linux/pm_runtime.h>
-#include "gt/intel_lrc_reg.h" /* for shadow reg list */
+#include "gt/intel_engine_regs.h"
#include "i915_drv.h"
#include "i915_iosf_mbi.h"
}
}
-static const struct reg_whitelist {
- i915_reg_t offset_ldw;
- i915_reg_t offset_udw;
- u8 min_graphics_ver;
- u8 max_graphics_ver;
- u8 size;
-} reg_read_whitelist[] = { {
- .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
- .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
- .min_graphics_ver = 4,
- .max_graphics_ver = 12,
- .size = 8
-} };
-
-int i915_reg_read_ioctl(struct drm_device *dev,
- void *data, struct drm_file *file)
-{
- struct drm_i915_private *i915 = to_i915(dev);
- struct intel_uncore *uncore = &i915->uncore;
- struct drm_i915_reg_read *reg = data;
- struct reg_whitelist const *entry;
- intel_wakeref_t wakeref;
- unsigned int flags;
- int remain;
- int ret = 0;
-
- entry = reg_read_whitelist;
- remain = ARRAY_SIZE(reg_read_whitelist);
- while (remain) {
- u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);
-
- GEM_BUG_ON(!is_power_of_2(entry->size));
- GEM_BUG_ON(entry->size > 8);
- GEM_BUG_ON(entry_offset & (entry->size - 1));
-
- if (IS_GRAPHICS_VER(i915, entry->min_graphics_ver, entry->max_graphics_ver) &&
- entry_offset == (reg->offset & -entry->size))
- break;
- entry++;
- remain--;
- }
-
- if (!remain)
- return -EINVAL;
-
- flags = reg->offset & (entry->size - 1);
-
- with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
- if (entry->size == 8 && flags == I915_REG_READ_8B_WA)
- reg->val = intel_uncore_read64_2x32(uncore,
- entry->offset_ldw,
- entry->offset_udw);
- else if (entry->size == 8 && flags == 0)
- reg->val = intel_uncore_read64(uncore,
- entry->offset_ldw);
- else if (entry->size == 4 && flags == 0)
- reg->val = intel_uncore_read(uncore, entry->offset_ldw);
- else if (entry->size == 2 && flags == 0)
- reg->val = intel_uncore_read16(uncore,
- entry->offset_ldw);
- else if (entry->size == 1 && flags == 0)
- reg->val = intel_uncore_read8(uncore,
- entry->offset_ldw);
- else
- ret = -EINVAL;
- }
-
- return ret;
-}
-
/**
* __intel_wait_for_register_fw - wait until register matches expected state
* @uncore: the struct intel_uncore
#include <linux/bitops.h>
#include <linux/types.h>
+#include "vlv_sideband_reg.h"
+
enum pipe;
struct drm_i915_private;
--- /dev/null
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef _VLV_SIDEBAND_REG_H_
+#define _VLV_SIDEBAND_REG_H_
+
+/* See configdb bunit SB addr map */
+#define BUNIT_REG_BISOC 0x11
+
+/* PUNIT_REG_*SSPM0 */
+#define _SSPM0_SSC(val) ((val) << 0)
+#define SSPM0_SSC_MASK _SSPM0_SSC(0x3)
+#define SSPM0_SSC_PWR_ON _SSPM0_SSC(0x0)
+#define SSPM0_SSC_CLK_GATE _SSPM0_SSC(0x1)
+#define SSPM0_SSC_RESET _SSPM0_SSC(0x2)
+#define SSPM0_SSC_PWR_GATE _SSPM0_SSC(0x3)
+#define _SSPM0_SSS(val) ((val) << 24)
+#define SSPM0_SSS_MASK _SSPM0_SSS(0x3)
+#define SSPM0_SSS_PWR_ON _SSPM0_SSS(0x0)
+#define SSPM0_SSS_CLK_GATE _SSPM0_SSS(0x1)
+#define SSPM0_SSS_RESET _SSPM0_SSS(0x2)
+#define SSPM0_SSS_PWR_GATE _SSPM0_SSS(0x3)
+
+/* PUNIT_REG_*SSPM1 */
+#define SSPM1_FREQSTAT_SHIFT 24
+#define SSPM1_FREQSTAT_MASK (0x1f << SSPM1_FREQSTAT_SHIFT)
+#define SSPM1_FREQGUAR_SHIFT 8
+#define SSPM1_FREQGUAR_MASK (0x1f << SSPM1_FREQGUAR_SHIFT)
+#define SSPM1_FREQ_SHIFT 0
+#define SSPM1_FREQ_MASK (0x1f << SSPM1_FREQ_SHIFT)
+
+#define PUNIT_REG_VEDSSPM0 0x32
+#define PUNIT_REG_VEDSSPM1 0x33
+
+#define PUNIT_REG_DSPSSPM 0x36
+#define DSPFREQSTAT_SHIFT_CHV 24
+#define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
+#define DSPFREQGUAR_SHIFT_CHV 8
+#define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
+#define DSPFREQSTAT_SHIFT 30
+#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
+#define DSPFREQGUAR_SHIFT 14
+#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
+#define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */
+#define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */
+#define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */
+#define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
+#define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
+#define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
+#define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
+#define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
+#define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
+#define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
+#define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
+#define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
+#define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
+#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
+#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
+
+#define PUNIT_REG_ISPSSPM0 0x39
+#define PUNIT_REG_ISPSSPM1 0x3a
+
+#define PUNIT_REG_PWRGT_CTRL 0x60
+#define PUNIT_REG_PWRGT_STATUS 0x61
+#define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2))
+#define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2))
+#define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2))
+#define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2))
+#define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2))
+
+#define PUNIT_PWGT_IDX_RENDER 0
+#define PUNIT_PWGT_IDX_MEDIA 1
+#define PUNIT_PWGT_IDX_DISP2D 3
+#define PUNIT_PWGT_IDX_DPIO_CMN_BC 5
+#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6
+#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7
+#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8
+#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9
+#define PUNIT_PWGT_IDX_DPIO_RX0 10
+#define PUNIT_PWGT_IDX_DPIO_RX1 11
+#define PUNIT_PWGT_IDX_DPIO_CMN_D 12
+
+#define PUNIT_REG_GPU_LFM 0xd3
+#define PUNIT_REG_GPU_FREQ_REQ 0xd4
+#define PUNIT_REG_GPU_FREQ_STS 0xd8
+#define GPLLENABLE (1 << 4)
+#define GENFREQSTATUS (1 << 0)
+#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
+#define PUNIT_REG_CZ_TIMESTAMP 0xce
+
+#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
+#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
+
+#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
+#define FB_GFX_FREQ_FUSE_MASK 0xff
+#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
+#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
+#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
+
+#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
+#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
+
+#define PUNIT_REG_DDR_SETUP2 0x139
+#define FORCE_DDR_FREQ_REQ_ACK (1 << 8)
+#define FORCE_DDR_LOW_FREQ (1 << 1)
+#define FORCE_DDR_HIGH_FREQ (1 << 0)
+
+#define PUNIT_GPU_STATUS_REG 0xdb
+#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
+#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
+#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
+#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
+
+#define PUNIT_GPU_DUTYCYCLE_REG 0xdf
+#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
+#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
+
+#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
+#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
+#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
+#define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
+#define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
+#define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
+#define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
+#define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
+#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
+#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
+
+#define VLV_TURBO_SOC_OVERRIDE 0x04
+#define VLV_OVERRIDE_EN 1
+#define VLV_SOC_TDP_EN (1 << 1)
+#define VLV_BIAS_CPU_125_SOC_875 (6 << 2)
+#define CHV_BIAS_CPU_50_SOC_50 (3 << 2)
+
+/* vlv2 north clock has */
+#define CCK_FUSE_REG 0x8
+#define CCK_FUSE_HPLL_FREQ_MASK 0x3
+#define CCK_REG_DSI_PLL_FUSE 0x44
+#define CCK_REG_DSI_PLL_CONTROL 0x48
+#define DSI_PLL_VCO_EN (1 << 31)
+#define DSI_PLL_LDO_GATE (1 << 30)
+#define DSI_PLL_P1_POST_DIV_SHIFT 17
+#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
+#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
+#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
+#define DSI_PLL_MUX_MASK (3 << 9)
+#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
+#define DSI_PLL_MUX_DSI0_CCK (1 << 10)
+#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
+#define DSI_PLL_MUX_DSI1_CCK (1 << 9)
+#define DSI_PLL_CLK_GATE_MASK (0xf << 5)
+#define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
+#define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
+#define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
+#define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
+#define DSI_PLL_LOCK (1 << 0)
+#define CCK_REG_DSI_PLL_DIVIDER 0x4c
+#define DSI_PLL_LFSR (1 << 31)
+#define DSI_PLL_FRACTION_EN (1 << 30)
+#define DSI_PLL_FRAC_COUNTER_SHIFT 27
+#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
+#define DSI_PLL_USYNC_CNT_SHIFT 18
+#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
+#define DSI_PLL_N1_DIV_SHIFT 16
+#define DSI_PLL_N1_DIV_MASK (3 << 16)
+#define DSI_PLL_M1_DIV_SHIFT 0
+#define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
+#define CCK_CZ_CLOCK_CONTROL 0x62
+#define CCK_GPLL_CLOCK_CONTROL 0x67
+#define CCK_DISPLAY_CLOCK_CONTROL 0x6b
+#define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c
+#define CCK_TRUNK_FORCE_ON (1 << 17)
+#define CCK_TRUNK_FORCE_OFF (1 << 16)
+#define CCK_FREQUENCY_STATUS (0x1f << 8)
+#define CCK_FREQUENCY_STATUS_SHIFT 8
+#define CCK_FREQUENCY_VALUES (0x1f << 0)
+
+#endif /* _VLV_SIDEBAND_REG_H_ */
*/
spinlock_t commit_lock;
-#ifdef CONFIG_DEBUG_FS
/**
* @debugfs_entry:
*
* Debugfs directory for this CRTC.
*/
struct dentry *debugfs_entry;
-#endif
/**
* @crc:
INTEL_VGA_DEVICE(0x46C2, info), \
INTEL_VGA_DEVICE(0x46C3, info)
+/* ADL-N */
+#define INTEL_ADLN_IDS(info) \
+ INTEL_VGA_DEVICE(0x46D0, info), \
+ INTEL_VGA_DEVICE(0x46D1, info), \
+ INTEL_VGA_DEVICE(0x46D2, info)
+
/* RPL-S */
#define INTEL_RPLS_IDS(info) \
INTEL_VGA_DEVICE(0xA780, info), \
projects / platform / kernel / linux-starfive.git / commitdiff