r600/sfn: Override Array access handling in backend assembler

Since we do thi sin the scheduler, there is no need to do this in the
backend again.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>

diff --git a/src/gallium/drivers/r600/sfn/sfn_nir.cpp b/src/gallium/drivers/r600/sfn/sfn_nir.cpp
index 73328f4aeb16c91f87d3fdfed8971389e6f5a949..4ba3fb5d8d9a581abbb36afadc75e220b160e839 100644 (file)
--- a/src/gallium/drivers/r600/sfn/sfn_nir.cpp
+++ b/src/gallium/drivers/r600/sfn/sfn_nir.cpp
@@ -31,6 +31,7 @@
 #include "nir.h"
 #include "nir_builder.h"
 #include "nir_intrinsics.h"
+#include "r600_asm.h"
 #include "sfn_assembler.h"
 #include "sfn_debug.h"
 #include "sfn_instr_tex.h"
@@ -1041,6 +1042,11 @@ r600_shader_from_nir(struct r600_context *rctx,
                       rscreen->b.family,
                       rscreen->has_compressed_msaa_texturing);
 
+   /* We already schedule the code with this in mind, no need to handle this
+    * in the backend assembler */
+   pipeshader->shader.bc.ar_handling = AR_HANDLE_NORMAL;
+   pipeshader->shader.bc.r6xx_nop_after_rel_dst = 0;
+
 
    r600::sfn_log << r600::SfnLog::shader_info << "pipeshader->shader.processor_type = "
                  << pipeshader->shader.processor_type << "\n";

diff --git a/src/gallium/drivers/r600/sfn/tests/sfn_optimizer_test.cpp b/src/gallium/drivers/r600/sfn/tests/sfn_optimizer_test.cpp
index 6ad5dd9491f06c8ed5d5c96f37cdd9e7d1e1f2e7..dfa6f7bf6f36e832c6938717df4b45e8472ffaca 100644 (file)
--- a/src/gallium/drivers/r600/sfn/tests/sfn_optimizer_test.cpp
+++ b/src/gallium/drivers/r600/sfn/tests/sfn_optimizer_test.cpp
@@ -750,6 +750,75 @@ BLOCK_END)";
 
 }
 
+TEST_F(TestShaderFromNir, ScheduleSplitLoadAddrAndNOPAfterIndirectDestRV770_2)
+{
+   const char *input =
+R"(FS
+CHIPCLASS R700
+FAMILY RV770
+PROP MAX_COLOR_EXPORTS:1
+PROP COLOR_EXPORTS:1
+PROP COLOR_EXPORT_MASK:15
+PROP WRITE_ALL_COLORS:0
+OUTPUT LOC:0 NAME:1 MASK:15
+ARRAYS A1[2].x
+SHADER
+BLOCK_START
+  ALU MOV S1.x : KC0[0].x {W}
+  ALU MOV S1.y : KC0[0].y {W}
+  ALU ADD S1.z : KC0[0].z KC0[2].z {W}
+  ALU ADD S1.w : KC0[0].w KC0[2].w {W}
+  ALU MOV A1[S1.x].x : KC0[1].y {WL}
+  ALU ADD S2.x : A1[1].x S1.y {W}
+  ALU ADD S2.y : KC0[1].y S1.z {W}
+  ALU ADD S2.z : KC0[1].z S1.w {W}
+  ALU ADD S2.w : KC0[1].w S1.w {WL}
+  EXPORT_DONE PIXEL 0 S2.xyzw
+BLOCK_END)";
+
+
+   const char *expect =
+R"(FS
+CHIPCLASS R700
+FAMILY RV770
+PROP MAX_COLOR_EXPORTS:1
+PROP COLOR_EXPORTS:1
+PROP COLOR_EXPORT_MASK:15
+PROP WRITE_ALL_COLORS:0
+OUTPUT LOC:0 NAME:1 MASK:15
+ARRAYS A1[2].x
+SHADER
+BLOCK_START
+ALU_GROUP_BEGIN
+   ALU MOVA_INT AR : KC0[0].x {L}
+ALU_GROUP_END
+ALU_GROUP_BEGIN
+    ALU MOV A1[AR].x : KC0[1].y {WL}
+ALU_GROUP_END
+ALU_GROUP_BEGIN
+   ALU ADD S1.z : KC0[0].z KC0[2].z {W}
+   ALU ADD S1.w : KC0[0].w KC0[2].w {WL}
+ALU_GROUP_END
+ALU_GROUP_BEGIN
+   ALU ADD S2.x@chgr : A1[1].x KC0[0].y {W}
+   ALU ADD S2.y@chgr : KC0[1].y S1.z{s} {WL}
+ALU_GROUP_END
+ALU_GROUP_BEGIN
+   ALU ADD S2.z@chgr : KC0[1].z S1.w{s} {W}
+   ALU ADD S2.w@chgr : KC0[1].w S1.w{s} {WL}
+ALU_GROUP_END
+BLOCK_END
+BLOCK_START
+  EXPORT_DONE PIXEL 0 S2.xyzw
+BLOCK_END)";
+
+   auto sh = from_string(input);
+   split_address_loads(*sh);
+   optimize(*sh);
+   check(schedule(sh), expect);
+
+}
+