pci: renesas: Fix BAR mapping on Gen3

Because the first PCIExAR(n) register is configured with the mapping,
It is the second PCIExAR(n) register that must be written with 0, not
the last one. Update the n from 4 to 1 to select the correct register.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c
index 6b08409..34a561e 100644 (file)
--- a/drivers/pci/pci-rcar-gen3.c
+++ b/drivers/pci/pci-rcar-gen3.c
@@ -358,9 +358,9 @@ static int rcar_gen3_pcie_probe(struct udevice *dev)
                break;
        }
 
-       writel(0, priv->regs + PCIEPRAR(4));
-       writel(0, priv->regs + PCIELAR(4));
-       writel(0, priv->regs + PCIELAMR(4));
+       writel(0, priv->regs + PCIEPRAR(1));
+       writel(0, priv->regs + PCIELAR(1));
+       writel(0, priv->regs + PCIELAMR(1));
 
        ret = rcar_gen3_pcie_hw_init(dev);
        if (ret)