(wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs1),
(vti.Mask true_mask), (XLenVT srcvalue)))),
- (!cast<Instruction>(instruction_name#"_WV_"#vti.LMul.MX)
- wti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>;
+ (!cast<Instruction>(instruction_name#"_WV_"#vti.LMul.MX#"_TIED")
+ wti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW,
+ TAIL_AGNOSTIC)>;
def : Pat<(op (wti.Vector wti.RegClass:$rs2),
(wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
(fwti.Vector (extop (fvti.Vector fvti.RegClass:$rs1),
(fvti.Mask true_mask), VLOpFrag)),
srcvalue, (fwti.Mask true_mask), VLOpFrag)),
- (!cast<Instruction>(instruction_name#"_WV_"#fvti.LMul.MX)
+ (!cast<Instruction>(instruction_name#"_WV_"#fvti.LMul.MX#"_TIED")
fwti.RegClass:$rs2, fvti.RegClass:$rs1,
- GPR:$vl, fvti.Log2SEW)>;
+ GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fwti.Vector (op (fwti.Vector fwti.RegClass:$rs2),
(fwti.Vector (extop (fvti.Vector (SplatFPOp fvti.ScalarRegClass:$rs1)),
(fvti.Mask true_mask), VLOpFrag)),
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vle32.v v16, (a0)
+; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, mu
-; CHECK-NEXT: vslidedown.vi v24, v16, 16
+; CHECK-NEXT: vslidedown.vi v0, v24, 16
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vfmv.v.f v8, fa0
-; CHECK-NEXT: vfwcvt.f.f.v v0, v8
-; CHECK-NEXT: vfwadd.wv v8, v0, v16
-; CHECK-NEXT: vfwadd.wv v16, v0, v24
+; CHECK-NEXT: vfwcvt.f.f.v v16, v8
+; CHECK-NEXT: vfwadd.wv v8, v16, v24
+; CHECK-NEXT: vfwadd.wv v16, v16, v0
; CHECK-NEXT: ret
%a = load <32 x float>, <32 x float>* %x
%b = insertelement <32 x float> poison, float %y, i32 0
; CHECK-LABEL: vfwadd_wv_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle32.v v9, (a0)
-; CHECK-NEXT: vle16.v v10, (a1)
-; CHECK-NEXT: vfwadd.wv v8, v9, v10
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vfwadd.wv v8, v8, v9
; CHECK-NEXT: ret
%a = load <2 x float>, <2 x float>* %x
%b = load <2 x half>, <2 x half>* %y
; CHECK-LABEL: vfwadd_wv_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle32.v v9, (a0)
-; CHECK-NEXT: vle16.v v10, (a1)
-; CHECK-NEXT: vfwadd.wv v8, v9, v10
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vfwadd.wv v8, v8, v9
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = load <4 x half>, <4 x half>* %y
; CHECK-LABEL: vfwadd_wv_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle32.v v10, (a0)
-; CHECK-NEXT: vle16.v v12, (a1)
-; CHECK-NEXT: vfwadd.wv v8, v10, v12
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle16.v v10, (a1)
+; CHECK-NEXT: vfwadd.wv v8, v8, v10
; CHECK-NEXT: ret
%a = load <8 x float>, <8 x float>* %x
%b = load <8 x half>, <8 x half>* %y
; CHECK-LABEL: vfwadd_wv_v16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle32.v v12, (a0)
-; CHECK-NEXT: vle16.v v16, (a1)
-; CHECK-NEXT: vfwadd.wv v8, v12, v16
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle16.v v12, (a1)
+; CHECK-NEXT: vfwadd.wv v8, v8, v12
; CHECK-NEXT: ret
%a = load <16 x float>, <16 x float>* %x
%b = load <16 x half>, <16 x half>* %y
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
-; CHECK-NEXT: vle32.v v16, (a0)
-; CHECK-NEXT: vle16.v v24, (a1)
-; CHECK-NEXT: vfwadd.wv v8, v16, v24
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle16.v v16, (a1)
+; CHECK-NEXT: vfwadd.wv v8, v8, v16
; CHECK-NEXT: ret
%a = load <32 x float>, <32 x float>* %x
%b = load <32 x half>, <32 x half>* %y
; CHECK-LABEL: vfwadd_wv_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle64.v v9, (a0)
-; CHECK-NEXT: vle32.v v10, (a1)
-; CHECK-NEXT: vfwadd.wv v8, v9, v10
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vfwadd.wv v8, v8, v9
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = load <2 x float>, <2 x float>* %y
; CHECK-LABEL: vfwadd_wv_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle64.v v10, (a0)
-; CHECK-NEXT: vle32.v v12, (a1)
-; CHECK-NEXT: vfwadd.wv v8, v10, v12
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle32.v v10, (a1)
+; CHECK-NEXT: vfwadd.wv v8, v8, v10
; CHECK-NEXT: ret
%a = load <4 x double>, <4 x double>* %x
%b = load <4 x float>, <4 x float>* %y
; CHECK-LABEL: vfwadd_wv_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle64.v v12, (a0)
-; CHECK-NEXT: vle32.v v16, (a1)
-; CHECK-NEXT: vfwadd.wv v8, v12, v16
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle32.v v12, (a1)
+; CHECK-NEXT: vfwadd.wv v8, v8, v12
; CHECK-NEXT: ret
%a = load <8 x double>, <8 x double>* %x
%b = load <8 x float>, <8 x float>* %y
; CHECK-LABEL: vfwadd_wv_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vle64.v v16, (a0)
-; CHECK-NEXT: vle32.v v24, (a1)
-; CHECK-NEXT: vfwadd.wv v8, v16, v24
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle32.v v16, (a1)
+; CHECK-NEXT: vfwadd.wv v8, v8, v16
; CHECK-NEXT: ret
%a = load <16 x double>, <16 x double>* %x
%b = load <16 x float>, <16 x float>* %y
; CHECK-LABEL: vfwsub_wv_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle32.v v9, (a0)
-; CHECK-NEXT: vle16.v v10, (a1)
-; CHECK-NEXT: vfwsub.wv v8, v9, v10
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vfwsub.wv v8, v8, v9
; CHECK-NEXT: ret
%a = load <2 x float>, <2 x float>* %x
%b = load <2 x half>, <2 x half>* %y
; CHECK-LABEL: vfwsub_wv_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle32.v v9, (a0)
-; CHECK-NEXT: vle16.v v10, (a1)
-; CHECK-NEXT: vfwsub.wv v8, v9, v10
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vfwsub.wv v8, v8, v9
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = load <4 x half>, <4 x half>* %y
; CHECK-LABEL: vfwsub_wv_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle32.v v10, (a0)
-; CHECK-NEXT: vle16.v v12, (a1)
-; CHECK-NEXT: vfwsub.wv v8, v10, v12
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle16.v v10, (a1)
+; CHECK-NEXT: vfwsub.wv v8, v8, v10
; CHECK-NEXT: ret
%a = load <8 x float>, <8 x float>* %x
%b = load <8 x half>, <8 x half>* %y
; CHECK-LABEL: vfwsub_wv_v16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle32.v v12, (a0)
-; CHECK-NEXT: vle16.v v16, (a1)
-; CHECK-NEXT: vfwsub.wv v8, v12, v16
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle16.v v12, (a1)
+; CHECK-NEXT: vfwsub.wv v8, v8, v12
; CHECK-NEXT: ret
%a = load <16 x float>, <16 x float>* %x
%b = load <16 x half>, <16 x half>* %y
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
-; CHECK-NEXT: vle32.v v16, (a0)
-; CHECK-NEXT: vle16.v v24, (a1)
-; CHECK-NEXT: vfwsub.wv v8, v16, v24
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle16.v v16, (a1)
+; CHECK-NEXT: vfwsub.wv v8, v8, v16
; CHECK-NEXT: ret
%a = load <32 x float>, <32 x float>* %x
%b = load <32 x half>, <32 x half>* %y
; CHECK-LABEL: vfwsub_wv_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle64.v v9, (a0)
-; CHECK-NEXT: vle32.v v10, (a1)
-; CHECK-NEXT: vfwsub.wv v8, v9, v10
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vfwsub.wv v8, v8, v9
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = load <2 x float>, <2 x float>* %y
; CHECK-LABEL: vfwsub_wv_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle64.v v10, (a0)
-; CHECK-NEXT: vle32.v v12, (a1)
-; CHECK-NEXT: vfwsub.wv v8, v10, v12
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle32.v v10, (a1)
+; CHECK-NEXT: vfwsub.wv v8, v8, v10
; CHECK-NEXT: ret
%a = load <4 x double>, <4 x double>* %x
%b = load <4 x float>, <4 x float>* %y
; CHECK-LABEL: vfwsub_wv_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle64.v v12, (a0)
-; CHECK-NEXT: vle32.v v16, (a1)
-; CHECK-NEXT: vfwsub.wv v8, v12, v16
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle32.v v12, (a1)
+; CHECK-NEXT: vfwsub.wv v8, v8, v12
; CHECK-NEXT: ret
%a = load <8 x double>, <8 x double>* %x
%b = load <8 x float>, <8 x float>* %y
; CHECK-LABEL: vfwsub_wv_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vle64.v v16, (a0)
-; CHECK-NEXT: vle32.v v24, (a1)
-; CHECK-NEXT: vfwsub.wv v8, v16, v24
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle32.v v16, (a1)
+; CHECK-NEXT: vfwsub.wv v8, v8, v16
; CHECK-NEXT: ret
%a = load <16 x double>, <16 x double>* %x
%b = load <16 x float>, <16 x float>* %y
; CHECK-LABEL: vfwadd_wv_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfwadd.wv v10, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: vfwadd.wv v8, v8, v9
; CHECK-NEXT: ret
%vc = fpext <vscale x 1 x float> %vb to <vscale x 1 x double>
%vd = fadd <vscale x 1 x double> %va, %vc
; CHECK-LABEL: vfwadd_wv_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfwadd.wv v12, v8, v10
-; CHECK-NEXT: vmv2r.v v8, v12
+; CHECK-NEXT: vfwadd.wv v8, v8, v10
; CHECK-NEXT: ret
%vc = fpext <vscale x 2 x float> %vb to <vscale x 2 x double>
%vd = fadd <vscale x 2 x double> %va, %vc
; CHECK-LABEL: vfwadd_wv_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfwadd.wv v16, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v16
+; CHECK-NEXT: vfwadd.wv v8, v8, v12
; CHECK-NEXT: ret
%vc = fpext <vscale x 4 x float> %vb to <vscale x 4 x double>
%vd = fadd <vscale x 4 x double> %va, %vc
; CHECK-LABEL: vfwadd_wv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfwadd.wv v24, v8, v16
-; CHECK-NEXT: vmv8r.v v8, v24
+; CHECK-NEXT: vfwadd.wv v8, v8, v16
; CHECK-NEXT: ret
%vc = fpext <vscale x 8 x float> %vb to <vscale x 8 x double>
%vd = fadd <vscale x 8 x double> %va, %vc
; CHECK-LABEL: vfwsub_wv_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfwsub.wv v10, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: vfwsub.wv v8, v8, v9
; CHECK-NEXT: ret
%vc = fpext <vscale x 1 x float> %vb to <vscale x 1 x double>
%vd = fsub <vscale x 1 x double> %va, %vc
; CHECK-LABEL: vfwsub_wv_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfwsub.wv v12, v8, v10
-; CHECK-NEXT: vmv2r.v v8, v12
+; CHECK-NEXT: vfwsub.wv v8, v8, v10
; CHECK-NEXT: ret
%vc = fpext <vscale x 2 x float> %vb to <vscale x 2 x double>
%vd = fsub <vscale x 2 x double> %va, %vc
; CHECK-LABEL: vfwsub_wv_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfwsub.wv v16, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v16
+; CHECK-NEXT: vfwsub.wv v8, v8, v12
; CHECK-NEXT: ret
%vc = fpext <vscale x 4 x float> %vb to <vscale x 4 x double>
%vd = fsub <vscale x 4 x double> %va, %vc
; CHECK-LABEL: vfwsub_wv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfwsub.wv v24, v8, v16
-; CHECK-NEXT: vmv8r.v v8, v24
+; CHECK-NEXT: vfwsub.wv v8, v8, v16
; CHECK-NEXT: ret
%vc = fpext <vscale x 8 x float> %vb to <vscale x 8 x double>
%vd = fsub <vscale x 8 x double> %va, %vc