Avoid ICE of move pattern from memory to memory.
gcc/ChangeLog:
PR target/103895
* config/i386/sse.md (*bit_and_float_vector_all_ones):
Force_reg operand 1 to avoid ICE.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr103895.c: New test.
"TARGET_SSE && ix86_pre_reload_split ()"
"#"
"&& 1"
- [(set (match_dup 0) (match_dup 1))])
+ [(set (match_dup 0) (match_dup 1))]
+ "operands[1] = force_reg (<MODE>mode, operands[1]);")
(define_expand "copysign<mode>3"
[(set (match_dup 4)
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-Og -ffloat-store" } */
+
+#include <emmintrin.h>
+typedef float vFloat __attribute__((__vector_size__(16)));
+float bar_dr;
+vFloat bar_f1;
+void bar() {
+ static vFloat m0;
+ vFloat fa1 = _mm_andnot_ps(m0, bar_f1);
+ __attribute__((__vector_size__(2 * sizeof(double)))) double v3 =
+ _mm_cvtps_pd(fa1);
+ vFloat r1 = _mm_cvtpd_ps(v3);
+ _mm_storeu_ps(&bar_dr, r1);
+}
+