clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKS

The way hw_onecell_data is declared:
struct clk_hw_onecell_data {
	unsigned int num;
	struct clk_hw *hws[];
};

makes it impossible to have the clk_hw table declared outside while
using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible
array member.

Completely move out of hw_onecell_data and add a custom
devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw
in order to finally get rid on the NR_CLKS define.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-6-38172d17c27a@linaro.org
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index ea88309..135da8f 100644 (file)
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -100,6 +100,7 @@ config COMMON_CLK_AXG_AUDIO
        select COMMON_CLK_MESON_REGMAP
        select COMMON_CLK_MESON_PHASE
        select COMMON_CLK_MESON_SCLK_DIV
+       select COMMON_CLK_MESON_CLKC_UTILS
        select REGMAP_MMIO
        help
          Support for the audio clock controller on AmLogic A113D devices,

diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
index 5016682..6917e35 100644 (file)
--- a/drivers/clk/meson/axg-audio.c
+++ b/drivers/clk/meson/axg-audio.c
@@ -15,6 +15,7 @@
 #include <linux/reset-controller.h>
 #include <linux/slab.h>
 
+#include "meson-clkc-utils.h"
 #include "axg-audio.h"
 #include "clk-regmap.h"
 #include "clk-phase.h"
@@ -811,436 +812,424 @@ static struct clk_regmap sm1_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL(
  * Array of all clocks provided by this provider
  * The input clocks of the controller will be populated at runtime
  */
-static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {
-       .hws = {
-               [AUD_CLKID_DDR_ARB]             = &ddr_arb.hw,
-               [AUD_CLKID_PDM]                 = &pdm.hw,
-               [AUD_CLKID_TDMIN_A]             = &tdmin_a.hw,
-               [AUD_CLKID_TDMIN_B]             = &tdmin_b.hw,
-               [AUD_CLKID_TDMIN_C]             = &tdmin_c.hw,
-               [AUD_CLKID_TDMIN_LB]            = &tdmin_lb.hw,
-               [AUD_CLKID_TDMOUT_A]            = &tdmout_a.hw,
-               [AUD_CLKID_TDMOUT_B]            = &tdmout_b.hw,
-               [AUD_CLKID_TDMOUT_C]            = &tdmout_c.hw,
-               [AUD_CLKID_FRDDR_A]             = &frddr_a.hw,
-               [AUD_CLKID_FRDDR_B]             = &frddr_b.hw,
-               [AUD_CLKID_FRDDR_C]             = &frddr_c.hw,
-               [AUD_CLKID_TODDR_A]             = &toddr_a.hw,
-               [AUD_CLKID_TODDR_B]             = &toddr_b.hw,
-               [AUD_CLKID_TODDR_C]             = &toddr_c.hw,
-               [AUD_CLKID_LOOPBACK]            = &loopback.hw,
-               [AUD_CLKID_SPDIFIN]             = &spdifin.hw,
-               [AUD_CLKID_SPDIFOUT]            = &spdifout.hw,
-               [AUD_CLKID_RESAMPLE]            = &resample.hw,
-               [AUD_CLKID_POWER_DETECT]        = &power_detect.hw,
-               [AUD_CLKID_MST_A_MCLK_SEL]      = &mst_a_mclk_sel.hw,
-               [AUD_CLKID_MST_B_MCLK_SEL]      = &mst_b_mclk_sel.hw,
-               [AUD_CLKID_MST_C_MCLK_SEL]      = &mst_c_mclk_sel.hw,
-               [AUD_CLKID_MST_D_MCLK_SEL]      = &mst_d_mclk_sel.hw,
-               [AUD_CLKID_MST_E_MCLK_SEL]      = &mst_e_mclk_sel.hw,
-               [AUD_CLKID_MST_F_MCLK_SEL]      = &mst_f_mclk_sel.hw,
-               [AUD_CLKID_MST_A_MCLK_DIV]      = &mst_a_mclk_div.hw,
-               [AUD_CLKID_MST_B_MCLK_DIV]      = &mst_b_mclk_div.hw,
-               [AUD_CLKID_MST_C_MCLK_DIV]      = &mst_c_mclk_div.hw,
-               [AUD_CLKID_MST_D_MCLK_DIV]      = &mst_d_mclk_div.hw,
-               [AUD_CLKID_MST_E_MCLK_DIV]      = &mst_e_mclk_div.hw,
-               [AUD_CLKID_MST_F_MCLK_DIV]      = &mst_f_mclk_div.hw,
-               [AUD_CLKID_MST_A_MCLK]          = &mst_a_mclk.hw,
-               [AUD_CLKID_MST_B_MCLK]          = &mst_b_mclk.hw,
-               [AUD_CLKID_MST_C_MCLK]          = &mst_c_mclk.hw,
-               [AUD_CLKID_MST_D_MCLK]          = &mst_d_mclk.hw,
-               [AUD_CLKID_MST_E_MCLK]          = &mst_e_mclk.hw,
-               [AUD_CLKID_MST_F_MCLK]          = &mst_f_mclk.hw,
-               [AUD_CLKID_SPDIFOUT_CLK_SEL]    = &spdifout_clk_sel.hw,
-               [AUD_CLKID_SPDIFOUT_CLK_DIV]    = &spdifout_clk_div.hw,
-               [AUD_CLKID_SPDIFOUT_CLK]        = &spdifout_clk.hw,
-               [AUD_CLKID_SPDIFIN_CLK_SEL]     = &spdifin_clk_sel.hw,
-               [AUD_CLKID_SPDIFIN_CLK_DIV]     = &spdifin_clk_div.hw,
-               [AUD_CLKID_SPDIFIN_CLK]         = &spdifin_clk.hw,
-               [AUD_CLKID_PDM_DCLK_SEL]        = &pdm_dclk_sel.hw,
-               [AUD_CLKID_PDM_DCLK_DIV]        = &pdm_dclk_div.hw,
-               [AUD_CLKID_PDM_DCLK]            = &pdm_dclk.hw,
-               [AUD_CLKID_PDM_SYSCLK_SEL]      = &pdm_sysclk_sel.hw,
-               [AUD_CLKID_PDM_SYSCLK_DIV]      = &pdm_sysclk_div.hw,
-               [AUD_CLKID_PDM_SYSCLK]          = &pdm_sysclk.hw,
-               [AUD_CLKID_MST_A_SCLK_PRE_EN]   = &mst_a_sclk_pre_en.hw,
-               [AUD_CLKID_MST_B_SCLK_PRE_EN]   = &mst_b_sclk_pre_en.hw,
-               [AUD_CLKID_MST_C_SCLK_PRE_EN]   = &mst_c_sclk_pre_en.hw,
-               [AUD_CLKID_MST_D_SCLK_PRE_EN]   = &mst_d_sclk_pre_en.hw,
-               [AUD_CLKID_MST_E_SCLK_PRE_EN]   = &mst_e_sclk_pre_en.hw,
-               [AUD_CLKID_MST_F_SCLK_PRE_EN]   = &mst_f_sclk_pre_en.hw,
-               [AUD_CLKID_MST_A_SCLK_DIV]      = &mst_a_sclk_div.hw,
-               [AUD_CLKID_MST_B_SCLK_DIV]      = &mst_b_sclk_div.hw,
-               [AUD_CLKID_MST_C_SCLK_DIV]      = &mst_c_sclk_div.hw,
-               [AUD_CLKID_MST_D_SCLK_DIV]      = &mst_d_sclk_div.hw,
-               [AUD_CLKID_MST_E_SCLK_DIV]      = &mst_e_sclk_div.hw,
-               [AUD_CLKID_MST_F_SCLK_DIV]      = &mst_f_sclk_div.hw,
-               [AUD_CLKID_MST_A_SCLK_POST_EN]  = &mst_a_sclk_post_en.hw,
-               [AUD_CLKID_MST_B_SCLK_POST_EN]  = &mst_b_sclk_post_en.hw,
-               [AUD_CLKID_MST_C_SCLK_POST_EN]  = &mst_c_sclk_post_en.hw,
-               [AUD_CLKID_MST_D_SCLK_POST_EN]  = &mst_d_sclk_post_en.hw,
-               [AUD_CLKID_MST_E_SCLK_POST_EN]  = &mst_e_sclk_post_en.hw,
-               [AUD_CLKID_MST_F_SCLK_POST_EN]  = &mst_f_sclk_post_en.hw,
-               [AUD_CLKID_MST_A_SCLK]          = &mst_a_sclk.hw,
-               [AUD_CLKID_MST_B_SCLK]          = &mst_b_sclk.hw,
-               [AUD_CLKID_MST_C_SCLK]          = &mst_c_sclk.hw,
-               [AUD_CLKID_MST_D_SCLK]          = &mst_d_sclk.hw,
-               [AUD_CLKID_MST_E_SCLK]          = &mst_e_sclk.hw,
-               [AUD_CLKID_MST_F_SCLK]          = &mst_f_sclk.hw,
-               [AUD_CLKID_MST_A_LRCLK_DIV]     = &mst_a_lrclk_div.hw,
-               [AUD_CLKID_MST_B_LRCLK_DIV]     = &mst_b_lrclk_div.hw,
-               [AUD_CLKID_MST_C_LRCLK_DIV]     = &mst_c_lrclk_div.hw,
-               [AUD_CLKID_MST_D_LRCLK_DIV]     = &mst_d_lrclk_div.hw,
-               [AUD_CLKID_MST_E_LRCLK_DIV]     = &mst_e_lrclk_div.hw,
-               [AUD_CLKID_MST_F_LRCLK_DIV]     = &mst_f_lrclk_div.hw,
-               [AUD_CLKID_MST_A_LRCLK]         = &mst_a_lrclk.hw,
-               [AUD_CLKID_MST_B_LRCLK]         = &mst_b_lrclk.hw,
-               [AUD_CLKID_MST_C_LRCLK]         = &mst_c_lrclk.hw,
-               [AUD_CLKID_MST_D_LRCLK]         = &mst_d_lrclk.hw,
-               [AUD_CLKID_MST_E_LRCLK]         = &mst_e_lrclk.hw,
-               [AUD_CLKID_MST_F_LRCLK]         = &mst_f_lrclk.hw,
-               [AUD_CLKID_TDMIN_A_SCLK_SEL]    = &tdmin_a_sclk_sel.hw,
-               [AUD_CLKID_TDMIN_B_SCLK_SEL]    = &tdmin_b_sclk_sel.hw,
-               [AUD_CLKID_TDMIN_C_SCLK_SEL]    = &tdmin_c_sclk_sel.hw,
-               [AUD_CLKID_TDMIN_LB_SCLK_SEL]   = &tdmin_lb_sclk_sel.hw,
-               [AUD_CLKID_TDMOUT_A_SCLK_SEL]   = &tdmout_a_sclk_sel.hw,
-               [AUD_CLKID_TDMOUT_B_SCLK_SEL]   = &tdmout_b_sclk_sel.hw,
-               [AUD_CLKID_TDMOUT_C_SCLK_SEL]   = &tdmout_c_sclk_sel.hw,
-               [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
-               [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
-               [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
-               [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
-               [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
-               [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
-               [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
-               [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
-               [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
-               [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
-               [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
-               [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
-               [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
-               [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
-               [AUD_CLKID_TDMIN_A_SCLK]        = &tdmin_a_sclk.hw,
-               [AUD_CLKID_TDMIN_B_SCLK]        = &tdmin_b_sclk.hw,
-               [AUD_CLKID_TDMIN_C_SCLK]        = &tdmin_c_sclk.hw,
-               [AUD_CLKID_TDMIN_LB_SCLK]       = &tdmin_lb_sclk.hw,
-               [AUD_CLKID_TDMOUT_A_SCLK]       = &axg_tdmout_a_sclk.hw,
-               [AUD_CLKID_TDMOUT_B_SCLK]       = &axg_tdmout_b_sclk.hw,
-               [AUD_CLKID_TDMOUT_C_SCLK]       = &axg_tdmout_c_sclk.hw,
-               [AUD_CLKID_TDMIN_A_LRCLK]       = &tdmin_a_lrclk.hw,
-               [AUD_CLKID_TDMIN_B_LRCLK]       = &tdmin_b_lrclk.hw,
-               [AUD_CLKID_TDMIN_C_LRCLK]       = &tdmin_c_lrclk.hw,
-               [AUD_CLKID_TDMIN_LB_LRCLK]      = &tdmin_lb_lrclk.hw,
-               [AUD_CLKID_TDMOUT_A_LRCLK]      = &tdmout_a_lrclk.hw,
-               [AUD_CLKID_TDMOUT_B_LRCLK]      = &tdmout_b_lrclk.hw,
-               [AUD_CLKID_TDMOUT_C_LRCLK]      = &tdmout_c_lrclk.hw,
-               [AUD_CLKID_TOP]                 = &axg_aud_top,
-               [NR_CLKS] = NULL,
-       },
-       .num = NR_CLKS,
+static struct clk_hw *axg_audio_hw_clks[] = {
+       [AUD_CLKID_DDR_ARB]             = &ddr_arb.hw,
+       [AUD_CLKID_PDM]                 = &pdm.hw,
+       [AUD_CLKID_TDMIN_A]             = &tdmin_a.hw,
+       [AUD_CLKID_TDMIN_B]             = &tdmin_b.hw,
+       [AUD_CLKID_TDMIN_C]             = &tdmin_c.hw,
+       [AUD_CLKID_TDMIN_LB]            = &tdmin_lb.hw,
+       [AUD_CLKID_TDMOUT_A]            = &tdmout_a.hw,
+       [AUD_CLKID_TDMOUT_B]            = &tdmout_b.hw,
+       [AUD_CLKID_TDMOUT_C]            = &tdmout_c.hw,
+       [AUD_CLKID_FRDDR_A]             = &frddr_a.hw,
+       [AUD_CLKID_FRDDR_B]             = &frddr_b.hw,
+       [AUD_CLKID_FRDDR_C]             = &frddr_c.hw,
+       [AUD_CLKID_TODDR_A]             = &toddr_a.hw,
+       [AUD_CLKID_TODDR_B]             = &toddr_b.hw,
+       [AUD_CLKID_TODDR_C]             = &toddr_c.hw,
+       [AUD_CLKID_LOOPBACK]            = &loopback.hw,
+       [AUD_CLKID_SPDIFIN]             = &spdifin.hw,
+       [AUD_CLKID_SPDIFOUT]            = &spdifout.hw,
+       [AUD_CLKID_RESAMPLE]            = &resample.hw,
+       [AUD_CLKID_POWER_DETECT]        = &power_detect.hw,
+       [AUD_CLKID_MST_A_MCLK_SEL]      = &mst_a_mclk_sel.hw,
+       [AUD_CLKID_MST_B_MCLK_SEL]      = &mst_b_mclk_sel.hw,
+       [AUD_CLKID_MST_C_MCLK_SEL]      = &mst_c_mclk_sel.hw,
+       [AUD_CLKID_MST_D_MCLK_SEL]      = &mst_d_mclk_sel.hw,
+       [AUD_CLKID_MST_E_MCLK_SEL]      = &mst_e_mclk_sel.hw,
+       [AUD_CLKID_MST_F_MCLK_SEL]      = &mst_f_mclk_sel.hw,
+       [AUD_CLKID_MST_A_MCLK_DIV]      = &mst_a_mclk_div.hw,
+       [AUD_CLKID_MST_B_MCLK_DIV]      = &mst_b_mclk_div.hw,
+       [AUD_CLKID_MST_C_MCLK_DIV]      = &mst_c_mclk_div.hw,
+       [AUD_CLKID_MST_D_MCLK_DIV]      = &mst_d_mclk_div.hw,
+       [AUD_CLKID_MST_E_MCLK_DIV]      = &mst_e_mclk_div.hw,
+       [AUD_CLKID_MST_F_MCLK_DIV]      = &mst_f_mclk_div.hw,
+       [AUD_CLKID_MST_A_MCLK]          = &mst_a_mclk.hw,
+       [AUD_CLKID_MST_B_MCLK]          = &mst_b_mclk.hw,
+       [AUD_CLKID_MST_C_MCLK]          = &mst_c_mclk.hw,
+       [AUD_CLKID_MST_D_MCLK]          = &mst_d_mclk.hw,
+       [AUD_CLKID_MST_E_MCLK]          = &mst_e_mclk.hw,
+       [AUD_CLKID_MST_F_MCLK]          = &mst_f_mclk.hw,
+       [AUD_CLKID_SPDIFOUT_CLK_SEL]    = &spdifout_clk_sel.hw,
+       [AUD_CLKID_SPDIFOUT_CLK_DIV]    = &spdifout_clk_div.hw,
+       [AUD_CLKID_SPDIFOUT_CLK]        = &spdifout_clk.hw,
+       [AUD_CLKID_SPDIFIN_CLK_SEL]     = &spdifin_clk_sel.hw,
+       [AUD_CLKID_SPDIFIN_CLK_DIV]     = &spdifin_clk_div.hw,
+       [AUD_CLKID_SPDIFIN_CLK]         = &spdifin_clk.hw,
+       [AUD_CLKID_PDM_DCLK_SEL]        = &pdm_dclk_sel.hw,
+       [AUD_CLKID_PDM_DCLK_DIV]        = &pdm_dclk_div.hw,
+       [AUD_CLKID_PDM_DCLK]            = &pdm_dclk.hw,
+       [AUD_CLKID_PDM_SYSCLK_SEL]      = &pdm_sysclk_sel.hw,
+       [AUD_CLKID_PDM_SYSCLK_DIV]      = &pdm_sysclk_div.hw,
+       [AUD_CLKID_PDM_SYSCLK]          = &pdm_sysclk.hw,
+       [AUD_CLKID_MST_A_SCLK_PRE_EN]   = &mst_a_sclk_pre_en.hw,
+       [AUD_CLKID_MST_B_SCLK_PRE_EN]   = &mst_b_sclk_pre_en.hw,
+       [AUD_CLKID_MST_C_SCLK_PRE_EN]   = &mst_c_sclk_pre_en.hw,
+       [AUD_CLKID_MST_D_SCLK_PRE_EN]   = &mst_d_sclk_pre_en.hw,
+       [AUD_CLKID_MST_E_SCLK_PRE_EN]   = &mst_e_sclk_pre_en.hw,
+       [AUD_CLKID_MST_F_SCLK_PRE_EN]   = &mst_f_sclk_pre_en.hw,
+       [AUD_CLKID_MST_A_SCLK_DIV]      = &mst_a_sclk_div.hw,
+       [AUD_CLKID_MST_B_SCLK_DIV]      = &mst_b_sclk_div.hw,
+       [AUD_CLKID_MST_C_SCLK_DIV]      = &mst_c_sclk_div.hw,
+       [AUD_CLKID_MST_D_SCLK_DIV]      = &mst_d_sclk_div.hw,
+       [AUD_CLKID_MST_E_SCLK_DIV]      = &mst_e_sclk_div.hw,
+       [AUD_CLKID_MST_F_SCLK_DIV]      = &mst_f_sclk_div.hw,
+       [AUD_CLKID_MST_A_SCLK_POST_EN]  = &mst_a_sclk_post_en.hw,
+       [AUD_CLKID_MST_B_SCLK_POST_EN]  = &mst_b_sclk_post_en.hw,
+       [AUD_CLKID_MST_C_SCLK_POST_EN]  = &mst_c_sclk_post_en.hw,
+       [AUD_CLKID_MST_D_SCLK_POST_EN]  = &mst_d_sclk_post_en.hw,
+       [AUD_CLKID_MST_E_SCLK_POST_EN]  = &mst_e_sclk_post_en.hw,
+       [AUD_CLKID_MST_F_SCLK_POST_EN]  = &mst_f_sclk_post_en.hw,
+       [AUD_CLKID_MST_A_SCLK]          = &mst_a_sclk.hw,
+       [AUD_CLKID_MST_B_SCLK]          = &mst_b_sclk.hw,
+       [AUD_CLKID_MST_C_SCLK]          = &mst_c_sclk.hw,
+       [AUD_CLKID_MST_D_SCLK]          = &mst_d_sclk.hw,
+       [AUD_CLKID_MST_E_SCLK]          = &mst_e_sclk.hw,
+       [AUD_CLKID_MST_F_SCLK]          = &mst_f_sclk.hw,
+       [AUD_CLKID_MST_A_LRCLK_DIV]     = &mst_a_lrclk_div.hw,
+       [AUD_CLKID_MST_B_LRCLK_DIV]     = &mst_b_lrclk_div.hw,
+       [AUD_CLKID_MST_C_LRCLK_DIV]     = &mst_c_lrclk_div.hw,
+       [AUD_CLKID_MST_D_LRCLK_DIV]     = &mst_d_lrclk_div.hw,
+       [AUD_CLKID_MST_E_LRCLK_DIV]     = &mst_e_lrclk_div.hw,
+       [AUD_CLKID_MST_F_LRCLK_DIV]     = &mst_f_lrclk_div.hw,
+       [AUD_CLKID_MST_A_LRCLK]         = &mst_a_lrclk.hw,
+       [AUD_CLKID_MST_B_LRCLK]         = &mst_b_lrclk.hw,
+       [AUD_CLKID_MST_C_LRCLK]         = &mst_c_lrclk.hw,
+       [AUD_CLKID_MST_D_LRCLK]         = &mst_d_lrclk.hw,
+       [AUD_CLKID_MST_E_LRCLK]         = &mst_e_lrclk.hw,
+       [AUD_CLKID_MST_F_LRCLK]         = &mst_f_lrclk.hw,
+       [AUD_CLKID_TDMIN_A_SCLK_SEL]    = &tdmin_a_sclk_sel.hw,
+       [AUD_CLKID_TDMIN_B_SCLK_SEL]    = &tdmin_b_sclk_sel.hw,
+       [AUD_CLKID_TDMIN_C_SCLK_SEL]    = &tdmin_c_sclk_sel.hw,
+       [AUD_CLKID_TDMIN_LB_SCLK_SEL]   = &tdmin_lb_sclk_sel.hw,
+       [AUD_CLKID_TDMOUT_A_SCLK_SEL]   = &tdmout_a_sclk_sel.hw,
+       [AUD_CLKID_TDMOUT_B_SCLK_SEL]   = &tdmout_b_sclk_sel.hw,
+       [AUD_CLKID_TDMOUT_C_SCLK_SEL]   = &tdmout_c_sclk_sel.hw,
+       [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
+       [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
+       [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
+       [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
+       [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
+       [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
+       [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
+       [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
+       [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
+       [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
+       [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
+       [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
+       [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
+       [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
+       [AUD_CLKID_TDMIN_A_SCLK]        = &tdmin_a_sclk.hw,
+       [AUD_CLKID_TDMIN_B_SCLK]        = &tdmin_b_sclk.hw,
+       [AUD_CLKID_TDMIN_C_SCLK]        = &tdmin_c_sclk.hw,
+       [AUD_CLKID_TDMIN_LB_SCLK]       = &tdmin_lb_sclk.hw,
+       [AUD_CLKID_TDMOUT_A_SCLK]       = &axg_tdmout_a_sclk.hw,
+       [AUD_CLKID_TDMOUT_B_SCLK]       = &axg_tdmout_b_sclk.hw,
+       [AUD_CLKID_TDMOUT_C_SCLK]       = &axg_tdmout_c_sclk.hw,
+       [AUD_CLKID_TDMIN_A_LRCLK]       = &tdmin_a_lrclk.hw,
+       [AUD_CLKID_TDMIN_B_LRCLK]       = &tdmin_b_lrclk.hw,
+       [AUD_CLKID_TDMIN_C_LRCLK]       = &tdmin_c_lrclk.hw,
+       [AUD_CLKID_TDMIN_LB_LRCLK]      = &tdmin_lb_lrclk.hw,
+       [AUD_CLKID_TDMOUT_A_LRCLK]      = &tdmout_a_lrclk.hw,
+       [AUD_CLKID_TDMOUT_B_LRCLK]      = &tdmout_b_lrclk.hw,
+       [AUD_CLKID_TDMOUT_C_LRCLK]      = &tdmout_c_lrclk.hw,
+       [AUD_CLKID_TOP]                 = &axg_aud_top,
 };
 
 /*
  * Array of all G12A clocks provided by this provider
  * The input clocks of the controller will be populated at runtime
  */
-static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = {
-       .hws = {
-               [AUD_CLKID_DDR_ARB]             = &ddr_arb.hw,
-               [AUD_CLKID_PDM]                 = &pdm.hw,
-               [AUD_CLKID_TDMIN_A]             = &tdmin_a.hw,
-               [AUD_CLKID_TDMIN_B]             = &tdmin_b.hw,
-               [AUD_CLKID_TDMIN_C]             = &tdmin_c.hw,
-               [AUD_CLKID_TDMIN_LB]            = &tdmin_lb.hw,
-               [AUD_CLKID_TDMOUT_A]            = &tdmout_a.hw,
-               [AUD_CLKID_TDMOUT_B]            = &tdmout_b.hw,
-               [AUD_CLKID_TDMOUT_C]            = &tdmout_c.hw,
-               [AUD_CLKID_FRDDR_A]             = &frddr_a.hw,
-               [AUD_CLKID_FRDDR_B]             = &frddr_b.hw,
-               [AUD_CLKID_FRDDR_C]             = &frddr_c.hw,
-               [AUD_CLKID_TODDR_A]             = &toddr_a.hw,
-               [AUD_CLKID_TODDR_B]             = &toddr_b.hw,
-               [AUD_CLKID_TODDR_C]             = &toddr_c.hw,
-               [AUD_CLKID_LOOPBACK]            = &loopback.hw,
-               [AUD_CLKID_SPDIFIN]             = &spdifin.hw,
-               [AUD_CLKID_SPDIFOUT]            = &spdifout.hw,
-               [AUD_CLKID_RESAMPLE]            = &resample.hw,
-               [AUD_CLKID_POWER_DETECT]        = &power_detect.hw,
-               [AUD_CLKID_SPDIFOUT_B]          = &spdifout_b.hw,
-               [AUD_CLKID_MST_A_MCLK_SEL]      = &mst_a_mclk_sel.hw,
-               [AUD_CLKID_MST_B_MCLK_SEL]      = &mst_b_mclk_sel.hw,
-               [AUD_CLKID_MST_C_MCLK_SEL]      = &mst_c_mclk_sel.hw,
-               [AUD_CLKID_MST_D_MCLK_SEL]      = &mst_d_mclk_sel.hw,
-               [AUD_CLKID_MST_E_MCLK_SEL]      = &mst_e_mclk_sel.hw,
-               [AUD_CLKID_MST_F_MCLK_SEL]      = &mst_f_mclk_sel.hw,
-               [AUD_CLKID_MST_A_MCLK_DIV]      = &mst_a_mclk_div.hw,
-               [AUD_CLKID_MST_B_MCLK_DIV]      = &mst_b_mclk_div.hw,
-               [AUD_CLKID_MST_C_MCLK_DIV]      = &mst_c_mclk_div.hw,
-               [AUD_CLKID_MST_D_MCLK_DIV]      = &mst_d_mclk_div.hw,
-               [AUD_CLKID_MST_E_MCLK_DIV]      = &mst_e_mclk_div.hw,
-               [AUD_CLKID_MST_F_MCLK_DIV]      = &mst_f_mclk_div.hw,
-               [AUD_CLKID_MST_A_MCLK]          = &mst_a_mclk.hw,
-               [AUD_CLKID_MST_B_MCLK]          = &mst_b_mclk.hw,
-               [AUD_CLKID_MST_C_MCLK]          = &mst_c_mclk.hw,
-               [AUD_CLKID_MST_D_MCLK]          = &mst_d_mclk.hw,
-               [AUD_CLKID_MST_E_MCLK]          = &mst_e_mclk.hw,
-               [AUD_CLKID_MST_F_MCLK]          = &mst_f_mclk.hw,
-               [AUD_CLKID_SPDIFOUT_CLK_SEL]    = &spdifout_clk_sel.hw,
-               [AUD_CLKID_SPDIFOUT_CLK_DIV]    = &spdifout_clk_div.hw,
-               [AUD_CLKID_SPDIFOUT_CLK]        = &spdifout_clk.hw,
-               [AUD_CLKID_SPDIFOUT_B_CLK_SEL]  = &spdifout_b_clk_sel.hw,
-               [AUD_CLKID_SPDIFOUT_B_CLK_DIV]  = &spdifout_b_clk_div.hw,
-               [AUD_CLKID_SPDIFOUT_B_CLK]      = &spdifout_b_clk.hw,
-               [AUD_CLKID_SPDIFIN_CLK_SEL]     = &spdifin_clk_sel.hw,
-               [AUD_CLKID_SPDIFIN_CLK_DIV]     = &spdifin_clk_div.hw,
-               [AUD_CLKID_SPDIFIN_CLK]         = &spdifin_clk.hw,
-               [AUD_CLKID_PDM_DCLK_SEL]        = &pdm_dclk_sel.hw,
-               [AUD_CLKID_PDM_DCLK_DIV]        = &pdm_dclk_div.hw,
-               [AUD_CLKID_PDM_DCLK]            = &pdm_dclk.hw,
-               [AUD_CLKID_PDM_SYSCLK_SEL]      = &pdm_sysclk_sel.hw,
-               [AUD_CLKID_PDM_SYSCLK_DIV]      = &pdm_sysclk_div.hw,
-               [AUD_CLKID_PDM_SYSCLK]          = &pdm_sysclk.hw,
-               [AUD_CLKID_MST_A_SCLK_PRE_EN]   = &mst_a_sclk_pre_en.hw,
-               [AUD_CLKID_MST_B_SCLK_PRE_EN]   = &mst_b_sclk_pre_en.hw,
-               [AUD_CLKID_MST_C_SCLK_PRE_EN]   = &mst_c_sclk_pre_en.hw,
-               [AUD_CLKID_MST_D_SCLK_PRE_EN]   = &mst_d_sclk_pre_en.hw,
-               [AUD_CLKID_MST_E_SCLK_PRE_EN]   = &mst_e_sclk_pre_en.hw,
-               [AUD_CLKID_MST_F_SCLK_PRE_EN]   = &mst_f_sclk_pre_en.hw,
-               [AUD_CLKID_MST_A_SCLK_DIV]      = &mst_a_sclk_div.hw,
-               [AUD_CLKID_MST_B_SCLK_DIV]      = &mst_b_sclk_div.hw,
-               [AUD_CLKID_MST_C_SCLK_DIV]      = &mst_c_sclk_div.hw,
-               [AUD_CLKID_MST_D_SCLK_DIV]      = &mst_d_sclk_div.hw,
-               [AUD_CLKID_MST_E_SCLK_DIV]      = &mst_e_sclk_div.hw,
-               [AUD_CLKID_MST_F_SCLK_DIV]      = &mst_f_sclk_div.hw,
-               [AUD_CLKID_MST_A_SCLK_POST_EN]  = &mst_a_sclk_post_en.hw,
-               [AUD_CLKID_MST_B_SCLK_POST_EN]  = &mst_b_sclk_post_en.hw,
-               [AUD_CLKID_MST_C_SCLK_POST_EN]  = &mst_c_sclk_post_en.hw,
-               [AUD_CLKID_MST_D_SCLK_POST_EN]  = &mst_d_sclk_post_en.hw,
-               [AUD_CLKID_MST_E_SCLK_POST_EN]  = &mst_e_sclk_post_en.hw,
-               [AUD_CLKID_MST_F_SCLK_POST_EN]  = &mst_f_sclk_post_en.hw,
-               [AUD_CLKID_MST_A_SCLK]          = &mst_a_sclk.hw,
-               [AUD_CLKID_MST_B_SCLK]          = &mst_b_sclk.hw,
-               [AUD_CLKID_MST_C_SCLK]          = &mst_c_sclk.hw,
-               [AUD_CLKID_MST_D_SCLK]          = &mst_d_sclk.hw,
-               [AUD_CLKID_MST_E_SCLK]          = &mst_e_sclk.hw,
-               [AUD_CLKID_MST_F_SCLK]          = &mst_f_sclk.hw,
-               [AUD_CLKID_MST_A_LRCLK_DIV]     = &mst_a_lrclk_div.hw,
-               [AUD_CLKID_MST_B_LRCLK_DIV]     = &mst_b_lrclk_div.hw,
-               [AUD_CLKID_MST_C_LRCLK_DIV]     = &mst_c_lrclk_div.hw,
-               [AUD_CLKID_MST_D_LRCLK_DIV]     = &mst_d_lrclk_div.hw,
-               [AUD_CLKID_MST_E_LRCLK_DIV]     = &mst_e_lrclk_div.hw,
-               [AUD_CLKID_MST_F_LRCLK_DIV]     = &mst_f_lrclk_div.hw,
-               [AUD_CLKID_MST_A_LRCLK]         = &mst_a_lrclk.hw,
-               [AUD_CLKID_MST_B_LRCLK]         = &mst_b_lrclk.hw,
-               [AUD_CLKID_MST_C_LRCLK]         = &mst_c_lrclk.hw,
-               [AUD_CLKID_MST_D_LRCLK]         = &mst_d_lrclk.hw,
-               [AUD_CLKID_MST_E_LRCLK]         = &mst_e_lrclk.hw,
-               [AUD_CLKID_MST_F_LRCLK]         = &mst_f_lrclk.hw,
-               [AUD_CLKID_TDMIN_A_SCLK_SEL]    = &tdmin_a_sclk_sel.hw,
-               [AUD_CLKID_TDMIN_B_SCLK_SEL]    = &tdmin_b_sclk_sel.hw,
-               [AUD_CLKID_TDMIN_C_SCLK_SEL]    = &tdmin_c_sclk_sel.hw,
-               [AUD_CLKID_TDMIN_LB_SCLK_SEL]   = &tdmin_lb_sclk_sel.hw,
-               [AUD_CLKID_TDMOUT_A_SCLK_SEL]   = &tdmout_a_sclk_sel.hw,
-               [AUD_CLKID_TDMOUT_B_SCLK_SEL]   = &tdmout_b_sclk_sel.hw,
-               [AUD_CLKID_TDMOUT_C_SCLK_SEL]   = &tdmout_c_sclk_sel.hw,
-               [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
-               [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
-               [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
-               [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
-               [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
-               [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
-               [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
-               [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
-               [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
-               [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
-               [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
-               [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
-               [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
-               [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
-               [AUD_CLKID_TDMIN_A_SCLK]        = &tdmin_a_sclk.hw,
-               [AUD_CLKID_TDMIN_B_SCLK]        = &tdmin_b_sclk.hw,
-               [AUD_CLKID_TDMIN_C_SCLK]        = &tdmin_c_sclk.hw,
-               [AUD_CLKID_TDMIN_LB_SCLK]       = &tdmin_lb_sclk.hw,
-               [AUD_CLKID_TDMOUT_A_SCLK]       = &g12a_tdmout_a_sclk.hw,
-               [AUD_CLKID_TDMOUT_B_SCLK]       = &g12a_tdmout_b_sclk.hw,
-               [AUD_CLKID_TDMOUT_C_SCLK]       = &g12a_tdmout_c_sclk.hw,
-               [AUD_CLKID_TDMIN_A_LRCLK]       = &tdmin_a_lrclk.hw,
-               [AUD_CLKID_TDMIN_B_LRCLK]       = &tdmin_b_lrclk.hw,
-               [AUD_CLKID_TDMIN_C_LRCLK]       = &tdmin_c_lrclk.hw,
-               [AUD_CLKID_TDMIN_LB_LRCLK]      = &tdmin_lb_lrclk.hw,
-               [AUD_CLKID_TDMOUT_A_LRCLK]      = &tdmout_a_lrclk.hw,
-               [AUD_CLKID_TDMOUT_B_LRCLK]      = &tdmout_b_lrclk.hw,
-               [AUD_CLKID_TDMOUT_C_LRCLK]      = &tdmout_c_lrclk.hw,
-               [AUD_CLKID_TDM_MCLK_PAD0]       = &g12a_tdm_mclk_pad_0.hw,
-               [AUD_CLKID_TDM_MCLK_PAD1]       = &g12a_tdm_mclk_pad_1.hw,
-               [AUD_CLKID_TDM_LRCLK_PAD0]      = &g12a_tdm_lrclk_pad_0.hw,
-               [AUD_CLKID_TDM_LRCLK_PAD1]      = &g12a_tdm_lrclk_pad_1.hw,
-               [AUD_CLKID_TDM_LRCLK_PAD2]      = &g12a_tdm_lrclk_pad_2.hw,
-               [AUD_CLKID_TDM_SCLK_PAD0]       = &g12a_tdm_sclk_pad_0.hw,
-               [AUD_CLKID_TDM_SCLK_PAD1]       = &g12a_tdm_sclk_pad_1.hw,
-               [AUD_CLKID_TDM_SCLK_PAD2]       = &g12a_tdm_sclk_pad_2.hw,
-               [AUD_CLKID_TOP]                 = &axg_aud_top,
-               [NR_CLKS] = NULL,
-       },
-       .num = NR_CLKS,
+static struct clk_hw *g12a_audio_hw_clks[] = {
+       [AUD_CLKID_DDR_ARB]             = &ddr_arb.hw,
+       [AUD_CLKID_PDM]                 = &pdm.hw,
+       [AUD_CLKID_TDMIN_A]             = &tdmin_a.hw,
+       [AUD_CLKID_TDMIN_B]             = &tdmin_b.hw,
+       [AUD_CLKID_TDMIN_C]             = &tdmin_c.hw,
+       [AUD_CLKID_TDMIN_LB]            = &tdmin_lb.hw,
+       [AUD_CLKID_TDMOUT_A]            = &tdmout_a.hw,
+       [AUD_CLKID_TDMOUT_B]            = &tdmout_b.hw,
+       [AUD_CLKID_TDMOUT_C]            = &tdmout_c.hw,
+       [AUD_CLKID_FRDDR_A]             = &frddr_a.hw,
+       [AUD_CLKID_FRDDR_B]             = &frddr_b.hw,
+       [AUD_CLKID_FRDDR_C]             = &frddr_c.hw,
+       [AUD_CLKID_TODDR_A]             = &toddr_a.hw,
+       [AUD_CLKID_TODDR_B]             = &toddr_b.hw,
+       [AUD_CLKID_TODDR_C]             = &toddr_c.hw,
+       [AUD_CLKID_LOOPBACK]            = &loopback.hw,
+       [AUD_CLKID_SPDIFIN]             = &spdifin.hw,
+       [AUD_CLKID_SPDIFOUT]            = &spdifout.hw,
+       [AUD_CLKID_RESAMPLE]            = &resample.hw,
+       [AUD_CLKID_POWER_DETECT]        = &power_detect.hw,
+       [AUD_CLKID_SPDIFOUT_B]          = &spdifout_b.hw,
+       [AUD_CLKID_MST_A_MCLK_SEL]      = &mst_a_mclk_sel.hw,
+       [AUD_CLKID_MST_B_MCLK_SEL]      = &mst_b_mclk_sel.hw,
+       [AUD_CLKID_MST_C_MCLK_SEL]      = &mst_c_mclk_sel.hw,
+       [AUD_CLKID_MST_D_MCLK_SEL]      = &mst_d_mclk_sel.hw,
+       [AUD_CLKID_MST_E_MCLK_SEL]      = &mst_e_mclk_sel.hw,
+       [AUD_CLKID_MST_F_MCLK_SEL]      = &mst_f_mclk_sel.hw,
+       [AUD_CLKID_MST_A_MCLK_DIV]      = &mst_a_mclk_div.hw,
+       [AUD_CLKID_MST_B_MCLK_DIV]      = &mst_b_mclk_div.hw,
+       [AUD_CLKID_MST_C_MCLK_DIV]      = &mst_c_mclk_div.hw,
+       [AUD_CLKID_MST_D_MCLK_DIV]      = &mst_d_mclk_div.hw,
+       [AUD_CLKID_MST_E_MCLK_DIV]      = &mst_e_mclk_div.hw,
+       [AUD_CLKID_MST_F_MCLK_DIV]      = &mst_f_mclk_div.hw,
+       [AUD_CLKID_MST_A_MCLK]          = &mst_a_mclk.hw,
+       [AUD_CLKID_MST_B_MCLK]          = &mst_b_mclk.hw,
+       [AUD_CLKID_MST_C_MCLK]          = &mst_c_mclk.hw,
+       [AUD_CLKID_MST_D_MCLK]          = &mst_d_mclk.hw,
+       [AUD_CLKID_MST_E_MCLK]          = &mst_e_mclk.hw,
+       [AUD_CLKID_MST_F_MCLK]          = &mst_f_mclk.hw,
+       [AUD_CLKID_SPDIFOUT_CLK_SEL]    = &spdifout_clk_sel.hw,
+       [AUD_CLKID_SPDIFOUT_CLK_DIV]    = &spdifout_clk_div.hw,
+       [AUD_CLKID_SPDIFOUT_CLK]        = &spdifout_clk.hw,
+       [AUD_CLKID_SPDIFOUT_B_CLK_SEL]  = &spdifout_b_clk_sel.hw,
+       [AUD_CLKID_SPDIFOUT_B_CLK_DIV]  = &spdifout_b_clk_div.hw,
+       [AUD_CLKID_SPDIFOUT_B_CLK]      = &spdifout_b_clk.hw,
+       [AUD_CLKID_SPDIFIN_CLK_SEL]     = &spdifin_clk_sel.hw,
+       [AUD_CLKID_SPDIFIN_CLK_DIV]     = &spdifin_clk_div.hw,
+       [AUD_CLKID_SPDIFIN_CLK]         = &spdifin_clk.hw,
+       [AUD_CLKID_PDM_DCLK_SEL]        = &pdm_dclk_sel.hw,
+       [AUD_CLKID_PDM_DCLK_DIV]        = &pdm_dclk_div.hw,
+       [AUD_CLKID_PDM_DCLK]            = &pdm_dclk.hw,
+       [AUD_CLKID_PDM_SYSCLK_SEL]      = &pdm_sysclk_sel.hw,
+       [AUD_CLKID_PDM_SYSCLK_DIV]      = &pdm_sysclk_div.hw,
+       [AUD_CLKID_PDM_SYSCLK]          = &pdm_sysclk.hw,
+       [AUD_CLKID_MST_A_SCLK_PRE_EN]   = &mst_a_sclk_pre_en.hw,
+       [AUD_CLKID_MST_B_SCLK_PRE_EN]   = &mst_b_sclk_pre_en.hw,
+       [AUD_CLKID_MST_C_SCLK_PRE_EN]   = &mst_c_sclk_pre_en.hw,
+       [AUD_CLKID_MST_D_SCLK_PRE_EN]   = &mst_d_sclk_pre_en.hw,
+       [AUD_CLKID_MST_E_SCLK_PRE_EN]   = &mst_e_sclk_pre_en.hw,
+       [AUD_CLKID_MST_F_SCLK_PRE_EN]   = &mst_f_sclk_pre_en.hw,
+       [AUD_CLKID_MST_A_SCLK_DIV]      = &mst_a_sclk_div.hw,
+       [AUD_CLKID_MST_B_SCLK_DIV]      = &mst_b_sclk_div.hw,
+       [AUD_CLKID_MST_C_SCLK_DIV]      = &mst_c_sclk_div.hw,
+       [AUD_CLKID_MST_D_SCLK_DIV]      = &mst_d_sclk_div.hw,
+       [AUD_CLKID_MST_E_SCLK_DIV]      = &mst_e_sclk_div.hw,
+       [AUD_CLKID_MST_F_SCLK_DIV]      = &mst_f_sclk_div.hw,
+       [AUD_CLKID_MST_A_SCLK_POST_EN]  = &mst_a_sclk_post_en.hw,
+       [AUD_CLKID_MST_B_SCLK_POST_EN]  = &mst_b_sclk_post_en.hw,
+       [AUD_CLKID_MST_C_SCLK_POST_EN]  = &mst_c_sclk_post_en.hw,
+       [AUD_CLKID_MST_D_SCLK_POST_EN]  = &mst_d_sclk_post_en.hw,
+       [AUD_CLKID_MST_E_SCLK_POST_EN]  = &mst_e_sclk_post_en.hw,
+       [AUD_CLKID_MST_F_SCLK_POST_EN]  = &mst_f_sclk_post_en.hw,
+       [AUD_CLKID_MST_A_SCLK]          = &mst_a_sclk.hw,
+       [AUD_CLKID_MST_B_SCLK]          = &mst_b_sclk.hw,
+       [AUD_CLKID_MST_C_SCLK]          = &mst_c_sclk.hw,
+       [AUD_CLKID_MST_D_SCLK]          = &mst_d_sclk.hw,
+       [AUD_CLKID_MST_E_SCLK]          = &mst_e_sclk.hw,
+       [AUD_CLKID_MST_F_SCLK]          = &mst_f_sclk.hw,
+       [AUD_CLKID_MST_A_LRCLK_DIV]     = &mst_a_lrclk_div.hw,
+       [AUD_CLKID_MST_B_LRCLK_DIV]     = &mst_b_lrclk_div.hw,
+       [AUD_CLKID_MST_C_LRCLK_DIV]     = &mst_c_lrclk_div.hw,
+       [AUD_CLKID_MST_D_LRCLK_DIV]     = &mst_d_lrclk_div.hw,
+       [AUD_CLKID_MST_E_LRCLK_DIV]     = &mst_e_lrclk_div.hw,
+       [AUD_CLKID_MST_F_LRCLK_DIV]     = &mst_f_lrclk_div.hw,
+       [AUD_CLKID_MST_A_LRCLK]         = &mst_a_lrclk.hw,
+       [AUD_CLKID_MST_B_LRCLK]         = &mst_b_lrclk.hw,
+       [AUD_CLKID_MST_C_LRCLK]         = &mst_c_lrclk.hw,
+       [AUD_CLKID_MST_D_LRCLK]         = &mst_d_lrclk.hw,
+       [AUD_CLKID_MST_E_LRCLK]         = &mst_e_lrclk.hw,
+       [AUD_CLKID_MST_F_LRCLK]         = &mst_f_lrclk.hw,
+       [AUD_CLKID_TDMIN_A_SCLK_SEL]    = &tdmin_a_sclk_sel.hw,
+       [AUD_CLKID_TDMIN_B_SCLK_SEL]    = &tdmin_b_sclk_sel.hw,
+       [AUD_CLKID_TDMIN_C_SCLK_SEL]    = &tdmin_c_sclk_sel.hw,
+       [AUD_CLKID_TDMIN_LB_SCLK_SEL]   = &tdmin_lb_sclk_sel.hw,
+       [AUD_CLKID_TDMOUT_A_SCLK_SEL]   = &tdmout_a_sclk_sel.hw,
+       [AUD_CLKID_TDMOUT_B_SCLK_SEL]   = &tdmout_b_sclk_sel.hw,
+       [AUD_CLKID_TDMOUT_C_SCLK_SEL]   = &tdmout_c_sclk_sel.hw,
+       [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
+       [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
+       [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
+       [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
+       [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
+       [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
+       [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
+       [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
+       [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
+       [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
+       [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
+       [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
+       [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
+       [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
+       [AUD_CLKID_TDMIN_A_SCLK]        = &tdmin_a_sclk.hw,
+       [AUD_CLKID_TDMIN_B_SCLK]        = &tdmin_b_sclk.hw,
+       [AUD_CLKID_TDMIN_C_SCLK]        = &tdmin_c_sclk.hw,
+       [AUD_CLKID_TDMIN_LB_SCLK]       = &tdmin_lb_sclk.hw,
+       [AUD_CLKID_TDMOUT_A_SCLK]       = &g12a_tdmout_a_sclk.hw,
+       [AUD_CLKID_TDMOUT_B_SCLK]       = &g12a_tdmout_b_sclk.hw,
+       [AUD_CLKID_TDMOUT_C_SCLK]       = &g12a_tdmout_c_sclk.hw,
+       [AUD_CLKID_TDMIN_A_LRCLK]       = &tdmin_a_lrclk.hw,
+       [AUD_CLKID_TDMIN_B_LRCLK]       = &tdmin_b_lrclk.hw,
+       [AUD_CLKID_TDMIN_C_LRCLK]       = &tdmin_c_lrclk.hw,
+       [AUD_CLKID_TDMIN_LB_LRCLK]      = &tdmin_lb_lrclk.hw,
+       [AUD_CLKID_TDMOUT_A_LRCLK]      = &tdmout_a_lrclk.hw,
+       [AUD_CLKID_TDMOUT_B_LRCLK]      = &tdmout_b_lrclk.hw,
+       [AUD_CLKID_TDMOUT_C_LRCLK]      = &tdmout_c_lrclk.hw,
+       [AUD_CLKID_TDM_MCLK_PAD0]       = &g12a_tdm_mclk_pad_0.hw,
+       [AUD_CLKID_TDM_MCLK_PAD1]       = &g12a_tdm_mclk_pad_1.hw,
+       [AUD_CLKID_TDM_LRCLK_PAD0]      = &g12a_tdm_lrclk_pad_0.hw,
+       [AUD_CLKID_TDM_LRCLK_PAD1]      = &g12a_tdm_lrclk_pad_1.hw,
+       [AUD_CLKID_TDM_LRCLK_PAD2]      = &g12a_tdm_lrclk_pad_2.hw,
+       [AUD_CLKID_TDM_SCLK_PAD0]       = &g12a_tdm_sclk_pad_0.hw,
+       [AUD_CLKID_TDM_SCLK_PAD1]       = &g12a_tdm_sclk_pad_1.hw,
+       [AUD_CLKID_TDM_SCLK_PAD2]       = &g12a_tdm_sclk_pad_2.hw,
+       [AUD_CLKID_TOP]                 = &axg_aud_top,
 };
 
 /*
  * Array of all SM1 clocks provided by this provider
  * The input clocks of the controller will be populated at runtime
  */
-static struct clk_hw_onecell_data sm1_audio_hw_onecell_data = {
-       .hws = {
-               [AUD_CLKID_DDR_ARB]             = &ddr_arb.hw,
-               [AUD_CLKID_PDM]                 = &pdm.hw,
-               [AUD_CLKID_TDMIN_A]             = &tdmin_a.hw,
-               [AUD_CLKID_TDMIN_B]             = &tdmin_b.hw,
-               [AUD_CLKID_TDMIN_C]             = &tdmin_c.hw,
-               [AUD_CLKID_TDMIN_LB]            = &tdmin_lb.hw,
-               [AUD_CLKID_TDMOUT_A]            = &tdmout_a.hw,
-               [AUD_CLKID_TDMOUT_B]            = &tdmout_b.hw,
-               [AUD_CLKID_TDMOUT_C]            = &tdmout_c.hw,
-               [AUD_CLKID_FRDDR_A]             = &frddr_a.hw,
-               [AUD_CLKID_FRDDR_B]             = &frddr_b.hw,
-               [AUD_CLKID_FRDDR_C]             = &frddr_c.hw,
-               [AUD_CLKID_TODDR_A]             = &toddr_a.hw,
-               [AUD_CLKID_TODDR_B]             = &toddr_b.hw,
-               [AUD_CLKID_TODDR_C]             = &toddr_c.hw,
-               [AUD_CLKID_LOOPBACK]            = &loopback.hw,
-               [AUD_CLKID_SPDIFIN]             = &spdifin.hw,
-               [AUD_CLKID_SPDIFOUT]            = &spdifout.hw,
-               [AUD_CLKID_RESAMPLE]            = &resample.hw,
-               [AUD_CLKID_SPDIFOUT_B]          = &spdifout_b.hw,
-               [AUD_CLKID_MST_A_MCLK_SEL]      = &sm1_mst_a_mclk_sel.hw,
-               [AUD_CLKID_MST_B_MCLK_SEL]      = &sm1_mst_b_mclk_sel.hw,
-               [AUD_CLKID_MST_C_MCLK_SEL]      = &sm1_mst_c_mclk_sel.hw,
-               [AUD_CLKID_MST_D_MCLK_SEL]      = &sm1_mst_d_mclk_sel.hw,
-               [AUD_CLKID_MST_E_MCLK_SEL]      = &sm1_mst_e_mclk_sel.hw,
-               [AUD_CLKID_MST_F_MCLK_SEL]      = &sm1_mst_f_mclk_sel.hw,
-               [AUD_CLKID_MST_A_MCLK_DIV]      = &sm1_mst_a_mclk_div.hw,
-               [AUD_CLKID_MST_B_MCLK_DIV]      = &sm1_mst_b_mclk_div.hw,
-               [AUD_CLKID_MST_C_MCLK_DIV]      = &sm1_mst_c_mclk_div.hw,
-               [AUD_CLKID_MST_D_MCLK_DIV]      = &sm1_mst_d_mclk_div.hw,
-               [AUD_CLKID_MST_E_MCLK_DIV]      = &sm1_mst_e_mclk_div.hw,
-               [AUD_CLKID_MST_F_MCLK_DIV]      = &sm1_mst_f_mclk_div.hw,
-               [AUD_CLKID_MST_A_MCLK]          = &sm1_mst_a_mclk.hw,
-               [AUD_CLKID_MST_B_MCLK]          = &sm1_mst_b_mclk.hw,
-               [AUD_CLKID_MST_C_MCLK]          = &sm1_mst_c_mclk.hw,
-               [AUD_CLKID_MST_D_MCLK]          = &sm1_mst_d_mclk.hw,
-               [AUD_CLKID_MST_E_MCLK]          = &sm1_mst_e_mclk.hw,
-               [AUD_CLKID_MST_F_MCLK]          = &sm1_mst_f_mclk.hw,
-               [AUD_CLKID_SPDIFOUT_CLK_SEL]    = &spdifout_clk_sel.hw,
-               [AUD_CLKID_SPDIFOUT_CLK_DIV]    = &spdifout_clk_div.hw,
-               [AUD_CLKID_SPDIFOUT_CLK]        = &spdifout_clk.hw,
-               [AUD_CLKID_SPDIFOUT_B_CLK_SEL]  = &spdifout_b_clk_sel.hw,
-               [AUD_CLKID_SPDIFOUT_B_CLK_DIV]  = &spdifout_b_clk_div.hw,
-               [AUD_CLKID_SPDIFOUT_B_CLK]      = &spdifout_b_clk.hw,
-               [AUD_CLKID_SPDIFIN_CLK_SEL]     = &spdifin_clk_sel.hw,
-               [AUD_CLKID_SPDIFIN_CLK_DIV]     = &spdifin_clk_div.hw,
-               [AUD_CLKID_SPDIFIN_CLK]         = &spdifin_clk.hw,
-               [AUD_CLKID_PDM_DCLK_SEL]        = &pdm_dclk_sel.hw,
-               [AUD_CLKID_PDM_DCLK_DIV]        = &pdm_dclk_div.hw,
-               [AUD_CLKID_PDM_DCLK]            = &pdm_dclk.hw,
-               [AUD_CLKID_PDM_SYSCLK_SEL]      = &pdm_sysclk_sel.hw,
-               [AUD_CLKID_PDM_SYSCLK_DIV]      = &pdm_sysclk_div.hw,
-               [AUD_CLKID_PDM_SYSCLK]          = &pdm_sysclk.hw,
-               [AUD_CLKID_MST_A_SCLK_PRE_EN]   = &mst_a_sclk_pre_en.hw,
-               [AUD_CLKID_MST_B_SCLK_PRE_EN]   = &mst_b_sclk_pre_en.hw,
-               [AUD_CLKID_MST_C_SCLK_PRE_EN]   = &mst_c_sclk_pre_en.hw,
-               [AUD_CLKID_MST_D_SCLK_PRE_EN]   = &mst_d_sclk_pre_en.hw,
-               [AUD_CLKID_MST_E_SCLK_PRE_EN]   = &mst_e_sclk_pre_en.hw,
-               [AUD_CLKID_MST_F_SCLK_PRE_EN]   = &mst_f_sclk_pre_en.hw,
-               [AUD_CLKID_MST_A_SCLK_DIV]      = &mst_a_sclk_div.hw,
-               [AUD_CLKID_MST_B_SCLK_DIV]      = &mst_b_sclk_div.hw,
-               [AUD_CLKID_MST_C_SCLK_DIV]      = &mst_c_sclk_div.hw,
-               [AUD_CLKID_MST_D_SCLK_DIV]      = &mst_d_sclk_div.hw,
-               [AUD_CLKID_MST_E_SCLK_DIV]      = &mst_e_sclk_div.hw,
-               [AUD_CLKID_MST_F_SCLK_DIV]      = &mst_f_sclk_div.hw,
-               [AUD_CLKID_MST_A_SCLK_POST_EN]  = &mst_a_sclk_post_en.hw,
-               [AUD_CLKID_MST_B_SCLK_POST_EN]  = &mst_b_sclk_post_en.hw,
-               [AUD_CLKID_MST_C_SCLK_POST_EN]  = &mst_c_sclk_post_en.hw,
-               [AUD_CLKID_MST_D_SCLK_POST_EN]  = &mst_d_sclk_post_en.hw,
-               [AUD_CLKID_MST_E_SCLK_POST_EN]  = &mst_e_sclk_post_en.hw,
-               [AUD_CLKID_MST_F_SCLK_POST_EN]  = &mst_f_sclk_post_en.hw,
-               [AUD_CLKID_MST_A_SCLK]          = &mst_a_sclk.hw,
-               [AUD_CLKID_MST_B_SCLK]          = &mst_b_sclk.hw,
-               [AUD_CLKID_MST_C_SCLK]          = &mst_c_sclk.hw,
-               [AUD_CLKID_MST_D_SCLK]          = &mst_d_sclk.hw,
-               [AUD_CLKID_MST_E_SCLK]          = &mst_e_sclk.hw,
-               [AUD_CLKID_MST_F_SCLK]          = &mst_f_sclk.hw,
-               [AUD_CLKID_MST_A_LRCLK_DIV]     = &mst_a_lrclk_div.hw,
-               [AUD_CLKID_MST_B_LRCLK_DIV]     = &mst_b_lrclk_div.hw,
-               [AUD_CLKID_MST_C_LRCLK_DIV]     = &mst_c_lrclk_div.hw,
-               [AUD_CLKID_MST_D_LRCLK_DIV]     = &mst_d_lrclk_div.hw,
-               [AUD_CLKID_MST_E_LRCLK_DIV]     = &mst_e_lrclk_div.hw,
-               [AUD_CLKID_MST_F_LRCLK_DIV]     = &mst_f_lrclk_div.hw,
-               [AUD_CLKID_MST_A_LRCLK]         = &mst_a_lrclk.hw,
-               [AUD_CLKID_MST_B_LRCLK]         = &mst_b_lrclk.hw,
-               [AUD_CLKID_MST_C_LRCLK]         = &mst_c_lrclk.hw,
-               [AUD_CLKID_MST_D_LRCLK]         = &mst_d_lrclk.hw,
-               [AUD_CLKID_MST_E_LRCLK]         = &mst_e_lrclk.hw,
-               [AUD_CLKID_MST_F_LRCLK]         = &mst_f_lrclk.hw,
-               [AUD_CLKID_TDMIN_A_SCLK_SEL]    = &tdmin_a_sclk_sel.hw,
-               [AUD_CLKID_TDMIN_B_SCLK_SEL]    = &tdmin_b_sclk_sel.hw,
-               [AUD_CLKID_TDMIN_C_SCLK_SEL]    = &tdmin_c_sclk_sel.hw,
-               [AUD_CLKID_TDMIN_LB_SCLK_SEL]   = &tdmin_lb_sclk_sel.hw,
-               [AUD_CLKID_TDMOUT_A_SCLK_SEL]   = &tdmout_a_sclk_sel.hw,
-               [AUD_CLKID_TDMOUT_B_SCLK_SEL]   = &tdmout_b_sclk_sel.hw,
-               [AUD_CLKID_TDMOUT_C_SCLK_SEL]   = &tdmout_c_sclk_sel.hw,
-               [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
-               [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
-               [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
-               [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
-               [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
-               [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
-               [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
-               [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
-               [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
-               [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
-               [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
-               [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
-               [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
-               [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
-               [AUD_CLKID_TDMIN_A_SCLK]        = &tdmin_a_sclk.hw,
-               [AUD_CLKID_TDMIN_B_SCLK]        = &tdmin_b_sclk.hw,
-               [AUD_CLKID_TDMIN_C_SCLK]        = &tdmin_c_sclk.hw,
-               [AUD_CLKID_TDMIN_LB_SCLK]       = &tdmin_lb_sclk.hw,
-               [AUD_CLKID_TDMOUT_A_SCLK]       = &g12a_tdmout_a_sclk.hw,
-               [AUD_CLKID_TDMOUT_B_SCLK]       = &g12a_tdmout_b_sclk.hw,
-               [AUD_CLKID_TDMOUT_C_SCLK]       = &g12a_tdmout_c_sclk.hw,
-               [AUD_CLKID_TDMIN_A_LRCLK]       = &tdmin_a_lrclk.hw,
-               [AUD_CLKID_TDMIN_B_LRCLK]       = &tdmin_b_lrclk.hw,
-               [AUD_CLKID_TDMIN_C_LRCLK]       = &tdmin_c_lrclk.hw,
-               [AUD_CLKID_TDMIN_LB_LRCLK]      = &tdmin_lb_lrclk.hw,
-               [AUD_CLKID_TDMOUT_A_LRCLK]      = &tdmout_a_lrclk.hw,
-               [AUD_CLKID_TDMOUT_B_LRCLK]      = &tdmout_b_lrclk.hw,
-               [AUD_CLKID_TDMOUT_C_LRCLK]      = &tdmout_c_lrclk.hw,
-               [AUD_CLKID_TDM_MCLK_PAD0]       = &sm1_tdm_mclk_pad_0.hw,
-               [AUD_CLKID_TDM_MCLK_PAD1]       = &sm1_tdm_mclk_pad_1.hw,
-               [AUD_CLKID_TDM_LRCLK_PAD0]      = &sm1_tdm_lrclk_pad_0.hw,
-               [AUD_CLKID_TDM_LRCLK_PAD1]      = &sm1_tdm_lrclk_pad_1.hw,
-               [AUD_CLKID_TDM_LRCLK_PAD2]      = &sm1_tdm_lrclk_pad_2.hw,
-               [AUD_CLKID_TDM_SCLK_PAD0]       = &sm1_tdm_sclk_pad_0.hw,
-               [AUD_CLKID_TDM_SCLK_PAD1]       = &sm1_tdm_sclk_pad_1.hw,
-               [AUD_CLKID_TDM_SCLK_PAD2]       = &sm1_tdm_sclk_pad_2.hw,
-               [AUD_CLKID_TOP]                 = &sm1_aud_top.hw,
-               [AUD_CLKID_TORAM]               = &toram.hw,
-               [AUD_CLKID_EQDRC]               = &eqdrc.hw,
-               [AUD_CLKID_RESAMPLE_B]          = &resample_b.hw,
-               [AUD_CLKID_TOVAD]               = &tovad.hw,
-               [AUD_CLKID_LOCKER]              = &locker.hw,
-               [AUD_CLKID_SPDIFIN_LB]          = &spdifin_lb.hw,
-               [AUD_CLKID_FRDDR_D]             = &frddr_d.hw,
-               [AUD_CLKID_TODDR_D]             = &toddr_d.hw,
-               [AUD_CLKID_LOOPBACK_B]          = &loopback_b.hw,
-               [AUD_CLKID_CLK81_EN]            = &sm1_clk81_en.hw,
-               [AUD_CLKID_SYSCLK_A_DIV]        = &sm1_sysclk_a_div.hw,
-               [AUD_CLKID_SYSCLK_A_EN]         = &sm1_sysclk_a_en.hw,
-               [AUD_CLKID_SYSCLK_B_DIV]        = &sm1_sysclk_b_div.hw,
-               [AUD_CLKID_SYSCLK_B_EN]         = &sm1_sysclk_b_en.hw,
-               [NR_CLKS] = NULL,
-       },
-       .num = NR_CLKS,
+static struct clk_hw *sm1_audio_hw_clks[] = {
+       [AUD_CLKID_DDR_ARB]             = &ddr_arb.hw,
+       [AUD_CLKID_PDM]                 = &pdm.hw,
+       [AUD_CLKID_TDMIN_A]             = &tdmin_a.hw,
+       [AUD_CLKID_TDMIN_B]             = &tdmin_b.hw,
+       [AUD_CLKID_TDMIN_C]             = &tdmin_c.hw,
+       [AUD_CLKID_TDMIN_LB]            = &tdmin_lb.hw,
+       [AUD_CLKID_TDMOUT_A]            = &tdmout_a.hw,
+       [AUD_CLKID_TDMOUT_B]            = &tdmout_b.hw,
+       [AUD_CLKID_TDMOUT_C]            = &tdmout_c.hw,
+       [AUD_CLKID_FRDDR_A]             = &frddr_a.hw,
+       [AUD_CLKID_FRDDR_B]             = &frddr_b.hw,
+       [AUD_CLKID_FRDDR_C]             = &frddr_c.hw,
+       [AUD_CLKID_TODDR_A]             = &toddr_a.hw,
+       [AUD_CLKID_TODDR_B]             = &toddr_b.hw,
+       [AUD_CLKID_TODDR_C]             = &toddr_c.hw,
+       [AUD_CLKID_LOOPBACK]            = &loopback.hw,
+       [AUD_CLKID_SPDIFIN]             = &spdifin.hw,
+       [AUD_CLKID_SPDIFOUT]            = &spdifout.hw,
+       [AUD_CLKID_RESAMPLE]            = &resample.hw,
+       [AUD_CLKID_SPDIFOUT_B]          = &spdifout_b.hw,
+       [AUD_CLKID_MST_A_MCLK_SEL]      = &sm1_mst_a_mclk_sel.hw,
+       [AUD_CLKID_MST_B_MCLK_SEL]      = &sm1_mst_b_mclk_sel.hw,
+       [AUD_CLKID_MST_C_MCLK_SEL]      = &sm1_mst_c_mclk_sel.hw,
+       [AUD_CLKID_MST_D_MCLK_SEL]      = &sm1_mst_d_mclk_sel.hw,
+       [AUD_CLKID_MST_E_MCLK_SEL]      = &sm1_mst_e_mclk_sel.hw,
+       [AUD_CLKID_MST_F_MCLK_SEL]      = &sm1_mst_f_mclk_sel.hw,
+       [AUD_CLKID_MST_A_MCLK_DIV]      = &sm1_mst_a_mclk_div.hw,
+       [AUD_CLKID_MST_B_MCLK_DIV]      = &sm1_mst_b_mclk_div.hw,
+       [AUD_CLKID_MST_C_MCLK_DIV]      = &sm1_mst_c_mclk_div.hw,
+       [AUD_CLKID_MST_D_MCLK_DIV]      = &sm1_mst_d_mclk_div.hw,
+       [AUD_CLKID_MST_E_MCLK_DIV]      = &sm1_mst_e_mclk_div.hw,
+       [AUD_CLKID_MST_F_MCLK_DIV]      = &sm1_mst_f_mclk_div.hw,
+       [AUD_CLKID_MST_A_MCLK]          = &sm1_mst_a_mclk.hw,
+       [AUD_CLKID_MST_B_MCLK]          = &sm1_mst_b_mclk.hw,
+       [AUD_CLKID_MST_C_MCLK]          = &sm1_mst_c_mclk.hw,
+       [AUD_CLKID_MST_D_MCLK]          = &sm1_mst_d_mclk.hw,
+       [AUD_CLKID_MST_E_MCLK]          = &sm1_mst_e_mclk.hw,
+       [AUD_CLKID_MST_F_MCLK]          = &sm1_mst_f_mclk.hw,
+       [AUD_CLKID_SPDIFOUT_CLK_SEL]    = &spdifout_clk_sel.hw,
+       [AUD_CLKID_SPDIFOUT_CLK_DIV]    = &spdifout_clk_div.hw,
+       [AUD_CLKID_SPDIFOUT_CLK]        = &spdifout_clk.hw,
+       [AUD_CLKID_SPDIFOUT_B_CLK_SEL]  = &spdifout_b_clk_sel.hw,
+       [AUD_CLKID_SPDIFOUT_B_CLK_DIV]  = &spdifout_b_clk_div.hw,
+       [AUD_CLKID_SPDIFOUT_B_CLK]      = &spdifout_b_clk.hw,
+       [AUD_CLKID_SPDIFIN_CLK_SEL]     = &spdifin_clk_sel.hw,
+       [AUD_CLKID_SPDIFIN_CLK_DIV]     = &spdifin_clk_div.hw,
+       [AUD_CLKID_SPDIFIN_CLK]         = &spdifin_clk.hw,
+       [AUD_CLKID_PDM_DCLK_SEL]        = &pdm_dclk_sel.hw,
+       [AUD_CLKID_PDM_DCLK_DIV]        = &pdm_dclk_div.hw,
+       [AUD_CLKID_PDM_DCLK]            = &pdm_dclk.hw,
+       [AUD_CLKID_PDM_SYSCLK_SEL]      = &pdm_sysclk_sel.hw,
+       [AUD_CLKID_PDM_SYSCLK_DIV]      = &pdm_sysclk_div.hw,
+       [AUD_CLKID_PDM_SYSCLK]          = &pdm_sysclk.hw,
+       [AUD_CLKID_MST_A_SCLK_PRE_EN]   = &mst_a_sclk_pre_en.hw,
+       [AUD_CLKID_MST_B_SCLK_PRE_EN]   = &mst_b_sclk_pre_en.hw,
+       [AUD_CLKID_MST_C_SCLK_PRE_EN]   = &mst_c_sclk_pre_en.hw,
+       [AUD_CLKID_MST_D_SCLK_PRE_EN]   = &mst_d_sclk_pre_en.hw,
+       [AUD_CLKID_MST_E_SCLK_PRE_EN]   = &mst_e_sclk_pre_en.hw,
+       [AUD_CLKID_MST_F_SCLK_PRE_EN]   = &mst_f_sclk_pre_en.hw,
+       [AUD_CLKID_MST_A_SCLK_DIV]      = &mst_a_sclk_div.hw,
+       [AUD_CLKID_MST_B_SCLK_DIV]      = &mst_b_sclk_div.hw,
+       [AUD_CLKID_MST_C_SCLK_DIV]      = &mst_c_sclk_div.hw,
+       [AUD_CLKID_MST_D_SCLK_DIV]      = &mst_d_sclk_div.hw,
+       [AUD_CLKID_MST_E_SCLK_DIV]      = &mst_e_sclk_div.hw,
+       [AUD_CLKID_MST_F_SCLK_DIV]      = &mst_f_sclk_div.hw,
+       [AUD_CLKID_MST_A_SCLK_POST_EN]  = &mst_a_sclk_post_en.hw,
+       [AUD_CLKID_MST_B_SCLK_POST_EN]  = &mst_b_sclk_post_en.hw,
+       [AUD_CLKID_MST_C_SCLK_POST_EN]  = &mst_c_sclk_post_en.hw,
+       [AUD_CLKID_MST_D_SCLK_POST_EN]  = &mst_d_sclk_post_en.hw,
+       [AUD_CLKID_MST_E_SCLK_POST_EN]  = &mst_e_sclk_post_en.hw,
+       [AUD_CLKID_MST_F_SCLK_POST_EN]  = &mst_f_sclk_post_en.hw,
+       [AUD_CLKID_MST_A_SCLK]          = &mst_a_sclk.hw,
+       [AUD_CLKID_MST_B_SCLK]          = &mst_b_sclk.hw,
+       [AUD_CLKID_MST_C_SCLK]          = &mst_c_sclk.hw,
+       [AUD_CLKID_MST_D_SCLK]          = &mst_d_sclk.hw,
+       [AUD_CLKID_MST_E_SCLK]          = &mst_e_sclk.hw,
+       [AUD_CLKID_MST_F_SCLK]          = &mst_f_sclk.hw,
+       [AUD_CLKID_MST_A_LRCLK_DIV]     = &mst_a_lrclk_div.hw,
+       [AUD_CLKID_MST_B_LRCLK_DIV]     = &mst_b_lrclk_div.hw,
+       [AUD_CLKID_MST_C_LRCLK_DIV]     = &mst_c_lrclk_div.hw,
+       [AUD_CLKID_MST_D_LRCLK_DIV]     = &mst_d_lrclk_div.hw,
+       [AUD_CLKID_MST_E_LRCLK_DIV]     = &mst_e_lrclk_div.hw,
+       [AUD_CLKID_MST_F_LRCLK_DIV]     = &mst_f_lrclk_div.hw,
+       [AUD_CLKID_MST_A_LRCLK]         = &mst_a_lrclk.hw,
+       [AUD_CLKID_MST_B_LRCLK]         = &mst_b_lrclk.hw,
+       [AUD_CLKID_MST_C_LRCLK]         = &mst_c_lrclk.hw,
+       [AUD_CLKID_MST_D_LRCLK]         = &mst_d_lrclk.hw,
+       [AUD_CLKID_MST_E_LRCLK]         = &mst_e_lrclk.hw,
+       [AUD_CLKID_MST_F_LRCLK]         = &mst_f_lrclk.hw,
+       [AUD_CLKID_TDMIN_A_SCLK_SEL]    = &tdmin_a_sclk_sel.hw,
+       [AUD_CLKID_TDMIN_B_SCLK_SEL]    = &tdmin_b_sclk_sel.hw,
+       [AUD_CLKID_TDMIN_C_SCLK_SEL]    = &tdmin_c_sclk_sel.hw,
+       [AUD_CLKID_TDMIN_LB_SCLK_SEL]   = &tdmin_lb_sclk_sel.hw,
+       [AUD_CLKID_TDMOUT_A_SCLK_SEL]   = &tdmout_a_sclk_sel.hw,
+       [AUD_CLKID_TDMOUT_B_SCLK_SEL]   = &tdmout_b_sclk_sel.hw,
+       [AUD_CLKID_TDMOUT_C_SCLK_SEL]   = &tdmout_c_sclk_sel.hw,
+       [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
+       [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
+       [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
+       [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
+       [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
+       [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
+       [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
+       [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
+       [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
+       [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
+       [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
+       [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
+       [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
+       [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
+       [AUD_CLKID_TDMIN_A_SCLK]        = &tdmin_a_sclk.hw,
+       [AUD_CLKID_TDMIN_B_SCLK]        = &tdmin_b_sclk.hw,
+       [AUD_CLKID_TDMIN_C_SCLK]        = &tdmin_c_sclk.hw,
+       [AUD_CLKID_TDMIN_LB_SCLK]       = &tdmin_lb_sclk.hw,
+       [AUD_CLKID_TDMOUT_A_SCLK]       = &g12a_tdmout_a_sclk.hw,
+       [AUD_CLKID_TDMOUT_B_SCLK]       = &g12a_tdmout_b_sclk.hw,
+       [AUD_CLKID_TDMOUT_C_SCLK]       = &g12a_tdmout_c_sclk.hw,
+       [AUD_CLKID_TDMIN_A_LRCLK]       = &tdmin_a_lrclk.hw,
+       [AUD_CLKID_TDMIN_B_LRCLK]       = &tdmin_b_lrclk.hw,
+       [AUD_CLKID_TDMIN_C_LRCLK]       = &tdmin_c_lrclk.hw,
+       [AUD_CLKID_TDMIN_LB_LRCLK]      = &tdmin_lb_lrclk.hw,
+       [AUD_CLKID_TDMOUT_A_LRCLK]      = &tdmout_a_lrclk.hw,
+       [AUD_CLKID_TDMOUT_B_LRCLK]      = &tdmout_b_lrclk.hw,
+       [AUD_CLKID_TDMOUT_C_LRCLK]      = &tdmout_c_lrclk.hw,
+       [AUD_CLKID_TDM_MCLK_PAD0]       = &sm1_tdm_mclk_pad_0.hw,
+       [AUD_CLKID_TDM_MCLK_PAD1]       = &sm1_tdm_mclk_pad_1.hw,
+       [AUD_CLKID_TDM_LRCLK_PAD0]      = &sm1_tdm_lrclk_pad_0.hw,
+       [AUD_CLKID_TDM_LRCLK_PAD1]      = &sm1_tdm_lrclk_pad_1.hw,
+       [AUD_CLKID_TDM_LRCLK_PAD2]      = &sm1_tdm_lrclk_pad_2.hw,
+       [AUD_CLKID_TDM_SCLK_PAD0]       = &sm1_tdm_sclk_pad_0.hw,
+       [AUD_CLKID_TDM_SCLK_PAD1]       = &sm1_tdm_sclk_pad_1.hw,
+       [AUD_CLKID_TDM_SCLK_PAD2]       = &sm1_tdm_sclk_pad_2.hw,
+       [AUD_CLKID_TOP]                 = &sm1_aud_top.hw,
+       [AUD_CLKID_TORAM]               = &toram.hw,
+       [AUD_CLKID_EQDRC]               = &eqdrc.hw,
+       [AUD_CLKID_RESAMPLE_B]          = &resample_b.hw,
+       [AUD_CLKID_TOVAD]               = &tovad.hw,
+       [AUD_CLKID_LOCKER]              = &locker.hw,
+       [AUD_CLKID_SPDIFIN_LB]          = &spdifin_lb.hw,
+       [AUD_CLKID_FRDDR_D]             = &frddr_d.hw,
+       [AUD_CLKID_TODDR_D]             = &toddr_d.hw,
+       [AUD_CLKID_LOOPBACK_B]          = &loopback_b.hw,
+       [AUD_CLKID_CLK81_EN]            = &sm1_clk81_en.hw,
+       [AUD_CLKID_SYSCLK_A_DIV]        = &sm1_sysclk_a_div.hw,
+       [AUD_CLKID_SYSCLK_A_EN]         = &sm1_sysclk_a_en.hw,
+       [AUD_CLKID_SYSCLK_B_DIV]        = &sm1_sysclk_b_div.hw,
+       [AUD_CLKID_SYSCLK_B_EN]         = &sm1_sysclk_b_en.hw,
 };
 
 
@@ -1745,7 +1734,7 @@ static const struct regmap_config axg_audio_regmap_cfg = {
 struct audioclk_data {
        struct clk_regmap *const *regmap_clks;
        unsigned int regmap_clk_num;
-       struct clk_hw_onecell_data *hw_onecell_data;
+       struct meson_clk_hw_data hw_clks;
        unsigned int reset_offset;
        unsigned int reset_num;
 };
@@ -1791,10 +1780,10 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
                data->regmap_clks[i]->map = map;
 
        /* Take care to skip the registered input clocks */
-       for (i = AUD_CLKID_DDR_ARB; i < data->hw_onecell_data->num; i++) {
+       for (i = AUD_CLKID_DDR_ARB; i < data->hw_clks.num; i++) {
                const char *name;
 
-               hw = data->hw_onecell_data->hws[i];
+               hw = data->hw_clks.hws[i];
                /* array might be sparse */
                if (!hw)
                        continue;
@@ -1808,8 +1797,7 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
                }
        }
 
-       ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
-                                       data->hw_onecell_data);
+       ret = devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks);
        if (ret)
                return ret;
 
@@ -1834,13 +1822,19 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
 static const struct audioclk_data axg_audioclk_data = {
        .regmap_clks = axg_clk_regmaps,
        .regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
-       .hw_onecell_data = &axg_audio_hw_onecell_data,
+       .hw_clks = {
+               .hws = axg_audio_hw_clks,
+               .num = ARRAY_SIZE(axg_audio_hw_clks),
+       },
 };
 
 static const struct audioclk_data g12a_audioclk_data = {
        .regmap_clks = g12a_clk_regmaps,
        .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
-       .hw_onecell_data = &g12a_audio_hw_onecell_data,
+       .hw_clks = {
+               .hws = g12a_audio_hw_clks,
+               .num = ARRAY_SIZE(g12a_audio_hw_clks),
+       },
        .reset_offset = AUDIO_SW_RESET,
        .reset_num = 26,
 };
@@ -1848,7 +1842,10 @@ static const struct audioclk_data g12a_audioclk_data = {
 static const struct audioclk_data sm1_audioclk_data = {
        .regmap_clks = sm1_clk_regmaps,
        .regmap_clk_num = ARRAY_SIZE(sm1_clk_regmaps),
-       .hw_onecell_data = &sm1_audio_hw_onecell_data,
+       .hw_clks = {
+               .hws = sm1_audio_hw_clks,
+               .num = ARRAY_SIZE(sm1_audio_hw_clks),
+       },
        .reset_offset = AUDIO_SM1_SW_RESET0,
        .reset_num = 39,
 };

diff --git a/drivers/clk/meson/axg-audio.h b/drivers/clk/meson/axg-audio.h
index fd65a7d..d6ed27c 100644 (file)
--- a/drivers/clk/meson/axg-audio.h
+++ b/drivers/clk/meson/axg-audio.h
@@ -138,6 +138,4 @@
 /* include the CLKIDs which are part of the DT bindings */
 #include <dt-bindings/clock/axg-audio-clkc.h>
 
-#define NR_CLKS        178
-
 #endif /*__AXG_AUDIO_CLKC_H */