arm64: dts: renesas: rzg2l: Add clock-names and reset-names to DMAC nodes

Add clock-names and reset-names to RZ/G2{L,LC,UL}, RZ/V2L and
RZ/Five DMAC nodes.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230315064726.22739-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index a970065..27c35a6 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -564,9 +564,11 @@
                                          "ch12", "ch13", "ch14", "ch15";
                        clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>,
                                 <&cpg CPG_MOD R9A07G043_DMAC_PCLK>;
+                       clock-names = "main", "register";
                        power-domains = <&cpg>;
                        resets = <&cpg R9A07G043_DMAC_ARESETN>,
                                 <&cpg R9A07G043_DMAC_RST_ASYNC>;
+                       reset-names = "arst", "rst_async";
                        #dma-cells = <1>;
                        dma-channels = <16>;
                };

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 79cffbf..7b68bbe 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -740,9 +740,11 @@
                                          "ch12", "ch13", "ch14", "ch15";
                        clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
                                 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
+                       clock-names = "main", "register";
                        power-domains = <&cpg>;
                        resets = <&cpg R9A07G044_DMAC_ARESETN>,
                                 <&cpg R9A07G044_DMAC_RST_ASYNC>;
+                       reset-names = "arst", "rst_async";
                        #dma-cells = <1>;
                        dma-channels = <16>;
                };

diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index c0ae9c7..cc11e58 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -746,9 +746,11 @@
                                          "ch12", "ch13", "ch14", "ch15";
                        clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>,
                                 <&cpg CPG_MOD R9A07G054_DMAC_PCLK>;
+                       clock-names = "main", "register";
                        power-domains = <&cpg>;
                        resets = <&cpg R9A07G054_DMAC_ARESETN>,
                                 <&cpg R9A07G054_DMAC_RST_ASYNC>;
+                       reset-names = "arst", "rst_async";
                        #dma-cells = <1>;
                        dma-channels = <16>;
                };