int intel_scu_ipc_read_mip(u8 *data, int len, int offset, int issigned);
int intel_scu_ipc_write_umip(u8 *data, int len, int offset);
-/* Penwell has 4 osc clocks */
-#define OSC_CLK_AUDIO 0 /* Audio */
-#define OSC_CLK_CAM0 1 /* Primary camera */
-#define OSC_CLK_CAM1 2 /* Secondary camera */
-#define OSC_CLK_DISP 3 /* Display buffer */
-
-int intel_scu_ipc_osc_clk(u8 clk, unsigned int khz);
-
-enum clk0_mode {
- CLK0_AUDIENCE = 0x4,
- CLK0_VIBRA1 = 0x8,
- CLK0_VIBRA2 = 0x10,
- CLK0_MSIC = 0x20,
- CLK0_QUERY = 0x1000,
-};
-
-int intel_scu_ipc_set_osc_clk0(unsigned int enable, enum clk0_mode mode);
-
extern struct blocking_notifier_head intel_scu_notifier;
static inline void intel_scu_notifier_add(struct notifier_block *nb)
#define SCU_AVAILABLE 1
#define SCU_DOWN 2
-#define MSIC_VPROG1_CTRL 0xD6
-#define MSIC_VPROG2_CTRL 0xD7
-#define MSIC_VPROG_ON 0xFF
-#define MSIC_VPROG_OFF 0
-
-/* Helpers to turn on/off msic vprog1 and vprog2 */
-static inline int intel_scu_ipc_msic_vprog1(int on)
-{
- return intel_scu_ipc_iowrite8(MSIC_VPROG1_CTRL,
- on ? MSIC_VPROG_ON : MSIC_VPROG_OFF);
-}
-
-static inline int intel_scu_ipc_msic_vprog2(int on)
-{
- return intel_scu_ipc_iowrite8(MSIC_VPROG2_CTRL,
- on ? MSIC_VPROG_ON : MSIC_VPROG_OFF);
-}
-
#endif
#ifndef _ASM_X86_INTEL_SCU_IPCUTIL_H_
-#define _ASM_X86_INTEL_SCU_IPCUTIL_H_
+#define _ASM_X86_INTEL_SCU_IPCUTIL_H_
+
+/* Penwell has 4 osc clocks */
+#define OSC_CLK_AUDIO 0 /* Audio */
+#define OSC_CLK_CAM0 1 /* Primary camera */
+#define OSC_CLK_CAM1 2 /* Secondary camera */
+#define OSC_CLK_DISP 3 /* Display buffer */
+
+int intel_scu_ipc_osc_clk(u8 clk, unsigned int khz);
+
+enum clk0_mode {
+ CLK0_AUDIENCE = 0x4,
+ CLK0_VIBRA1 = 0x8,
+ CLK0_VIBRA2 = 0x10,
+ CLK0_MSIC = 0x20,
+ CLK0_QUERY = 0x1000,
+};
+
+int intel_scu_ipc_set_osc_clk0(unsigned int enable, enum clk0_mode mode);
+
+/* Helpers to turn on/off msic vprog1 and vprog2 */
+int intel_scu_ipc_msic_vprog1(int on);
+int intel_scu_ipc_msic_vprog2(int on);
/* OSHOB-OS Handoff Buffer read */
int intel_scu_ipc_read_oshob(u8 *data, int len, int offset);
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/atomisp_platform.h>
-#include <asm/intel_scu_ipc.h>
+#include <asm/intel_scu_ipcutil.h>
#include <asm/intel-mid.h>
#include <media/v4l2-subdev.h>
#include "platform_camera.h"
#include <linux/delay.h>
#include <linux/atomisp_platform.h>
#include <asm/intel-mid.h>
-#include <asm/intel_scu_ipc.h>
+#include <asm/intel_scu_ipcutil.h>
#include <media/v4l2-subdev.h>
#include "platform_camera.h"
#include "platform_mt9m114.h"
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/atomisp_platform.h>
-#include <asm/intel_scu_ipc.h>
+#include <asm/intel_scu_ipcutil.h>
#include <asm/intel-mid.h>
#include <media/v4l2-subdev.h>
#include "platform_camera.h"
#include <linux/uaccess.h>
#include <linux/delay.h>
#include <linux/firmware.h>
-#include <asm/intel_scu_ipc.h>
+#include <asm/intel_scu_ipcutil.h>
#include <linux/a1026.h>
#include <linux/i2c.h>
*
* (C) Copyright 2008-2010 Intel Corporation
* Author: Sreedhara DS (sreedhara.ds@intel.com)
- * (C) Copyright 2010 Intel Corporation
+ * (C) Copyright 2010-2012 Intel Corporation
* Author: Sudha Krishnakumar (sudha.krishnakumar@intel.com)
*
* This program is free software; you can redistribute it and/or
* IPC-1 Driver provides an API for power control unit registers (e.g. MSIC)
* along with other APIs.
*/
+
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/init.h>
/* PM Qos struct */
static struct pm_qos_request_list *qos;
-/* Mode for Audio clock */
-static DEFINE_MUTEX(osc_clk0_lock);
-static unsigned int osc_clk0_mode;
-
/*
* Command Register (Write Only):
* A write to this register results in an interrupt to the SCU core processor
sysfs_remove_group(&dev->dev.kobj, &intel_scu_ipc_attr_group);
}
-int intel_scu_ipc_osc_clk(u8 clk, unsigned int khz)
-{
- /* SCU IPC COMMAND(osc clk on/off) definition:
- * ipc_wbuf[0] = clock to act on {0, 1, 2, 3}
- * ipc_wbuf[1] =
- * bit 0 - 1:on 0:off
- * bit 1 - if 1, read divider setting from bits 3:2 as follows:
- * bit [3:2] - 00: clk/1, 01: clk/2, 10: clk/4, 11: reserved
- */
- unsigned int base_freq;
- unsigned int div;
- u8 ipc_wbuf[16];
- int ipc_ret;
-
- if (clk > 3)
- return -EINVAL;
-
- ipc_wbuf[0] = clk;
- ipc_wbuf[1] = 0;
- if (khz) {
-#ifdef CONFIG_CTP_CRYSTAL_38M4
- base_freq = 38400;
-#else
- base_freq = 19200;
-#endif
- div = fls(base_freq / khz) - 1;
- if (div >= 3 || (1 << div) * khz != base_freq)
- return -EINVAL; /* Allow only exact frequencies */
- ipc_wbuf[1] = 0x03 | (div << 2);
- }
-
- ipc_ret = intel_scu_ipc_command(IPCMSG_OSC_CLK, 0,
- (u32 *)ipc_wbuf, 2, NULL, 0);
- if (ipc_ret != 0)
- pr_err("%s: failed to set osc clk(%d) output\n", __func__, clk);
-
- return ipc_ret;
-}
-EXPORT_SYMBOL_GPL(intel_scu_ipc_osc_clk);
-
-/*
- * OSC_CLK_AUDIO is connected to the MSIC as well as Audience, so it should be
- * turned on if any one of them requests it to be on and it should be turned off
- * only if no one needs it on.
- */
-int intel_scu_ipc_set_osc_clk0(unsigned int enable, enum clk0_mode mode)
-{
- int ret = 0, clk_enable;
- static const unsigned int clk_khz = 19200;
-
- pr_debug("set_clk0 request %s for Mode 0x%x\n",
- enable ? "ON" : "OFF", mode);
- mutex_lock(&osc_clk0_lock);
- if (mode == CLK0_QUERY) {
- ret = osc_clk0_mode;
- goto out;
- }
- if (enable) {
- /* if clock is already on, just add new user */
- if (osc_clk0_mode) {
- osc_clk0_mode |= mode;
- goto out;
- }
- osc_clk0_mode |= mode;
- pr_debug("set_clk0: enabling clk, mode 0x%x\n", osc_clk0_mode);
- clk_enable = 1;
- } else {
- osc_clk0_mode &= ~mode;
- pr_debug("set_clk0: disabling clk, mode 0x%x\n", osc_clk0_mode);
- /* others using the clock, cannot turn it of */
- if (osc_clk0_mode)
- goto out;
- clk_enable = 0;
- }
- pr_debug("configuring OSC_CLK_AUDIO now\n");
- ret = intel_scu_ipc_osc_clk(OSC_CLK_AUDIO, clk_enable ? clk_khz : 0);
-out:
- mutex_unlock(&osc_clk0_lock);
- return ret;
-}
-EXPORT_SYMBOL_GPL(intel_scu_ipc_set_osc_clk0);
-
/*
* Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1
* When ioc bit is set to 1, caller api must wait for interrupt handler called
unsigned int khz; /* clock frequency */
};
+/* Mode for Audio clock */
+static DEFINE_MUTEX(osc_clk0_lock);
+static unsigned int osc_clk0_mode;
+
+int intel_scu_ipc_osc_clk(u8 clk, unsigned int khz)
+{
+ /* SCU IPC COMMAND(osc clk on/off) definition:
+ * ipc_wbuf[0] = clock to act on {0, 1, 2, 3}
+ * ipc_wbuf[1] =
+ * bit 0 - 1:on 0:off
+ * bit 1 - if 1, read divider setting from bits 3:2 as follows:
+ * bit [3:2] - 00: clk/1, 01: clk/2, 10: clk/4, 11: reserved
+ */
+ unsigned int base_freq;
+ unsigned int div;
+ u8 ipc_wbuf[16];
+ int ipc_ret;
+
+ if (clk > 3)
+ return -EINVAL;
+
+ ipc_wbuf[0] = clk;
+ ipc_wbuf[1] = 0;
+ if (khz) {
+#ifdef CONFIG_CTP_CRYSTAL_38M4
+ base_freq = 38400;
+#else
+ base_freq = 19200;
+#endif
+ div = fls(base_freq / khz) - 1;
+ if (div >= 3 || (1 << div) * khz != base_freq)
+ return -EINVAL; /* Allow only exact frequencies */
+ ipc_wbuf[1] = 0x03 | (div << 2);
+ }
+
+ ipc_ret = intel_scu_ipc_command(IPCMSG_OSC_CLK, 0,
+ (u32 *)ipc_wbuf, 2, NULL, 0);
+ if (ipc_ret != 0)
+ pr_err("%s: failed to set osc clk(%d) output\n", __func__, clk);
+
+ return ipc_ret;
+}
+EXPORT_SYMBOL_GPL(intel_scu_ipc_osc_clk);
+
+/*
+ * OSC_CLK_AUDIO is connected to the MSIC as well as Audience, so it should be
+ * turned on if any one of them requests it to be on and it should be turned off
+ * only if no one needs it on.
+ */
+int intel_scu_ipc_set_osc_clk0(unsigned int enable, enum clk0_mode mode)
+{
+ int ret = 0, clk_enable;
+ static const unsigned int clk_khz = 19200;
+
+ pr_debug("set_clk0 request %s for Mode 0x%x\n",
+ enable ? "ON" : "OFF", mode);
+ mutex_lock(&osc_clk0_lock);
+ if (mode == CLK0_QUERY) {
+ ret = osc_clk0_mode;
+ goto out;
+ }
+ if (enable) {
+ /* if clock is already on, just add new user */
+ if (osc_clk0_mode) {
+ osc_clk0_mode |= mode;
+ goto out;
+ }
+ osc_clk0_mode |= mode;
+ pr_debug("set_clk0: enabling clk, mode 0x%x\n", osc_clk0_mode);
+ clk_enable = 1;
+ } else {
+ osc_clk0_mode &= ~mode;
+ pr_debug("set_clk0: disabling clk, mode 0x%x\n", osc_clk0_mode);
+ /* others using the clock, cannot turn it of */
+ if (osc_clk0_mode)
+ goto out;
+ clk_enable = 0;
+ }
+ pr_debug("configuring OSC_CLK_AUDIO now\n");
+ ret = intel_scu_ipc_osc_clk(OSC_CLK_AUDIO, clk_enable ? clk_khz : 0);
+out:
+ mutex_unlock(&osc_clk0_lock);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(intel_scu_ipc_set_osc_clk0);
+
+#define MSIC_VPROG1_CTRL 0xD6
+#define MSIC_VPROG2_CTRL 0xD7
+#define MSIC_VPROG_ON 0xFF
+#define MSIC_VPROG_OFF 0
+
+int intel_scu_ipc_msic_vprog1(int on)
+{
+ return intel_scu_ipc_iowrite8(MSIC_VPROG1_CTRL,
+ on ? MSIC_VPROG_ON : MSIC_VPROG_OFF);
+}
+EXPORT_SYMBOL_GPL(intel_scu_ipc_msic_vprog1);
+
+int intel_scu_ipc_msic_vprog2(int on)
+{
+ return intel_scu_ipc_iowrite8(MSIC_VPROG2_CTRL,
+ on ? MSIC_VPROG_ON : MSIC_VPROG_OFF);
+}
+EXPORT_SYMBOL_GPL(intel_scu_ipc_msic_vprog2);
+
/**
* scu_reg_access - implement register access ioctls
* @cmd: command we are doing (read/write/update)
misc_deregister(&scu_ipcutil);
}
-module_init(ipc_module_init);
+rootfs_initcall(ipc_module_init);
module_exit(ipc_module_exit);
MODULE_LICENSE("GPL v2");
#include <linux/delay.h>
#include <linux/ipc_device.h>
#include <asm/intel_scu_ipc.h>
+#include <asm/intel_scu_ipcutil.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <linux/gpio.h>
#include <linux/ipc_device.h>
#include <asm/intel-mid.h>
-#include <asm/intel_scu_ipc.h>
+#include <asm/intel_scu_ipcutil.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <linux/gpio.h>
#include <linux/ipc_device.h>
#include <asm/intel-mid.h>
-#include <asm/intel_scu_ipc.h>
+#include <asm/intel_scu_ipcutil.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
projects / kernel / kernel-mfld-blackbay.git / commitdiff