Operand(desc_ptr));
}
- bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), index);
+ Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
+ std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
+ elems[0] = index;
+ ctx->allocated_vec.emplace(dst.id(), elems);
+ bld.pseudo(aco_opcode::p_create_vector, Definition(dst), index,
+ Operand((unsigned)ctx->options->address32_hi));
}
void load_buffer(isel_context *ctx, unsigned num_components, unsigned component_size,
Builder bld(ctx->program, ctx->block);
- nir_intrinsic_instr* idx_instr = nir_instr_as_intrinsic(instr->src[0].ssa->parent_instr);
+ nir_alu_instr* mov_instr = nir_instr_as_alu(instr->src[0].ssa->parent_instr);
+ nir_intrinsic_instr* idx_instr = nir_instr_as_intrinsic(mov_instr->src[0].src.ssa->parent_instr);
unsigned desc_set = nir_intrinsic_desc_set(idx_instr);
unsigned binding = nir_intrinsic_binding(idx_instr);
radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
nir_intrinsic_vulkan_resource_index);
rsrc->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
- rsrc->num_components = 1;
+ rsrc->num_components = 2;
nir_intrinsic_set_desc_set(rsrc, desc_set);
nir_intrinsic_set_binding(rsrc, binding);
nir_ssa_dest_init(&rsrc->instr, &rsrc->dest, rsrc->num_components, 32, NULL);
nir_builder_instr_insert(b, &rsrc->instr);
- return &rsrc->dest.ssa;
+ return nir_channel(b, &rsrc->dest.ssa, 0);
}
0, 0, "radv", message);
}
+static bool
+lower_load_vulkan_descriptor(nir_shader *nir)
+{
+ nir_function_impl *entry = nir_shader_get_entrypoint(nir);
+ bool progress = false;
+ nir_builder b;
+
+ nir_builder_init(&b, entry);
+
+ nir_foreach_block(block, entry) {
+ nir_foreach_instr_safe(instr, block) {
+ if (instr->type != nir_instr_type_intrinsic)
+ continue;
+
+ nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
+ if (intrin->intrinsic != nir_intrinsic_load_vulkan_descriptor)
+ continue;
+
+ b.cursor = nir_before_instr(&intrin->instr);
+
+ nir_ssa_def *def = nir_vec2(&b,
+ nir_channel(&b, intrin->src[0].ssa, 0),
+ nir_imm_int(&b, 0));
+ nir_ssa_def_rewrite_uses(&intrin->dest.ssa,
+ nir_src_for_ssa(def));
+
+ nir_instr_remove(instr);
+ progress = true;
+ }
+ }
+
+ return progress;
+}
+
nir_shader *
radv_shader_compile_to_nir(struct radv_device *device,
struct radv_shader_module *module,
.module = module,
};
const struct spirv_to_nir_options spirv_options = {
- .lower_ubo_ssbo_access_to_offsets = true,
.caps = {
.amd_fragment_mask = true,
.amd_gcn_shader = true,
*/
nir_lower_var_copies(nir);
+ NIR_PASS_V(nir, nir_lower_explicit_io,
+ nir_var_mem_ubo | nir_var_mem_ssbo,
+ nir_address_format_32bit_index_offset);
+
+ NIR_PASS_V(nir, lower_load_vulkan_descriptor);
+
/* Lower deref operations for compute shared memory. */
if (nir->info.stage == MESA_SHADER_COMPUTE) {
NIR_PASS_V(nir, nir_lower_vars_to_explicit_types,