dev_priv->gart_size);
RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_18, 0x1000);
- RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_38, 0x1);
+ RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, 0x1);
RADEON_WRITE_IGPGART(RADEON_IGPGART_CTRL, 0x42040800);
RADEON_WRITE_IGPGART(RADEON_IGPGART_BASE_ADDR,
dev_priv->gart_info.bus_addr);
dev_priv->gart_size) & 0xffff0000) |
(dev_priv->gart_vm_start >> 16)));
- temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_38);
- RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_38, temp);
+ temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_ENABLE);
+ RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, temp);
- RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_2E);
- RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_2E, 0x1);
- RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_2E);
- RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_2E, 0x0);
+ RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
+ RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x1);
+ RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
+ RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x0);
}
}
#define RADEON_IGPGART_UNK_18 0x18
#define RADEON_IGPGART_CTRL 0x2b
#define RADEON_IGPGART_BASE_ADDR 0x2c
-#define RADEON_IGPGART_UNK_2E 0x2e
-#define RADEON_IGPGART_UNK_38 0x38
+#define RADEON_IGPGART_FLUSH 0x2e
+#define RADEON_IGPGART_ENABLE 0x38
#define RADEON_IGPGART_UNK_39 0x39