firmware: Add a barrier instruction for wait for boot hart

Multi-core communication via memory requires the addition of a barrier
instructions to ensure cache coherency.

Signed-off-by: Xiang Wang <wxjstz@126.com>

diff --git a/firmware/fw_base.S b/firmware/fw_base.S
index b28cfb5..ae14cc7 100644 (file)
--- a/firmware/fw_base.S
+++ b/firmware/fw_base.S
@@ -114,6 +114,7 @@ _fdt_reloc_done:
 
        /* Wait for boot hart */
 _wait_for_boot_hart:
+       fence   rw, rw
        la      a4, _boot_hart_done
        REG_L   a5, (a4)
        beqz    a5, _wait_for_boot_hart