radeonsi: don't bind the ESGS ring twice, handle the difference in the shader

The other shader is changed to modify the descriptor to get the required
values.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14266>

diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm_gs.c b/src/gallium/drivers/radeonsi/si_shader_llvm_gs.c
index 57c2c81..44ac3a5 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader_llvm_gs.c
+++ b/src/gallium/drivers/radeonsi/si_shader_llvm_gs.c
@@ -312,12 +312,28 @@ static void si_llvm_emit_primitive(struct ac_shader_abi *abi, unsigned stream)
 
 void si_preload_esgs_ring(struct si_shader_context *ctx)
 {
+   LLVMBuilderRef builder = ctx->ac.builder;
+
    if (ctx->screen->info.chip_class <= GFX8) {
-      unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? SI_GS_RING_ESGS : SI_ES_RING_ESGS;
-      LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, 0);
+      LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, SI_RING_ESGS, 0);
       LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->internal_bindings);
 
       ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
+
+      if (ctx->stage != MESA_SHADER_GEOMETRY) {
+         LLVMValueRef desc1 = LLVMBuildExtractElement(builder, ctx->esgs_ring, ctx->ac.i32_1, "");
+         LLVMValueRef desc3 = LLVMBuildExtractElement(builder, ctx->esgs_ring,
+                                                      LLVMConstInt(ctx->ac.i32, 3, 0), "");
+         desc1 = LLVMBuildOr(builder, desc1, LLVMConstInt(ctx->ac.i32,
+                                                          S_008F04_SWIZZLE_ENABLE(1), 0), "");
+         desc3 = LLVMBuildOr(builder, desc3, LLVMConstInt(ctx->ac.i32,
+                                                          S_008F0C_ELEMENT_SIZE(1) |
+                                                          S_008F0C_INDEX_STRIDE(3) |
+                                                          S_008F0C_ADD_TID_ENABLE(1), 0), "");
+         ctx->esgs_ring = LLVMBuildInsertElement(builder, ctx->esgs_ring, desc1, ctx->ac.i32_1, "");
+         ctx->esgs_ring = LLVMBuildInsertElement(builder, ctx->esgs_ring, desc3,
+                                                 LLVMConstInt(ctx->ac.i32, 3, 0), "");
+      }
    } else {
       if (USE_LDS_SYMBOLS) {
          /* Declare the ESGS ring as an explicit LDS symbol. */

diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index d5db567..3298db4 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -372,14 +372,13 @@ enum
    SI_PS_CONST_POLY_STIPPLE,
    SI_PS_CONST_SAMPLE_POSITIONS,
 
-   SI_ES_RING_ESGS,                    /* gfx6-8 */
-   SI_GS_RING_ESGS,                    /* gfx6-8 */
+   SI_RING_ESGS,                       /* gfx6-8 */
    SI_RING_GSVS,
 
    SI_NUM_INTERNAL_BINDINGS,
 
    /* Aliases to reuse slots that are unused on other generations. */
-   SI_GS_QUERY_BUF = SI_ES_RING_ESGS,  /* gfx10+ */
+   SI_GS_QUERY_BUF = SI_RING_ESGS,     /* gfx10+ */
 };
 
 /* Indices into sctx->descriptors, laid out so that gfx and compute pipelines

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.cpp b/src/gallium/drivers/radeonsi/si_state_shaders.cpp
index 9b4d650..8890ed1 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_shaders.cpp
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.cpp
@@ -3824,9 +3824,7 @@ bool si_update_gs_ring_buffers(struct si_context *sctx)
    /* Set ring bindings. */
    if (sctx->esgs_ring) {
       assert(sctx->chip_class <= GFX8);
-      si_set_ring_buffer(sctx, SI_ES_RING_ESGS, sctx->esgs_ring, 0, sctx->esgs_ring->width0, true,
-                         true, 4, 64, 0);
-      si_set_ring_buffer(sctx, SI_GS_RING_ESGS, sctx->esgs_ring, 0, sctx->esgs_ring->width0, false,
+      si_set_ring_buffer(sctx, SI_RING_ESGS, sctx->esgs_ring, 0, sctx->esgs_ring->width0, false,
                          false, 0, 0, 0);
    }
    if (sctx->gsvs_ring) {