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clk: zynqmp: Limit bestdiv with maxdiv
author
Rajan Vaja
<rajan.vaja@xilinx.com>
Mon, 2 Mar 2020 21:50:40 +0000
(13:50 -0800)
committer
Stephen Boyd
<sboyd@kernel.org>
Wed, 27 May 2020 00:58:59 +0000
(17:58 -0700)
Clock divider value should not be greater than maximum divider value.
So use minimum of best divider or maximum divider value.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Link:
https://lkml.kernel.org/r/1583185843-20707-2-git-send-email-jolly.shah@xilinx.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/zynqmp/divider.c
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diff --git
a/drivers/clk/zynqmp/divider.c
b/drivers/clk/zynqmp/divider.c
index
4be2cc7
..
5c41ddb
100644
(file)
--- a/
drivers/clk/zynqmp/divider.c
+++ b/
drivers/clk/zynqmp/divider.c
@@
-197,6
+197,8
@@
static long zynqmp_clk_divider_round_rate(struct clk_hw *hw,
if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac)
bestdiv = rate % *prate ? 1 : bestdiv;
+
+ bestdiv = min_t(u32, bestdiv, divider->max_div);
*prate = rate * bestdiv;
return rate;