* ira-int.h (target_ira_int): Add x_ira_useful_class_mode_regs.
(ira_useful_class_mode_regs): New macro.
* ira.c (clarify_prohibited_class_mode_regs): Set up
ira_useful_class_mode_regs.
* ira-color.c (setup_profitable_hard_regs): Use it to initialise
profitable_hard_regs.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@191996
138bc75d-0d04-0410-961f-
82ee72b054a4
2012-10-02 Richard Sandiford <rdsandiford@googlemail.com>
+ * ira-int.h (target_ira_int): Add x_ira_useful_class_mode_regs.
+ (ira_useful_class_mode_regs): New macro.
+ * ira.c (clarify_prohibited_class_mode_regs): Set up
+ ira_useful_class_mode_regs.
+ * ira-color.c (setup_profitable_hard_regs): Use it to initialise
+ profitable_hard_regs.
+
+2012-10-02 Richard Sandiford <rdsandiford@googlemail.com>
+
* ira.h (target_ira): Add x_ira_class_singleton.
(ira_class_singleton): New macro.
* ira.c (setup_prohibited_class_mode_regs): Set up ira_class_singleton.
CLEAR_HARD_REG_SET (data->profitable_hard_regs);
else
{
+ mode = ALLOCNO_MODE (a);
COPY_HARD_REG_SET (data->profitable_hard_regs,
- reg_class_contents[aclass]);
- AND_COMPL_HARD_REG_SET (data->profitable_hard_regs,
- ira_no_alloc_regs);
+ ira_useful_class_mode_regs[aclass][mode]);
nobj = ALLOCNO_NUM_OBJECTS (a);
for (k = 0; k < nobj; k++)
{
values for given mode are zero. */
HARD_REG_SET x_ira_prohibited_class_mode_regs[N_REG_CLASSES][NUM_MACHINE_MODES];
+ /* Index [CL][M] contains R if R appears somewhere in a register of the form:
+
+ (reg:M R'), R' not in x_ira_prohibited_class_mode_regs[CL][M]
+
+ For example, if:
+
+ - (reg:M 2) is valid and occupies two registers;
+ - register 2 belongs to CL; and
+ - register 3 belongs to the same pressure class as CL
+
+ then (reg:M 2) contributes to [CL][M] and registers 2 and 3 will be
+ in the set. */
+ HARD_REG_SET x_ira_useful_class_mode_regs[N_REG_CLASSES][NUM_MACHINE_MODES];
+
/* The value is number of elements in the subsequent array. */
int x_ira_important_classes_num;
(this_target_ira_int->x_ira_class_hard_reg_index)
#define ira_prohibited_class_mode_regs \
(this_target_ira_int->x_ira_prohibited_class_mode_regs)
+#define ira_useful_class_mode_regs \
+ (this_target_ira_int->x_ira_useful_class_mode_regs)
#define ira_important_classes_num \
(this_target_ira_int->x_ira_important_classes_num)
#define ira_important_classes \
for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
for (j = 0; j < NUM_MACHINE_MODES; j++)
- for (k = ira_class_hard_regs_num[cl] - 1; k >= 0; k--)
- {
- hard_regno = ira_class_hard_regs[cl][k];
- if (TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], hard_regno))
- continue;
- nregs = hard_regno_nregs[hard_regno][j];
- if (hard_regno + nregs > FIRST_PSEUDO_REGISTER)
- {
- SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j],
- hard_regno);
- continue;
- }
- pclass = ira_pressure_class_translate[REGNO_REG_CLASS (hard_regno)];
- for (nregs-- ;nregs >= 0; nregs--)
- if (((enum reg_class) pclass
- != ira_pressure_class_translate[REGNO_REG_CLASS
- (hard_regno + nregs)]))
+ {
+ CLEAR_HARD_REG_SET (ira_useful_class_mode_regs[cl][j]);
+ for (k = ira_class_hard_regs_num[cl] - 1; k >= 0; k--)
+ {
+ hard_regno = ira_class_hard_regs[cl][k];
+ if (TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], hard_regno))
+ continue;
+ nregs = hard_regno_nregs[hard_regno][j];
+ if (hard_regno + nregs > FIRST_PSEUDO_REGISTER)
{
SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j],
hard_regno);
- break;
+ continue;
}
- }
+ pclass = ira_pressure_class_translate[REGNO_REG_CLASS (hard_regno)];
+ for (nregs-- ;nregs >= 0; nregs--)
+ if (((enum reg_class) pclass
+ != ira_pressure_class_translate[REGNO_REG_CLASS
+ (hard_regno + nregs)]))
+ {
+ SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j],
+ hard_regno);
+ break;
+ }
+ if (!TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j],
+ hard_regno))
+ add_to_hard_reg_set (&ira_useful_class_mode_regs[cl][j],
+ (enum machine_mode) j, hard_regno);
+ }
+ }
}
\f
/* Allocate and initialize IRA_REGISTER_MOVE_COST, IRA_MAY_MOVE_IN_COST