MIPS: Unify naming style of vendor CP0.Config6 bits

Other vendor-defined registers use the vendor name as a prefix, not an
infix, so unify the naming style of CP0.Config6 bits.

Suggested-by: Maciej W. Rozycki" <macro@linux-mips.org>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Reviewed-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 20d6d40..11094d8 100644 (file)
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -689,35 +689,35 @@
 /* Config6 feature bits for proAptiv/P5600 */
 
 /* Jump register cache prediction disable */
-#define MIPS_CONF6_MTI_JRCD            (_ULCAST_(1) << 0)
+#define MTI_CONF6_JRCD         (_ULCAST_(1) << 0)
 /* MIPSr6 extensions enable */
-#define MIPS_CONF6_MTI_R6              (_ULCAST_(1) << 2)
+#define MTI_CONF6_R6           (_ULCAST_(1) << 2)
 /* IFU Performance Control */
-#define MIPS_CONF6_MTI_IFUPERFCTL      (_ULCAST_(3) << 10)
-#define MIPS_CONF6_MTI_SYND            (_ULCAST_(1) << 13)
+#define MTI_CONF6_IFUPERFCTL   (_ULCAST_(3) << 10)
+#define MTI_CONF6_SYND         (_ULCAST_(1) << 13)
 /* Sleep state performance counter disable */
-#define MIPS_CONF6_MTI_SPCD            (_ULCAST_(1) << 14)
+#define MTI_CONF6_SPCD         (_ULCAST_(1) << 14)
 /* proAptiv FTLB on/off bit */
-#define MIPS_CONF6_MTI_FTLBEN          (_ULCAST_(1) << 15)
+#define MTI_CONF6_FTLBEN       (_ULCAST_(1) << 15)
 /* Disable load/store bonding */
-#define MIPS_CONF6_MTI_DLSB            (_ULCAST_(1) << 21)
+#define MTI_CONF6_DLSB         (_ULCAST_(1) << 21)
 /* FTLB probability bits */
-#define MIPS_CONF6_MTI_FTLBP_SHIFT     (16)
+#define MTI_CONF6_FTLBP_SHIFT  (16)
 
 /* Config6 feature bits for Loongson-3 */
 
 /* Loongson-3 internal timer bit */
-#define MIPS_CONF6_LOONGSON_INTIMER    (_ULCAST_(1) << 6)
+#define LOONGSON_CONF6_INTIMER (_ULCAST_(1) << 6)
 /* Loongson-3 external timer bit */
-#define MIPS_CONF6_LOONGSON_EXTIMER    (_ULCAST_(1) << 7)
+#define LOONGSON_CONF6_EXTIMER (_ULCAST_(1) << 7)
 /* Loongson-3 SFB on/off bit, STFill in manual */
-#define MIPS_CONF6_LOONGSON_SFBEN      (_ULCAST_(1) << 8)
+#define LOONGSON_CONF6_SFBEN   (_ULCAST_(1) << 8)
 /* Loongson-3's LL on exclusive cacheline */
-#define MIPS_CONF6_LOONGSON_LLEXC      (_ULCAST_(1) << 16)
+#define LOONGSON_CONF6_LLEXC   (_ULCAST_(1) << 16)
 /* Loongson-3's SC has a random delay */
-#define MIPS_CONF6_LOONGSON_SCRAND     (_ULCAST_(1) << 17)
+#define LOONGSON_CONF6_SCRAND  (_ULCAST_(1) << 17)
 /* Loongson-3 FTLB on/off bit, VTLBOnly in manual */
-#define MIPS_CONF6_LOONGSON_FTLBDIS    (_ULCAST_(1) << 22)
+#define LOONGSON_CONF6_FTLBDIS (_ULCAST_(1) << 22)
 
 #define MIPS_CONF7_WII         (_ULCAST_(1) << 31)
 

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index def1659..c231c1b 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -635,14 +635,14 @@ static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
                config = read_c0_config6();
 
                if (flags & FTLB_EN)
-                       config |= MIPS_CONF6_MTI_FTLBEN;
+                       config |= MTI_CONF6_FTLBEN;
                else
-                       config &= ~MIPS_CONF6_MTI_FTLBEN;
+                       config &= ~MTI_CONF6_FTLBEN;
 
                if (flags & FTLB_SET_PROB) {
-                       config &= ~(3 << MIPS_CONF6_MTI_FTLBP_SHIFT);
+                       config &= ~(3 << MTI_CONF6_FTLBP_SHIFT);
                        config |= calculate_ftlb_probability(c)
-                                 << MIPS_CONF6_MTI_FTLBP_SHIFT;
+                                 << MTI_CONF6_FTLBP_SHIFT;
                }
 
                write_c0_config6(config);
@@ -662,10 +662,10 @@ static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
                config = read_c0_config6();
                if (flags & FTLB_EN)
                        /* Enable FTLB */
-                       write_c0_config6(config & ~MIPS_CONF6_LOONGSON_FTLBDIS);
+                       write_c0_config6(config & ~LOONGSON_CONF6_FTLBDIS);
                else
                        /* Disable FTLB */
-                       write_c0_config6(config | MIPS_CONF6_LOONGSON_FTLBDIS);
+                       write_c0_config6(config | LOONGSON_CONF6_FTLBDIS);
                break;
        default:
                return 1;

diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c
index d9c462c..9d03bd0 100644 (file)
--- a/arch/mips/kvm/vz.c
+++ b/arch/mips/kvm/vz.c
@@ -129,7 +129,7 @@ static inline unsigned int kvm_vz_config5_guest_wrmask(struct kvm_vcpu *vcpu)
 
 static inline unsigned int kvm_vz_config6_guest_wrmask(struct kvm_vcpu *vcpu)
 {
-       return MIPS_CONF6_LOONGSON_INTIMER | MIPS_CONF6_LOONGSON_EXTIMER;
+       return LOONGSON_CONF6_INTIMER | LOONGSON_CONF6_EXTIMER;
 }
 
 /*
@@ -189,7 +189,7 @@ static inline unsigned int kvm_vz_config5_user_wrmask(struct kvm_vcpu *vcpu)
 static inline unsigned int kvm_vz_config6_user_wrmask(struct kvm_vcpu *vcpu)
 {
        return kvm_vz_config6_guest_wrmask(vcpu) |
-               MIPS_CONF6_LOONGSON_SFBEN | MIPS_CONF6_LOONGSON_FTLBDIS;
+               LOONGSON_CONF6_SFBEN | LOONGSON_CONF6_FTLBDIS;
 }
 
 static gpa_t kvm_vz_gva_to_gpa_cb(gva_t gva)

diff --git a/arch/mips/loongson64/cpucfg-emul.c b/arch/mips/loongson64/cpucfg-emul.c
index cd619b4..630927e 100644 (file)
--- a/arch/mips/loongson64/cpucfg-emul.c
+++ b/arch/mips/loongson64/cpucfg-emul.c
@@ -57,11 +57,11 @@ static void decode_loongson_config6(struct cpuinfo_mips *c)
 {
        u32 config6 = read_c0_config6();
 
-       if (config6 & MIPS_CONF6_LOONGSON_SFBEN)
+       if (config6 & LOONGSON_CONF6_SFBEN)
                c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_SFBP;
-       if (config6 & MIPS_CONF6_LOONGSON_LLEXC)
+       if (config6 & LOONGSON_CONF6_LLEXC)
                c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_LLEXC;
-       if (config6 & MIPS_CONF6_LOONGSON_SCRAND)
+       if (config6 & LOONGSON_CONF6_SCRAND)
                c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_SCRAND;
 }
 

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 49569e5..fc5a6d2 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1066,12 +1066,12 @@ static inline int alias_74k_erratum(struct cpuinfo_mips *c)
                if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
                        present = 1;
                if (rev == PRID_REV_ENCODE_332(2, 4, 0))
-                       write_c0_config6(read_c0_config6() | MIPS_CONF6_MTI_SYND);
+                       write_c0_config6(read_c0_config6() | MTI_CONF6_SYND);
                break;
        case PRID_IMP_1074K:
                if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
                        present = 1;
-                       write_c0_config6(read_c0_config6() | MIPS_CONF6_MTI_SYND);
+                       write_c0_config6(read_c0_config6() | MTI_CONF6_SYND);
                }
                break;
        default: