* config/tc-arm.c (md_assemble): Allow barrier instructions on

	ARMv6-M cores.

	* gas/arm/archv6m.s: Add dmb, dsb, and isb.
	* gas/arm/archv6m.d: Likewise.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index b3f22a8..8b8db8e 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2009-03-01  Mark Mitchell  <mark@codesourcery.com>
+
+       * config/tc-arm.c (md_assemble): Allow barrier instructions on
+       ARMv6-M cores.
+
 2009-03-01  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 
        * configure: Regenerate.

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index a1e5d12..bb783bd 100644 (file)
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -14747,7 +14747,8 @@ md_assemble (char *str)
          /* Implicit require narrow instructions on Thumb-1.  This avoids
             relaxation accidentally introducing Thumb-2 instructions.  */
          if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
-             && !ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr))
+             && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
+                  || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
            inst.size_req = 2;
        }
 
@@ -14805,7 +14806,8 @@ md_assemble (char *str)
         This is overly pessimistic for relaxable instructions.  */
       if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
           || inst.relax)
-         && !ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr))
+         && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
+              || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
        ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
                                arm_ext_v6t2);
     }

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 31c1dd0..69d31f4 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2009-03-01  Mark Mitchell  <mark@codesourcery.com>
+
+       * gas/arm/archv6m.s: Add dmb, dsb, and isb.
+       * gas/arm/archv6m.d: Likewise.
+
 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
 
        * gas/ppc/e500mc.d ("wait", "waitsrv", "waitimpl"): Add tests.

diff --git a/gas/testsuite/gas/arm/archv6m.d b/gas/testsuite/gas/arm/archv6m.d
index 31d06a3..2ad48a7 100644 (file)
--- a/gas/testsuite/gas/arm/archv6m.d
+++ b/gas/testsuite/gas/arm/archv6m.d
@@ -13,3 +13,6 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> bf40        sev
 0[0-9a-f]+ <[^>]+> 4408        add     r0, r1
 0[0-9a-f]+ <[^>]+> 46c0        nop.*
+0[0-9a-f]+ <[^>]+> f3bf 8f5f   dmb     sy
+0[0-9a-f]+ <[^>]+> f3bf 8f4f   dsb     sy
+0[0-9a-f]+ <[^>]+> f3bf 8f6f   isb     sy

diff --git a/gas/testsuite/gas/arm/archv6m.s b/gas/testsuite/gas/arm/archv6m.s
index 158b6a6..013bba9 100644 (file)
--- a/gas/testsuite/gas/arm/archv6m.s
+++ b/gas/testsuite/gas/arm/archv6m.s
@@ -14,3 +14,7 @@ foo:
        sev
        add r0, r0, r1
        nop
+       dmb
+       dsb
+       isb
+