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irqchip/gic-v3-its: Fix access width for gicr_syncr
author
Heyi Guo
<guoheyi@huawei.com>
Tue, 25 Feb 2020 09:00:23 +0000
(17:00 +0800)
committer
Marc Zyngier
<maz@kernel.org>
Sun, 8 Mar 2020 14:25:46 +0000
(14:25 +0000)
GICR_SYNCR is a 32bit register, so it is better to access it with
32bit access width, though we have not seen any real problem.
Signed-off-by: Heyi Guo <guoheyi@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link:
https://lore.kernel.org/r/20200225090023.28020-1-guoheyi@huawei.com
drivers/irqchip/irq-gic-v3-its.c
patch
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diff --git
a/drivers/irqchip/irq-gic-v3-its.c
b/drivers/irqchip/irq-gic-v3-its.c
index
83b1186
..
6bb2bea
100644
(file)
--- a/
drivers/irqchip/irq-gic-v3-its.c
+++ b/
drivers/irqchip/irq-gic-v3-its.c
@@
-1321,7
+1321,7
@@
static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
static void wait_for_syncr(void __iomem *rdbase)
{
- while (
gic_read_lpir
(rdbase + GICR_SYNCR) & 1)
+ while (
readl_relaxed
(rdbase + GICR_SYNCR) & 1)
cpu_relax();
}