(set_attr "mode" "DI,TI,TI")])
(define_insn "*<insn><mode>3"
- [(set (match_operand:VI_32 0 "register_operand" "=x,Yw")
- (sat_plusminus:VI_32
- (match_operand:VI_32 1 "register_operand" "<comm>0,Yw")
- (match_operand:VI_32 2 "register_operand" "x,Yw")))]
+ [(set (match_operand:VI_16_32 0 "register_operand" "=x,Yw")
+ (sat_plusminus:VI_16_32
+ (match_operand:VI_16_32 1 "register_operand" "<comm>0,Yw")
+ (match_operand:VI_16_32 2 "register_operand" "x,Yw")))]
"TARGET_SSE2"
"@
p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
(set_attr "mode" "DI,TI,TI")])
(define_insn "*eq<mode>3"
- [(set (match_operand:VI_32 0 "register_operand" "=x,x")
- (eq:VI_32
- (match_operand:VI_32 1 "register_operand" "%0,x")
- (match_operand:VI_32 2 "register_operand" "x,x")))]
+ [(set (match_operand:VI_16_32 0 "register_operand" "=x,x")
+ (eq:VI_16_32
+ (match_operand:VI_16_32 1 "register_operand" "%0,x")
+ (match_operand:VI_16_32 2 "register_operand" "x,x")))]
"TARGET_SSE2"
"@
pcmpeq<mmxvecsize>\t{%2, %0|%0, %2}
(set_attr "mode" "DI,TI,TI")])
(define_insn "*gt<mode>3"
- [(set (match_operand:VI_32 0 "register_operand" "=x,x")
- (gt:VI_32
- (match_operand:VI_32 1 "register_operand" "0,x")
- (match_operand:VI_32 2 "register_operand" "x,x")))]
+ [(set (match_operand:VI_16_32 0 "register_operand" "=x,x")
+ (gt:VI_16_32
+ (match_operand:VI_16_32 1 "register_operand" "0,x")
+ (match_operand:VI_16_32 2 "register_operand" "x,x")))]
"TARGET_SSE2"
"@
pcmpgt<mmxvecsize>\t{%2, %0|%0, %2}
(set_attr "mode" "TI")])
(define_insn "*xop_maskcmp<mode>3"
- [(set (match_operand:VI_32 0 "register_operand" "=x")
- (match_operator:VI_32 1 "ix86_comparison_int_operator"
- [(match_operand:VI_32 2 "register_operand" "x")
- (match_operand:VI_32 3 "register_operand" "x")]))]
+ [(set (match_operand:VI_16_32 0 "register_operand" "=x")
+ (match_operator:VI_16_32 1 "ix86_comparison_int_operator"
+ [(match_operand:VI_16_32 2 "register_operand" "x")
+ (match_operand:VI_16_32 3 "register_operand" "x")]))]
"TARGET_XOP"
"vpcom%Y1<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "sse4arg")
(set_attr "mode" "TI")])
(define_insn "*xop_maskcmp_uns<mode>3"
- [(set (match_operand:VI_32 0 "register_operand" "=x")
- (match_operator:VI_32 1 "ix86_comparison_uns_operator"
- [(match_operand:VI_32 2 "register_operand" "x")
- (match_operand:VI_32 3 "register_operand" "x")]))]
+ [(set (match_operand:VI_16_32 0 "register_operand" "=x")
+ (match_operator:VI_16_32 1 "ix86_comparison_uns_operator"
+ [(match_operand:VI_16_32 2 "register_operand" "x")
+ (match_operand:VI_16_32 3 "register_operand" "x")]))]
"TARGET_XOP"
"vpcom%Y1u<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "ssecmp")
})
(define_expand "vec_cmp<mode><mode>"
- [(set (match_operand:VI_32 0 "register_operand")
- (match_operator:VI_32 1 ""
- [(match_operand:VI_32 2 "register_operand")
- (match_operand:VI_32 3 "register_operand")]))]
+ [(set (match_operand:VI_16_32 0 "register_operand")
+ (match_operator:VI_16_32 1 ""
+ [(match_operand:VI_16_32 2 "register_operand")
+ (match_operand:VI_16_32 3 "register_operand")]))]
"TARGET_SSE2"
{
bool ok = ix86_expand_int_vec_cmp (operands);
})
(define_expand "vec_cmpu<mode><mode>"
- [(set (match_operand:VI_32 0 "register_operand")
- (match_operator:VI_32 1 ""
- [(match_operand:VI_32 2 "register_operand")
- (match_operand:VI_32 3 "register_operand")]))]
+ [(set (match_operand:VI_16_32 0 "register_operand")
+ (match_operator:VI_16_32 1 ""
+ [(match_operand:VI_16_32 2 "register_operand")
+ (match_operand:VI_16_32 3 "register_operand")]))]
"TARGET_SSE2"
{
bool ok = ix86_expand_int_vec_cmp (operands);
--- /dev/null
+/* PR target/103861 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+typedef char vec __attribute__((vector_size(2)));
+
+vec lt (vec a, vec b) { return a < b; }
+vec le (vec a, vec b) { return a <= b; }
+vec eq (vec a, vec b) { return a == b; }
+vec ne (vec a, vec b) { return a != b; }
+vec ge (vec a, vec b) { return a >= b; }
+vec gt (vec a, vec b) { return a > b; }
+
+typedef unsigned char uvec __attribute__((vector_size(2)));
+
+vec ltu (uvec a, uvec b) { return a < b; }
+vec leu (uvec a, uvec b) { return a <= b; }
+vec geu (uvec a, uvec b) { return a >= b; }
+vec gtu (uvec a, uvec b) { return a > b; }
+
+/* { dg-final { scan-assembler-not "cmpb" } } */