These SoCs has two SPI controllers. One of it is quite similar to previous
ones, but with internal clock divider removed; the other added MIPI DBI
Type-C offload based on the first one.
Add basical support for these controllers. As we're not going to
support the DBI functionality now, just implement the two kinds of
controllers as the same.
Co-developed-by: Icenowy Zheng <icenowy@aosc.io
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com
Reviewed-by: Andre Przywara <andre.przywara@arm.com
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com
Link: https://lore.kernel.org/r/20230510081121.3463710-5-bigunclemax@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org
.has_clk_ctl = true,
};
+static const struct sun6i_spi_cfg sun50i_r329_spi_cfg = {
+ .fifo_depth = SUN8I_FIFO_DEPTH,
+};
+
static const struct of_device_id sun6i_spi_match[] = {
{ .compatible = "allwinner,sun6i-a31-spi", .data = &sun6i_a31_spi_cfg },
{ .compatible = "allwinner,sun8i-h3-spi", .data = &sun8i_h3_spi_cfg },
+ {
+ .compatible = "allwinner,sun50i-r329-spi",
+ .data = &sun50i_r329_spi_cfg
+ },
{}
};
MODULE_DEVICE_TABLE(of, sun6i_spi_match);