bool isS16ImmX16() const { return Kind == Expression ||
(Kind == Immediate && isInt<16>(getImm()) &&
(getImm() & 15) == 0); }
- bool isS34ImmX16() const { return Kind == Expression ||
- (Kind == Immediate && isInt<34>(getImm()) &&
- (getImm() & 15) == 0); }
+ bool isS34ImmX16() const {
+ return Kind == Expression ||
+ (Kind == Immediate && isInt<34>(getImm()) && (getImm() & 15) == 0);
+ }
bool isS34Imm() const {
// Once the PC-Rel ABI is finalized, evaluate whether a 34-bit
// ContextImmediate is needed.
raw_ostream &O) {
printS34ImmOperand(MI, OpNo, O);
O << '(';
- printImmZeroOperand(MI, OpNo+1, O);
+ printImmZeroOperand(MI, OpNo + 1, O);
O << ')';
}
raw_ostream &O) {
printS34ImmOperand(MI, OpNo, O);
O << '(';
- printOperand(MI, OpNo+1, O);
+ printOperand(MI, OpNo + 1, O);
O << ')';
}
// Encode (imm, reg) as a memri34, which has the low 34-bits as the
// displacement and the next 5 bits as the register #.
assert(MI.getOperand(OpNo + 1).isReg() && "Expecting a register.");
- uint64_t RegBits =
- getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI) << 34;
-
+ uint64_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI)
+ << 34;
const MCOperand &MO = MI.getOperand(OpNo);
return ((getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL) | RegBits;
}