clksource:starfive-timer: Modify the default clock frequency

timer on soc is 24M.

Signed-off-by: samin <samin.guo@starfivetech.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7110-evb.dts b/arch/riscv/boot/dts/starfive/jh7110-evb.dts
index bce5855..4155a95 100755 (executable)
--- a/arch/riscv/boot/dts/starfive/jh7110-evb.dts
+++ b/arch/riscv/boot/dts/starfive/jh7110-evb.dts
@@ -11,7 +11,3 @@
        model = "StarFive JH7110 EVB";
        compatible = "starfive,jh7110-evb", "starfive,jh7110";
 };
-
-&timer {
-       clock-frequency = <24000000>;
-};
\ No newline at end of file

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index f189189..9c3fc15 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -360,7 +360,7 @@
                                 <&clkgen JH7110_TIMER_CLK_APB>;
                        clock-names = "timer0", "timer1",
                                      "timer2", "timer3", "apb_clk";
-                       clock-frequency = <2000000>;
+                       clock-frequency = <24000000>;
                        status = "okay";
                };
 
@@ -369,7 +369,6 @@
                        reg = <0x0 0x13070000 0x0 0x10000>;
                        interrupts = <68>;
                        interrupt-names = "wdog";
-                       clock-frequency = <2000000>;
                        clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>,
                                 <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
                        clock-names = "core_clk", "apb_clk";

diff --git a/drivers/watchdog/starfive-wdt.c b/drivers/watchdog/starfive-wdt.c
index a6d38d2..f572936 100755 (executable)
--- a/drivers/watchdog/starfive-wdt.c
+++ b/drivers/watchdog/starfive-wdt.c
@@ -205,7 +205,6 @@ MODULE_DEVICE_TABLE(platform, si5wdt_ids);
 
 static int si5wdt_get_clock_rate(struct stf_si5_wdt *wdt)
 {
-#ifdef HWBOARD_FPGA
        int ret;
        u32 freq;
 
@@ -215,14 +214,13 @@ static int si5wdt_get_clock_rate(struct stf_si5_wdt *wdt)
                wdt->freq = (u64)freq;
                return 0;
        }
-       dev_err(wdt->dev, "get rate failed, need clock-frequency define in dts.\n");
-#else
+       dev_dbg(wdt->dev, "get rate failed, need clock-frequency define in dts.\n");
+
        if (!IS_ERR(wdt->core_clk)) {
                wdt->freq = clk_get_rate(wdt->core_clk);
                return 0;
        }
-#endif
-
+       dev_err(wdt->dev, "get clock-frequency failed\n");
        return -ENOENT;
 }