Correct r5900 sanitization.

diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index b605dbc..835dbdb 100644 (file)
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -3735,10 +3735,12 @@ sim_engine_run (sd, next_cpu_nr, siggnal)
        HIACCESS--;
       if (LOACCESS > 0)
        LOACCESS--;
+      /* start-sanitize-r5900 */
       if (HI1ACCESS > 0)
        HI1ACCESS--;
       if (LO1ACCESS > 0)
        LO1ACCESS--;
+      /* end-sanitize-r5900 */
 #endif /* WARN_LOHI */
 
       /* For certain MIPS architectures, GPR[0] is hardwired to zero. We

diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h
index b096069..7809714 100644 (file)
--- a/sim/mips/sim-main.h
+++ b/sim/mips/sim-main.h
@@ -471,7 +471,7 @@ struct _sim_cpu {
   if ((HIACCESS != 0) || (LOACCESS != 0)) \
     sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
 }
-  /* end-sanitize-r5900 */
+  /* start-sanitize-r5900 */
 #undef CHECKHILO
 #define CHECKHILO(s) {\
   if ((HIACCESS != 0) || (LOACCESS != 0) || (HI1ACCESS != 0) || (LO1ACCESS != 0))\