#define NAND_ECC_NONE (0x0)
#define NAND_ECC_BCH8 (0x1)
#define NAND_ECC_BCH8_1K (0x2)
-#define NAND_ECC_BCH16_1K (0x3)
-#define NAND_ECC_BCH24_1K (0x4)
-#define NAND_ECC_BCH24_1K_M8 (0x3)
-#define NAND_ECC_BCH30_1K (0x5)
-#define NAND_ECC_BCH30_1K_M8 (0x4)
-#define NAND_ECC_BCH40_1K (0x6)
-#define NAND_ECC_BCH40_1K_M8 (0x5)
-#define NAND_ECC_BCH50_1K_M8 (0x6)
+#define NAND_ECC_BCH24_1K (0x3)
+#define NAND_ECC_BCH30_1K (0x4)
+#define NAND_ECC_BCH40_1K (0x5)
/*NAND_ECC_BCH50_1K only for mtd for general*/
#define NAND_ECC_BCH50_1K (0x6)
#define NAND_ECC_BCH60_1K (0x7)
aml_chip->ecc_max = 8;
chip->ecc.steps = mtd->writesize / chip->ecc.size;
break;
- /*don't support for new chip(greater than m8)*/
- case NAND_ECC_BCH16_1K_MODE:
- chip->ecc.strength = 16;
- chip->ecc.size = NAND_ECC_UNIT_1KSIZE;
- chip->ecc.bytes = NAND_BCH16_1K_ECC_SIZE;
- aml_chip->bch_mode = NAND_ECC_BCH16_1K;
- aml_chip->user_byte_mode = 2;
- aml_chip->ecc_cnt_limit = 14;
- aml_chip->ecc_max = 16;
- chip->ecc.steps = mtd->writesize / chip->ecc.size;
- break;
case NAND_ECC_BCH24_1K_MODE:
chip->ecc.strength = 24;
0,
(NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
+ {"A revision NAND 512MB TC58NVG2S0HBAI6 ",
+ {NAND_MFR_TOSHIBA, 0xdc, 0x90, 0x26, 0x76},
+ 4096,
+ 512,
+ 0x40000,
+ 256,
+ 1,
+ 20,
+ 25,
+ 0,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
+
{"A revision NAND 2Gib MT29F2G08-A",
{NAND_MFR_MICRON, 0xda, 0x90, 0x95, 0x06},
2048,
break;
case 64:
case 128:
+ case 256:
mtd_set_ooblayout(mtd, &nand_ooblayout_lp_hamming_ops);
break;
default: