static bool valid_stolen_size(struct drm_i915_private *i915, struct resource *dsm)
{
- return (dsm->start != 0 || HAS_BAR2_SMEM_STOLEN(i915)) && dsm->end > dsm->start;
+ return (dsm->start != 0 || HAS_LMEMBAR_SMEM_STOLEN(i915)) && dsm->end > dsm->start;
}
static int adjust_stolen(struct drm_i915_private *i915,
* address range since it's local to the gpu.
*
* Starting MTL, in IGFX devices the stolen memory is exposed via
- * BAR2 and shall be considered similar to stolen lmem.
+ * LMEMBAR and shall be considered similar to stolen lmem.
*/
- if (HAS_LMEM(i915) || HAS_BAR2_SMEM_STOLEN(i915))
+ if (HAS_LMEM(i915) || HAS_LMEMBAR_SMEM_STOLEN(i915))
return 0;
/*
MISSING_CASE(reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK);
}
- if (HAS_BAR2_SMEM_STOLEN(i915))
+ if (HAS_LMEMBAR_SMEM_STOLEN(i915))
/* the base is initialized to stolen top so subtract size to get base */
*base -= *size;
else
if (!i915_pci_resource_valid(pdev, GEN12_LMEM_BAR))
return ERR_PTR(-ENXIO);
- if (HAS_BAR2_SMEM_STOLEN(i915) || IS_DG1(i915)) {
+ if (HAS_LMEMBAR_SMEM_STOLEN(i915) || IS_DG1(i915)) {
lmem_size = pci_resource_len(pdev, GEN12_LMEM_BAR);
} else {
resource_size_t lmem_range;
lmem_size *= SZ_1G;
}
- if (HAS_BAR2_SMEM_STOLEN(i915)) {
+ if (HAS_LMEMBAR_SMEM_STOLEN(i915)) {
/*
* MTL dsm size is in GGC register.
* Also MTL uses offset to DSMBASE in ptes, so i915
}
io_size = dsm_size;
- if (HAS_BAR2_SMEM_STOLEN(i915)) {
+ if (HAS_LMEMBAR_SMEM_STOLEN(i915)) {
io_start = pci_resource_start(pdev, GEN12_LMEM_BAR) + SZ_8M;
} else if (pci_resource_len(pdev, GEN12_LMEM_BAR) < lmem_size) {
io_start = 0;
#define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
-#define HAS_BAR2_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
- GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+#define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
+ GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
/* intel_device_info.c */
static inline struct intel_device_info *