ASoC: SOF: Intel: add IP identifier
authorPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Thu, 14 Apr 2022 18:48:17 +0000 (13:48 -0500)
committerMark Brown <broonie@kernel.org>
Tue, 19 Apr 2022 11:03:46 +0000 (12:03 +0100)
This patch adds an IP identifier for each Intel platform. The
identifier will be used to select different code branches or
constants.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20220414184817.362215-16-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/sof/intel/apl.c
sound/soc/sof/intel/bdw.c
sound/soc/sof/intel/byt.c
sound/soc/sof/intel/cnl.c
sound/soc/sof/intel/icl.c
sound/soc/sof/intel/pci-tng.c
sound/soc/sof/intel/shim.h
sound/soc/sof/intel/tgl.c

index 4762846d8a336159a6982b180704ff900315af68..cb499f3905cec9d434297406d2b9d58b75389052 100644 (file)
@@ -77,5 +77,6 @@ const struct sof_intel_dsp_desc apl_chip_info = {
        .ssp_base_offset = APL_SSP_BASE_OFFSET,
        .quirks = SOF_INTEL_PROCEN_FMT_QUIRK,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .hw_ip_version = SOF_INTEL_CAVS_1_5_PLUS,
 };
 EXPORT_SYMBOL_NS(apl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
index 3449eeccd9e8ef4132217ddf210209c1f6cc2038..73a20172bf77d87a85b3daf060fe7de2e92c1ade 100644 (file)
@@ -637,6 +637,7 @@ static struct snd_sof_dsp_ops sof_bdw_ops = {
 static const struct sof_intel_dsp_desc bdw_chip_info = {
        .cores_num = 1,
        .host_managed_cores_mask = 1,
+       .hw_ip_version = SOF_INTEL_BROADWELL,
 };
 
 static const struct sof_dev_desc sof_acpi_broadwell_desc = {
index 3db125d82a1e5abfb72d8ab4856316395c9a20da..08376e8fdc61cf72da1733e4560af67736432617 100644 (file)
@@ -295,6 +295,7 @@ static struct snd_sof_dsp_ops sof_byt_ops = {
 static const struct sof_intel_dsp_desc byt_chip_info = {
        .cores_num = 1,
        .host_managed_cores_mask = 1,
+       .hw_ip_version = SOF_INTEL_BAYTRAIL,
 };
 
 /* cherrytrail and braswell ops */
@@ -378,6 +379,7 @@ static struct snd_sof_dsp_ops sof_cht_ops = {
 static const struct sof_intel_dsp_desc cht_chip_info = {
        .cores_num = 1,
        .host_managed_cores_mask = 1,
+       .hw_ip_version = SOF_INTEL_BAYTRAIL,
 };
 
 /* BYTCR uses different IRQ index */
index 86b683486f06f6a1dbc0845d9c7be61740c588fd..f5bac91c335ba0476ae91d8124f6ba6360b33e31 100644 (file)
@@ -297,6 +297,7 @@ const struct sof_intel_dsp_desc cnl_chip_info = {
        .sdw_alh_base = SDW_ALH_BASE,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .hw_ip_version = SOF_INTEL_CAVS_1_8,
 };
 EXPORT_SYMBOL_NS(cnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -325,5 +326,6 @@ const struct sof_intel_dsp_desc jsl_chip_info = {
        .sdw_alh_base = SDW_ALH_BASE,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .hw_ip_version = SOF_INTEL_CAVS_2_0,
 };
 EXPORT_SYMBOL_NS(jsl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
index 2e4d371f7860d1e3443115072091798e711c2fc5..8dd56269693445ca0788121a55e5d91e9e158f22 100644 (file)
@@ -142,5 +142,6 @@ const struct sof_intel_dsp_desc icl_chip_info = {
        .sdw_alh_base = SDW_ALH_BASE,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .hw_ip_version = SOF_INTEL_CAVS_2_0,
 };
 EXPORT_SYMBOL_NS(icl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
index ca313c7db47ebee2e618eb9550907f158eb7f657..14f11528f06988de7850d65da8d7b7d426efaea7 100644 (file)
@@ -210,6 +210,7 @@ struct snd_sof_dsp_ops sof_tng_ops = {
 const struct sof_intel_dsp_desc tng_chip_info = {
        .cores_num = 1,
        .host_managed_cores_mask = 1,
+       .hw_ip_version = SOF_INTEL_TANGIER,
 };
 
 static const struct sof_dev_desc tng_desc = {
index 3eb09941ae6e9a44c4b58e3947803a42fbecf834..1fd7b485d8212efb190a95a42e24298d2fc0902c 100644 (file)
 #ifndef __SOF_INTEL_SHIM_H
 #define __SOF_INTEL_SHIM_H
 
+enum sof_intel_hw_ip_version {
+       SOF_INTEL_TANGIER,
+       SOF_INTEL_BAYTRAIL,
+       SOF_INTEL_BROADWELL,
+       SOF_INTEL_CAVS_1_5,     /* SkyLake, KabyLake, AmberLake */
+       SOF_INTEL_CAVS_1_5_PLUS,/* ApolloLake, GeminiLake */
+       SOF_INTEL_CAVS_1_8,     /* CannonLake, CometLake, CoffeeLake */
+       SOF_INTEL_CAVS_2_0,     /* IceLake, JasperLake */
+       SOF_INTEL_CAVS_2_5,     /* TigerLake, AlderLake */
+};
+
 /*
  * SHIM registers for BYT, BSW, CHT, BDW
  */
@@ -171,6 +182,7 @@ struct sof_intel_dsp_desc {
        u32 sdw_shim_base;
        u32 sdw_alh_base;
        u32 quirks;
+       enum sof_intel_hw_ip_version hw_ip_version;
        bool (*check_sdw_irq)(struct snd_sof_dev *sdev);
        bool (*check_ipc_irq)(struct snd_sof_dev *sdev);
 };
index 32d7e15126c266f2b507afbc4ffbaa5d02c9de32..816571305f247a2ace5fd0631a1cd3b1cb01385d 100644 (file)
@@ -113,6 +113,7 @@ const struct sof_intel_dsp_desc tgl_chip_info = {
        .sdw_alh_base = SDW_ALH_BASE,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .hw_ip_version = SOF_INTEL_CAVS_2_5,
 };
 EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -134,6 +135,7 @@ const struct sof_intel_dsp_desc tglh_chip_info = {
        .sdw_alh_base = SDW_ALH_BASE,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .hw_ip_version = SOF_INTEL_CAVS_2_5,
 };
 EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -155,6 +157,7 @@ const struct sof_intel_dsp_desc ehl_chip_info = {
        .sdw_alh_base = SDW_ALH_BASE,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .hw_ip_version = SOF_INTEL_CAVS_2_5,
 };
 EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -176,5 +179,6 @@ const struct sof_intel_dsp_desc adls_chip_info = {
        .sdw_alh_base = SDW_ALH_BASE,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .hw_ip_version = SOF_INTEL_CAVS_2_5,
 };
 EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);