meson-gxbb-nanopi-k2.dtb \
meson-gxbb-p200.dtb \
meson-gxbb-p201.dtb \
+ meson-gxbb-wetek-hub.dtb \
+ meson-gxbb-wetek-play2.dtb \
meson-gxl-s805x-libretech-ac.dtb \
meson-gxl-s905d-libretech-pc.dtb \
meson-gxl-s905w-jethome-jethub-j80.dtb \
meson-gxl-s905x-libretech-cc.dtb \
meson-gxl-s905x-libretech-cc-v2.dtb \
meson-gxl-s905x-p212.dtb \
+ meson-gxm-gt1-ultimate.dtb \
meson-gxm-khadas-vim2.dtb \
meson-gxm-s912-libretech-pc.dtb \
meson-gxm-wetek-core2.dtb \
meson-g12a-radxa-zero.dtb \
meson-g12a-sei510.dtb \
meson-g12a-u200.dtb \
+ meson-g12b-a311d-bananapi-m2s.dtb \
meson-g12b-a311d-khadas-vim3.dtb \
+ meson-g12b-bananapi-cm4-cm4io.dtb \
+ meson-g12b-gsking-x.dtb \
meson-g12b-gtking.dtb \
meson-g12b-gtking-pro.dtb \
- meson-g12b-gsking-x.dtb \
meson-g12b-odroid-go-ultra.dtb \
meson-g12b-odroid-n2.dtb \
meson-g12b-odroid-n2l.dtb \
meson-g12b-odroid-n2-plus.dtb \
+ meson-g12b-radxa-zero2.dtb \
+ meson-sm1-bananapi-m2-pro.dtb \
meson-sm1-bananapi-m5.dtb \
meson-sm1-khadas-vim3l.dtb \
meson-sm1-odroid-c4.dtb \
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-a311d.dtsi"
+#include "meson-g12b-bananapi.dtsi"
+
+/ {
+ compatible = "bananapi,bpi-m2s", "amlogic,a311d", "amlogic,g12b";
+ model = "BananaPi M2S";
+
+ aliases {
+ i2c0 = &i2c1;
+ i2c1 = &i2c3;
+ };
+};
+
+/* Camera (CSI) bus */
+&i2c1 {
+ status = "okay";
+ pinctrl-0 = <&i2c1_sda_h6_pins>, <&i2c1_sck_h7_pins>;
+ pinctrl-names = "default";
+};
+
+/* Display (DSI) bus */
+&i2c3 {
+ status = "okay";
+ pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
+ pinctrl-names = "default";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
+ */
+
+#include "meson-g12-common-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-bananapi-cm4.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ compatible = "bananapi,bpi-cm4io", "bananapi,bpi-cm4", "amlogic,a311d", "amlogic,g12b";
+ model = "BananaPi BPI-CM4IO Baseboard with BPI-CM4 Module";
+
+ aliases {
+ ethernet0 = ðmac;
+ i2c0 = &i2c1;
+ i2c1 = &i2c3;
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 2>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1710000>;
+
+ button-function {
+ label = "Function";
+ linux,code = <KEY_FN>;
+ press-threshold-microvolt = <10000>;
+ };
+ };
+
+ hdmi_connector: hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-blue {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-green {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "BPI-CM4IO";
+ audio-aux-devs = <&tdmout_b>;
+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-3 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+ };
+ };
+
+ /* hdmi glue */
+ dai-link-4 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&cecb_AO {
+ status = "okay";
+};
+
+ðmac {
+ status = "okay";
+};
+
+&hdmi_tx {
+ status = "okay";
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+/* CSI port */
+&i2c1 {
+ status = "okay";
+};
+
+/* DSI port for touchscreen */
+&i2c3 {
+ status = "okay";
+};
+
+/* miniPCIe port with USB + SIM slot */
+&pcie {
+ status = "okay";
+};
+
+&sd_emmc_b {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
+
+/* Peripheral Only USB-C port */
+&usb {
+ dr_mode = "peripheral";
+
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
+ */
+
+#include "meson-g12b-a311d.dtsi"
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+
+/ {
+ aliases {
+ serial0 = &uart_AO;
+ rtc1 = &vrtc;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOAO_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ emmc_1v8: regulator-emmc-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "EMMC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ dc_in: regulator-dc-in {
+ compatible = "regulator-fixed";
+ regulator-name = "DC_IN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ vddio_c: regulator-vddio-c {
+ compatible = "regulator-gpio";
+ regulator-name = "VDDIO_C";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ enable-gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ regulator-always-on;
+
+ gpios = <&gpio_ao GPIOAO_9 GPIO_OPEN_DRAIN>;
+ gpios-states = <1>;
+
+ states = <1800000 0>,
+ <3300000 1>;
+ };
+
+ vddao_1v8: regulator-vddao-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ vddao_3v3: regulator-vddao-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_in>;
+ regulator-always-on;
+ };
+
+ vddcpu_a: regulator-vddcpu-a {
+ /*
+ * MP8756GD DC/DC Regulator.
+ */
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU_A";
+ regulator-min-microvolt = <680000>;
+ regulator-max-microvolt = <1040000>;
+
+ pwm-supply = <&dc_in>;
+
+ pwms = <&pwm_ab 0 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vddcpu_b: regulator-vddcpu-b {
+ /*
+ * SY8120B1ABC DC/DC Regulator.
+ */
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU_B";
+ regulator-min-microvolt = <680000>;
+ regulator-max-microvolt = <1040000>;
+
+ pwm-supply = <&dc_in>;
+
+ pwms = <&pwm_AO_cd 1 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+};
+
+&arb {
+ status = "okay";
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+&cec_AO {
+ pinctrl-0 = <&cec_ao_a_h_pins>;
+ pinctrl-names = "default";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cecb_AO {
+ pinctrl-0 = <&cec_ao_b_h_pins>;
+ pinctrl-names = "default";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cpu0 {
+ cpu-supply = <&vddcpu_b>;
+ operating-points-v2 = <&cpu_opp_table_0>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu1 {
+ cpu-supply = <&vddcpu_b>;
+ operating-points-v2 = <&cpu_opp_table_0>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu100 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu101 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu102 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu103 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&ext_mdio {
+ external_phy: ethernet-phy@0 {
+ /* Realtek RTL8211F (0x001cc916) */
+ reg = <0>;
+ max-speed = <1000>;
+
+ interrupt-parent = <&gpio_intc>;
+ /* MAC_INTR on GPIOZ_14 */
+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+/* Ethernet to be enabled in baseboard DT */
+ðmac {
+ pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
+ pinctrl-names = "default";
+ phy-mode = "rgmii-txid";
+ phy-handle = <&external_phy>;
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
+/* HDMI to be enabled in baseboard DT */
+&hdmi_tx {
+ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&dc_in>;
+};
+
+/* "Camera" I2C bus */
+&i2c1 {
+ pinctrl-0 = <&i2c1_sda_h6_pins>, <&i2c1_sck_h7_pins>;
+ pinctrl-names = "default";
+};
+
+/* Main I2C bus */
+&i2c2 {
+ pinctrl-0 = <&i2c2_sda_x_pins>, <&i2c2_sck_x_pins>;
+ pinctrl-names = "default";
+};
+
+/* "ID" I2C bus */
+&i2c3 {
+ pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
+ pinctrl-names = "default";
+};
+
+&pcie {
+ reset-gpios = <&gpio GPIOA_8 GPIO_ACTIVE_LOW>;
+};
+
+&pwm_ab {
+ pinctrl-0 = <&pwm_a_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin0";
+
+ status = "okay";
+};
+
+&pwm_ef {
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pwm_AO_cd {
+ pinctrl-0 = <&pwm_ao_d_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin1";
+
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vddao_1v8>;
+
+ status = "okay";
+};
+
+/* on-module SDIO WiFi */
+&sd_emmc_a {
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ sd-uhs-sdr104;
+ max-frequency = <50000000>;
+
+ non-removable;
+ disable-wp;
+
+ /* WiFi firmware requires power in suspend */
+ keep-power-in-suspend;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddao_3v3>;
+
+ status = "okay";
+
+ rtl8822cs: wifi@1 {
+ reg = <1>;
+ };
+};
+
+/* SD card to be enabled in baseboard DT */
+&sd_emmc_b {
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_c>;
+};
+
+/* on-module eMMC */
+&sd_emmc_c {
+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddao_1v8>;
+
+ status = "okay";
+};
+
+&tdmif_b {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+/* on-module UART BT */
+&uart_A {
+ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+
+ status = "okay";
+
+ bluetooth {
+ compatible = "realtek,rtl8822cs-bt";
+ enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+ host-wake-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
+ device-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&uart_AO {
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&usb {
+ phys = <&usb2_phy0>, <&usb2_phy1>;
+ phy-names = "usb2-phy0", "usb2-phy1";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-g12-common-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ * Copyright (c) 2023 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ rtc1 = &vrtc;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>; /* 2 GiB or 4 GiB */
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 2>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1710000>;
+
+ button-function {
+ label = "RST";
+ linux,code = <KEY_POWER>;
+ press-threshold-microvolt = <10000>;
+ };
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+
+ fan0: pwm-fan {
+ compatible = "pwm-fan";
+ #cooling-cells = <2>;
+ cooling-min-state = <0>;
+ cooling-max-state = <3>;
+ cooling-levels = <0 120 170 220>;
+ pwms = <&pwm_cd 1 40000 0>;
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ dc_in: regulator-dc-in {
+ compatible = "regulator-fixed";
+ regulator-name = "DC_IN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ vcc_5v: regulator-vcc-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_in>;
+
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ };
+
+ vcc_3v3: regulator-vcc-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vsys_3v3>;
+ regulator-always-on;
+ };
+
+ vcc_1v8: regulator-vcc-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
+ vddao_1v8: regulator-vddao-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vsys_3v3>;
+ regulator-always-on;
+ };
+
+ vddcpu_a: regulator-vddcpu-a {
+ compatible = "pwm-regulator";
+ regulator-name = "VDDCPU_A";
+ regulator-min-microvolt = <690000>;
+ regulator-max-microvolt = <1050000>;
+ pwm-supply = <&dc_in>;
+ pwms = <&pwm_ab 0 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vddcpu_b: regulator-vddcpu-b {
+ compatible = "pwm-regulator";
+ regulator-name = "VDDCPU_B";
+ regulator-min-microvolt = <690000>;
+ regulator-max-microvolt = <1050000>;
+ pwm-supply = <&vsys_3v3>;
+ pwms = <&pwm_AO_cd 1 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vsys_3v3: regulator-vsys-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VSYS_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_in>;
+ regulator-always-on;
+ };
+
+ emmc_1v8: regulator-emmc-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "EMMC_AO1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
+ usb_pwr: regulator-usb-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "USB_PWR";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_5v>;
+
+ gpio = <&gpio GPIOA_6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "BPI-M2S";
+ audio-aux-devs = <&tdmout_b>;
+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-3 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+ };
+ };
+
+ /* hdmi glue */
+ dai-link-4 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&arb {
+ status = "okay";
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+&cecb_AO {
+ pinctrl-0 = <&cec_ao_b_h_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cpu0 {
+ cpu-supply = <&vddcpu_b>;
+ operating-points-v2 = <&cpu_opp_table_0>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu1 {
+ cpu-supply = <&vddcpu_b>;
+ operating-points-v2 = <&cpu_opp_table_0>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu100 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu101 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu102 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu103 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+ðmac {
+ pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-handle = <&external_phy>;
+ amlogic,tx-delay-ns = <2>;
+};
+
+&ext_mdio {
+ external_phy: ethernet-phy@0 {
+ /* Realtek RTL8211F (0x001cc916) */
+ reg = <0>;
+ max-speed = <1000>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <80000>;
+ reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+
+ interrupt-parent = <&gpio_intc>;
+ /* MAC_INTR on GPIOZ_14 */
+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&vcc_5v>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+/* Main i2c bus */
+&i2c2 {
+ status = "okay";
+ pinctrl-0 = <&i2c2_sda_x_pins>, <&i2c2_sck_x_pins>;
+ pinctrl-names = "default";
+};
+
+&pcie {
+ status = "okay";
+ reset-gpios = <&gpio GPIOA_8 GPIO_ACTIVE_LOW>;
+};
+
+&pwm_ab {
+ status = "okay";
+ pinctrl-0 = <&pwm_a_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin0";
+};
+
+&pwm_cd {
+ status = "okay";
+ pinctrl-0 = <&pwm_d_x6_pins>;
+ pinctrl-names = "default";
+ pwm-gpios = <&gpio GPIOAO_10 GPIO_ACTIVE_HIGH>;
+};
+
+&pwm_ef {
+ status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_AO_cd {
+ pinctrl-0 = <&pwm_ao_d_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin1";
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddao_1v8>;
+};
+
+/* SDIO */
+&sd_emmc_a {
+ /* enable if WiFi/BT board connected */
+ status = "disabled";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ sd-uhs-sdr104;
+ max-frequency = <50000000>;
+
+ non-removable;
+ disable-wp;
+
+ /* WiFi firmware requires power in suspend */
+ keep-power-in-suspend;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vsys_3v3>;
+ vqmmc-supply = <&vddao_1v8>;
+
+ rtl8822cs: wifi@1 {
+ reg = <1>;
+ };
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&vsys_3v3>;
+ vqmmc-supply = <&vsys_3v3>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&emmc_1v8>;
+};
+
+&tdmif_b {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
+
+&uart_A {
+ /* enable if WiFi/BT board connected */
+ status = "disabled";
+ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "realtek,rtl8822cs-bt";
+ enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+ host-wake-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
+ device-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb2_phy0 {
+ phy-supply = <&dc_in>;
+};
+
+&usb2_phy1 {
+ phy-supply = <&usb_pwr>;
+};
+
+&usb3_pcie_phy {
+ phy-supply = <&usb_pwr>;
+};
+
+&usb {
+ status = "okay";
+ dr_mode = "peripheral";
+ phys = <&usb2_phy0>, <&usb2_phy1>;
+ phy-names = "usb2-phy0", "usb2-phy1";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-g12-common-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
+ * Copyright (c) 2022 Radxa Limited
+ * Author: Yuntian Zhang <yt@radxa.com>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-a311d.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ compatible = "radxa,zero2", "amlogic,a311d", "amlogic,g12b";
+ model = "Radxa Zero2";
+
+ aliases {
+ serial0 = &uart_AO;
+ serial2 = &uart_A;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ poll-interval = <100>;
+ power-button {
+ label = "power";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpio_ao GPIOAO_3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-green {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio GPIOA_12 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ ao_5v: regulator-ao-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "AO_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ vcc_1v8: regulator-vcc-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
+ vcc_3v3: regulator-vcc-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ /* FIXME: actually controlled by VDDCPU_B_EN */
+ };
+
+ vddao_1v8: regulator-vddao-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ vddao_3v3: regulator-vddao-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&ao_5v>;
+ regulator-always-on;
+ };
+
+ vddcpu_a: regulator-vddcpu-a {
+ /*
+ * MP8756GD Regulator.
+ */
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU_A";
+ regulator-min-microvolt = <730000>;
+ regulator-max-microvolt = <1022000>;
+
+ pwm-supply = <&ao_5v>;
+
+ pwms = <&pwm_ab 0 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vddcpu_b: regulator-vddcpu-b {
+ /*
+ * Silergy SY8120B1ABC Regulator.
+ */
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU_B";
+ regulator-min-microvolt = <730000>;
+ regulator-max-microvolt = <1022000>;
+
+ pwm-supply = <&ao_5v>;
+
+ pwms = <&pwm_AO_cd 1 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "RADXA-ZERO2";
+ audio-aux-devs = <&tdmout_b>;
+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-3 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+ };
+ };
+
+ /* hdmi glue */
+ dai-link-4 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+
+ wifi32k: clock-0 {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+};
+
+&arb {
+ status = "okay";
+};
+
+&cec_AO {
+ pinctrl-0 = <&cec_ao_a_h_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cecb_AO {
+ pinctrl-0 = <&cec_ao_b_h_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vddcpu_b>;
+ operating-points-v2 = <&cpu_opp_table_0>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu1 {
+ cpu-supply = <&vddcpu_b>;
+ operating-points-v2 = <&cpu_opp_table_0>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu100 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu101 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu102 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu103 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
+&gpio {
+ gpio-line-names =
+ /* GPIOZ */
+ "PIN_27", "PIN_28", "PIN_7", "PIN_11", "PIN_13", "PIN_15", "PIN_18", "PIN_40",
+ "", "", "", "", "", "", "", "",
+ /* GPIOH */
+ "", "", "", "", "PIN_19", "PIN_21", "PIN_24", "PIN_23",
+ "",
+ /* BOOT */
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "EMMC_PWRSEQ", "", "", "",
+ /* GPIOC */
+ "", "", "", "", "", "", "SD_CD", "PIN_36",
+ /* GPIOA */
+ "PIN_32", "PIN_12", "PIN_35", "", "", "PIN_38", "", "",
+ "", "", "", "", "LED_GREEN", "PIN_31", "PIN_3", "PIN_5",
+ /* GPIOX */
+ "", "", "", "", "", "", "SDIO_PWRSEQ", "",
+ "", "", "", "", "", "", "", "",
+ "", "BT_SHUTDOWN", "", "";
+};
+
+&gpio_ao {
+ gpio-line-names =
+ /* GPIOAO */
+ "PIN_8", "PIN_10", "", "BTN_POWER", "", "", "", "PIN_29",
+ "PIN_33", "PIN_37", "FAN", "",
+ /* GPIOE */
+ "", "", "";
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&ao_5v>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&ir {
+ status = "disabled";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_ab {
+ pinctrl-0 = <&pwm_a_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin0";
+ status = "okay";
+};
+
+&pwm_ef {
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin0";
+ status = "okay";
+};
+
+&pwm_AO_ab {
+ pinctrl-0 = <&pwm_ao_a_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin0";
+ status = "okay";
+};
+
+&pwm_AO_cd {
+ pinctrl-0 = <&pwm_ao_d_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin1";
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddao_1v8>;
+};
+
+/* SDIO */
+&sd_emmc_a {
+ status = "okay";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+
+ /* WiFi firmware requires power to be kept while in suspend */
+ keep-power-in-suspend;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddao_1v8>;
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddao_3v3>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+};
+
+&tdmif_b {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
+
+&uart_A {
+ status = "okay";
+ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+ max-speed = <2000000>;
+ clocks = <&wifi32k>;
+ clock-names = "lpo";
+ };
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-s922x.dtsi"
+#include "meson-g12b-bananapi.dtsi"
+
+/ {
+ compatible = "bananapi,bpi-m2s", "amlogic,s922x", "amlogic,g12b";
+ model = "BananaPi M2S";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 BayLibre, Inc.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include "meson-gxbb-wetek.dtsi"
+#include <dt-bindings/sound/meson-aiu.h>
+
+/ {
+ compatible = "wetek,hub", "amlogic,meson-gxbb";
+ model = "WeTek Hub";
+
+ sound {
+ compatible = "amlogic,gx-sound-card";
+ model = "WETEK-HUB";
+ assigned-clocks = <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>,
+ <&clkc CLKID_MPLL2>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
+ dai-format = "i2s";
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
+ };
+ };
+
+ dai-link-2 {
+ sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
+
+ codec-0 {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&aiu {
+ status = "okay";
+};
+
+&ir {
+ linux,rc-map-name = "rc-wetek-hub";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 BayLibre, Inc.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include "meson-gxbb-wetek.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/sound/meson-aiu.h>
+
+/ {
+ compatible = "wetek,play2", "amlogic,meson-gxbb";
+ model = "WeTek Play 2";
+
+ spdif_dit: audio-codec-0 {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ status = "okay";
+ sound-name-prefix = "DIT";
+ };
+
+ leds {
+ led-wifi {
+ label = "wetek-play:wifi-status";
+ gpios = <&gpio GPIODV_26 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-ethernet {
+ label = "wetek-play:ethernet-status";
+ gpios = <&gpio GPIODV_27 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ poll-interval = <100>;
+
+ button {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ sound {
+ compatible = "amlogic,gx-sound-card";
+ model = "WETEK-PLAY2";
+ assigned-clocks = <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>,
+ <&clkc CLKID_MPLL2>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
+ dai-format = "i2s";
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
+ };
+ };
+
+ dai-link-3 {
+ sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>;
+
+ codec-0 {
+ sound-dai = <&spdif_dit>;
+ };
+ };
+
+ dai-link-4 {
+ sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
+
+ codec-0 {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&aiu {
+ status = "okay";
+ pinctrl-0 = <&spdif_out_y_pins>;
+ pinctrl-names = "default";
+};
+
+&i2c_A {
+ status = "okay";
+ pinctrl-0 = <&i2c_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb1_phy {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&ir {
+ linux,rc-map-name = "rc-wetek-play2";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-gx-u-boot.dtsi"
+
+ðmac {
+ snps,reset-gpio = <&gpio GPIOZ_14 0>;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-active-low;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 Andreas Färber
+ * Copyright (c) 2016 BayLibre, Inc.
+ * Author: Kevin Hilman <khilman@kernel.org>
+ */
+
+#include "meson-gxbb.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-power {
+ /* red in suspend or power-off */
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_POWER;
+ gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ panic-indicator;
+ };
+ };
+
+ usb_pwr: regulator-usb-pwrs {
+ compatible = "regulator-fixed";
+
+ regulator-name = "USB_PWR";
+
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ cvbs-connector {
+ compatible = "composite-video-connector";
+
+ port {
+ cvbs_connector_in: endpoint {
+ remote-endpoint = <&cvbs_vdac_out>;
+ };
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+};
+
+&cec_AO {
+ status = "okay";
+ pinctrl-0 = <&ao_cec_pins>;
+ pinctrl-names = "default";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
+};
+
+ðmac {
+ status = "okay";
+ pinctrl-0 = <ð_rgmii_pins>;
+ pinctrl-names = "default";
+
+ phy-handle = <ð_phy0>;
+ phy-mode = "rgmii";
+
+ amlogic,tx-delay-ns = <2>;
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eth_phy0: ethernet-phy@0 {
+ /* Realtek RTL8211F (0x001cc916) */
+ reg = <0>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <80000>;
+ reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
+
+ interrupt-parent = <&gpio_intc>;
+ /* MAC_INTR on GPIOZ_15 */
+ interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&vddio_ao18>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_ef {
+ status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&clkc CLKID_FCLK_DIV4>;
+ clock-names = "clkin0";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "okay";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+
+ non-removable;
+ disable-wp;
+
+ /* WiFi firmware requires power to be kept while in suspend */
+ keep-power-in-suspend;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vcc_3v3>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_A {
+ status = "okay";
+ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb0_phy {
+ status = "okay";
+ phy-supply = <&usb_pwr>;
+};
+
+&usb0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-gxl-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-gxm.dtsi"
+#include "meson-gx-p23x-q20x.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ compatible = "azw,gt1-ultimate", "amlogic,s912", "amlogic,meson-gxm";
+ model = "Beelink GT1 Ultimate";
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-white {
+ color = <LED_COLOR_ID_WHITE>;
+ function = LED_FUNCTION_POWER;
+ gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ panic-indicator;
+ };
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1710000>;
+
+ button-function {
+ label = "update";
+ linux,code = <KEY_VENDOR>;
+ press-threshold-microvolt = <10000>;
+ };
+ };
+};
+
+ðmac {
+ pinctrl-0 = <ð_pins>;
+ pinctrl-names = "default";
+ phy-handle = <&external_phy>;
+ amlogic,tx-delay-ns = <2>;
+ phy-mode = "rgmii";
+};
+
+&external_mdio {
+ external_phy: ethernet-phy@0 {
+ /* Realtek RTL8211F (0x001cc916) */
+ reg = <0>;
+ max-speed = <1000>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <80000>;
+ reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
+
+ interrupt-parent = <&gpio_intc>;
+ /* MAC_INTR on GPIOZ_15 */
+ interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&ir {
+ linux,rc-map-name = "rc-beelink-gs1";
+};
+
+&sd_emmc_a {
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+&uart_A {
+ status = "okay";
+ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+ max-speed = <2000000>;
+ clocks = <&wifi32k>;
+ clock-names = "lpo";
+ };
+};
--- /dev/null
+
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-sm1-u-boot.dtsi"
+
+ðmac {
+ snps,reset-gpio = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-active-low;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 BayLibre SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include "meson-sm1-bananapi.dtsi"
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ compatible = "bananapi,bpi-m2-pro", "amlogic,sm1";
+ model = "Banana Pi BPI-M2-PRO";
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "BPI-M2-PRO";
+ audio-aux-devs = <&tdmout_b>;
+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-3 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+ };
+ };
+
+ /* hdmi glue */
+ dai-link-4 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
+&tdmif_b {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
/dts-v1/;
-#include "meson-sm1.dtsi"
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include "meson-sm1-bananapi.dtsi"
#include <dt-bindings/sound/meson-g12a-toacodec.h>
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
compatible = "bananapi,bpi-m5", "amlogic,sm1";
model = "Banana Pi BPI-M5";
- adc_keys {
- compatible = "adc-keys";
- io-channels = <&saradc 2>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1800000>;
-
- key {
- label = "SW3";
- linux,code = <BTN_3>;
- press-threshold-microvolt = <1700000>;
- };
- };
-
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
/* TOFIX: handle CVBS_DET on SARADC channel 0 */
cvbs-connector {
compatible = "composite-video-connector";
};
};
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- key {
- label = "SW1";
- linux,code = <BTN_1>;
- gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
- interrupt-parent = <&gpio_intc>;
- interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
- };
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_tx_tmds_out>;
- };
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- green {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_STATUS;
- gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
- };
-
- blue {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_STATUS;
- gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x40000000>;
- };
-
- emmc_1v8: regulator-emmc_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "EMMC_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- };
-
- dc_in: regulator-dc_in {
- compatible = "regulator-fixed";
- regulator-name = "DC_IN";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- vddio_c: regulator-vddio_c {
- compatible = "regulator-gpio";
- regulator-name = "VDDIO_C";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-always-on;
-
- gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_DRAIN>;
- gpios-states = <1>;
-
- states = <1800000 0>,
- <3300000 1>;
- };
-
- tflash_vdd: regulator-tflash_vdd {
- compatible = "regulator-fixed";
- regulator-name = "TFLASH_VDD";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&dc_in>;
- gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
- enable-active-high;
- regulator-always-on;
- };
-
- vddao_1v8: regulator-vddao_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- };
-
- vddao_3v3: regulator-vddao_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&dc_in>;
- regulator-always-on;
- };
-
- vddcpu: regulator-vddcpu {
- /*
- * SY8120B1ABC DC/DC Regulator.
- */
- compatible = "pwm-regulator";
-
- regulator-name = "VDDCPU";
- regulator-min-microvolt = <690000>;
- regulator-max-microvolt = <1050000>;
-
- vin-supply = <&dc_in>;
-
- pwms = <&pwm_AO_cd 1 1250 0>;
- pwm-dutycycle-range = <100 0>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* USB Hub Power Enable */
- vl_pwr_en: regulator-vl_pwr_en {
- compatible = "regulator-fixed";
- regulator-name = "VL_PWR_EN";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_in>;
-
- gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
sound {
compatible = "amlogic,axg-sound-card";
model = "BPI-M5";
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
- status = "okay";
dai-link-0 {
sound-dai = <&frddr_a>;
status = "okay";
};
-&arb {
- status = "okay";
-};
&clkc_audio {
status = "okay";
};
-&cpu0 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu1 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU1_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu2 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU2_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu3 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU3_CLK>;
- clock-latency = <50000>;
-};
-
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
remote-endpoint = <&cvbs_connector_in>;
};
};
-&ext_mdio {
- external_phy: ethernet-phy@0 {
- /* Realtek RTL8211F (0x001cc916) */
- reg = <0>;
- max-speed = <1000>;
-
- interrupt-parent = <&gpio_intc>;
- /* MAC_INTR on GPIOZ_14 */
- interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-ðmac {
- pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
- pinctrl-names = "default";
- status = "okay";
- phy-mode = "rgmii-txid";
- phy-handle = <&external_phy>;
-};
-
&frddr_a {
status = "okay";
};
status = "okay";
};
-&gpio {
- gpio-line-names =
- /* GPIOZ */
- "ETH_MDIO", /* GPIOZ_0 */
- "ETH_MDC", /* GPIOZ_1 */
- "ETH_RXCLK", /* GPIOZ_2 */
- "ETH_RX_DV", /* GPIOZ_3 */
- "ETH_RXD0", /* GPIOZ_4 */
- "ETH_RXD1", /* GPIOZ_5 */
- "ETH_RXD2", /* GPIOZ_6 */
- "ETH_RXD3", /* GPIOZ_7 */
- "ETH_TXCLK", /* GPIOZ_8 */
- "ETH_TXEN", /* GPIOZ_9 */
- "ETH_TXD0", /* GPIOZ_10 */
- "ETH_TXD1", /* GPIOZ_11 */
- "ETH_TXD2", /* GPIOZ_12 */
- "ETH_TXD3", /* GPIOZ_13 */
- "ETH_INTR", /* GPIOZ_14 */
- "ETH_NRST", /* GPIOZ_15 */
- /* GPIOH */
- "HDMI_SDA", /* GPIOH_0 */
- "HDMI_SCL", /* GPIOH_1 */
- "HDMI_HPD", /* GPIOH_2 */
- "HDMI_CEC", /* GPIOH_3 */
- "VL-RST_N", /* GPIOH_4 */
- "CON1-P36", /* GPIOH_5 */
- "VL-PWREN", /* GPIOH_6 */
- "WiFi_3V3_1V8", /* GPIOH_7 */
- "TFLASH_VDD_EN", /* GPIOH_8 */
- /* BOOT */
- "eMMC_D0", /* BOOT_0 */
- "eMMC_D1", /* BOOT_1 */
- "eMMC_D2", /* BOOT_2 */
- "eMMC_D3", /* BOOT_3 */
- "eMMC_D4", /* BOOT_4 */
- "eMMC_D5", /* BOOT_5 */
- "eMMC_D6", /* BOOT_6 */
- "eMMC_D7", /* BOOT_7 */
- "eMMC_CLK", /* BOOT_8 */
- "",
- "eMMC_CMD", /* BOOT_10 */
- "",
- "eMMC_RST#", /* BOOT_12 */
- "eMMC_DS", /* BOOT_13 */
- /* GPIOC */
- "SD_D0_B", /* GPIOC_0 */
- "SD_D1_B", /* GPIOC_1 */
- "SD_D2_B", /* GPIOC_2 */
- "SD_D3_B", /* GPIOC_3 */
- "SD_CLK_B", /* GPIOC_4 */
- "SD_CMD_B", /* GPIOC_5 */
- "CARD_EN_DET", /* GPIOC_6 */
- "",
- /* GPIOA */
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "",
- "CON1-P27", /* GPIOA_14 */
- "CON1-P28", /* GPIOA_15 */
- /* GPIOX */
- "CON1-P16", /* GPIOX_0 */
- "CON1-P18", /* GPIOX_1 */
- "CON1-P22", /* GPIOX_2 */
- "CON1-P11", /* GPIOX_3 */
- "CON1-P13", /* GPIOX_4 */
- "CON1-P07", /* GPIOX_5 */
- "CON1-P33", /* GPIOX_6 */
- "CON1-P15", /* GPIOX_7 */
- "CON1-P19", /* GPIOX_8 */
- "CON1-P21", /* GPIOX_9 */
- "CON1-P24", /* GPIOX_10 */
- "CON1-P23", /* GPIOX_11 */
- "CON1-P08", /* GPIOX_12 */
- "CON1-P10", /* GPIOX_13 */
- "CON1-P29", /* GPIOX_14 */
- "CON1-P31", /* GPIOX_15 */
- "CON1-P26", /* GPIOX_16 */
- "CON1-P03", /* GPIOX_17 */
- "CON1-P05", /* GPIOX_18 */
- "CON1-P32"; /* GPIOX_19 */
-
- /*
- * WARNING: The USB Hub on the BPI-M5 needs a reset signal
- * to be turned high in order to be detected by the USB Controller
- * This signal should be handled by a USB specific power sequence
- * in order to reset the Hub when USB bus is powered down.
- */
- usb-hub {
- gpio-hog;
- gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "usb-hub-reset";
- };
-};
-
-&gpio_ao {
- gpio-line-names =
- /* GPIOAO */
- "DEBUG TX", /* GPIOAO_0 */
- "DEBUG RX", /* GPIOAO_1 */
- "SYS_LED2", /* GPIOAO_2 */
- "UPDATE_KEY", /* GPIOAO_3 */
- "CON1-P40", /* GPIOAO_4 */
- "IR_IN", /* GPIOAO_5 */
- "TF_3V3N_1V8_EN", /* GPIOAO_6 */
- "CON1-P35", /* GPIOAO_7 */
- "CON1-P12", /* GPIOAO_8 */
- "CON1-P37", /* GPIOAO_9 */
- "CON1-P38", /* GPIOAO_10 */
- "SYS_LED", /* GPIOAO_11 */
- /* GPIOE */
- "VDDEE_PWM", /* GPIOE_0 */
- "VDDCPU_PWM", /* GPIOE_1 */
- "TF_PWR_EN"; /* GPIOE_2 */
-};
-
-&hdmi_tx {
- status = "okay";
- pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
- pinctrl-names = "default";
- hdmi-supply = <&dc_in>;
-};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
-
-&ir {
- status = "okay";
- pinctrl-0 = <&remote_input_ao_pins>;
- pinctrl-names = "default";
-};
-
-&pwm_AO_cd {
- pinctrl-0 = <&pwm_ao_d_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin1";
- status = "okay";
-};
-
-&saradc {
- status = "okay";
- vref-supply = <&vddao_1v8>;
-};
-
-/* SD card */
-&sd_emmc_b {
- status = "okay";
- pinctrl-0 = <&sdcard_c_pins>;
- pinctrl-1 = <&sdcard_clk_gate_c_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <50000000>;
- disable-wp;
-
- /* TOFIX: SD card is barely usable in SDR modes */
-
- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
- vmmc-supply = <&tflash_vdd>;
- vqmmc-supply = <&vddio_c>;
-};
-
-/* eMMC */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- max-frequency = <200000000>;
- disable-wp;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&emmc_1v8>;
-};
-
&tdmif_b {
status = "okay";
};
&toddr_c {
status = "okay";
};
-
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
-&usb {
- status = "okay";
-};
-
-&usb2_phy0 {
- phy-supply = <&dc_in>;
-};
-
-&usb2_phy1 {
- /* Enable the hub which is connected to this port */
- phy-supply = <&vl_pwr_en>;
-};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 BayLibre SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-sm1.dtsi"
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+
+/ {
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 2>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+
+ button-sw3 {
+ label = "SW3";
+ linux,code = <BTN_3>;
+ press-threshold-microvolt = <1700000>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key {
+ label = "SW1";
+ linux,code = <BTN_1>;
+ gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&gpio_intc>;
+ interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-green {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
+ };
+
+ led-blue {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ emmc_1v8: regulator-emmc_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "EMMC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ dc_in: regulator-dc_in {
+ compatible = "regulator-fixed";
+ regulator-name = "DC_IN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ vddio_c: regulator-vddio_c {
+ compatible = "regulator-gpio";
+ regulator-name = "VDDIO_C";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ enable-gpios = <&gpio_ao GPIOE_2 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ regulator-always-on;
+
+ gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_DRAIN>;
+ gpios-states = <1>;
+
+ states = <1800000 0>,
+ <3300000 1>;
+ };
+
+ tflash_vdd: regulator-tflash_vdd {
+ compatible = "regulator-fixed";
+ regulator-name = "TFLASH_VDD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_in>;
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ vddao_1v8: regulator-vddao_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_in>;
+ regulator-always-on;
+ };
+
+ vddcpu: regulator-vddcpu {
+ /*
+ * SY8120B1ABC DC/DC Regulator.
+ */
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU";
+ regulator-min-microvolt = <690000>;
+ regulator-max-microvolt = <1050000>;
+
+ pwm-supply = <&dc_in>;
+
+ pwms = <&pwm_AO_cd 1 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* USB Hub Power Enable */
+ vl_pwr_en: regulator-vl_pwr_en {
+ compatible = "regulator-fixed";
+ regulator-name = "VL_PWR_EN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_in>;
+
+ gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&arb {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu1 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU1_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu2 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU2_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu3 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU3_CLK>;
+ clock-latency = <50000>;
+};
+
+&ext_mdio {
+ external_phy: ethernet-phy@0 {
+ /* Realtek RTL8211F (0x001cc916) */
+ reg = <0>;
+ max-speed = <1000>;
+
+ interrupt-parent = <&gpio_intc>;
+ /* MAC_INTR on GPIOZ_14 */
+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+ðmac {
+ pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ phy-mode = "rgmii-txid";
+ phy-handle = <&external_phy>;
+};
+
+&gpio {
+ gpio-line-names =
+ /* GPIOZ */
+ "ETH_MDIO", /* GPIOZ_0 */
+ "ETH_MDC", /* GPIOZ_1 */
+ "ETH_RXCLK", /* GPIOZ_2 */
+ "ETH_RX_DV", /* GPIOZ_3 */
+ "ETH_RXD0", /* GPIOZ_4 */
+ "ETH_RXD1", /* GPIOZ_5 */
+ "ETH_RXD2", /* GPIOZ_6 */
+ "ETH_RXD3", /* GPIOZ_7 */
+ "ETH_TXCLK", /* GPIOZ_8 */
+ "ETH_TXEN", /* GPIOZ_9 */
+ "ETH_TXD0", /* GPIOZ_10 */
+ "ETH_TXD1", /* GPIOZ_11 */
+ "ETH_TXD2", /* GPIOZ_12 */
+ "ETH_TXD3", /* GPIOZ_13 */
+ "ETH_INTR", /* GPIOZ_14 */
+ "ETH_NRST", /* GPIOZ_15 */
+ /* GPIOH */
+ "HDMI_SDA", /* GPIOH_0 */
+ "HDMI_SCL", /* GPIOH_1 */
+ "HDMI_HPD", /* GPIOH_2 */
+ "HDMI_CEC", /* GPIOH_3 */
+ "VL-RST_N", /* GPIOH_4 */
+ "CON1-P36", /* GPIOH_5 */
+ "VL-PWREN", /* GPIOH_6 */
+ "WiFi_3V3_1V8", /* GPIOH_7 */
+ "TFLASH_VDD_EN", /* GPIOH_8 */
+ /* BOOT */
+ "eMMC_D0", /* BOOT_0 */
+ "eMMC_D1", /* BOOT_1 */
+ "eMMC_D2", /* BOOT_2 */
+ "eMMC_D3", /* BOOT_3 */
+ "eMMC_D4", /* BOOT_4 */
+ "eMMC_D5", /* BOOT_5 */
+ "eMMC_D6", /* BOOT_6 */
+ "eMMC_D7", /* BOOT_7 */
+ "eMMC_CLK", /* BOOT_8 */
+ "",
+ "eMMC_CMD", /* BOOT_10 */
+ "",
+ "eMMC_RST#", /* BOOT_12 */
+ "eMMC_DS", /* BOOT_13 */
+ "", "",
+ /* GPIOC */
+ "SD_D0_B", /* GPIOC_0 */
+ "SD_D1_B", /* GPIOC_1 */
+ "SD_D2_B", /* GPIOC_2 */
+ "SD_D3_B", /* GPIOC_3 */
+ "SD_CLK_B", /* GPIOC_4 */
+ "SD_CMD_B", /* GPIOC_5 */
+ "CARD_EN_DET", /* GPIOC_6 */
+ "",
+ /* GPIOA */
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "",
+ "CON1-P27", /* GPIOA_14 */
+ "CON1-P28", /* GPIOA_15 */
+ /* GPIOX */
+ "CON1-P16", /* GPIOX_0 */
+ "CON1-P18", /* GPIOX_1 */
+ "CON1-P22", /* GPIOX_2 */
+ "CON1-P11", /* GPIOX_3 */
+ "CON1-P13", /* GPIOX_4 */
+ "CON1-P07", /* GPIOX_5 */
+ "CON1-P33", /* GPIOX_6 */
+ "CON1-P15", /* GPIOX_7 */
+ "CON1-P19", /* GPIOX_8 */
+ "CON1-P21", /* GPIOX_9 */
+ "CON1-P24", /* GPIOX_10 */
+ "CON1-P23", /* GPIOX_11 */
+ "CON1-P08", /* GPIOX_12 */
+ "CON1-P10", /* GPIOX_13 */
+ "CON1-P29", /* GPIOX_14 */
+ "CON1-P31", /* GPIOX_15 */
+ "CON1-P26", /* GPIOX_16 */
+ "CON1-P03", /* GPIOX_17 */
+ "CON1-P05", /* GPIOX_18 */
+ "CON1-P32"; /* GPIOX_19 */
+
+ /*
+ * WARNING: The USB Hub needs a reset signal to be turned high in
+ * order to be detected by the USB Controller. This signal should
+ * be handled by a USB specific power sequence to reset the Hub
+ * when the USB bus is powered down.
+ */
+ usb-hub-hog {
+ gpio-hog;
+ gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "usb-hub-reset";
+ };
+};
+
+&gpio_ao {
+ gpio-line-names =
+ /* GPIOAO */
+ "DEBUG TX", /* GPIOAO_0 */
+ "DEBUG RX", /* GPIOAO_1 */
+ "SYS_LED2", /* GPIOAO_2 */
+ "UPDATE_KEY", /* GPIOAO_3 */
+ "CON1-P40", /* GPIOAO_4 */
+ "IR_IN", /* GPIOAO_5 */
+ "TF_3V3N_1V8_EN", /* GPIOAO_6 */
+ "CON1-P35", /* GPIOAO_7 */
+ "CON1-P12", /* GPIOAO_8 */
+ "CON1-P37", /* GPIOAO_9 */
+ "CON1-P38", /* GPIOAO_10 */
+ "SYS_LED", /* GPIOAO_11 */
+ /* GPIOE */
+ "VDDEE_PWM", /* GPIOE_0 */
+ "VDDCPU_PWM", /* GPIOE_1 */
+ "TF_PWR_EN"; /* GPIOE_2 */
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&dc_in>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_AO_cd {
+ pinctrl-0 = <&pwm_ao_d_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin1";
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddao_1v8>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ /* TOFIX: SD card is barely usable in SDR modes */
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&tflash_vdd>;
+ vqmmc-supply = <&vddio_c>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&emmc_1v8>;
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb2_phy0 {
+ phy-supply = <&dc_in>;
+};
+
+&usb2_phy1 {
+ /* Enable the hub which is connected to this port */
+ phy-supply = <&vl_pwr_en>;
+};
S: Maintained
L: u-boot-amlogic@groups.io
F: board/amlogic/beelink-s922x/
+F: configs/beelink-gsking-x_defconfig
F: configs/beelink-gtking_defconfig
F: configs/beelink-gtkingpro_defconfig
-F: configs/beelink-gsking-x_defconfig
+F: doc/board/amlogic/beelink-gskingx.rst
F: doc/board/amlogic/beelink-gtking.rst
F: doc/board/amlogic/beelink-gtkingpro.rst
F: configs/nanopi-k2_defconfig
F: configs/odroid-c2_defconfig
F: configs/p200_defconfig
+F: configs/wetek-hub_defconfig
+F: configs/wetek-play2_defconfig
F: doc/board/amlogic/p200.rst
F: doc/board/amlogic/nanopi-k2.rst
F: doc/board/amlogic/odroid-c2.rst
+F: doc/board/amlogic/wetek-hub.rst
+F: doc/board/amlogic/wetek-play2.rst
L: u-boot-amlogic@groups.io
F: board/amlogic/q200/
F: include/configs/q200.h
+F: configs/beelink-gt1-ultimate_defconfig
F: configs/khadas-vim2_defconfig
F: configs/libretech-s905d-pc_defconfig
F: configs/libretech-s912-pc_defconfig
F: configs/wetek-core2_defconfig
+F: doc/board/amlogic/beelink-gt1-ultimate.rst
F: doc/board/amlogic/khadas-vim2.rst
F: doc/board/amlogic/wetek-core2.rst
L: u-boot-amlogic@groups.io
F: board/amlogic/u200/
F: configs/u200_defconfig
+F: configs/bananapi-m2pro_defconfig
F: configs/bananapi-m5_defconfig
F: configs/radxa-zero_defconfig
F: doc/board/amlogic/u200.rst
+F: doc/board/amlogic/bananapi-m2pro.rst
+F: doc/board/amlogic/bananapi-m5.rst
F: doc/board/amlogic/radxa-zero.rst
S: Maintained
L: u-boot-amlogic@groups.io
F: board/amlogic/w400/
+F: configs/bananapi-cm4-cm4io_defconfig
+F: configs/bananapi-m2s_defconfig
+F: configs/radxa-zero2_defconfig
F: doc/board/amlogic/w400.rst
+F: doc/board/amlogic/bananapi-cm4io.rst
+F: doc/board/amlogic/bananapi-m2s.rst
+F: doc/board/amlogic/radxa-zero2.rst
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-bananapi-cm4-cm4io"
+CONFIG_MESON_G12A=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING="bpi-cm4io"
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_DEBUG_UART=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
+CONFIG_REMAKE_ELF=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_SYS_MAXARGS=32
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MESON_G12A=y
+CONFIG_PCI=y
+CONFIG_PCIE_DW_MESON=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SYSINFO=y
+CONFIG_SYSINFO_SMBIOS=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_OF_LIBFDT_OVERLAY=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-bananapi-m2-pro"
+CONFIG_MESON_G12A=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING="bpi-m2-pro"
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_DEBUG_UART=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
+CONFIG_REMAKE_ELF=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_SYS_MAXARGS=32
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MESON_G12A=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_OF_LIBFDT_OVERLAY=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-a311d-bananapi-m2s"
+CONFIG_MESON_G12A=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" bpi-m2s"
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
+CONFIG_REMAKE_ELF=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_SYS_MAXARGS=32
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_AHCI_PCI=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MESON_G12A=y
+CONFIG_PCI=y
+CONFIG_PCIE_DW_MESON=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_OF_LIBFDT_OVERLAY=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-gxm-gt1-ultimate"
+CONFIG_DM_RESET=y
+CONFIG_MESON_GXM=y
+CONFIG_DEBUG_UART_BASE=0xc81004c0
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" beelink-gt1"
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_SYS_MAXARGS=32
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SARADC_MESON=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MMIOREG=y
+CONFIG_MESON_GXL_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_GXL=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_GX_VPU_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_GXL=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_POWER_DOMAIN=y
-CONFIG_MESON_GX_VPU_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-radxa-zero2"
+CONFIG_MESON_G12A=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" radxa-zero2"
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_DEBUG_UART=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
+CONFIG_REMAKE_ELF=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_SYS_MAXARGS=32
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+# CONFIG_PHY_REALTEK is not set
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+# CONFIG_ETH_DESIGNWARE_MESON8B is not set
+CONFIG_MDIO_MUX_MESON_G12A=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_POWER_DOMAIN=y
-CONFIG_MESON_GX_VPU_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DEBUG_UART_ANNOUNCE=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_TEXT_BASE=0x01000000
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEBUG_UART_BASE=0xc81004c0
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" wetek-hub"
+CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-wetek-hub"
+CONFIG_DEBUG_UART=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SARADC_MESON=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_PHY=y
+CONFIG_MESON_GXBB_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_GXBB=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SYSINFO=y
+CONFIG_SYSINFO_SMBIOS=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_OF_LIBFDT_OVERLAY=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_TEXT_BASE=0x01000000
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEBUG_UART_BASE=0xc81004c0
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" wetek-play2"
+CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-wetek-play2"
+CONFIG_DEBUG_UART=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SARADC_MESON=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_PHY=y
+CONFIG_MESON_GXBB_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_GXBB=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SYSINFO=y
+CONFIG_SYSINFO_SMBIOS=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_OF_LIBFDT_OVERLAY=y
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for BananaPi CM4 with CM4IO (A311D)
+==========================================
+
+BPI-CM4 is a system-on-module board manufactured by Sinovoip. It follows the Raspberry Pi
+CM4 interface specification but with a single HDMI port and a single DSI output:
+
+ - Amlogic A311D Arm Cortex-A53 dual-core + Cortex-A73 quad-core SoC
+ - 4GB DDR4 SDRAM
+ - 16GB eMMC
+ - NPU
+ - HDMI 2.1 display
+ - Gigabit Ethernet
+ - RTL8822CS WiFi (a/b/g/n/ac) + BT 5.0
+
+BPI-CM4IO is a carrier board for the BPI-CM4 module with the following specification:
+
+ - CM4 interface
+ - HDMI interface
+ - MIPI CSI interface
+ - MIPI DSI interface
+ - Ethernet interface
+ - PCIe interface
+ - SD (micro)
+ - SIM (micro)
+ - 26-pin GPIO
+ - UART serial
+ - 1x USB-C (power)
+ - 2x USB 2.0
+
+Schematics are available from the manufacturer: https://wiki.banana-pi.org/Banana_Pi_BPI-CM4
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-none-elf-
+ $ make bananapi-cm4io_defconfig
+ $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh bananapi-cm4io /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
+
+.. code-block:: bash
+
+ $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+
+ $ DIR=bananapi-cm4io
+ $ git clone --depth 1 https://github.com/Dangku/amlogic-u-boot.git -b khadas-g12b-v2015.01-m2s $DIR
+
+ $ cd $DIR
+ $ make bananapi_cm4_defconfig
+ $ make
+ $ export UBDIR=$PWD
+
+Go back to the mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+ $ mkdir fip
+
+ $ wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
+ $ cp $UBDIR/build/scp_task/bl301.bin fip/
+ $ cp $UBDIR/build/board/bananapi/bananpi_cm4/firmware/acs.bin fip/
+ $ cp $UBDIR/fip/g12a/bl2.bin fip/
+ $ cp $UBDIR/fip/g12a/bl30.bin fip/
+ $ cp $UBDIR/fip/g12a/bl31.img fip/
+ $ cp $UBDIR/fip/g12a/ddr3_1d.fw fip/
+ $ cp $UBDIR/fip/g12a/ddr4_1d.fw fip/
+ $ cp $UBDIR/fip/g12a/ddr4_2d.fw fip/
+ $ cp $UBDIR/fip/g12a/diag_lpddr4.fw fip/
+ $ cp $UBDIR/fip/g12a/lpddr3_1d.fw fip/
+ $ cp $UBDIR/fip/g12a/lpddr4_1d.fw fip/
+ $ cp $UBDIR/fip/g12a/lpddr4_2d.fw fip/
+ $ cp $UBDIR/fip/g12a/piei.fw fip/
+ $ cp $UBDIR/fip/g12a/aml_ddr.fw fip/
+ $ cp u-boot.bin fip/bl33.bin
+
+ $ sh fip/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ $ sh fip/blx_fix.sh \
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ $ $UBDIR/fip/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
+ $ $UBDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
+ $ $UBDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
+ $ $UBDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33 --compress lz4
+ $ $UBDIR/fip/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
+ --output fip/bl2.n.bin.sig
+ $ $UBDIR/fip/g12b/aml_encrypt_g12b --bootmk \
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --ddrfw9 fip/lpddr3_1d.fw \
+ --level v3
+
+Then write the image to SD or eMMC with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/boot_device
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for BananaPi BPI-M2-PRO (S905X3)
+=======================================
+
+BananaPi BPI-M2-PRO is a Single Board Computer manufactured by Sinovoip with the
+following specification:
+
+ - Amlogic S905X3 Arm Cortex-A55 quad-core SoC
+ - 2GB DDR4 SDRAM
+ - 16GB eMMC
+ - Gigabit Ethernet
+ - RTL8821CU USB WiFi (a/b/g/n/ac) + BT 5.0
+ - HDMI 2.1 display
+ - 40-pin GPIO header
+ - 2x USB 3.0 Host
+ - 1x DC Jack (power)
+ - microSD
+ - UART serial
+ - Infrared receiver
+
+Schematics are available from the manufacturer: https://wiki.banana-pi.org/Banana_Pi_BPI-M2_Pro
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-none-elf-
+ $ make bananapi-m2pro_defconfig
+ $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh bananapi-m2pro /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
+
+.. code-block:: bash
+
+ $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+
+ $ DIR=bananapi-m2pro
+ $ git clone --depth 1 https://github.com/Dangku/amlogic-u-boot.git -b odroidg12-v2015.01-c4-m5 $DIR
+
+ $ cd $DIR
+ $ make bananapi_m2pro_defconfig
+ $ make
+ $ export UBOOTDIR=$PWD
+
+Go back to the mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+ $ mkdir fip
+
+ $ wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
+ $ cp $UBOOTDIR/build/scp_task/bl301.bin fip/
+ $ cp $UBOOTDIR/build/board/bananapi/bananpi_m5/firmware/acs.bin fip/
+ $ cp $UBOOTDIR/fip/g12a/bl2.bin fip/
+ $ cp $UBOOTDIR/fip/g12a/bl30.bin fip/
+ $ cp $UBOOTDIR/fip/g12a/bl31.img fip/
+ $ cp $UBOOTDIR/fip/g12a/ddr3_1d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/ddr4_1d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/ddr4_2d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/diag_lpddr4.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/lpddr3_1d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/lpddr4_1d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/lpddr4_2d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/piei.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/aml_ddr.fw fip/
+ $ cp u-boot.bin fip/bl33.bin
+
+ $ sh fip/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ $ sh fip/blx_fix.sh \
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33 --compress lz4
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
+ --output fip/bl2.n.bin.sig
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bootmk \
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --ddrfw9 fip/lpddr3_1d.fw \
+ --level v3
+
+Then write the image to SD or eMMC with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/boot_device
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for BananaPi M2S (A311D & S922X)
+=======================================
+
+BananaPi BPI-M2S ships is a Single Board Computer manufactured by Sinovoip that ships in
+two variants with Amlogic S922X or A311D SoC and the following common specification:
+
+- 16GB eMMC
+- HDMI 2.1a video
+- 2x 10/100/1000 Base-T Ethernet (1x RTL8211F, 1x RTL811H)
+- 2x USB 2.0 ports
+- 2x Status LED's (green/blue)
+- 1x Power/Reset button
+- 1x micro SD card slot
+- 40-pin GPIO header
+- PWM fan header
+- UART header
+
+The S992X variant has:
+- 2GB LPDDR4 RAM
+
+The A311D variant has:
+
+- 4GB LPDDR4 RAM
+- NPU (5.0 TOPS)
+- MIPI DSI header
+- MIPI CSI header
+
+An optional RTL8822CS SDIO WiFi/BT mezzanine is available for both board variants.
+
+Schematics are available from the manufacturer: https://wiki.banana-pi.org/Banana_Pi_BPI-M2S
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-none-elf-
+ $ make bananapi-m2s_defconfig
+ $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh bananapi-m2s /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
+
+.. code-block:: bash
+
+ $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+
+ $ DIR=bananapi-m2s
+ $ git clone --depth 1 https://github.com/Dangku/amlogic-u-boot.git -b khadas-g12b-v2015.01-m2s $DIR
+
+ $ cd $DIR
+ $ make bananapi_m2s_defconfig
+ $ make
+ $ export UBDIR=$PWD
+
+Go back to the mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+ $ mkdir fip
+
+ $ wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
+ $ cp $UBDIR/build/scp_task/bl301.bin fip/
+ $ cp $UBDIR/build/board/bananapi/bananpi_m2s/firmware/acs.bin fip/
+ $ cp $UBDIR/fip/g12a/bl2.bin fip/
+ $ cp $UBDIR/fip/g12a/bl30.bin fip/
+ $ cp $UBDIR/fip/g12a/bl31.img fip/
+ $ cp $UBDIR/fip/g12a/ddr3_1d.fw fip/
+ $ cp $UBDIR/fip/g12a/ddr4_1d.fw fip/
+ $ cp $UBDIR/fip/g12a/ddr4_2d.fw fip/
+ $ cp $UBDIR/fip/g12a/diag_lpddr4.fw fip/
+ $ cp $UBDIR/fip/g12a/lpddr3_1d.fw fip/
+ $ cp $UBDIR/fip/g12a/lpddr4_1d.fw fip/
+ $ cp $UBDIR/fip/g12a/lpddr4_2d.fw fip/
+ $ cp $UBDIR/fip/g12a/piei.fw fip/
+ $ cp $UBDIR/fip/g12a/aml_ddr.fw fip/
+ $ cp u-boot.bin fip/bl33.bin
+
+ $ sh fip/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ $ sh fip/blx_fix.sh \
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ $ $UBDIR/fip/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
+ $ $UBDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
+ $ $UBDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
+ $ $UBDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33 --compress lz4
+ $ $UBDIR/fip/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
+ --output fip/bl2.n.bin.sig
+ $ $UBDIR/fip/g12b/aml_encrypt_g12b --bootmk \
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --ddrfw9 fip/lpddr3_1d.fw \
+ --level v3
+
+Then write the image to SD or eMMC with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/boot_device
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for BananaPi BPI-M5 (S905X3)
+===================================
+
+BananaPi BPI-M5 is a Single Board Computer manufactured by Sinovoip with the following
+specification:
+
+ - Amlogic S905X3 Arm Cortex-A55 quad-core SoC
+ - 4GB DDR4 SDRAM
+ - 16GB eMMC
+ - Gigabit Ethernet
+ - HDMI 2.1 display
+ - 40-pin GPIO header
+ - 4x USB 3.0 Host
+ - 1x USB-C (power)
+ - microSD
+ - UART serial
+ - Infrared receiver
+
+Schematics are available from the manufacturer: https://wiki.banana-pi.org/Banana_Pi_BPI-M5
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-none-elf-
+ $ make bananapi-m5_defconfig
+ $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh bananapi-m5 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
+
+.. code-block:: bash
+
+ $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+
+ $ DIR=bananapi-m5
+ $ git clone --depth 1 https://github.com/Dangku/amlogic-u-boot.git -b odroidg12-v2015.01-c4-m5 $DIR
+
+ $ cd $DIR
+ $ make bananapi_m5_defconfig
+ $ make
+ $ export UBOOTDIR=$PWD
+
+Go back to the mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+ $ mkdir fip
+
+ $ wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
+ $ cp $UBOOTDIR/build/scp_task/bl301.bin fip/
+ $ cp $UBOOTDIR/build/board/bananapi/bananpi_m5/firmware/acs.bin fip/
+ $ cp $UBOOTDIR/fip/g12a/bl2.bin fip/
+ $ cp $UBOOTDIR/fip/g12a/bl30.bin fip/
+ $ cp $UBOOTDIR/fip/g12a/bl31.img fip/
+ $ cp $UBOOTDIR/fip/g12a/ddr3_1d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/ddr4_1d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/ddr4_2d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/diag_lpddr4.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/lpddr3_1d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/lpddr4_1d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/lpddr4_2d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/piei.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/aml_ddr.fw fip/
+ $ cp u-boot.bin fip/bl33.bin
+
+ $ sh fip/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ $ sh fip/blx_fix.sh \
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33 --compress lz4
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
+ --output fip/bl2.n.bin.sig
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bootmk \
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --ddrfw9 fip/lpddr3_1d.fw \
+ --level v3
+
+Then write the image to SD or eMMC with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/boot_device
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Beelink GS-King-X (S922X)
+====================================
+
+The Shenzen AZW (Beelink) GS-King-X is based on the Amlogic W400 reference board with an
+S922X-H chip and the following specifications:
+
+- 4GB LPDDR4 RAM
+- 64GB eMMC storage
+- 10/100/1000 Base-T Ethernet
+- AP6356S Wireless (802.11 a/b/g/n/ac, BT 4.1)
+- HDMI 2.1 video
+- S/PDIF optical output
+- 2x ESS9018 audio DACs
+- 4x Ricor RT6862 audio amps
+- Analogue headphone output
+- 1x USB 2.0 OTG port
+- 3x USB 3.0 ports
+- IR receiver
+- 1x micro SD card slot (internal)
+- USB SATA controller with 2x 3.5" drive bays
+- 1x Power on/off button
+
+Beelink do not provide public schematics, but have been willing to share them with known
+distro developers to assist with development.
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-none-elf-
+ $ make beelink-gsking-x_defconfig
+ $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh beelink-s922x /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Beelink released an Amlogic "SDK" dump in their forums but the U-Boot sources included
+result in 2GB RAM detected. The following FIPs were generated with newer sources and
+detect 4GB RAM: https://github.com/LibreELEC/amlogic-boot-fip/tree/master/beelink-s922x
+
+.. code-block:: bash
+
+ $ wget https://github.com/LibreELEC/amlogic-boot-fip/archive/master.zip
+ $ unzip master.zip
+ $ export FIPDIR=$PWD/amlogic-boot-fip/beelink-s922x
+
+Go back to the mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+ $ mkdir fip
+ $ cp $FIPDIR/* fip/
+ $ cp u-boot.bin fip/bl33.bin
+
+ $ sh fip/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ $ sh fip/blx_fix.sh \
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ $ fip/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
+ $ fip/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
+ $ fip/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
+ $ fip/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33
+ $ fip/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
+ --output fip/bl2.n.bin.sig
+ $ fip/aml_encrypt_g12b --bootmk \
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --level v3
+
+Then write U-Boot to SD or eMMC with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/boot_device
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Beelink GT1 Ultimate (S912)
+======================================
+
+Beelink GT1 Ultimate is an Android STB manufactured by Shenzen AZW (Beelink) with the
+following specification:
+
+- 2GB or 3GB DDR3 RAM
+- 32GB eMMC
+- HDMI 2.1 video
+- S/PDIF optical output
+- 10/100/1000 Ethernet
+- AP6356S Wireless (802.11 a/b/g/n/ac, BT 4.2)
+- 3x USB 2.0 ports
+- IR receiver
+- 1x micro SD card slot
+- 1x Power LED (white)
+- 1x Reset button (internal)
+
+The GT1 (non-ultimate) board has QCA9377 WiFi/BT but is otherwise identical and should
+be capable of booting images prepared for the Ultimate box (NB: there are known clones
+of both boxes which may differ in specifications).
+
+Beelink do not provide public schematics, but have been willing to share them with known
+distro developers on request.
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+Â Â Â $ export CROSS_COMPILE=aarch64-none-elf-
+Â Â Â $ make beelink-gt1-ultimate_defconfig
+Â Â Â $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+Â Â Â $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+Â Â Â $ cd amlogic-boot-fip
+Â Â Â $ mkdir my-output-dir
+Â Â Â $ ./build-fip.sh beelink-gt1 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide firmware sources or tools needed to create the bootloader image
+and Beelink has not publicly shared the U-Boot sources needed to build the FIP binaries
+for signing. However you can download them from the amlogic-fip-repo.
+
+.. code-block:: bash
+
+Â Â Â $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+Â Â Â $ cd amlogic-boot-fip/beelink-gt1
+Â Â Â $ export FIPDIR=$PWD
+
+Go back to the mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+Â Â Â $ mkdir fip
+Â Â Â $ cp $FIPDIR/bl2.bin fip/
+Â Â Â $ cp $FIPDIR/acs.bin fip/
+Â Â Â $ cp $FIPDIR/bl21.bin fip/
+Â Â Â $ cp $FIPDIR/bl30.bin fip/
+Â Â Â $ cp $FIPDIR/bl301.bin fip/
+Â Â Â $ cp $FIPDIR/bl31.img fip/
+Â Â Â $ cp u-boot.bin fip/bl33.bin
+
+Â Â Â $ $FIPDIR/blx_fix.sh \
+Â Â Â Â Â Â Â Â Â Â Â Â Â fip/bl30.bin \
+Â Â Â Â Â Â Â Â Â Â Â Â Â fip/zero_tmp \
+Â Â Â Â Â Â Â Â Â Â Â Â Â fip/bl30_zero.bin \
+Â Â Â Â Â Â Â Â Â Â Â Â Â fip/bl301.bin \
+Â Â Â Â Â Â Â Â Â Â Â Â Â fip/bl301_zero.bin \
+Â Â Â Â Â Â Â Â Â Â Â Â Â fip/bl30_new.bin \
+Â Â Â Â Â Â Â Â Â Â Â Â Â bl30
+
+Â Â Â $ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+Â Â Â $ $FIPDIR/blx_fix.sh \
+Â Â Â Â Â Â Â Â Â Â Â Â Â fip/bl2_acs.bin \
+Â Â Â Â Â Â Â Â Â Â Â Â Â fip/zero_tmp \
+Â Â Â Â Â Â Â Â Â Â Â Â Â fip/bl2_zero.bin \
+Â Â Â Â Â Â Â Â Â Â Â Â Â fip/bl21.bin \
+Â Â Â Â Â Â Â Â Â Â Â Â Â fip/bl21_zero.bin \
+Â Â Â Â Â Â Â Â Â Â Â Â Â fip/bl2_new.bin \
+Â Â Â Â Â Â Â Â Â Â Â Â Â bl2
+
+Â Â Â $ $FIPDIR/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
+Â Â Â $ $FIPDIR/aml_encrypt_gxl --bl3enc --input fip/bl31.img
+Â Â Â $ $FIPDIR/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
+Â Â Â $ $FIPDIR/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
+Â Â Â $ $FIPDIR/aml_encrypt_gxl --bootmk \
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â --output fip/u-boot.bin \
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â --bl2 fip/bl2.n.bin.sig \
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â --bl30 fip/bl30_new.bin.enc \
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â --bl31 fip/bl31.img.enc \
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â --bl33 fip/bl33.bin.enc
+
+Then write U-Boot to SD or eMMC with:
+
+.. code-block:: bash
+
+Â Â Â $ DEV=/dev/boot_device
+Â Â Â $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+Â Â Â $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for Beelink GT-King
-==========================
+U-Boot for Beelink GT-King (S922X)
+==================================
-The Shenzen AZW (Beelink) GT-King is based on the Amlogic W400 reference
-board with an S922X-H chip.
+The Shenzen AZW (Beelink) GT-King is based on the Amlogic W400 reference board with an
+S922X-H chip and the following specifications:
- 4GB LPDDR4 RAM
- 64GB eMMC storage
- IR receiver
- 1x micro SD card slot
-Beelink do not provide public schematics, but have been willing
-to share them with known distro developers on request.
+Beelink do not provide public schematics, but have been willing to share them with known
+distro developers to assist with development.
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make beelink-gtking_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-Amlogic does not provide sources for the firmware and for tools needed
-to create the bootloader image. Beelink have provided the Amlogic "SDK"
-in their forums, but the u-boot sources included result in 2GB RAM being
-detected. The following FIPs were generated with newer private sources
-and give correct (4GB) RAM detection:
+.. code-block:: bash
-https://github.com/LibreELEC/amlogic-boot-fip/tree/master/beelink-s922x
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh beelink-s922x /path/to/u-boot/u-boot.bin my-output-dir
-NB: Beelink use a common board config for GT-King, GT-King Pro and the
-GS-King-X model, hence the "beelink-s922x" name.
+U-Boot Manual Signing
+---------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `beelink-s922x`
+Beelink released an Amlogic "SDK" dump in their forums, but the U-Boot sources included
+result in 2GB RAM detected. The following FIPs were generated with newer sources and
+detect 4GB RAM: https://github.com/LibreELEC/amlogic-boot-fip/tree/master/beelink-s922x
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ sh fip/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ sh fip/blx_fix.sh \
- fip/bl2.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/acs.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ fip/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
- --output fip/bl30_new.bin.g12a.enc \
- --level v3
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
$ fip/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
- --output fip/bl30_new.bin.enc \
- --level v3 --type bl30
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
$ fip/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
- --output fip/bl31.img.enc \
- --level v3 --type bl31
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
$ fip/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
- --output fip/bl33.bin.enc \
- --level v3 --type bl33
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33
$ fip/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
- --output fip/bl2.n.bin.sig
+ --output fip/bl2.n.bin.sig
$ fip/aml_encrypt_g12b --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc \
- --ddrfw1 fip/ddr4_1d.fw \
- --ddrfw2 fip/ddr4_2d.fw \
- --ddrfw3 fip/ddr3_1d.fw \
- --ddrfw4 fip/piei.fw \
- --ddrfw5 fip/lpddr4_1d.fw \
- --ddrfw6 fip/lpddr4_2d.fw \
- --ddrfw7 fip/diag_lpddr4.fw \
- --ddrfw8 fip/aml_ddr.fw \
- --level v3
-
-and then write the image to SD with:
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --level v3
+
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for Beelink GT-King Pro
-==============================
+U-Boot for Beelink GT-King Pro (S922X)
+======================================
-The Shenzen AZW (Beelink) GT-King Pro is based on the Amlogic W400 reference
-board with an S922X-H chip.
+The Shenzen AZW (Beelink) GT-King Pro is based on the Amlogic W400 reference board with
+an S922X-H chip and the following specifications:
- 4GB LPDDR4 RAM
- 64GB eMMC storage
- 1x SD card slot
- 1x Power on/off button
-Beelink do not provide public schematics, but have been willing
-to share them with known distro developers on request.
+Beelink do not provide public schematics, but have been willing to share them with known
+distro developers to assist with development.
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make beelink-gtkingpro_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-Amlogic does not provide sources for the firmware and for tools needed
-to create the bootloader image. Beelink have provided the Amlogic "SDK"
-in their forums, but the u-boot sources included result in 2GB RAM being
-detected. The following FIPs were generated with newer private sources
-and give correct (4GB) RAM detection:
+.. code-block:: bash
-https://github.com/LibreELEC/amlogic-boot-fip/tree/master/beelink-s922x
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh beelink-s922x /path/to/u-boot/u-boot.bin my-output-dir
-NB: Beelink use a common board config for GT-King, GT-King Pro and the
-GS-King-X model, hence the "beelink-s922x" name.
+U-Boot Manual Signing
+---------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `beelink-s922x`
+Beelink released an Amlogic "SDK" dump in their forums, but the U-Boot sources included
+result in 2GB RAM detected. The following FIPs were generated with newer sources and
+detect 4GB RAM: https://github.com/LibreELEC/amlogic-boot-fip/tree/master/beelink-s922x
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ sh fip/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ sh fip/blx_fix.sh \
- fip/bl2.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/acs.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ fip/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
- --output fip/bl30_new.bin.g12a.enc \
- --level v3
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
$ fip/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
- --output fip/bl30_new.bin.enc \
- --level v3 --type bl30
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
$ fip/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
- --output fip/bl31.img.enc \
- --level v3 --type bl31
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
$ fip/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
- --output fip/bl33.bin.enc \
- --level v3 --type bl33
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33
$ fip/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
- --output fip/bl2.n.bin.sig
+ --output fip/bl2.n.bin.sig
$ fip/aml_encrypt_g12b --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc \
- --ddrfw1 fip/ddr4_1d.fw \
- --ddrfw2 fip/ddr4_2d.fw \
- --ddrfw3 fip/ddr3_1d.fw \
- --ddrfw4 fip/piei.fw \
- --ddrfw5 fip/lpddr4_1d.fw \
- --ddrfw6 fip/lpddr4_2d.fw \
- --ddrfw7 fip/diag_lpddr4.fw \
- --ddrfw8 fip/aml_ddr.fw \
- --level v3
-
-and then write the image to SD with:
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --level v3
+
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
Amlogic SoC Boot Flow
=====================
-The Amlogic SoCs have a pre-defined boot sequence in the SoC ROM code. Here are
-the possible boot sources of different SoC families supported by U-Boot:
+Amlogic SoCs follow a pre-defined boot sequence stored in SoC ROM code. The possible boot
+sequences of the different SoC families are:
-GX* & AXG family
+GX* & AXG Family
----------------
-+----------+--------------------+-------+-------+---------------+---------------+
-| | 1 | 2 | 3 | 4 | 5 |
-+==========+====================+=======+=======+===============+===============+
-| S905 | POC=0: SPI NOR | eMMC | NAND | SD Card | USB Device |
-| S905X | | | | | |
-| S905L | | | | | |
-| S905W | | | | | |
-| S912 | | | | | |
-+----------+--------------------+-------+-------+---------------+---------------+
-| S805X | POC=0: SPI NOR | eMMC | NAND | USB Device | - |
-| A113D | | | | | |
-| A113X | | | | | |
-+----------+--------------------+-------+-------+---------------+---------------+
++----------+-------------------+---------+---------+---------+---------+
+| | 1 | 2 | 3 | 4 | 5 |
++==========+===================+=========+=========+=========+=========+
+| S905 | POC=0: SPI NOR | eMMC | NAND | SD | USB |
+| S905D | | | | | |
+| S905L | | | | | |
+| S905W | | | | | |
+| S905X | | | | | |
+| S905Y | | | | | |
+| S912 | | | | | |
++----------+-------------------+---------+---------+---------+---------+
+| S805X | POC=0: SPI NOR | eMMC | NAND | USB | - |
+| A113D | | | | | |
+| A113X | | | | | |
++----------+-------------------+---------+---------+---------+---------+
POC pin: `NAND_CLE`
-Some boards provide a button to force USB BOOT which disables the eMMC clock signal
-to bypass the eMMC stage. Others have removable eMMC modules; removing the eMMC and
-SDCard will allow boot from USB.
+Some boards provide a button to force USB boot by disabling the eMMC clock signal and
+allowing the eMMC step to be bypassed. Others have removable eMMC modules; removing an
+eMMC module and SD card will allow boot from USB.
-An exception is the lafrite board (aml-s805x-xx) which has no SDCard slot and boots
-from SPI. The only ways to boot the lafrite board from USB are:
+An exception is the Libre Computer AML-S805X-XX (LaFrite) board which has no SD card
+slot and boots from SPI. Booting a LaFrite board from USB requires either:
- - Erase the first sectors of SPI NOR flash
- - Insert an HDMI boot plug forcing boot over USB
+ - Erasing the first sectors of SPI NOR flash
+ - Inserting an HDMI boot plug forcing boot over USB
-The VIM1 and initial VIM2 boards provide a test point on the eMMC signals to block
-the storage from answering and continue to the next boot step.
+The VIM1 and initial VIM2 boards provide a test point on the eMMC signals to block the
+storage from answering, allowing boot to continue with the next boot step.
-The USB Device boot uses the first USB interface. On some boards this port is only
-available on an USB-A type connector and needs an special Type-A to Type-A cable to
-communicate with the BootROM.
+USB boot uses the first USB interface. On some boards this port is only available on a
+USB-A type connector and requires a special Type-A to Type-A cable to communicate with
+the BootROM.
-G12* & SM1 family
+G12* & SM1 Family
-----------------
-+-------+-------+-------+---------------+---------------+---------------+---------------+
-| POC0 | POC1 | POC2 | 1 | 2 | 3 | 4 |
-+=======+=======+=======+===============+===============+===============+===============+
-| 0 | 0 | 0 | USB Device | SPI NOR | NAND/eMMC | SDCard |
-+-------+-------+-------+---------------+---------------+---------------+---------------+
-| 0 | 0 | 1 | USB Device | NAND/eMMC | SDCard | - |
-+-------+-------+-------+---------------+---------------+---------------+---------------+
-| 0 | 1 | 0 | SPI NOR | NAND/eMMC | SDCard | USB Device |
-+-------+-------+-------+---------------+---------------+---------------+---------------+
-| 0 | 1 | 1 | SPI NAND | NAND/eMMC | USB Device | - |
-+-------+-------+-------+---------------+---------------+---------------+---------------+
-| 1 | 0 | 0 | USB Device | SPI NOR | NAND/eMMC | SDCard |
-+-------+-------+-------+---------------+---------------+---------------+---------------+
-| 1 | 0 | 1 | USB Device | NAND/eMMC | SDCard | - |
-+-------+-------+-------+---------------+---------------+---------------+---------------+
-| 1 | 1 | 0 | SPI NOR | NAND/eMMC | SDCard | USB Device |
-+-------+-------+-------+---------------+---------------+---------------+---------------+
-| 1 | 1 | 1 | NAND/eMMC | SDCard | USB Device | - |
-+-------+-------+-------+---------------+---------------+---------------+---------------+
-
-The last option (1/1/1) is the normal default seen on production devices.
++-------+-------+-------+------------+------------+------------+-----------+
+| POC0 | POC1 | POC2 | 1 | 2 | 3 | 4 |
++=======+=======+=======+============+============+============+===========+
+| 0 | 0 | 0 | USB | SPI-NOR | NAND/eMMC | SD |
++-------+-------+-------+------------+------------+-------------+----------+
+| 0 | 0 | 1 | USB | NAND/eMMC | SD | - |
++-------+-------+-------+------------+------------+------------+-----------+
+| 0 | 1 | 0 | SPI-NOR | NAND/eMMC | SD | USB |
++-------+-------+-------+------------+------------+------------+-----------+
+| 0 | 1 | 1 | SPI-NAND | NAND/eMMC | USB | - |
++-------+-------+-------+------------+------------+------------+-----------+
+| 1 | 0 | 0 | USB | SPI-NOR | NAND/eMMC | SD |
++-------+-------+-------+------------+------------+------------+-----------+
+| 1 | 0 | 1 | USB | NAND/eMMC | SD | - |
++-------+-------+-------+------------+------------+------------+-----------+
+| 1 | 1 | 0 | SPI-NOR | NAND/eMMC | SD | USB |
++-------+-------+-------+------------+------------+------------+-----------+
+| 1 | 1 | 1 | NAND/eMMC | SD | USB | - |
++-------+-------+-------+------------+------------+------------+-----------+
+
+The last option (1/1/1) is the normal default seen on production devices:
* POC0 pin: `BOOT_4` (0 and all other 1 means SPI NAND boot first)
* POC1 pin: `BOOT_5` (0 and all other 1 means USB Device boot first
* POC2 pin: `BOOT_6` (0 and all other 1 means SPI NOR boot first)
Most boards provide a button to force USB BOOT which lowers `BOOT_5` to 0. Some boards
-provide a test point on the eMMC or SPI NOR clock signals to block the storage from
-answering and continue to the next boot step.
+provide a test point on eMMC or SPI NOR clock signals to block storage from answering
+and allowing boot to continue from the next boot step.
-The Khadas VIM3/3L boards embed a microcontroller which sets POC signals according
-to its configuration or a specific key press sequence to either boot from SPI NOR
-or eMMC then SDCard, or boot as an USB Device.
+The Khadas VIM3/3L boards embed a microcontroller which sets POC signals according to
+its configuration or a specific key press sequence to either boot from SPI NOR or eMMC
+then SD card, or boot as a USB device.
-The Odroid N2/N2+ has a hardware switch to select between SPI NOR or eMMC boot.
+The Odroid N2/N2+ has a hardware switch to select between SPI NOR or eMMC boot. The
+Odroid HC4 has a button to disable SPI-NOR allowing boot from SD card.
Boot Modes
----------
- * SDCard
+ * SD
-The BootROM fetches the first SDCard sectors in one sequence, then checks the content
-of the data. The BootROM expects to find the FIP binary in sector 1, 512 bytes offset
-from the start.
+The BootROM fetches the first SD card sectors in one sequence then checks the content of
+the data. It expects to find the FIP binary in sector 1, 512 bytes offset from the start.
* eMMC
-The BootROM fetches the first sectors in one sequence, first on the main partition,
-and then on the Boot0 followed by Boot1 HW partitions. After each read, the BootROM
-checks the data and looks to the next partition if it fails. The BootROM expects to
-find the FIP binary in sector 1, 512 bytes offset from the start.
+The BootROM fetches the first sectors of the main partition in one sequence then checks
+the content of the data. On GXL and newer boards it expects to find the FIP binary in
+sector 1, 512 bytes offset from the start. If not found it checks the boot0 partition,
+then the boot1 partition. On GXBB it expects to find the FIP binary at an offset that
+conflicts with MBR partition tables, but this has been worked around (thus avoiding the
+need for a partition scheme that relocates the MBR). For a more detailed explanation
+please see: https://github.com/LibreELEC/amlogic-boot-fip/pull/8
- * SPI NOR
+ * SPI-NOR
-The BootROM fetches the first SPI NOR sectors in one sequence, then checks the content
-of the data. The BootROM expects to find the FIP binary in sector 1, 512 bytes offset
-from the start.
+The BootROM fetches the first SPI NOR sectors in one sequence then checks the content of
+the data. It expects to find the FIP binary in sector 1, 512 bytes offset from the start.
- * NAND & SPI NAND
+ * NAND & SPI-NAND
These modes are rarely used in open platforms and no details are available.
- * USB Device
+ * USB
-The BootROM sets the USB Gadget interface to serve a custom USB protocol with the
-USB ID 1b8e:c003. The Amlogic `update` utility is designed to use this protocol. It
-is also implemented in the Amlogic Vendor U-Boot.
+The BootROM supports a custom USB protocol and sets the USB Gadget interface to use the
+USB ID 1b8e:c003. The Amlogic `update` utility uses this protocol. It is also supported
+in the Amlogic vendor U-Boot sources.
-The open-source `pyamlboot` utility https://github.com/superna9999/pyamlboot also
-implements this protocol and can load U-Boot in memory in order to start the SoC
-without any attached storage or to recover from a failed/incorrect image flash.
+The `pyamlboot` utility https://github.com/superna9999/pyamlboot is open-source and also
+implements the USB protocol. It can load U-Boot into memory to start the SoC without the
+storage being attached, or to recover the device from a failed/incorrect image flash.
-HDMI Recovery
--------------
+HDMI Recovery Dongle
+--------------------
-The BootROM also briefly reads 8 bytes at address I2C 0x52 offset 0xf8 (248) on the
-HDMI DDC bus. If the content is `boot@USB` it will force USB boot mode. If the content
-is `boot@SDC` it will force SDCard boot mode.
+The BootROM also reads 8 bytes at address I2C 0x52 offset 0xf8 (248) on the HDMI DDC bus
+during startup. The content `boot@USB` forces USB boot. The content `boot@SDC` forces SD
+card boot. The content `boot@SPI` forces SPI-NOT boot. If an SD card or USB device does
+not enumerate the BootROM continues with the normal boot sequence.
-If USB Device doesn't enumerate or SD Card boot step doesn't work, the BootROM will
-continue with the normal boot sequence.
+HDMI boot dongles can be created by connecting a 256bytes EEPROM set to answer on address
+0x52, with `boot@USB` or `boot@SDC` or `boot@SPI` programmed at offset 0xf8 (248).
-Special boot dongles can be built by connecting a 256bytes EEPROM set to answer on
-address 0x52, and program `boot@USB` or `boot@SDC` at offset 0xf8 (248).
-
-Note: If the SoC is booted with USB Device forced at first step, it will keep the boot
-order on warm reboot. Only cold reboot (power removed) will reset the boot order.
+If the SoC is booted with USB Device forced at first step, it will retain the forced boot
+order on warm reboot. Only cold reboot (removing power) will reset the boot order.
This matrix concerns the actual source code version.
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| | S905 | S905X | S912 | A113X | S905X2 | S922X | S905X3 |
-| | | S805X | S905D | | S905D2 | A311D | S905D3 |
-| | | S905W | | | S905Y2 | | |
-+===============================+===========+=================+==============+=============+============+=============+==============+
-| Boards | Odroid-C2 | P212 | Khadas VIM2 | S400 | U200 | Odroid-N2 | SEI610 |
-| | Nanopi-K2 | Khadas-VIM | Libretech-PC | JetHub J100 | SEI510 | Khadas-VIM3 | Khadas-VIM3L |
-| | P200 | LibreTech-CC v1 | WeTek Core2 | | Radxa Zero | GT-King/Pro | Odroid-C4 |
-| | P201 | LibreTech-AC v2 | | | | GSKing-X | Odroid-HC4 |
-| | | JetHub J80 | | | | Odroid-Go- | BananaPi-M5 |
-| | | | | | | Ultra | |
-| | | | | | | Odroid-N2L | |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| UART | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| Pinctrl/GPIO | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| Clock Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| PWM | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| Reset Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| Infrared Decoder | No | No | No | No | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| Ethernet | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| Multi-core | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| Fuse access | **Yes** | **Yes** |**Yes** |**Yes** |**Yes** |**Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| SPI (FC) | **Yes** | **Yes** | **Yes** | **Yes** |**Yes** | **Yes** | No |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| SPI (CC) | No | No | No | No | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| I2C | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| USB | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| USB OTG | No | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| eMMC | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| SDCard | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| NAND | No | No | No | No | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| ADC | **Yes** | **Yes** | **Yes** | **Yes** | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| CVBS Output | **Yes** | **Yes** | **Yes** | *N/A* | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| HDMI Output | **Yes** | **Yes** | **Yes** | *N/A* | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| CEC | No | No | No | *N/A* | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| Thermal Sensor | No | No | No | No | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| LCD/LVDS Output | No | *N/A* | No | No | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| MIPI DSI Output | *N/A* | *N/A* | *N/A* | No | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| SoC (version) information | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| PCIe (+NVMe) | *N/A* | *N/A* | *N/A* | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| Watchdog | *N/A* | **Yes** | *N/A* | *N/A* | *N/A* | *N/A* | *N/A* |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| SoCs | S905 | S805X | S912 | A113X | S905X2 | S922X | S905X3 |
+| | | S905X | S905D | | S905D2 | A311D | S905D3 |
+| | | S905W | | | S905Y2 | | |
++===================+===========+==========+==========+==========+==========+==========+==========+
+| UART | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| Pinctrl/GPIO | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| Clock Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| PWM | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| Reset Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| Infrared Decoder | No | No | No | No | No | No | No |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| Ethernet | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| Multi-core | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| Fuse access | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| SPI (FC) | **Yes** | **Yes** | **Yes** | **Yes** |**Yes** | **Yes** | No |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| SPI (CC) | No | No | No | No | No | No | No |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| I2C | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| USB | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| USB OTG | No | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| eMMC | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| SDCard | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| NAND | No | No | No | No | No | No | No |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| ADC | **Yes** | **Yes** | **Yes** | **Yes** | No | No | No |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| CVBS Output | **Yes** | **Yes** | **Yes** | *N/A* | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| HDMI Output | **Yes** | **Yes** | **Yes** | *N/A* | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| CEC | No | No | No | *N/A* | No | No | No |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| Thermal Sensor | No | No | No | No | No | No | No |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| LCD/LVDS Output | No | *N/A* | No | No | No | No | No |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| MIPI DSI Output | *N/A* | *N/A* | *N/A* | No | No | No | No |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| SoC Rev/Info | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| PCIe (+NVMe) | *N/A* | *N/A* | *N/A* | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| Watchdog | *N/A* | **Yes** | *N/A* | *N/A* | *N/A* | *N/A* | *N/A* |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
Boot Documentation
------------------
.. toctree::
:maxdepth: 1
- pre-generated-fip
boot-flow
+ pre-generated-fip
Board Documentation
-------------------
.. toctree::
:maxdepth: 1
+ bananapi-cm4io
+ bananapi-m2pro
+ bananapi-m2s
+ bananapi-m5
+ beelink-gskingx
+ beelink-gt1-ultimate
beelink-gtking
beelink-gtkingpro
- jethub-j100
jethub-j80
+ jethub-j100
+ khadas-vim
khadas-vim2
- khadas-vim3l
khadas-vim3
- khadas-vim
+ khadas-vim3l
libretech-ac
libretech-cc
nanopi-k2
odroid-c2
odroid-c4
+ odroid-hc4
odroid-n2
odroid-n2l
odroid-go-ultra
p212
q200
radxa-zero
- s400
+ radxa-zero2
sei510
sei610
+ s400
u200
wetek-core2
+ wetek-hub
+ wetek-play2
w400
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for JetHub J100
-=======================
+U-Boot for JetHub J100 (A113X)
+==============================
-JetHome Jethub D1 (http://jethome.ru/jethub-d1) is a series of home
-automation controller manufactured by JetHome with the following
-specifications:
+JetHome Jethub D1 (http://jethome.ru/jethub-d1) is a home automation controller device
+manufactured by JetHome with the following specifications:
- Amlogic A113X (ARM Cortex-A53) quad-core up to 1.5GHz
- no video out
- DC source with a voltage of 9 to 56 V / Passive POE
- DIN Rail Mounting case
-Basic version also has:
+The basic version also has:
- - TI CC2538 + CC2592 Zigbee Wireless Module with up to 20dBm output
- power and Zigbee 3.0 support.
+ - TI CC2538 + CC2592 Zigbee Wireless with upto 20dBm output power and Zigbee 3.0
- 1 x 1-Wire
- 2 x RS-485
- 4 x dry contact digital GPIO inputs
- 3 x relay GPIO outputs
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make jethub_j100_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `jethub-j100`
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh jethub-j100 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain binaries
-from the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ cd jethub-u-boot
$ export FIPDIR=$PWD
-Go back to mainline U-boot source tree then :
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
bl2
$ $FIPDIR/j100/aml_encrypt_axg --bl3sig --input fip/bl30_new.bin \
- --output fip/bl30_new.bin.enc \
- --level v3 --type bl30
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
$ $FIPDIR/j100/aml_encrypt_axg --bl3sig --input fip/bl31.img \
- --output fip/bl31.img.enc \
- --level v3 --type bl31
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
$ $FIPDIR/j100/aml_encrypt_axg --bl3sig --input fip/bl33.bin --compress lz4 \
- --output fip/bl33.bin.enc \
- --level v3 --type bl33
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33
$ $FIPDIR/j100/aml_encrypt_axg --bl2sig --input fip/bl2_new.bin \
- --output fip/bl2.n.bin.sig
+ --output fip/bl2.n.bin.sig
$ $FIPDIR/j100/aml_encrypt_axg --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc --level v3
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc --level v3
-and then write the image to eMMC with:
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_emmc_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for JetHub J80
-======================
+U-Boot for JetHub J80 (S905W)
+=============================
-JetHome Jethub H1 (http://jethome.ru/jethub-h1) is a home automation
-controller manufactured by JetHome with the following specifications:
+JetHome Jethub H1 (http://jethome.ru/jethub-h1) is a home automation controller device
+manufactured by JetHome with the following specifications:
- Amlogic S905W (ARM Cortex-A53) quad-core up to 1.5GHz
- No video out
- DC source 5V microUSB
- Square plastic case
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make jethub_j80_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `jethub-j80`
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh jethub-j80 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain binaries
-from the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ cd jethub-u-boot
$ export FIPDIR=$PWD
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ $FIPDIR/j80/aml_encrypt_gxl --bl3enc --input fip/bl33.bin --compress lz4
$ $FIPDIR/j80/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
$ $FIPDIR/j80/aml_encrypt_gxl --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc
-and then write the image to SD/eMMC with:
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for Khadas VIM
-======================
+U-Boot for Khadas VIM (S905X)
+=============================
-Khadas VIM is an Open Source DIY Box manufactured by Shenzhen Wesion
-Technology Co., Ltd with the following specifications:
+Khadas VIM is a Single Board Computer manufactured by Shenzhen Wesion Technology Co. Ltd
+with the following specifications:
- Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz
- ARM Mali 450 GPU
- 2GB DDR3 SDRAM
+ - 8GB/16GB eMMC
- 10/100 Ethernet
- HDMI 2.0 4K/60Hz display
- 40-pin GPIO header
- 2 x USB 2.0 Host, 1 x USB 2.0 Type-C OTG
- - 8GB/16GBeMMC
- microSD
- SDIO Wifi Module, Bluetooth
- - Two channels IR receiver
+ - Two channel IR receiver
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make khadas-vim_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `khadas-vim`
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh khadas-vim /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ $FIPDIR/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
$ $FIPDIR/blx_fix.sh \
- fip/bl2_acs.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/bl21.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
$ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
$ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
$ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
$ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc
-and then write the image to SD with:
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for Khadas VIM2
-=======================
+U-Boot for Khadas VIM2 (S912)
+=============================
-Khadas VIM2 is an Open Source DIY Box manufactured by Shenzhen Wesion
-Technology Co., Ltd with the following specifications:
+Khadas VIM2 is a Single Board Computer manufactured by Shenzhen Wesion Technology Co. Ltd
+with the following specifications:
- Amlogic S912 ARM Cortex-A53 octo-core SoC @ 1.5GHz
- ARM Mali T860 GPU
- - 2/3GB DDR4 SDRAM
+ - 2GB/3GB DDR4 SDRAM
+ - 16GB/32GB/64GB eMMC
- 10/100/1000 Ethernet
- HDMI 2.0 4K/60Hz display
- 40-pin GPIO header
- 2 x USB 2.0 Host, 1 x USB 2.0 Type-C OTG
- - 16GB/32GB/64GB eMMC
- 2MB SPI Flash
- microSD
- SDIO Wifi Module, Bluetooth
- Two channels IR receiver
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make khadas-vim2_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh khadas-vim2 /path/to/u-boot/u-boot.bin my-output-dir
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `khadas-vim2`
+U-Boot Manual Signing
+---------------------
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ make
$ export FIPDIR=$PWD/fip
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ $FIPDIR/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
$ $FIPDIR/blx_fix.sh \
- fip/bl2_acs.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/bl21.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
$ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
$ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
$ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
$ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc
-and then write the image to SD with:
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
$ DEV=/dev/your_sd_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for Khadas VIM3
-======================
+U-Boot for Khadas VIM3 (A311D)
+==============================
-Khadas VIM3 is a single board computer manufactured by Shenzhen Wesion
-Technology Co., Ltd. with the following specifications:
+Khadas VIM3 is a Single Board Computer manufactured by Shenzhen Wesion Technology Co. Ltd
+with the following specifications:
- Amlogic A311D Arm Cortex-A53 dual-core + Cortex-A73 quad-core SoC
- 4GB LPDDR4 SDRAM
PCIe Setup
----------
-The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
-lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
-an USB3.0 Type A connector and a M.2 Key M slot.
-The PHY driving these differential lines is shared between
-the USB3.0 controller and the PCIe Controller, thus only
-a single controller can use it.
-To setup for PCIe, run the following commands from U-Boot:
+The on-board MCU can mux the PCIe/USB3.0 shared differential lines using a FUSB340TMX USB
+3.1 SuperSpeed Data Switch between a USB3.0 Type-A connector and an M.2 Key M slot. The
+PHY driving these differential lines is shared between the USB3.0 controller and the PCIe
+Controller, thus only a single controller can use it.
+
+To setup for PCIe run the following commands from U-Boot then power-cycle the board:
.. code-block:: none
i2c dev i2c@5000
i2c mw 0x18 0x33 1
-Then power-cycle the board.
-
-To set back to USB3.0, run the following commands from U-Boot:
+To revert to USB3.0 run the following commands from U-Boot then power-cycle the board:
.. code-block:: none
i2c dev i2c@5000
i2c mw 0x18 0x33 0
-Then power-cycle the board.
-
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make khadas-vim3_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh khadas-vim3 /path/to/u-boot/u-boot.bin my-output-dir
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `khadas-vim3`
+U-Boot Manual Signing
+---------------------
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
$ DIR=vim3-u-boot
- $ git clone --depth 1 \
- https://github.com/khadas/u-boot.git -b khadas-vims-v2015.01 \
- $DIR
+ $ git clone --depth 1 https://github.com/khadas/u-boot.git -b khadas-vims-v2015.01 $DIR
$ cd vim3-u-boot
$ make kvim3_defconfig
$ make CROSS_COMPILE=aarch64-none-elf-
$ export UBOOTDIR=$PWD
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ bash fip/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ bash fip/blx_fix.sh \
- fip/bl2.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/acs.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
- --output fip/bl30_new.bin.g12a.enc \
- --level v3
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
$ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
- --output fip/bl30_new.bin.enc \
- --level v3 --type bl30
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
$ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
- --output fip/bl31.img.enc \
- --level v3 --type bl31
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
$ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
- --output fip/bl33.bin.enc \
- --level v3 --type bl33 --compress lz4
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33 --compress lz4
$ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
- --output fip/bl2.n.bin.sig
+ --output fip/bl2.n.bin.sig
$ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc \
- --ddrfw1 fip/ddr4_1d.fw \
- --ddrfw2 fip/ddr4_2d.fw \
- --ddrfw3 fip/ddr3_1d.fw \
- --ddrfw4 fip/piei.fw \
- --ddrfw5 fip/lpddr4_1d.fw \
- --ddrfw6 fip/lpddr4_2d.fw \
- --ddrfw7 fip/diag_lpddr4.fw \
- --ddrfw8 fip/aml_ddr.fw \
- --ddrfw9 fip/lpddr3_1d.fw \
- --level v3
-
-and then write the image to SD with:
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --ddrfw9 fip/lpddr3_1d.fw \
+ --level v3
+
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for Khadas VIM3L
-=======================
+U-Boot for Khadas VIM3L (S905D3)
+================================
-Khadas VIM3L is a single board computer manufactured by Shenzhen Wesion
-Technology Co., Ltd. with the following specifications:
+Khadas VIM3L is a Single Board Computer manufactured by Shenzhen Wesion Technology Co. Ltd
+with the following specifications:
- Amlogic S905D3 Arm Cortex-A55 quad-core SoC
- 2GB LPDDR4 SDRAM
PCIe Setup
----------
-The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
-lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
-an USB3.0 Type A connector and a M.2 Key M slot.
-The PHY driving these differential lines is shared between
-the USB3.0 controller and the PCIe Controller, thus only
-a single controller can use it.
-To setup for PCIe, run the following commands from U-Boot:
+The on-board MCU can mux the PCIe/USB3.0 shared differential lines using a FUSB340TMX USB
+3.1 SuperSpeed Data Switch between a USB3.0 Type-A connector and an M.2 Key-M slot. The
+PHY driving these differential lines is shared between the USB3.0 controller and the PCIe
+Controller, thus only a single controller can use it.
+
+To setup for PCIe run the following commands from U-Boot then power-cycle the board:
.. code-block:: none
i2c dev i2c@5000
i2c mw 0x18 0x33 1
-Then power-cycle the board.
-
-To set back to USB3.0, run the following commands from U-Boot:
+To revert to USB3.0 run the following commands from U-Boot then power-cycle the board:
.. code-block:: none
i2c dev i2c@5000
i2c mw 0x18 0x33 0
-Then power-cycle the board.
-
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make khadas-vim3l_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh khadas-vim3l /path/to/u-boot/u-boot.bin my-output-dir
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `khadas-vim3l`
+U-Boot Manual Signing
+---------------------
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
$ DIR=vim3l-u-boot
- $ git clone --depth 1 \
- https://github.com/khadas/u-boot.git -b khadas-vims-v2015.01 \
- $DIR
+ $ git clone --depth 1 https://github.com/khadas/u-boot.git -b khadas-vims-v2015.01 $DIR
$ cd vim3l-u-boot
$ make kvim3l_defconfig
$ make CROSS_COMPILE=aarch64-none-elf-
$ export UBOOTDIR=$PWD
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ bash fip/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ bash fip/blx_fix.sh \
- fip/bl2.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/acs.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
- --output fip/bl30_new.bin.g12a.enc \
- --level v3
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
$ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
- --output fip/bl30_new.bin.enc \
- --level v3 --type bl30
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
$ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
- --output fip/bl31.img.enc \
- --level v3 --type bl31
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
$ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
- --output fip/bl33.bin.enc \
- --level v3 --type bl33 --compress lz4
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33 --compress lz4
$ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
- --output fip/bl2.n.bin.sig
+ --output fip/bl2.n.bin.sig
$ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc \
- --ddrfw1 fip/ddr4_1d.fw \
- --ddrfw2 fip/ddr4_2d.fw \
- --ddrfw3 fip/ddr3_1d.fw \
- --ddrfw4 fip/piei.fw \
- --ddrfw5 fip/lpddr4_1d.fw \
- --ddrfw6 fip/lpddr4_2d.fw \
- --ddrfw7 fip/diag_lpddr4.fw \
- --ddrfw8 fip/aml_ddr.fw \
- --ddrfw9 fip/lpddr3_1d.fw \
- --level v3
-
-and then write the image to SD with:
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --ddrfw9 fip/lpddr3_1d.fw \
+ --level v3
+
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for LibreTech AC
-=======================
+U-Boot for LibreTech-AC 'LaFrite' (S805X)
+=========================================
-LibreTech AC is a single board computer manufactured by Libre Technology
+LibreTech-AC aka 'LaFrite' is a Single Board Computer manufactured by Libre Computer
with the following specifications:
- Amlogic S805X ARM Cortex-A53 quad-core SoC @ 1.2GHz
- HDMI 2.0 4K/60Hz display
- 40-pin GPIO header
- 4 x USB 2.0 Host
- - eMMC, SPI NOR Flash
+ - SPI NOR Flash
+ - Removable eMMC module
- Infrared receiver
Schematics are available on the manufacturer website.
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make libretech-ac_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `lafrite`
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh lafrite /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ make
$ export UBOOTDIR=$PWD
-Download the latest Amlogic Buildroot package, and extract it :
+Download the latest Amlogic buildroot package and extract it:
.. code-block:: bash
$ tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180418.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180418/bootloader
$ export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180418
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ sh $UBOOTDIR/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ $BRDIR/bootloader/uboot-repo/fip/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
$ sh $UBOOTDIR/blx_fix.sh \
- fip/bl2_acs.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/bl21.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
$ $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
$ $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
$ $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
$ $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc
-and then write the image to SD with:
+Then write U-Boot to USB or SPI-NOR with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for LibreTech CCs
-========================
+U-Boot for LibreTech CC 'LePotato' (S905X)
+==========================================
-LibreTech CC is a single board computer manufactured by Libre Technology
-with the following specifications:
+LibreTech CC is a Single Board Computer manufactured by Libre Computer Technology with
+the following specifications:
-V1:
+v1:
- Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz
- ARM Mali 450 GPU
- Infrared receiver
- Jack for CVBS and Audio
-V2:
+v2:
- Added SPI NOR
- Removed Jack
Schematics are available on the manufacturer website.
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
Use libretech-cc_v2_defconfig for v2.
-Image creation
---------------
-
-To boot the system, u-boot must be combined with several earlier stage
-bootloaders:
-
-* bl2.bin: vendor-provided binary blob
-* bl21.bin: built from vendor u-boot source
-* bl30.bin: vendor-provided binary blob
-* bl301.bin: built from vendor u-boot source
-* bl31.bin: vendor-provided binary blob
-* acs.bin: built from vendor u-boot source
-
-These binaries and the tools required below have been collected and prebuilt
-for convenience at <https://github.com/BayLibre/u-boot/releases/>. These
-apply to both v1 and v2.
-
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `lepotato`
-
-Download and extract the libretech-cc release from there, and set FIPDIR to
-point to the `fip` subdirectory.
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
.. code-block:: bash
- $ export FIPDIR=/path/to/extracted/fip
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh lepotato /path/to/u-boot/u-boot.bin my-output-dir
-Alternatively, you can obtain the original vendor u-boot tree which
-contains the required blobs and sources, and build yourself.
-Note that old compilers are required for this to build. The compilers here
-are suggested by Amlogic, and they are 32-bit x86 binaries.
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ make
$ export FIPDIR=$PWD/fip
-Once you have the binaries available (either through the prebuilt download,
-or having built the vendor u-boot yourself), you can then proceed to glue
-everything together. Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ $FIPDIR/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
$ $FIPDIR/blx_fix.sh \
- fip/bl2_acs.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/bl21.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
$ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
$ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
$ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
$ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc
-and then write the image to SD with:
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
-
-Note that Amlogic provides aml_encrypt_gxl as a 32-bit x86 binary with no
-source code. Should you prefer to avoid that, there are open source reverse
-engineered versions available:
-
-1. gxlimg <https://github.com/repk/gxlimg>, which comes with a handy
- Makefile that automates the whole process.
-2. meson-tools <https://github.com/afaerber/meson-tools>
-
-However, these community-developed alternatives are not endorsed by or
-supported by Amlogic.
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for NanoPi-K2
-====================
+U-Boot for NanoPi-K2 (S905)
+===========================
-NanoPi-K2 is a single board computer manufactured by FriendlyElec
-with the following specifications:
+NanoPi-K2 is a single board computer manufactured by FriendlyElec with the following
+specifications:
- Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz
- ARM Mali 450 GPU
Schematics are available on the manufacturer website.
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make nanopi-k2_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `nanopi-k2`
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh nanopi-k2 /path/to/u-boot/u-boot.bin my-output-dir
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
$ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
$ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
- $ git clone https://github.com/BayLibre/u-boot.git -b libretech-cc amlogic-u-boot
$ git clone https://github.com/friendlyarm/u-boot.git -b nanopi-k2-v2015.01 amlogic-u-boot
$ cd amlogic-u-boot
$ sed -i 's/aarch64-linux-gnu-/aarch64-none-elf-/' Makefile
$ make
$ export FIPDIR=$PWD/fip
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ cp $FIPDIR/gxb/bl301.bin fip/
$ cp $FIPDIR/gxb/bl31.img fip/
$ cp u-boot.bin fip/bl33.bin
+ $ wget https://github.com/LibreELEC/amlogic-boot-fip/raw/master/nanopi-k2/bl1.bin.hardkernel fip/bl1.bin.hardkernel
+ $ chmod +x fip/bl1.bin.hardkernel
+ $ wget https://github.com/LibreELEC/amlogic-boot-fip/raw/master/nanopi-k2/aml_chksum fip/aml_chksum
+ $ chmod +x fip/aml_chksum
$ $FIPDIR/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
-
- $ $FIPDIR/fip_create \
- --bl30 fip/bl30_new.bin \
- --bl31 fip/bl31.img \
- --bl33 fip/bl33.bin \
- fip/fip.bin
-
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ $ $FIPDIR/fip_create --bl30 fip/bl30_new.bin \
+ --bl31 fip/bl31.img \
+ --bl33 fip/bl33.bin \
+ fip/fip.bin
+
+ $ sed -i 's/\x73\x02\x08\x91/\x1F\x20\x03\xD5/' fip/bl2.bin
$ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
$ $FIPDIR/blx_fix.sh \
- fip/bl2_acs.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/bl21.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ cat fip/bl2_new.bin fip/fip.bin > fip/boot_new.bin
$ $FIPDIR/gxb/aml_encrypt_gxb --bootsig \
- --input fip/boot_new.bin
- --output fip/u-boot.bin
+ --input fip/boot_new.bin
+ --output fip/u-boot.bin
-and then write the image to SD with:
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
- $ dd if=fip/u-boot.bin of=$DEV conv=fsync,notrunc bs=512 seek=1
+ $ DEV=/dev/boot_device
+ $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 conv=fsync
+ $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 seek=9 skip=8 count=87 conv=fsync,notrunc
+ $ dd if=/dev/zero of=fip/u-boot.bin.gxbb bs=512 seek=8 count=1 conv=fsync,notrunc
+ $ dd if=bl1.bin.hardkernel of=fip/u-boot.bin.gxbb bs=512 seek=2 skip=2 count=1 conv=fsync,notrunc
+ $ ./aml_chksum fip/u-boot.bin.gxbb
+ $ dd if=fip/u-boot.gxbb of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.gxbb of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for ODROID-C2
-====================
+U-Boot for ODROID-C2 (S905)
+===========================
-ODROID-C2 is a single board computer manufactured by Hardkernel
-Co. Ltd with the following specifications:
+ODROID-C2 is a single board computer manufactured by Hardkernel with the following
+specifications:
- - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 2GHz
+ - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz
- ARM Mali 450 GPU
- 2GB DDR3 SDRAM
- Gigabit Ethernet
- eMMC, microSD
- Infrared receiver
-Schematics are available on the manufacturer website.
+Schematics are available on the manufacturer website: https://wiki.odroid.com
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make odroid-c2_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `odroid-c2`
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh odroid-c2 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ DIR=odroid-c2
- $ git clone --depth 1 \
- https://github.com/hardkernel/u-boot.git -b odroidc2-v2015.01 \
- $DIR
+ $ git clone --depth 1 https://github.com/hardkernel/u-boot.git -b odroidc2-v2015.01 $DIR
+
$ $DIR/fip/fip_create --bl30 $DIR/fip/gxb/bl30.bin \
- --bl301 $DIR/fip/gxb/bl301.bin \
- --bl31 $DIR/fip/gxb/bl31.bin \
- --bl33 u-boot.bin \
- $DIR/fip.bin
+ --bl301 $DIR/fip/gxb/bl301.bin \
+ --bl31 $DIR/fip/gxb/bl31.bin \
+ --bl33 u-boot.bin \
+ $DIR/fip.bin
+
$ $DIR/fip/fip_create --dump $DIR/fip.bin
$ cat $DIR/fip/gxb/bl2.package $DIR/fip.bin > $DIR/boot_new.bin
$ $DIR/fip/gxb/aml_encrypt_gxb --bootsig \
- --input $DIR/boot_new.bin \
- --output $DIR/u-boot.img
+ --input $DIR/boot_new.bin \
+ --output $DIR/u-boot.img
$ dd if=$DIR/u-boot.img of=$DIR/u-boot.gxbb bs=512 skip=96
-and then write the image to SD with:
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/your_boot_device
$ BL1=$DIR/sd_fuse/bl1.bin.hardkernel
$ dd if=$BL1 of=$DEV conv=fsync bs=1 count=442
$ dd if=$BL1 of=$DEV conv=fsync bs=512 skip=1 seek=1
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for ODROID-C4
-====================
+U-Boot for ODROID-C4 (S905X3)
+=============================
-ODROID-C4 is a single board computer manufactured by Hardkernel
-Co. Ltd with the following specifications:
+ODROID-C4 is a Single Board Computer manufactured by Hardkernel with the following
+specifications:
- Amlogic S905X3 Arm Cortex-A55 quad-core SoC
- 4GB DDR4 SDRAM
- UART serial
- Infrared receiver
-The ODROID-HC4 is a variant with a PCIe-SATA controller, the same commands
-applies for HC4.
-
Schematics are available on the manufacturer website.
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make odroid-c4_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh odroid-c4 /path/to/u-boot/u-boot.bin my-output-dir
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `odroid-c4` or `odroid-hc4`
+U-Boot Manual Signing
+---------------------
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ make
$ export UBOOTDIR=$PWD
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ sh fip/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ sh fip/blx_fix.sh \
- fip/bl2.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/acs.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
- --output fip/bl30_new.bin.g12a.enc \
- --level v3
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
$ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
- --output fip/bl30_new.bin.enc \
- --level v3 --type bl30
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
$ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
- --output fip/bl31.img.enc \
- --level v3 --type bl31
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
$ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
- --output fip/bl33.bin.enc \
- --level v3 --type bl33 --compress lz4
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33 --compress lz4
$ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
- --output fip/bl2.n.bin.sig
+ --output fip/bl2.n.bin.sig
$ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc \
- --ddrfw1 fip/ddr4_1d.fw \
- --ddrfw2 fip/ddr4_2d.fw \
- --ddrfw3 fip/ddr3_1d.fw \
- --ddrfw4 fip/piei.fw \
- --ddrfw5 fip/lpddr4_1d.fw \
- --ddrfw6 fip/lpddr4_2d.fw \
- --ddrfw7 fip/diag_lpddr4.fw \
- --ddrfw8 fip/aml_ddr.fw \
- --ddrfw9 fip/lpddr3_1d.fw \
- --level v3
-
-and then write the image to SD with:
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --ddrfw9 fip/lpddr3_1d.fw \
+ --level v3
+
+Then write the image to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for ODROID-GO-ULTRA
-==========================
+U-Boot for ODROID-GO-ULTRA (S922X)
+==================================
-The Odroid Go Ultra is a portable gaming device with the following
-characteristics:
+The ODROID GO ULTRA is a portable gaming device with the following characteristics:
- Amlogic S922X SoC
- RK817 & RK818 PMICs
- 2x ADC Analog Joysticks
- USB-C Port for USB2 Device and Charging
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make odroid-go-ultra_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-Pleaser refer to :doc:`pre-generated-fip` with codename `odroid-go-ultra`
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh odroid-go-ultra /path/to/u-boot/u-boot.bin my-output-dir
+
+Then write the image to SD or eMMC with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/boot_device
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for ODROID-HC4 (S905X3)
+==============================
+
+ODROID-HC4 is a variant of the ODROID-C4 single board computer manufactured by Hardkernel
+with the following specification:
+
+ - Amlogic S905X3 Arm Cortex-A55 quad-core SoC
+ - 4GB DDR4 SDRAM
+ - 16MB XT25F128B SPI-NOR flash
+ - Gigabit Ethernet
+ - HDMI 2.1 display
+ - 7-pin GPIO header for OLED display and RTC
+ - 1x USB 2.0 host (micro)
+ - 2x SATA ports via ASM1061 PCIe to SATA controller
+ - microSD
+ - UART serial
+ - Infrared receiver
+
+Schematics are available on the manufacturer website.
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-none-elf-
+ $ make odroid-hc4_defconfig
+ $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh odroid-hc4 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
+
+.. code-block:: bash
+
+ $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+
+ $ DIR=odroid-hc4
+ $ git clone --depth 1 https://github.com/hardkernel/u-boot.git -b odroidg12-v2015.01 $DIR
+
+ $ cd odroid-hc4
+ $ make odroidc4_defconfig
+ $ make
+ $ export UBOOTDIR=$PWD
+
+Go back to mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+ $ mkdir fip
+
+ $ wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
+ $ cp $UBOOTDIR/build/scp_task/bl301.bin fip/
+ $ cp $UBOOTDIR/build/board/hardkernel/odroidc4/firmware/acs.bin fip/
+ $ cp $UBOOTDIR/fip/g12a/bl2.bin fip/
+ $ cp $UBOOTDIR/fip/g12a/bl30.bin fip/
+ $ cp $UBOOTDIR/fip/g12a/bl31.img fip/
+ $ cp $UBOOTDIR/fip/g12a/ddr3_1d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/ddr4_1d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/ddr4_2d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/diag_lpddr4.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/lpddr3_1d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/lpddr4_1d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/lpddr4_2d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/piei.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/aml_ddr.fw fip/
+ $ cp u-boot.bin fip/bl33.bin
+
+ $ sh fip/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ $ sh fip/blx_fix.sh \
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33 --compress lz4
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
+ --output fip/bl2.n.bin.sig
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bootmk \
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --ddrfw9 fip/lpddr3_1d.fw \
+ --level v3
+
+Then write U-Boot to SD or SPI-NOR with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/boot_device
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for ODROID-N2
-====================
+U-Boot for ODROID-N2/N2+ (S922X)
+================================
-ODROID-N2 is a single board computer manufactured by Hardkernel
-Co. Ltd with the following specifications:
+ODROID-N2 and ODROID-N2+ are a Single Board Computers manufactured by Hardkernel with the
+following specifications:
- Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC
- 4GB DDR4 SDRAM
- eMMC, microSD
- Infrared receiver
-Schematics are available on the manufacturer website.
+ODROID-N2+ uses Rev-C silicon allowing higher CPU opp-points. U-Boot contains logic to
+read the model detail from SARADC and select the correct device-tree file if FDTDIR is
+used instead of an FDT reference to a specfic device-tree.
-U-Boot compilation
+Schematics are available on the manufacturer website: https://wiki.odroid.com
+
+U-Boot Compilation
------------------
.. code-block:: bash
$ make odroid-n2_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh odroid-n2 /path/to/u-boot/u-boot.bin my-output-dir
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `odroid-n2` or `odroid-n2-plus`
+U-Boot Manual Signing
+---------------------
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
$ DIR=odroid-n2
- $ git clone --depth 1 \
- https://github.com/hardkernel/u-boot.git -b odroidn2-v2015.01 \
- $DIR
+ $ git clone --depth 1 https://github.com/hardkernel/u-boot.git -b odroidn2-v2015.01 $DIR
$ cd odroid-n2
$ make odroidn2_defconfig
$ make
$ export UBOOTDIR=$PWD
- Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ sh fip/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ sh fip/blx_fix.sh \
- fip/bl2.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/acs.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
- --output fip/bl30_new.bin.g12a.enc \
- --level v3
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
$ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
- --output fip/bl30_new.bin.enc \
- --level v3 --type bl30
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
$ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
- --output fip/bl31.img.enc \
- --level v3 --type bl31
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
$ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
- --output fip/bl33.bin.enc \
- --level v3 --type bl33 --compress lz4
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33 --compress lz4
$ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
- --output fip/bl2.n.bin.sig
+ --output fip/bl2.n.bin.sig
$ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc \
- --ddrfw1 fip/ddr4_1d.fw \
- --ddrfw2 fip/ddr4_2d.fw \
- --ddrfw3 fip/ddr3_1d.fw \
- --ddrfw4 fip/piei.fw \
- --ddrfw5 fip/lpddr4_1d.fw \
- --ddrfw6 fip/lpddr4_2d.fw \
- --ddrfw7 fip/diag_lpddr4.fw \
- --ddrfw8 fip/aml_ddr.fw \
- --level v3
-
-and then write the image to SD with:
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --level v3
+
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for ODROID-N2L
-=====================
+U-Boot for ODROID-N2L (S922X)
+=============================
-ODROID-N2L is a single board computer manufactured by Hardkernel
-Co. Ltd with the following specifications:
+ODROID-N2L is a Single Board Computer manufactured by Hardkernel with the following
+specifications:
- Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC
- 4GB DDR4 SDRAM
- HDMI 2.1 4K/60Hz display
- 40-pin GPIO header
- - 1 x USB 3.0 Host, 1 x USB USB 2.0 Host
+ - 1x USB 3.0 Host
+ - 1x USB 2.0 Host
- eMMC, microSD
- MIPI DSI Port
-Schematics are available on the manufacturer website.
+Schematics are available on the manufacturer website: https://wiki.odroid.com
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make odroid-n2l_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `odroid-n2l`
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh odroid-n2l /path/to/u-boot/u-boot.bin my-output-dir
+
+Then write U-Boot to SD or eMMC with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/boot_device
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for Amlogic P200
-=======================
+U-Boot for Amlogic P200 (S905)
+==============================
-P200 is a reference board manufactured by Amlogic with the following
-specifications:
+P200 is a reference board manufactured by Amlogic with the following specification:
- Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz
- ARM Mali 450 GPU
- 2GB DDR3 SDRAM
- Gigabit Ethernet
- HDMI 2.0 4K/60Hz display
- - 2 x USB 2.0 Host
+ - 2x USB 2.0 Host
- eMMC, microSD
- Infrared receiver
- SDIO WiFi Module
- - CVBS+Stereo Audio Jack
+ - CVBS + Stereo Audio Jack
Schematics are available from Amlogic on demand.
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make p200_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `p200`
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh p200 /path/to/u-boot/u-boot.bin my-output-dir
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image but sources have been shared by Linux development contractor, Baylibre:
.. code-block:: bash
$ make
$ export FIPDIR=$PWD/fip
-Go back to mainline U-boot source tree then :
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ cp $FIPDIR/gxb/bl301.bin fip/
$ cp $FIPDIR/gxb/bl31.img fip/
$ cp u-boot.bin fip/bl33.bin
+ $ wget https://github.com/LibreELEC/amlogic-boot-fip/raw/master/nanopi-k2/bl1.bin.hardkernel fip/bl1.bin.hardkernel
+ $ chmod +x fip/bl1.bin.hardkernel
+ $ wget https://github.com/LibreELEC/amlogic-boot-fip/raw/master/nanopi-k2/aml_chksum fip/aml_chksum
+ $ chmod +x fip/aml_chksum
$ $FIPDIR/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
$ $FIPDIR/blx_fix.sh \
- fip/bl2_acs.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/bl21.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
-
- $ $FIPDIR/fip_create --bl30 fip/bl30_new.bin --bl31 fip/bl31.img --bl33 fip/bl33.bin fip/fip.bin
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ $ $FIPDIR/fip_create --bl30 fip/bl30_new.bin \
+ --bl31 fip/bl31.img \
+ --bl33 fip/bl33.bin \
+ fip/fip.bin
$ cat fip/bl2_new.bin fip/fip.bin >fip/boot_new.bin
- $ $FIPDIR/gxb/aml_encrypt_gxb --bootsig --input fip/boot_new.bin --output fip/u-boot.bin
+ $ $FIPDIR/gxb/aml_encrypt_gxb --bootsig \
+ --input fip/boot_new.bin \
+ --output fip/u-boot.bin
and then write the image to SD with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ DEV=/dev/boot_device
+ $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 conv=fsync
+ $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 seek=9 skip=8 count=87 conv=fsync,notrunc
+ $ dd if=/dev/zero of=fip/u-boot.bin.gxbb bs=512 seek=8 count=1 conv=fsync,notrunc
+ $ dd if=bl1.bin.hardkernel of=fip/u-boot.bin.gxbb bs=512 seek=2 skip=2 count=1 conv=fsync,notrunc
+ $ ./aml_chksum fip/u-boot.bin.gxbb
+ $ dd if=fip/u-boot.gxbb of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.gxbb of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for Amlogic P201
-=======================
+U-Boot for Amlogic P201 (S905)
+==============================
-P201 is a reference board manufactured by Amlogic with the following
-specifications:
+P201 is a reference board manufactured by Amlogic with the following specifications:
- Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz
- ARM Mali 450 GPU
- 2GB DDR3 SDRAM
- 10/100 Ethernet
- HDMI 2.0 4K/60Hz display
- - 2 x USB 2.0 Host
+ - 2x USB 2.0 Host
- eMMC, microSD
- Infrared receiver
- SDIO WiFi Module
- - CVBS+Stereo Audio Jack
+ - CVBS + Stereo Audio Jack
Schematics are available from Amlogic on demand.
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make p201_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `p201`
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh p201 /path/to/u-boot/u-boot.bin my-output-dir
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image but sources have been shared by Linux development contractor, Baylibre:
.. code-block:: bash
$ cp $FIPDIR/gxb/bl301.bin fip/
$ cp $FIPDIR/gxb/bl31.img fip/
$ cp u-boot.bin fip/bl33.bin
+ $ wget https://github.com/LibreELEC/amlogic-boot-fip/raw/master/nanopi-k2/bl1.bin.hardkernel fip/bl1.bin.hardkernel
+ $ chmod +x fip/bl1.bin.hardkernel
+ $ wget https://github.com/LibreELEC/amlogic-boot-fip/raw/master/nanopi-k2/aml_chksum fip/aml_chksum
+ $ chmod +x fip/aml_chksum
$ $FIPDIR/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
$ $FIPDIR/blx_fix.sh \
- fip/bl2_acs.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/bl21.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
-
- $ $FIPDIR/fip_create --bl30 fip/bl30_new.bin --bl31 fip/bl31.img --bl33 fip/bl33.bin fip/fip.bin
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ $ $FIPDIR/fip_create --bl30 fip/bl30_new.bin \
+ --bl31 fip/bl31.img \
+ --bl33 fip/bl33.bin \
+ fip/fip.bin
$ cat fip/bl2_new.bin fip/fip.bin >fip/boot_new.bin
- $ $FIPDIR/gxb/aml_encrypt_gxb --bootsig --input fip/boot_new.bin --output fip/u-boot.bin
+ $ $FIPDIR/gxb/aml_encrypt_gxb --bootsig \
+ --input fip/boot_new.bin \
+ --output fip/u-boot.bin
-and then write the image to SD with:
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ DEV=/dev/boot_device
+ $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 conv=fsync
+ $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 seek=9 skip=8 count=87 conv=fsync,notrunc
+ $ dd if=/dev/zero of=fip/u-boot.bin.gxbb bs=512 seek=8 count=1 conv=fsync,notrunc
+ $ dd if=bl1.bin.hardkernel of=fip/u-boot.bin.gxbb bs=512 seek=2 skip=2 count=1 conv=fsync,notrunc
+ $ ./aml_chksum fip/u-boot.bin.gxbb
+ $ dd if=fip/u-boot.gxbb of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.gxbb of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-Pre-Generated FIP file set
-==========================
+Pre-Generated FIP File Repo
+===========================
-The Amlogic ARMv8 based SoCs uses a vendor variant of the Trusted Firmware-A
-boot architecture.
+Pre-built Flattened Image Package (FIP) sources and Amlogic signing binaries for many
+commercially available boards and some Android STB devices are collected for use with
+distro build-systems here: https://github.com/LibreELEC/amlogic-boot-fip
-You can find documentation on the Trusted Firmware-A architecture on: https://www.trustedfirmware.org/projects/tf-a/
+Using the pre-built FIP sources to sign U-Boot is simple, e.g. for LePotato:
-The Trusted Firmware-A uses the following boot elements (simplified):
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh lepotato /path/to/u-boot/u-boot.bin my-output-dir
+
+Then write U-Boot to SD or eMMC with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/boot_device
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
+
+Files Included
+--------------
+
+Amlogic ARMv8 SoCs use a vendor modified variant of the ARM Trusted Firmware-A boot
+architecture. See documentation here: https://www.trustedfirmware.org/projects/tf-a/
+
+Trusted Firmware-A uses the following boot elements (simplified):
+
+- BL1: First boot step implemented in ROM on Amlogic SoCs
+
+- BL2: Second boot step used to initialize the SoC main clocks & DDR interface. BL21
+ and ACS board-specific binaries must be "inserted" into the BL2 binary before signing
+ and packaging in order to be flashed on the platform
+
+- BL30: Amlogic Secure Co-Processor (SCP) firmware used to handle all system management
+ operations (DVFS, suspend/resume, ..)
+
+- BL301: Amlogic Secure Co-Processor (SCP) board-specific firmware "plug-in" to handle
+ custom DVFS & suspend-resume parameters
-- BL1: First boot step, implemented in ROM on Amlogic SoCs
-- BL2: Second boot step, used to initialize the SoC main clocks & DDR interface. The BL21 and ACS board-specific binaries are "inserted" in the BL32 binary before signing/packaging in order to be flashed on the platform.
-- BL30: Amlogic Secure Co-Processor (SCP) firmware used to handle all the system management operations (DVFS, suspend/resume, ...)
-- BL301: Amlogic Secure Co-Processor (SCP) board-specific firmware "plug-in" to handle custom DVFS & suspend-resume parameters
- BL31: Initializes the interrupt controller and the system management interface (PSCI)
-- BL32 (Optional): Is the Trusted Environment Execution (TEE) Operating System to run secure Trusted Apps, e.g. OP-TEE
+
+- BL32 (Optional): Is the Trusted Environment Execution (TEE) Operating System used to
+ run secure Trusted Apps, e.g. OP-TEE
+
- BL33: Is the last non-secure step, usually U-Boot which loads Linux
-Amlogic provides in binary form:
+Amlogic sources provide the following binaries:
- bl2.bin
- bl30.bin
- bl31.img
- bl32.bin
-And for lastest SoCs, Amlogic also provides the DDR drivers used by the BL2 binary.
+For G12A/B and SM1 Amlogic also provides DDR drivers used by the BL2 binary:
+
+- ddr4_1d.fw
+- ddr4_2d.fw
+- ddr3_1d.fw
+- piei.fw
+- lpddr4_1d.fw
+- lpddr4_2d.fw
+- diag_lpddr4.fw
+- aml_ddr.fw
+
+The following files are generated from the Amlogic U-Boot fork:
+
+- acs.bin: Contains the PLL & DDR parameters for the board
+- bl301.bin: Contains the DVFS & suspend-resume handling code for the board
+- bl33.bin: U-boot binary image
+
+The acs.bin and bl301.bin files use U-Boot GPL-2.0+ headers and U-Boot build system and
+are thus considered to be issued from GPL-2.0+ source code.
+
+Amlogic alo provides pre-compiled x86_64 and Python2 binaries:
-The licence of these files wasn't clear until recently, the currently Amlogic distribution licence
-is the following:
+- aml_encrypt_gxb
+- aml_encrypt_gxl
+- aml_encrypt_g12a
+- aml_encrypt_g12b
+- acs_tool.pyc
+
+The repo replaces the pre-compiled acs_tool.pyc with a Python3 acs_tool.py that can be
+used with modern build hosts.
+
+The repo also provides the following files used with GXBB boards:
+
+- bl1.bin.hardkernel
+- aml_chksum
+
+The repo also supports the open-source 'gxlimg' signing tool that can be used to sign
+U-Boot binaries for GXL/GXM/G12A/G12B/SM1 boards: https://github.com/repk/gxlimg
+
+Licensing
+---------
+
+The licence of Amlogic provided binaries was not historically clear but has now been
+clarified. The current Amlogic distribution licence is below:
.. code-block:: C
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-The following files are generated from the Amlogic U-Boot fork:
-
-- acs.bin: contains the PLL & DDR parameters for the board
-- bl301.bin: contains the DVFS & suspend-resume handling code for the board
-- bl33.bin: U-boot binary image
-
-The acs.bin & bl301.bin uses the U-Boot GPL-2.0+ headers & build systems, thus those
-are considered issued from GPL-2.0+ source code.
-
-The tools used to sign & package those binary files are delivered in binary format
-for Intel x86-64 and Python 2.x only.
-
-A collection of pre-built with the corresponding Amlogic binaries for the common
-commercially available boards were collected in the https://github.com/LibreELEC/amlogic-boot-fip
-repository.
-
-Using this collection for a commercially available board is very easy.
-
-Here considering the Libre Computer AML-S905X-CC, which codename is `lepotato`:
-
-.. code-block:: bash
-
- $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
- $ cd amlogic-boot-fip
- $ mkdir my-output-dir
- $ ./build-fip.sh lepotato /path/to/u-boot/u-boot.bin my-output-dir
-
-and then write the image to SD with:
-
-.. code-block:: bash
-
- $ DEV=/dev/your_sd_device
- $ dd if=my-output-dir/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=my-output-dir/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for Amlogic Q200
-=======================
+U-Boot for Amlogic Q200 (S912)
+==============================
-Q200 is a reference board manufactured by Amlogic with the following
-specifications:
+Q200 is a reference board manufactured by Amlogic with the following specifications:
- Amlogic S912 ARM Cortex-A53 octo-core SoC @ 1.5GHz
- ARM Mali T860 GPU
- 2/3GB DDR4 SDRAM
- 10/100/1000 Ethernet
- HDMI 2.0 4K/60Hz display
- - 2 x USB 2.0 Host, 1 x USB 2.0 Device
+ - 2x USB 2.0 Host
+ - 1x USB 2.0 Device
- 16GB/32GB/64GB eMMC
- 2MB SPI Flash
- microSD
- SDIO Wifi Module, Bluetooth
- IR receiver
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make khadas-vim2_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh q200 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image but sources have been shared by Linux development contractor, Baylibre:
.. code-block:: bash
$ make
$ export FIPDIR=$PWD/fip
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ $FIPDIR/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
$ $FIPDIR/blx_fix.sh \
- fip/bl2_acs.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/bl21.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
$ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
$ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
$ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
$ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc
-and then write the image to SD with:
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for Radxa Zero
-=====================
+U-Boot for Radxa Zero (S905Y2)
+==============================
-Radxa Zero is a small form factor SBC based on the Amlogic S905Y2
-chipset that ships in a number of RAM/eMMC configurations:
+Radxa Zero is a small form factor SBC based on the Amlogic S905Y2 chipset that ships in
+a number of RAM/eMMC configurations:
-Boards with 512MB/1GB LPDDR4 RAM have no eMMC storage and BCM43436
-wireless (2.4GHz b/g/n) while 2GB/4GB boards have 8/16/32/64/128GB
-eMMC storage and BCM4345 wireless (2.4/5GHz a/b/g/n/ac).
+512MB/1GB LPDDR4 RAM boards have no eMMC and BCM43436 wireless (2.4GHz b/g/n) while the
+2GB/4GB boards have 8/16/32/64/128GB eMMC and BCM4345 wireless (2.4/5GHz a/b/g/n/ac).
- Amlogic S905Y2 quad-core Cortex-A53
- Mali G31-MP2 GPU
- 1x micro SD Card slot
- 40 Pin GPIO header
-Schematics are available on the manufacturer website:
+Schematics are available on the manufacturer website: https://dl.radxa.com/zero/docs/hw
-https://dl.radxa.com/zero/docs/hw/RADAX_ZERO_V13_SCH_20210309.pdf
-
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make radxa-zero_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh radxa-zero /path/to/u-boot/u-boot.bin my-output-dir
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `radxa-zero`
+U-Boot Manual Signing
+---------------------
-Amlogic does not provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-git trees published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ cd ../fip/radxa-zero
$ make
-This will generate:
+This will generate the signed U-Boot binaries:
.. code-block:: bash
$ u-boot.bin u-boot.bin.sd.bin u-boot.bin.usb.bl2 u-boot.bin.usb.tpl
-Then write the image to SD with:
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Radxa Zero2 (A311D)
+==============================
+
+Radxa Zero2 is a small form factor SBC based on the Amlogic A311D chipset with the
+following specification:
+
+- Amlogic A311D (Quad A73 + Dual A53) CPU
+- 4GB LPDDR4 RAM
+- 32/64/128GB eMMC
+- Mali G52-MP4 GPU
+- HDMI 2.1 output (micro)
+- BCM4345 WiFi (2.4/5GHz a/b/g/n/ac) and BT 5.0
+- 1x USB 2.0 port - Type C (OTG)
+- 1x USB 3.0 port - Type C (Host)
+- 1x micro SD Card slot
+- 40 Pin GPIO header
+
+Schematics are available on request from Radxa.
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-none-elf-
+ $ make radxa-zero2_defconfig
+ $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh radxa-zero2 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
+
+.. code-block:: bash
+
+ $ git clone -b radxa-zero-v2021.07 https://github.com/radxa/u-boot.git
+ $ git clone https://github.com/radxa/fip.git
+
+ $ sudo apt-get install -y gcc-aarch64-linux-gnu device-tree-compiler libncurses5 libncurses5-dev
+ $ sudo apt-get install -y bc python dosfstools flex build-essential libssl-dev mtools
+
+ $ wget https://developer.arm.com/-/media/Files/downloads/gnu-a/10.3-2021.07/binrel/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz
+ $ sudo tar xvf gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz -C /opt
+
+ $ export CROSS_COMPILE=/opt/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf/bin/aarch64-none-elf-
+ $ export ARCH=arm
+ $ cd u-boot
+ $ make radxa-zero2_defconfig
+ $ make
+
+ $ cp u-boot.bin ../fip/radxa-zero2/bl33.bin
+ $ cd ../fip/radxa-zero2
+ $ make
+
+This will generate the signed U-Boot binaries:
+
+.. code-block:: bash
+
+ $ u-boot.bin u-boot.bin.sd.bin u-boot.bin.usb.bl2 u-boot.bin.usb.tpl
+
+Then write U-Boot to SD or eMMC with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/boot_device
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for Amlogic S400
-=======================
+U-Boot for Amlogic S400 (A113X)
+===============================
-S400 is a reference board manufactured by Amlogic with the following
-specifications:
+S400 is a reference board manufactured by Amlogic with the following specifications:
- - Amlogic A113DX ARM Cortex-A53 quad-core SoC @ 1.2GHz
+ - Amlogic A113X ARM Cortex-A53 quad-core SoC @ 1.2GHz
- 1GB DDR4 SDRAM
- 10/100 Ethernet
- - 2 x USB 2.0 Host
+ - 2x USB 2.0 Host
- eMMC
- Infrared receiver
- SDIO WiFi Module
Schematics are available from Amlogic on demand.
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make s400_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `s400`
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh s400 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image but sources have been shared by Linux development contractor, Baylibre:
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ $FIPDIR/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
$ $FIPDIR/blx_fix.sh \
- fip/bl2_acs.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/bl21.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl30_new.bin \
- --output fip/bl30_new.bin.enc \
- --level v3 --type bl30
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
$ $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl31.img \
- --output fip/bl31.img.enc \
- --level v3 --type bl31
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
$ $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl33.bin --compress lz4 \
- --output fip/bl33.bin.enc \
- --level v3 --type bl33
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33
$ $FIPDIR/axg/aml_encrypt_axg --bl2sig --input fip/bl2_new.bin \
- --output fip/bl2.n.bin.sig
+ --output fip/bl2.n.bin.sig
$ $FIPDIR/axg/aml_encrypt_axg --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc --level v3
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc --level v3
-and then write the image to SD with:
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for Amlogic SEI510
-=========================
+U-Boot for Amlogic SEI510 (S905X2)
+==================================
-SEI510 is a customer board manufactured by SEI Robotics with the following
-specifications:
+SEI510 is a customer board manufactured by SEI Robotics with the following specification:
- Amlogic S905X2 ARM Cortex-A53 quad-core SoC
- 2GB DDR4 SDRAM
- 10/100 Ethernet (Internal PHY)
- - 1 x USB 3.0 Host
+ - 1x USB 3.0 Host
- eMMC
- SDcard
- Infrared receiver
- SDIO WiFi Module
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make sei510_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `sei510`
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh sei510 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ make
$ export UBOOTDIR=$PWD
-Download the latest Amlogic Buildroot package, and extract it :
+Download the latest Amlogic Buildroot package and extract it:
.. code-block:: bash
$ export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706
$ export FIPDIR=$BRDIR/bootloader/uboot-repo/fip
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ sh fip/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ sh fip/blx_fix.sh \
- fip/bl2.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/acs.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ $FIPDIR/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
- --output fip/bl30_new.bin.g12a.enc \
- --level v3
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
$ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
- --output fip/bl30_new.bin.enc \
- --level v3 --type bl30
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
$ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
- --output fip/bl31.img.enc \
- --level v3 --type bl31
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
$ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
- --output fip/bl33.bin.enc \
- --level v3 --type bl33
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33
$ $FIPDIR/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
- --output fip/bl2.n.bin.sig
+ --output fip/bl2.n.bin.sig
$ $FIPDIR/g12a/aml_encrypt_g12a --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc \
- --ddrfw1 fip/ddr4_1d.fw \
- --ddrfw2 fip/ddr4_2d.fw \
- --ddrfw3 fip/ddr3_1d.fw \
- --ddrfw4 fip/piei.fw \
- --ddrfw5 fip/lpddr4_1d.fw \
- --ddrfw6 fip/lpddr4_2d.fw \
- --ddrfw7 fip/diag_lpddr4.fw \
- --level v3
-
-and then write the image to SD with:
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --level v3
+
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for Amlogic SEI610
-=========================
+U-Boot for Amlogic SEI610 (S905X3)
+==================================
-SEI610 is a customer board manufactured by SEI Robotics with the following
-specifications:
+SEI610 is a customer board manufactured by SEI Robotics with the following specification:
- Amlogic S905X3 ARM Cortex-A55 quad-core SoC
- 2GB DDR4 SDRAM
- 10/100 Ethernet (Internal PHY)
- - 1 x USB 3.0 Host
- - 1 x USB Type-C DRD
- - 1 x FTDI USB Serial Debug Interface
+ - 1x USB 3.0 Host
+ - 1x USB Type-C DRD
+ - 1x FTDI USB Serial Debug Interface
- eMMC
- SDcard
- Infrared receiver
- SDIO WiFi Module
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make sei610_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `sei610`
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh sei610 /path/to/u-boot/u-boot.bin my-output-dir
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ make
$ export UBOOTDIR=$PWD
-Download the latest Amlogic Buildroot package, and extract it :
+Download the latest Amlogic buildroot package and extract it:
.. code-block:: bash
$ export BRDIR=$PWD/buildroot-openlinux-A113-201901
$ export FIPDIR=$BRDIR/bootloader/uboot-repo/fip
-Go back to mainline U-Boot source tree then :
-
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ sh fip/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ sh fip/blx_fix.sh \
- fip/bl2.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/acs.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ $FIPDIR/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
- --output fip/bl30_new.bin.g12a.enc \
- --level v3
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
$ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
- --output fip/bl30_new.bin.enc \
- --level v3 --type bl30
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
$ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
- --output fip/bl31.img.enc \
- --level v3 --type bl31
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
$ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
- --output fip/bl33.bin.enc \
- --level v3 --type bl33
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33
$ $FIPDIR/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
- --output fip/bl2.n.bin.sig
+ --output fip/bl2.n.bin.sig
$ $FIPDIR/g12a/aml_encrypt_g12a --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc \
- --ddrfw1 fip/ddr4_1d.fw \
- --ddrfw2 fip/ddr4_2d.fw \
- --ddrfw3 fip/ddr3_1d.fw \
- --ddrfw4 fip/piei.fw \
- --ddrfw5 fip/lpddr4_1d.fw \
- --ddrfw6 fip/lpddr4_2d.fw \
- --ddrfw7 fip/diag_lpddr4.fw \
- --level v3
-
-and then write the image to SD with:
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --level v3
+
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for Amlogic U200
-=======================
+U-Boot for Amlogic U200 (S905X2)
+================================
-U200 is a reference board manufactured by Amlogic with the following
-specifications:
+U200 is a reference board manufactured by Amlogic with the following specification:
- Amlogic S905D2 ARM Cortex-A53 quad-core SoC
- 2GB DDR4 SDRAM
- 10/100 Ethernet (Internal PHY)
- - 1 x USB 3.0 Host
+ - 1x USB 3.0 Host
- eMMC
- SDcard
- Infrared receiver
Schematics are available from Amlogic on demand.
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make u200_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `u200`
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh u200 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ make
$ export UBOOTDIR=$PWD
-Download the latest Amlogic Buildroot package, and extract it :
+Download the latest Amlogic buildroot package and extract it:
.. code-block:: bash
$ export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706
$ export FIPDIR=$BRDIR/bootloader/uboot-repo/fip
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ sh fip/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ sh fip/blx_fix.sh \
- fip/bl2.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/acs.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ $FIPDIR/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
- --output fip/bl30_new.bin.g12a.enc \
- --level v3
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
$ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
- --output fip/bl30_new.bin.enc \
- --level v3 --type bl30
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
$ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
- --output fip/bl31.img.enc \
- --level v3 --type bl31
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
$ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
- --output fip/bl33.bin.enc \
- --level v3 --type bl33
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33
$ $FIPDIR/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
- --output fip/bl2.n.bin.sig
+ --output fip/bl2.n.bin.sig
$ $FIPDIR/g12a/aml_encrypt_g12a --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc \
- --ddrfw1 fip/ddr4_1d.fw \
- --ddrfw2 fip/ddr4_2d.fw \
- --ddrfw3 fip/ddr3_1d.fw \
- --ddrfw4 fip/piei.fw \
- --ddrfw5 fip/lpddr4_1d.fw \
- --ddrfw6 fip/lpddr4_2d.fw \
- --ddrfw7 fip/diag_lpddr4.fw \
- --level v3
-
-and then write the image to SD with:
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --level v3
+
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for Amlogic W400
-=======================
+U-Boot for Amlogic W400 (S922X)
+===============================
-U200 is a reference board manufactured by Amlogic with the following
-specifications:
+W400 is a reference board manufactured by Amlogic with the following specification:
- Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC
- 2GB DDR4 SDRAM
- 10/100 Ethernet (Internal PHY)
- - 1 x USB 3.0 Host
+ - 1x USB 3.0 Host
- eMMC
- SDcard
- Infrared receiver
Schematics are available from Amlogic on demand.
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make w400_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh jethub-j100 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ make
$ export UBOOTDIR=$PWD
-Download the latest Amlogic Buildroot package, and extract it :
+Download the latest Amlogic buildroot package and extract it:
.. code-block:: bash
$ export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706
$ export FIPDIR=$BRDIR/bootloader/uboot-repo/fip
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ sh fip/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ sh fip/blx_fix.sh \
- fip/bl2.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/acs.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ $FIPDIR/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
- --output fip/bl30_new.bin.g12a.enc \
- --level v3
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
$ $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
- --output fip/bl30_new.bin.enc \
- --level v3 --type bl30
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
$ $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
- --output fip/bl31.img.enc \
- --level v3 --type bl31
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
$ $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
- --output fip/bl33.bin.enc \
- --level v3 --type bl33
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33
$ $FIPDIR/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
- --output fip/bl2.n.bin.sig
+ --output fip/bl2.n.bin.sig
$ $FIPDIR/g12b/aml_encrypt_g12b --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc \
- --ddrfw1 fip/ddr4_1d.fw \
- --ddrfw2 fip/ddr4_2d.fw \
- --ddrfw3 fip/ddr3_1d.fw \
- --ddrfw4 fip/piei.fw \
- --ddrfw5 fip/lpddr4_1d.fw \
- --ddrfw6 fip/lpddr4_2d.fw \
- --ddrfw7 fip/diag_lpddr4.fw \
- --ddrfw8 fip/aml_ddr.fw \
- --level v3
-
-and then write the image to SD with:
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --level v3
+
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for WeTek Core2
-======================
+U-Boot for WeTek Core2 (S912)
+=============================
-WeTek Core2 is an Android STB based on the Q200 reference design with
-the following specifications:
+WeTek Core2 is an Android STB based on the Q200 reference design with the following
+specifications:
- Amlogic S912 ARM Cortex-A53 octo-core SoC @ 1.5GHz
- ARM Mali T820 GPU
- 3GB DDR4 SDRAM
- 10/100 Realtek RTL8152 Ethernet (internal USB)
- HDMI 2.0 4K/60Hz display
- - 2x USB 2.0 Host, 1x USB 2.0 OTG (internal)
+ - 2x USB 2.0 Host
+ - 1x USB 2.0 OTG (internal)
- 32GB eMMC
- microSD
- SDIO Wifi Module, Bluetooth
- Two channel IR receiver
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make wetek-core2_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `wetek-core2`
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh wetek-core2 /path/to/u-boot/u-boot.bin my-output-dir
-Amlogic does not provide sources for the firmware or the tools needed
-to create the bootloader image, and WeTek has not publicly shared the
-precompiled FIP binaries. However the public Khadas VIM2 sources also
-work with the Core2 box so we can use the Khadas git tree:
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide firmware sources or tools needed to create the bootloader image
+and WeTek has not publicly shared the precompiled FIP binaries. However the Khadas VIM2
+sources also work with the Core2 box so we can use the Khadas git tree:
.. code-block:: bash
$ make
$ export FIPDIR=$PWD/fip
-Go back to mainline U-Boot source tree then:
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ cp $FIPDIR/gxl/bl301.bin fip/
$ cp $FIPDIR/gxl/bl31.img fip/
$ cp u-boot.bin fip/bl33.bin
+
$ $FIPDIR/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
$ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
$ $FIPDIR/blx_fix.sh \
- fip/bl2_acs.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/bl21.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
$ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
$ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
$ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
$ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
$ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc
-then write the image to SD with:
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for WeTek Hub (S905)
+===========================
+
+WeTek Hub is a small form-factor Android STB manufactured by WeTek with the following
+specification:
+
+ - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz
+ - ARM Mali 450 GPU
+ - 1GB DDR3 SDRAM
+ - 8GB eMMC
+ - Gigabit Ethernet
+ - HDMI 2.0 4K/60Hz display
+ - 1x USB otg
+ - microSD
+ - UART jack
+ - Infrared receiver
+
+Schematics are not publicly available but have been shared privately to maintainers.
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-none-elf-
+ $ make wetek-hub_defconfig
+ $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh wetek-hub /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image and WeTek has not publicly shared the U-Boot sources needed to build FIP binaries
+for signing. However you can download them from the amlogic-fip-repo.
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip/wetek-hub
+ $ export FIPDIR=$PWD
+
+Go back to the mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+ $ mkdir fip
+
+ $ cp $FIPDIR/bl2.bin fip/
+ $ cp $FIPDIR/acs.bin fip/
+ $ cp $FIPDIR/bl21.bin fip/
+ $ cp $FIPDIR/bl30.bin fip/
+ $ cp $FIPDIR/bl301.bin fip/
+ $ cp $FIPDIR/bl31.img fip/
+ $ cp u-boot.bin fip/bl33.bin
+
+ $ $FIPDIR/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ $ $FIPDIR/fip_create --bl30 fip/bl30_new.bin \
+ --bl31 fip/bl31.img \
+ --bl33 fip/bl33.bin \
+ fip/fip.bin
+
+ $ sed -i 's/\x73\x02\x08\x91/\x1F\x20\x03\xD5/' fip/bl2.bin
+ $ python3 $FIPDIR/acs_tool.py fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+ $ $FIPDIR/blx_fix.sh \
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ $ cat fip/bl2_new.bin fip/fip.bin > fip/boot_new.bin
+
+ $ $FIPDIR/aml_encrypt_gxb --bootsig \
+ --input fip/boot_new.bin
+ --output fip/u-boot.bin
+
+Then write U-Boot to SD or eMMC with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/boot_device
+ $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 conv=fsync
+ $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 seek=9 skip=8 count=87 conv=fsync,notrunc
+ $ dd if=/dev/zero of=fip/u-boot.bin.gxbb bs=512 seek=8 count=1 conv=fsync,notrunc
+ $ dd if=bl1.bin.hardkernel of=fip/u-boot.bin.gxbb bs=512 seek=2 skip=2 count=1 conv=fsync,notrunc
+ $ ./aml_chksum fip/u-boot.bin.gxbb
+ $ dd if=fip/u-boot.gxbb of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.gxbb of=$DEV conv=fsync,notrunc bs=1 count=440
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for WeTek Play2 (S905)
+=============================
+
+WeTek Play2 is an Android STB manufactured by WeTek with the following specification:
+
+ - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz
+ - ARM Mali 450 GPU
+ - 2GB DDR3 SDRAM
+ - 8GB eMMC
+ - Gigabit Ethernet
+ - AP6335 (v1) or AP6255 (v2) WiFi (b/g/n) and BT 4.0
+ - HDMI 2.0 4K/60Hz display
+ - 2x USB 2.0 host
+ - 1x USB 2.0 otg
+ - microSD
+ - UART jack
+ - Infrared receiver
+ - Power LED (blue)
+ - Power button (case, front)
+ - Reset button (underside)
+ - DVB Card: DVB-S or DVB-T/C or ATSC
+
+Schematics are not publicly available but have been shared privately to maintainers.
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-none-elf-
+ $ make wetek-play2_defconfig
+ $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh wetek-play2 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image and WeTek has not publicly shared the U-Boot sources needed to build FIP binaries
+for signing. However you can download them from the amlogic-fip-repo.
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip/wetek-play2
+ $ export FIPDIR=$PWD
+
+Go back to the mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+ $ mkdir fip
+
+ $ cp $FIPDIR/bl2.bin fip/
+ $ cp $FIPDIR/acs.bin fip/
+ $ cp $FIPDIR/bl21.bin fip/
+ $ cp $FIPDIR/bl30.bin fip/
+ $ cp $FIPDIR/bl301.bin fip/
+ $ cp $FIPDIR/bl31.img fip/
+ $ cp u-boot.bin fip/bl33.bin
+
+ $ $FIPDIR/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ $ $FIPDIR/fip_create --bl30 fip/bl30_new.bin \
+ --bl31 fip/bl31.img \
+ --bl33 fip/bl33.bin \
+ fip/fip.bin
+
+ $ sed -i 's/\x73\x02\x08\x91/\x1F\x20\x03\xD5/' fip/bl2.bin
+ $ python3 $FIPDIR/acs_tool.py fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+ $ $FIPDIR/blx_fix.sh \
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ $ cat fip/bl2_new.bin fip/fip.bin > fip/boot_new.bin
+
+ $ $FIPDIR/aml_encrypt_gxb --bootsig \
+ --input fip/boot_new.bin
+ --output fip/u-boot.bin
+
+Then write U-Boot to SD or eMMC with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/boot_device
+ $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 conv=fsync
+ $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 seek=9 skip=8 count=87 conv=fsync,notrunc
+ $ dd if=/dev/zero of=fip/u-boot.bin.gxbb bs=512 seek=8 count=1 conv=fsync,notrunc
+ $ dd if=bl1.bin.hardkernel of=fip/u-boot.bin.gxbb bs=512 seek=2 skip=2 count=1 conv=fsync,notrunc
+ $ ./aml_chksum fip/u-boot.bin.gxbb
+ $ dd if=fip/u-boot.gxbb of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.gxbb of=$DEV conv=fsync,notrunc bs=1 count=440
projects / platform / kernel / u-boot.git / commitdiff