======================================================================
-Changes for U-Boot 1.1.4:
+Changes since U-Boot 1.1.4:
======================================================================
-* Rewrite of NAND code based on what is in 2.6.12 Linux kernel
+* Merge the new NAND code (testing-NAND brach)
+
+ Rewrite of NAND code based on what is in 2.6.12 Linux kernel
Patch by Ladislav Michl, 29 Jun 2005
+* Update default environment for INKA4x00 board.
+
+* Cleanup U-Boot boot messages on ARM.
+
+ To match the U-Boot user interface on ARM platforms to the U-Boot
+ standard (as on PPC platforms), some messages with debug character
+ are removed from the default U-Boot build.
+ Enable DEBUG for lib_arm/board.c to enable debug messages.
+ New CONFIG_DISPLAY_CPUINFO and CONFIG_DISPLAY_BOARDINFO options.
+ Patch by Stefan Roese, 24 Jan 2006
+
+* Fix various compiler warnings on ppc4xx builds (ELDK 4.0)
+ Patch by Stefan Roese, 18 Jan 2006
+
+* Add VGA support (CT69000) to CPCI750 board.
+ Insert missing __le32_to_cpu() for filesize in ext2fs_read_file().
+ Patch by Reinhard Arlt, 30 Dec 2005
+
+* PMC405 and CPCI405: Moved configuration of pci resources
+ into config file.
+ PMC405 and CPCI2DP: Added firmware download and booting via pci.
+ Patch by Matthias Fuchs, 20 Dec 2005
+
+* Fix 28F256J3A support on PM520 board
+ (without bank-switching only 32 MB can be accessed)
+
+* Fix mkimage bug with multifile images created on 64 bit systems.
+
+* Add support for 28F256J3A flash (=> 64 MB) on PM520 board
+
+* Fix compiler problem with at91rm9200dk board.
+ Patch by Eugen Bigz, 19 Dec 2005
+
+======================================================================
+Changes for U-Boot 1.1.4:
+======================================================================
+
+* Changes to Yellowstone & Yosemite 440EP/GR eval boards:
+ - Changed GPIO setup to enable another address line in order to
+ address 64M of FLASH.
+ - Added function sdram_tr1_set to auto calculate the tr1 value for
+ the DDR.
+ Patch by Steven Blakeslee, 12 Dec 2005
+
+* MPC5200: Set PCI retry counter to 0 = infinite retry;
+ The default of 255 is too short for slow devices.
+ Patch by Martin Nykodym, 12 Dec 2005
+
+* Change port configuration for O2DNT (CODEC1 on PSC1).
+
+* Fix register for PCI async mode on PPC440EP
+ Patch by Youngchul Bang, 08 Dec 2005
+
+* Fix U-Boot linking problems (add .eh_frame segment to linker script)
+ This segment may be required by some libgcc.a functions
+ (like _udivdi3).
+
+* Fix DPRAM offset/size for MPC8541/8555.
+ Simplify TQM85xx Makefile handling.
+
+* Fix data overflow (typo?) in rtc/ds1302.c
+
+* Fix U-Boot compilation for MIPS boards using ELDK 4.0
+
+* Add support for TQM8541/8555 boards, TQM85xx support reworked:
+ - Support for TQM8541/8555 boards added.
+ - Complete rework of TQM8540/8560 support.
+ - Common TQM85xx code now supports all current TQM85xx platforms
+ (TQM8540/8541/8555/8560).
+ - DDR SDRAM size detection added.
+ - CAS latency default values can be overwritten by setting "serial#"
+ to e.g. "ABC0001 casl=25" -> CAS latency 2.5 will be used.
+ If problems are detected with this non default CAS latency,
+ the default values will be used instead.
+ - Flash size detection added.
+ - Moved FCC ethernet driver initialization behind TSEC driver init
+ -> TSEC is first device.
+ Patch by Stefan Roese, 30 Nov 2005
+
+* Add support for AMCC 440SP, add support for AMCC Luan 440SP eval board.
+ Patch by John Otken, 23 Nov 2005
+
+* Changed PPC44x startup message (cpu info, speed...) to common style:
+ On PPC44x platforms, the startup message generated in "cpu.c" only
+ comprised the ppc type and revision but not additional information
+ like speed etc. Those speed infos where printed in the board specific
+ code. This new implementation now prints all CPU infos in the common
+ cpu specific code. No board specific code is needed anymore and
+ therefore removed from all current 44x implementations.
+ Patch by Stefan Roese, 27 Nov 2005
+
+* Adjust TQM834x PHY addresses for latest hardware revision.
+
+* Increase malloc arena on TQM5200 board to 256 kB.
+ With 64 kb uniform flash sector size the old value of 128 kB was
+ too small.
+
+* Fix miiphy global data initialization (problem on 4xx boards when
+ no ethaddr is assigned). Initialization moved from
+ miiphy_register() to eth_initialize().
+
+ Based on initial patch for 4xx platform by Matthias Fuchs.
+
+* Remove unnnecessary #include <linux/types.h> from include/asm-*/u-boot.h
+
+* Allow use of include/image.h and include/asm-*/u-boot.h in proprietary code.
+ The COPYING file was extended to make clear that these files can be
+ used in non-GPL code, too.
+ Also, a corresponding note was placed in the headers of the affected files.
+
+* Add support for Prodrive P3P440 board:
+ - Added onboard PPC440 DDR autodetection in cpu/ppc/sdram.c
+ - CFG_FLASH_QUIET_TEST added to use the common CFI driver
+ for bank autodetection
+ Patch by Stefan Roese, 22 Nov 2005
+
+* Change all '$(...)' variable references into '${...}'
+ which makes the environment compatible with the hush shell.
+ WARNING: Support for the old '$(...)' syntax will be
+ discontinued in a later version.
+
+* Minor changes to init flags in TQM834x PCI.
+
+* Fix Bamboo DDR SDRAM initialization (problem with onboard SDRAM)
+ Patch by Stefan Roese, 15 Nov 2005
+
+* New PPC 405EP board added: CMS700
+ Added CONFIG_NET_MULTI for VOM405 board.
+ Added reset_phy() for VOM405 board.
+ Patch by Matthias Fuchs, 09 Nov 2005
+
+* Updated PCI mapping for esd CPCI2DP board.
+ Add support for error LED.
+ Patch by Matthias Fuchs, 07 Nov 2005
+
+* Fix MPC85xx PCI support (pci_register_hose() before pci config access)
+ Patch by Stefan Roese, 07 Nov 2005
+
+* Correct PPC Timebase register definitions (SPRN_TBRL...)
+ Patch by Stefan Roese, 07 Nov 2005
+
+* Adjust bd->bi_flashstart on Yellowstone & Yosemite to correct size
+ Patch by Stefan Roese, 05 Nov 2005
+
+* Additional fix for external IRQ config on Yellowstone & Yosemite
+ Patch by Stefan Roese, 03 Nov 2005
+
+* Add support for Ocotea pass 3 with 440GX Rev. F
+ Patch by Stefan Roese, 01 Nov 2005
+
+* Fix external IRQ configuration on Yellowstone & Yosemite
+ Patch by Stefan Roese, 28 Oct 2005
+
+* Add support for multiple PHYs.
+ Tested on the following boards:
+ cmcpu2 (at91rm9200/ether.c)
+ PPChameleon (ppc4xx/4xx_enet.c)
+ yukon (mpc8220/fec.c)
+ uc100 (mpc8xx/fec.c)
+ tqm834x (mpc834x/tsec.c) with EEPRO100
+ lite5200 (mpc5xxx/fec.c) with EEPRO100 card (drivers/eepro100.c)
+ Main changes include:
+ common/miiphyutil.c
+ - miiphy_register routine was added to allow multiple PHYs to be registered
+ - miiphy_read and miiphy_write are now defined in this file, and
+ require additional argument (char *devname)
+ - other miiphy_* routines also require additional device name argument
+ ../lib_i386/board.c
+ ../lib_ppc/board.c
+ Calling reset_phy() was moved to be executed *after* eth_initialize().
+ This is necessary as now some of the implementations of reset_phy()
+ may need to use miiphy_reset() which is not allowed before eth_initialize()
+ as eth_initialize registers all required miiphy_* routines.
+ Tested on IP860 and PHY initializes properly after this change.
+
+* Correct includes for flat tree builder.
+
+* Fix conflicting types (flash_write()) in trab auto_update.c.
+
+* Add PCI support for the TQM834x board.
+
+* Add missing 4xx board to MAKEALL
+ Patch by Stefan Roese, 20 Oct 2005
+
+* Fix conflicting types (flash_write()) in esd auto_update.c
+ Patch by Stefan Roese, 20 Oct 2005
+
+* Fix problem with sleep in NetConsole (use get_timer())
+ Patch by Stefan Roese, 20 Oct 2005
+
+* Add NetConsole Support for AMCC eval boards
+ Patch by Stefan Roese, 20 Oct 2005
+
+* Fix NetConsole support on 4xx (only print eth link on 1st transfer)
+ Patch by Stefan Roese, 18 Oct 2005
+
+* Add fat & ext2 support to AMCC 440EP boards Yosemite & Bamboo.
+ Fix identation on ext2ls help entry.
+ Patch by Stefan Roese, 14 Oct 2005
+
+* Add support for TQM834x boards.
+ Cleanup.
+
+* Cleanup for GCC-4.x
+
+* Add documentation for Open Firmware Flat Tree and usage.
+ Patch by Pantelis Antoniou, 13 Oct 2005
+
+* Add missing files for Pantelis Antoniou's patch
+ Patch by Pantelis Antoniou, 04 Sep 2005
+
+* Fix problem in ppc4xx eth-driver without ethaddr (only without
+ CONFIG_NET_MULTI set)
+ Patch by Stefan Roese, 10 Oct 2005
+
+* Fix gzip bmp support (test if malloc fails, warning when truncated).
+ Increase CFG_VIDEO_LOGO_MAX_SIZE on HH405 board.
+ Patch by Stefan Roese, 07 Oct 2005
+
+* Add support for OF flat tree for the STXtc board.
+ Patch by Pantelis Antoniou, 04 Sep 2005
+
+* Support passing of OF flat trees to the kernel.
+ Patch by Pantelis Antoniou, 04 Sep 2005
+
+* Cleanup
+
+* Add support for NetSilicon NS7520 processor.
+ Patch by Art Shipkowski, 12 May 2005
+
+* Add support for AP1000 board.
+ Patch by James MacAulay, 07 Oct 2005
+
+* Eliminate hard-coded address of Ethernet transfer buffer on at91rm9200
+ Patch by Anders Larsen, 07 Oct 2005
+
+ The Atmel errata #11 states that the transfer buffer descriptor
+ table must be aligned on a 16-word boundary. As it turned out, this
+ is insufficient - it seems the table must be aligned on a boundary
+ at least as large as the table itself (in Linux this is not an
+ issue - the table is aligned on a PAGE_SIZE (4096) boundary).
+
+* Fixed compilation for ARM when using a (standard) hard-FP toolchain
+ Patch by Anders Larsen, 07 Oct 2005
+
+* Cleanup warnings for cpu/arm720t & cpu/arm1136 files.
+ sed the linker scripts, rather than pre-process them.
+ Patch by Peter Pearse, 07 Oct 2005
+
+* Update make target for ARM supported boards.
+ Use lowlevel_init() instead of platformsetup() [rename].
+ Patch by Peter Pearse, 06 Oct 2005
+
+* Fix booting from serial dataflash on AT91RM9200
+ Patch by Peter Menzebach, 29 Aug 2005
+
+* Add JFFS2 support for TRAB board
+ Patch by Martin Krause, 25 Aug 2005
+
+* Remove unnecessary dependency of netconsole on CONFIG_NET_MULTI
+ Patch by Marcus Hall, 24 Aug 2005
+
+* Fix the machine-id of the Cogent csb637 board
+ Patch by Anders Larsen, 05 Oct 2005
+
+* Complete support for the KwikByte KB920x boards
+ Patch by Anders Larsen, 05 Oct 2005
+
+* Set the AT91RM9200 clock to asynchronous mode
+ Patch by Anders Larsen, 03 May 2005
+
+* Set the AT91RM9200 clock to synchronous mode
+ Patch by Anders Larsen, 29 Apr 2005
+
+* Add support for Cogent csb637
+ Patch by Anders Larsen, 29 Apr 2005
+
+* Fix dm9161.c initialization
+ Patch by Anders Larsen, 29 Apr 2005
+
+* Fix problems introduced by Patch by Steven Scholz, 02 Mar 2005
+ (8e2be51de8dd03c1ce4d06cbb18ad06133d47cd5)
+
+* Move dm9161.c and lxt972.c into cpu/arm920t/at91rm9200
+ Patch by Anders Larsen, 29 Apr 2005
+
+* Fix device partition intialization for SystemACE disks.
+ Patch by Stephen Williams, 28 Apr 2005
+
+* Added support for KwikByte KB920x boards (based on AT91RM9200)
+ Patch by Matt ?? <kb9200_dev@kwikbyte.com>, 27 Apr 2005
+
+* Add support for S29GL064M-R3 flash chip on xsengine board
+ Patch by Kurt Stremerch, 18 Apr 2005
+
+* E500 update: repoint IVPR to RAM when code is relocated
+ Patch by Kylo Ginsberg, 13 Apr 2005
+
+* Fix loop end test in lib_generic/string.c:strswab()
+ Patch by Andrew Dyer, October 10, 2005
+ Signed-off-by: Andrew Dyer <amdyer@gmail.com>
+
+* Cleanup
+
+* Update ARM Integrator boards:
+ Correct addessing errors in platform files.
+ Split off common core module data from Integrator header files to
+ include/armcoremodule.h.
+ Patch by Peter Pearse, 04 Oct 2005
+
+* Make sure only supported compiler options are used
+ Import "cc-option" shell function from kernel and
+ use it to get the correct ARM GCC options for individual CPUs
+ Patch by Peter Pearse, 30 Jun 2005
+
+* Fix 440GR to print correct cpu revision
+ Patch by Stefan Roese, 04 Oct 2005
+
+* Change board message on AMCC Yosemite & Yellowstone to common style
+ Patch by Stefan Roese, 03 Oct 2005
+
+* Fix compiler warning
+
+* Fix FEC PHY addresses for TQM85xx boards
+
+* Fix uninitialized variable problem in hush shell
+ Patch by Lars Rostock, 26 Sep 2005
+
+* Undo change of f6e20fc6ca... to include/configs/trab.h
+ (Must have been an accident?)
+
+* Add support for AT91RM9200 OHCI Controller.
+ Patch by Eric Benard, 07 Apr 2005
+
+* Update ARM mach-types.h
+ Patch by Eric Benard, 07 Apr 2005
+
+* Add support for MP2USB board.
+ Patch by Eric Benard, 07 Apr 2005
+
+* Add board support for armadillo HT1070
+ Patch by Rowel Atienza, 06 Apr 2005
+
+* Second Ethernet address enabled for MPC885ADS and MPC8272ADS.
+ Patch by Vitaly Bordug, 30 Mar 2005
+
+* Add iopset command on mpc8xx
+ Patch by Daniel Eisenhut, 25 Mar 2005
+
+* Add support for MII in eepro100 driver.
+ Patch by Gleb Natapov, 21 Mar 2005
+
+* Fixes to the Lubbock (PXA 25x) support:
+ - Resolve the FIXME with respect to saving the u-boot environment.
+ - Make the default load address land in real memory.
+ - Fix lan91c96 SMC_{in,out}{b,w,l}() macros
+ Patch by David Brownell, 10 Mar 2005
+
+* Add Barco Streaming Video Card (SVC) and Sample Compress Network (SCN) board
+ Patch by Marc Leeman, 04 Mar 2005
+
+* OMAP242x H4 board update
+ - fix for ES2 differences.
+ - switch to using the cfi_flash driver.
+ - fix SRAM build address.
+ - fix for GP device operation.
+ - unlock SRAM for GP devices.
+ - display more device information.
+ - fix potential deadlock in omap24xx_i2c driver.
+ - fix DLL load values to match dpllout*1 operation.
+ - fix 2nd chip select init for combo DDR device.
+ - add support for CFI Intel 28F256L18 on H4 board.
+ Patch by Richard Woodruff, 03 Mar 2005
+
+* Fix formating in include/asm-arm/arch-at91rm9200/AT91RM9200.h
+ Patch by Steven Scholz, 02 Mar 2005
+
+* Fix typo in eth.c
+ Patch by Ara Avanesyan, 24 Feb 2005
+
+* Remove unneeded #include <malloc.h>
+ Patch by Ladislav Michl, 22 Feb 2005
+
+* Add cramfs support for m68k
+ Patch by Zachary Landau, 21 Feb 2005
+
+* Update ep8260: Fix flash timeouts; improve clock resolution for faster UARTs
+ Patch by Jeff Angielski, 21 Feb 2005
+
+* Fix au1x00_serial baud rate calculation:
+ remove hardcoded cpu clock divisor and use register instead;
+ round up instead of truncate
+ Patch by Andrew Dyer, 15 Feb 2005
+
+* Add Xilinx Spartan3 family FPGA support
+ Patch by Kurt Stremerch, 14 Feb 2005
+
+* Fix drivers/cfi_flash.c: use info->reset_cmd instead of FLASH_CMD_RESET
+ Patch by Zachary Landau, 11 Feb 2005
+
+* Fix VOH405 Support
+ Patch by Matthias Fuchs, 25 Sep 2005
+
+* Added support for PCI bridge on MPC8272ADS
+ Patch by Vitaly Bordug, Feb 09 2005
+
+* Update multicore CM9XX support for Integrator AP to allow booting from flash
+ Patch by Jean-Paul Saman, 8 Feb 2005
+
+* Fix strswab() to reliably find end of string
+ Patch by Andrew Dyer, 08 Feb 2005
+
+* Fix typos in include/ppc440.h
+ Patch by Andrew E Mileski, 04 Feb 2005
+
+* Add Vibren (was Accelent) PXA255 IDP Support
+ Patch by Cliff Brake, 04 Feb 2005
+
+* Fix tools/bmp_logo.c using incorrect offset to pixel data
+ Patch by Andrew Dyer, 31 Jan 2005
+
+* Add ARM946E cpu and core module targets; remap memory to 0x00000000
+ Patch by Peter Pearse, 2 Feb 2005
+
+* Fix error handling in tools/env/fw_env.c
+ Patch by Ara Avanesyan, 01 Feb 2005
+
+* Fix MGT5100 PSC baudrate calculation
+ Patch by Sebastian Schau, 27 Jan 2005
+
+* OMAP242x fix for GP device booting
+ - Add SRAM unlock for GP devices.
+ - Change DDR DLL unlock value to allow DPLLout*1 operation.
+ Patches by Richard Woodruff, 21 Jan 2005:
+
+* Add support for AMD's Pb1x00 eval board;
+ add MII routines to the au1x00 ethernet driver;
+ add USB ohci driver (work in progress)
+ Patch by Thomas Sailer, 20 Jan 2005
+
+* Update omap5912osk board
+ Use drivers/cfi_flash.c instead of private flash driver;
+ Remove hardcoded personalized settings from omap5912osk.h;
+ Fix spacing with (RO) marks in 'flinfo' output.
+ Patch by Michael Bendzick, 14 Jan 2005
+
+* Fix warnings for PCI code on ixp
+ Patch by Joe <lgxue@yahoo.com>, 13 Jan 2005
+
+* virtex2 fix for bogus download error messages
+ The virtex2 FPGA download code watches for init going active during
+ a download of config data as an error condition. init also goes
+ active after a configuration is finished in concert with the done
+ signal. So far, the code does not check for done active until all
+ of the configuration data is sent. If configuration data has a few
+ extra pad bytes at the end, this would cause an error message even
+ though the download had suceeded.
+ NOTE: virtex2 slave serial and spartan2 versions may still have the
+ same problem.
+ Patch by Andrew Dyer, 12 Jan 2005
+
+* Optimize flash_make_cmd in drivers/cfi_flash.c for little endian
+ Fix "WARNING: flash_make_cmd: unsuppported LittleEndian mode"
+ message when probing for nonexistent flash in little endian mode.
+ As a side effect more efficient and smaller code is generated,
+ which is always a Good Thing (TM).
+ Patch by Ladislav Michl, 24 Sep 2005
+
+* Update for TFTP using a fixed UDP port
+ Use the approved environment variable names. Added "tftpdstp" to
+ allow ports other than 69 per Tolunay Orkun's recommendation.
+ Patch by Jerry Van Baren, 12 Jan 2005
+
+* Allow to force TFTP to use a fixed UDP port
+ (Add a configuration option CONFIG_TFTP_PORT and optional env
+ variable tftpport)
+ Patch by Jerry Van Baren, 10 Jan 2005
+
+* Fix ethernet timeouts on dbau1550 and other au1x00 systems
+ Patch by Leif Lindholm, 29 Dec 2004
+
+* Cleanup: fix broken builds
+
+* Fix PHY address argument passing with mii info command
+ Patch by Andrew Dyer, 28 Dec 2004
+
+* Cleanup (PPC4xx is AMCC now)
+
+* esd CPCI2DP board added
+ Patch by Matthias Fuchs, 22 Sep 2005
+
+* esd PMC405 board updated
+ Patch by Matthias Fuchs, 22 Sep 2005
+
+* Add SM501 support to HH405 board.
+ Add support for gzip compressed bmp's (CONFIG_VIDEO_BMP_GZIP).
+ Add support for eeprom write-enable (CFG_EEPROM_WREN).
+ Patch by Stefan Roese, 22 Sep 2005
+
+* Fix autonegotiation in tsec ethernet driver
+ Patch by Stefan Roese, 21 Sep 2005
+
+* Fix bug in auto_update (trab board)
+ Patch by Martin Krause, 16 Sep 2005
+
+* Fix computation of framebuffer palette for 8bpp LCD bitmaps
+ Patch by Francesco Mandracci, 16 Sep 2005
+
+* Update configuration for INKA4x0 board
+
+* Update configuration for PM854 board
+ Based on patch by R. Loeffl, 20 Jul 2005
+
+* Add PCI support to TQM8540 and TQM8560 boards
+ Patch by Stefan Roese, 15 Sep 2005
+
+* Update AMCC Yosemite to get a consistent setup for all AMCC eval
+ boards (baudrate, environment...). Flash driver fixed.
+ Patch by Stefan Roese, 15 Sep 2005
+
+* Fix problem in 440GP ethernet driver (ebony). Add support for 2nd
+ ethernet port on ebony.
+ Patch by Stefan Roese, 7 Sep 2005
+
+* Added support for mtddevnum and mtddevname variables (mtdparts command)
+
+* Change default console baud rate for stxxtc board
+
+* Add I2C support to TQM8540 and TQM8560 boards (EEPROM, RTC, LM75-DTT).
+ Patch by Stefan Roese, 31 Aug 2005
+
+* Fix default command set (don't include CFG_CMD_DISPLAY command)
+ Patch by Pantelis Antoniou, 02 Sep 2005
+
+* Cleanup
+
+* Enable SM712 driver support for HMI1001 board.
+
+* Fix problems with ld version 2.16 (dot outside sections problem)
+ Pointed out by Gerhard Jaeger, 31 Aug 2005;
+ cf. http://sourceware.org/ml/binutils/2005-08/msg00412.html
+
+* Prepare U-Boot for gcc-4.x: fix global data pointer initialization
+
+* Adjust CS3 timings on HMI1001 board for dot matrix display under Linux
+
+* Add keyboard and dot matrix display support for HMI1001 board.
+
+* Prepare U-Boot for gcc-4.x
+
+* Fixed Bamboo port to enable running without DDR-DIMM
+ (Bamboo has also 64MB onboard DDR)
+ Patch by Stefan Roese, 24 Aug 2005
+
+* Merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
+ now handling all 4xx cpu's
+ Patch by Stefan Roese, 16 Aug 2005
+
+* Fix make dependencies for at91rm9200 and ks8695 cpus
+ Patch by Steven Scholz, 23 Aug 2005
+
+* Add JFFS2 support for TQM5200 board
+
+* Add esd cpci5200 and pf5200 boards
+ Patch by Reinhard Arlt, 22 Aug 2005
+
+* Fix sysclock for TQM8540 and TQM8560 boards
+ Patch by Martin Krause, 25 Jul 2005
+
+* Initialize serial# and ethaddr from manufacturer data in EEPROM on CMC-PU2
+ Patch by Martin Krause, 08 Jun 2005
+
+* Add new board specific commands for TQM5200/STK52XX
+ - Sound commands (beep, wav, sound)
+ - Test commands (led, can, backlight, rs232)
+ Patch by Martin Krause, 02 May 2005
+
+* Change main clock on CMC-PU2 board from 207 MHz to 179 MHz
+ because of a bug in the AT91RM9200 CPU PLL
+ Patch by Martin Krause, 22 Apr 2005
+
+* Add automatic HW detection for another CMC_PU2 variant
+ Patch by Martin Krause, 20 Apr 2005
+
+* Remove CONFIG_AT91RM9200DK in CMC-PU2 configuration
+ Patch by Martin Krause, 19 Apr 2005
+
+* Fix initialization problem on TQM5200 without SM501
+ Patch by Martin Krause, 08 Apr 2005
+
+* Add RTC support for STK52XX.200
+ Patch by Martin Krause, 07 Apr 2005
+
+* Add support for IFM o2dnt board
+
* Enable PCI on hmi1001 board
* Fix return values of the jffs2 commands ls/fsload/fsinfo,
applications that use U-Boot services by means of the jump table
provided by U-Boot exactly for this purpose - this is merely
considered normal use of U-Boot, and does *not* fall under the
-heading of "derived work". Also note that the GPL below is
-copyrighted by the Free Software Foundation, but the instance of code
-that it refers to (the U-Boot source code) is copyrighted by me and
-others who actually wrote it. -- Wolfgang Denk
+heading of "derived work".
+
+ The header files "include/image.h" and "include/asm-*/u-boot.h"
+define interfaces to U-Boot. Including these (unmodified) header
+files in another file is considered normal use of U-Boot, and does
+*not* fall under the heading of "derived work".
+
+ Also note that the GPL below is copyrighted by the Free Software
+Foundation, but the instance of code that it refers to (the U-Boot
+source code) is copyrighted by me and others who actually wrote it.
+-- Wolfgang Denk
=======================================================================
E: raphael.bossek@solutions4linux.de
D: 8xxrom-0.3.0
+N: Cliff Brake
+E: cliff.brake@gmail.com
+D: Port to Vibren PXA255 IDP platform
+W: http://www.vibren.com
+W: http://bec-systems.com
+
N: Rick Bronson
E: rick@efn.org
D: Atmel AT91RM9200DK and NAND support
E: thomas@corelatus.se
D: Support for GTH and dbau1x00 boards; lots of PCMCIA fixes
+N: Marc Leeman
+E: marc.leeman@barco.com
+D: Support for Barco Streaming Video Card (SVC) and Sample Compress Network (SCN)
+W: www.barco.com
+
N: The LEOX team
E: team@leox.org
D: Support for LEOX boards, DS164x RTC
D: Initial support for SSV-DNP1110, SMC91111 driver
W: www.elinos.com
+N: John Otken
+E: jotken@softadvances.com
+D: Support for AMCC Luan 440SP board
+
N: Tolunay Orkun
E: torkun@nextio.com
D: Support for Cogent CSB272 & CSB472 boards
N: Stefan Roese
E: stefan.roese@esd-electronics.com
-D: IBM PPC401/403/405GP Support; Windows environment support
+D: AMCC PPC401/403/405GP Support; Windows environment support
N: Erwin Rol
E: erwin@muffin.org
N: Travis B. Sawyer
E: travis.sawyer@sandburst.com
-D: Support for IBM PPC440GX, XES XPedite1000 440GX PrPMC board. IBM 440gx Ref Platform (Ocotea)
+D: Support for AMCC PPC440GX, XES XPedite1000 440GX PrPMC board. AMCC 440gx Ref Platform (Ocotea)
N: Paolo Scaffardi
E: arsenio@tin.it
E: r.schwebel@pengutronix.de
D: Support for csb226, logodl and innokom boards (PXA2xx)
+N: Art Shipkowski
+E: art@videon-central.com
+D: Support for NetSilicon NS7520
+
N: Yasushi Shoji
E: yashi@atmark-techno.com
D: Support for Xilinx MicroBlaze, for Atmark Techno SUZAKU FPGA board
E: azu@sysgo.de
D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
W: www.elinos.com
+
+N: James MacAulay
+E: james.macaulay@amirix.com
+D: Suppport for Amirix AP1000
+W: www.amirix.com
Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ cpci5200 MPC5200
+ pf5200 MPC5200
+
CPCI750 PPC750FX/GX
Yuli Barcohen <yuli@arabellasw.com>
AR405 PPC405GP
ASH405 PPC405EP
CANBT PPC405CR
+ CPCI2DP PPC405GP
CPCI405 PPC405GP
CPCI4052 PPC405GP
CPCI405AB PPC405GP
VOH405 PPC405EP
VOM405 PPC405EP
WUH405 PPC405EP
+ CMS700 PPC405EP
Frank Gottschling <fgottschling@eltec.de>
csb272 PPC405GP
csb472 PPC405GP
+John Otken <jotken@softadvances.com>
+
+ luan PPC440SP
+
Keith Outwater <Keith_Outwater@mvis.com>
GEN860T MPC860T
ep8260 MPC8260
Peter Pearse <peter.pearse@arm.com>
-
- Integrator/AP CM 926EJ-S, CM7x0T, CM9x0T
- Integrator/CP CM 926EJ-S CM920T, CM940T, CM922T-XA10
- Versatile/AB ARM926EJ-S
- Versatile/PB ARM926EJ-S
+ integratorcp All current ARM supplied &
+ supported core modules
+ - see http://www.arm.com
+ /products/DevTools
+ /Hardware_Platforms.html
+ versatile ARM926EJ-S
+ versatile ARM926EJ-S
Denis Peter <d.peter@mpl.ch>
Stefan Roese <sr@denx.de>
+ uc100 MPC857
+
+ TQM85xx MPC8540/8541/8555/8560
+
bamboo PPC440EP
bunbinga PPC405EP
ebony PPC440GP
ocotea PPC440GX
+ p3p440 PPC440GP
sycamore PPC405GPr
walnut PPC405GP
yellowstone PPC440GR
# Board CPU #
#########################################################################
+Rowel Atienza <rowel@diwalabs.com>
+
+ armadillo ARM720T
+
Rishi Bhattacharya <rishi@ti.com>
omap5912osk ARM926EJS
+Cliff Brake <cliff.brake@gmail.com>
+
+ pxa255_idp xscale
+
Rick Bronson <rick@efn.org>
AT91RM9200DK at91rm9200
#########################################################################
LIST_5xxx=" \
- icecube_5100 icecube_5200 EVAL5200 PM520 \
- Total5100 Total5200 Total5200_Rev2 TQM5200_auto \
+ cpci5200 icecube_5100 icecube_5200 EVAL5200 \
+ pf5200 PM520 Total5100 Total5200 \
+ Total5200_Rev2 TQM5200_auto o2dnt \
"
#########################################################################
#########################################################################
LIST_4xx=" \
- ADCIOP AR405 ASH405 bubinga \
- CANBT CPCI405 CPCI4052 CPCI405AB \
+ ADCIOP AP1000 AR405 ASH405 \
+ bubinga CANBT CMS700 CPCI2DP \
+ CPCI405 CPCI4052 CPCI405AB CPCI405DT \
CPCI440 CPCIISER4 CRAYL1 csb272 \
csb472 DASA_SIM DP405 DU405 \
- ebony ERIC EXBITGEN HUB405 \
- JSE KAREF METROBOX MIP405 \
- MIP405T ML2 ml300 ocotea \
- OCRTC ORSG PCI405 PIP405 \
- PLU405 PMC405 PPChameleonEVB VOH405 \
- W7OLMC W7OLMG walnut WUH405 \
- XPEDITE1K yellowstone yosemite \
+ ebony ERIC EXBITGEN G2000 \
+ HH405 HUB405 JSE KAREF \
+ luan METROBOX MIP405 MIP405T \
+ ML2 ml300 ocotea OCRTC \
+ ORSG p3p440 PCI405 PIP405 \
+ PLU405 PMC405 PPChameleonEVB sbc405 \
+ VOH405 VOM405 W7OLMC W7OLMG \
+ walnut WUH405 XPEDITE1K yellowstone \
+ yosemite \
"
#########################################################################
#########################################################################
LIST_824x=" \
- A3000 BMW CPC45 CU824 \
- debris eXalion HIDDEN_DRAGON MOUSSE \
- MUSENKI MVBLUE OXC PN62 \
- Sandpoint8240 Sandpoint8245 SL8245 utx8245 \
- sbc8240 \
+ A3000 barco BMW CPC45 \
+ CU824 debris eXalion HIDDEN_DRAGON \
+ MOUSSE MUSENKI MVBLUE OXC \
+ PN62 Sandpoint8240 Sandpoint8245 sbc8240 \
+ SL8245 utx8245 \
"
#########################################################################
#########################################################################
LIST_83xx=" \
- MPC8349ADS \
+ MPC8349ADS TQM834x\
"
MPC8540ADS MPC8540EVAL MPC8541CDS MPC8548CDS \
MPC8555CDS MPC8560ADS PM854 PM856 \
sbc8540 sbc8560 stxgp3 TQM8540 \
+ TQM8541 TQM8555 TQM8560 \
"
#########################################################################
## ARM7 Systems
#########################################################################
-LIST_ARM7="B2 ep7312 evb4510 impa7 modnet50"
+LIST_ARM7=" \
+ armadillo B2 ep7312 evb4510 \
+ impa7 integratorap ap7 ap720t \
+ modnet50 \
+"
#########################################################################
## ARM9 Systems
#########################################################################
LIST_ARM9=" \
- at91rm9200dk cmc_pu2 integratorcp integratorap \
- lpd7a400 mx1ads mx1fs2 omap1510inn \
- omap1610h2 omap1610inn omap730p2 scb9328 \
- smdk2400 smdk2410 trab VCMA9 \
- versatile voiceblue \
+ at91rm9200dk cmc_pu2 \
+ ap920t ap922_XA10 ap926ejs ap946es \
+ ap966 cp920t cp922_XA10 cp926ejs \
+ cp946es cp966 lpd7a400 mp2usb \
+ mx1ads mx1fs2 omap1510inn omap1610h2 \
+ omap1610inn omap730p2 scb9328 smdk2400 \
+ smdk2410 trab VCMA9 versatile \
+ versatileab versatilepb voiceblue
+"
+
+#########################################################################
+## ARM10 Systems
+#########################################################################
+LIST_ARM10=" \
+ integratorcp cp1026 \
"
#########################################################################
## ARM11 Systems
#########################################################################
-LIST_ARM11="omap2420h4"
+LIST_ARM11=" \
+ cp1136 omap2420h4 \
+"
#########################################################################
## Xscale Systems
LIST_pxa=" \
adsvix cerf250 cradle csb226 \
- innokom lubbock wepep250 xaeniax \
- xm250 xsengine \
+ innokom lubbock pxa255_idp wepep250 \
+ xaeniax xm250 xsengine \
"
LIST_ixp="ixdp425"
LIST_arm=" \
${LIST_SA} \
- ${LIST_ARM7} ${LIST_ARM9} ${LIST_ARM11} \
+ ${LIST_ARM7} ${LIST_ARM9} ${LIST_ARM10} ${LIST_ARM11} \
${LIST_pxa} ${LIST_ixp} \
"
do
case "$arg" in
ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|4xx|7xx|74xx| \
- arm|SA|ARM7|ARM9|ARM11|pxa|ixp| \
+ arm|SA|ARM7|ARM9|ARM10|ARM11|pxa|ixp| \
microblaze| \
mips|mips_el| \
nios|nios2| \
LIBS += rtc/librtc.a
LIBS += dtt/libdtt.a
LIBS += drivers/libdrivers.a
-LIBS += drivers/nand/libnand.a
LIBS += drivers/sk98lin/libsk98lin.a
LIBS += post/libpost.a post/cpu/libcpu.a
LIBS += common/libcommon.a
+LIBS += $(BOARDLIBS)
.PHONY : $(LIBS)
# Add GCC lib
aev_config: unconfig
@./mkconfig -a aev ppc mpc5xxx tqm5200
+cpci5200_config: unconfig
+ @./mkconfig -a cpci5200 ppc mpc5xxx cpci5200 esd
+
hmi1001_config: unconfig
@./mkconfig hmi1001 ppc mpc5xxx hmi1001
inka4x0_config: unconfig
@./mkconfig inka4x0 ppc mpc5xxx inka4x0
+o2dnt_config:
+ @./mkconfig -a o2dnt ppc mpc5xxx o2dnt
+
+pf5200_config: unconfig
+ @./mkconfig -a pf5200 ppc mpc5xxx pf5200 esd
+
PM520_config \
PM520_DDR_config \
PM520_ROMBOOT_config \
}
@./mkconfig -a Total5200 ppc mpc5xxx total5200
-TQM5200_auto_config \
+TQM5200_auto_config \
TQM5200_AA_config \
TQM5200_AB_config \
TQM5200_AC_config \
ADCIOP_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx adciop esd
+AP1000_config:unconfig
+ @./mkconfig $(@:_config=) ppc ppc4xx ap1000 amirix
+
APC405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx apc405 esd
}
@./mkconfig -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave
+CPCI2DP_config: unconfig
+ @./mkconfig $(@:_config=) ppc ppc4xx cpci2dp esd
+
CPCI405_config \
CPCI4052_config \
CPCI405DT_config \
KAREF_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx karef sandburst
+luan_config: unconfig
+ @./mkconfig $(@:_config=) ppc ppc4xx luan amcc
+
METROBOX_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx metrobox sandburst
ORSG_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx ocrtc esd
+p3p440_config: unconfig
+ @./mkconfig $(@:_config=) ppc ppc4xx p3p440 prodrive
+
PCI405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx pci405 esd
VOM405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx vom405 esd
+CMS700_config: unconfig
+ @./mkconfig $(@:_config=) ppc ppc4xx cms700 esd
+
W7OLMC_config \
W7OLMG_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx w7o
A3000_config: unconfig
@./mkconfig $(@:_config=) ppc mpc824x a3000
+barco_config: unconfig
+ @./mkconfig $(@:_config=) ppc mpc824x barco
+
BMW_config: unconfig
@./mkconfig $(@:_config=) ppc mpc824x bmw
utx8245_config: unconfig
@./mkconfig $(@:_config=) ppc mpc824x utx8245
-cobra5272_config : unconfig
- @./mkconfig $(@:_config=) m68k mcf52x2 cobra5272
-
#########################################################################
## MPC8260 Systems
#########################################################################
## Coldfire
#########################################################################
+cobra5272_config : unconfig
+ @./mkconfig $(@:_config=) m68k mcf52x2 cobra5272
+
M5272C3_config : unconfig
@./mkconfig $(@:_config=) m68k mcf52x2 m5272c3
MPC8349ADS_config: unconfig
@./mkconfig $(@:_config=) ppc mpc83xx mpc8349ads
+TQM834x_config: unconfig
+ @./mkconfig $(@:_config=) ppc mpc83xx tqm834x
+
#########################################################################
## MPC85xx Systems
#########################################################################
stxgp3_config: unconfig
@./mkconfig $(@:_config=) ppc mpc85xx stxgp3
-TQM8540_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc85xx tqm8540
-
-TQM8560_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc85xx tqm8560
+TQM8540_config \
+TQM8541_config \
+TQM8555_config \
+TQM8560_config: unconfig
+ @CTYPE=$(subst TQM,,$(@:_config=)); \
+ >include/config.h ; \
+ echo "... TQM"$${CTYPE}; \
+ echo "#define CONFIG_MPC$${CTYPE}">>include/config.h; \
+ echo "#define CONFIG_TQM$${CTYPE}">>include/config.h; \
+ echo "#define CONFIG_HOSTNAME tqm$${CTYPE}">>include/config.h; \
+ echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>include/config.h; \
+ echo "#define CFG_BOOTFILE \"bootfile=/tftpboot/tqm$${CTYPE}/uImage\0\"">>include/config.h
+ @./mkconfig -a TQM85xx ppc mpc85xx tqm85xx
#########################################################################
## 74xx/7xx Systems
cmc_pu2_config : unconfig
@./mkconfig $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
-integratorap_config : unconfig
- @./mkconfig $(@:_config=) arm arm926ejs integratorap
-
-integratorcp_config : unconfig
- @./mkconfig $(@:_config=) arm arm926ejs integratorcp
+csb637_config : unconfig
+ @./mkconfig $(@:_config=) arm arm920t csb637 NULL at91rm9200
+
+mp2usb_config : unconfig
+ @./mkconfig $(@:_config=) arm arm920t mp2usb NULL at91rm9200
+
+
+########################################################################
+## ARM Integrator boards - see doc/README-integrator for more info.
+integratorap_config \
+ap_config \
+ap966_config \
+ap922_config \
+ap922_XA10_config \
+ap7_config \
+ap720t_config \
+ap920t_config \
+ap926ejs_config \
+ap946es_config: unconfig
+ @board/integratorap/split_by_variant.sh $@
+
+integratorcp_config \
+cp_config \
+cp920t_config \
+cp926ejs_config \
+cp946es_config \
+cp1136_config \
+cp966_config \
+cp922_config \
+cp922_XA10_config \
+cp1026_config: unconfig
+ @board/integratorcp/split_by_variant.sh $@
+
+kb9202_config : unconfig
+ @./mkconfig $(@:_config=) arm arm920t kb9202 NULL at91rm9200
lpd7a400_config \
lpd7a404_config: unconfig
VCMA9_config : unconfig
@./mkconfig $(@:_config=) arm arm920t vcma9 mpl s3c24x0
-versatile_config : unconfig
- @./mkconfig $(@:_config=) arm arm926ejs versatile
+#========================================================================
+# ARM supplied Versatile development boards
+#========================================================================
+versatile_config \
+versatileab_config \
+versatilepb_config : unconfig
+ @board/versatile/split_by_variant.sh $@
voiceblue_smallflash_config \
voiceblue_config: unconfig
## ARM720T Systems
#########################################################################
+armadillo_config: unconfig
+ @./mkconfig $(@:_config=) arm arm720t armadillo
+
ep7312_config : unconfig
@./mkconfig $(@:_config=) arm arm720t ep7312
logodl_config : unconfig
@./mkconfig $(@:_config=) arm pxa logodl
+pxa255_idp_config: unconfig
+ @./mkconfig $(@:_config=) arm pxa pxa255_idp
+
wepep250_config : unconfig
@./mkconfig $(@:_config=) arm pxa wepep250
@echo "#define CONFIG_DBAU1550 1" >>include/config.h
@./mkconfig -a dbau1x00 mips mips dbau1x00
+pb1000_config : unconfig
+ @ >include/config.h
+ @echo "#define CONFIG_PB1000 1" >>include/config.h
+ @./mkconfig -a pb1x00 mips mips pb1x00
+
#########################################################################
## MIPS64 5Kc
#########################################################################
rm -f tools/env/fw_printenv tools/env/fw_setenv
rm -f board/cray/L1/bootscript.c board/cray/L1/bootscript.image
rm -f board/trab/trab_fkt board/voiceblue/eeprom
+ rm -f board/integratorap/u-boot.lds board/integratorcp/u-boot.lds
clobber: clean
find . -type f \( -name .depend \
- mpc85xx Files specific to Freescale MPC85xx CPUs
- nios Files specific to Altera NIOS CPUs
- nios2 Files specific to Altera Nios-II CPUs
- - ppc4xx Files specific to IBM PowerPC 4xx CPUs
+ - ppc4xx Files specific to AMCC PowerPC 4xx CPUs
- pxa Files specific to Intel XScale PXA CPUs
- s3c44b0 Files specific to Samsung S3C44B0 CPUs
- sa1100 Files specific to Intel StrongARM SA1100 CPUs
PowerPC based boards:
---------------------
- CONFIG_ADCIOP CONFIG_GEN860T CONFIG_PCI405
- CONFIG_ADS860 CONFIG_GENIETV CONFIG_PCIPPC2
- CONFIG_AMX860 CONFIG_GTH CONFIG_PCIPPC6
- CONFIG_AR405 CONFIG_gw8260 CONFIG_pcu_e
- CONFIG_BAB7xx CONFIG_hermes CONFIG_PIP405
- CONFIG_c2mon CONFIG_hymod CONFIG_PM826
- CONFIG_CANBT CONFIG_IAD210 CONFIG_ppmc8260
- CONFIG_CCM CONFIG_ICU862 CONFIG_QS823
- CONFIG_CMI CONFIG_IP860 CONFIG_QS850
- CONFIG_cogent_mpc8260 CONFIG_IPHASE4539 CONFIG_QS860T
- CONFIG_cogent_mpc8xx CONFIG_IVML24 CONFIG_RBC823
- CONFIG_CPCI405 CONFIG_IVML24_128 CONFIG_RPXClassic
- CONFIG_CPCI4052 CONFIG_IVML24_256 CONFIG_RPXlite
- CONFIG_CPCIISER4 CONFIG_IVMS8 CONFIG_RPXsuper
- CONFIG_CPU86 CONFIG_IVMS8_128 CONFIG_rsdproto
- CONFIG_CRAYL1 CONFIG_IVMS8_256 CONFIG_sacsng
- CONFIG_CSB272 CONFIG_JSE CONFIG_Sandpoint8240
- CONFIG_CU824 CONFIG_LANTEC CONFIG_Sandpoint8245
- CONFIG_DASA_SIM CONFIG_lwmon CONFIG_sbc8260
- CONFIG_DB64360 CONFIG_MBX CONFIG_sbc8560
- CONFIG_DB64460 CONFIG_MBX860T CONFIG_SM850
- CONFIG_DU405 CONFIG_MHPC CONFIG_SPD823TS
- CONFIG_DUET_ADS CONFIG_MIP405 CONFIG_STXGP3
- CONFIG_EBONY CONFIG_MOUSSE CONFIG_SXNI855T
- CONFIG_ELPPC CONFIG_MPC8260ADS CONFIG_TQM823L
- CONFIG_ELPT860 CONFIG_MPC8540ADS CONFIG_TQM8260
- CONFIG_ep8260 CONFIG_MPC8540EVAL CONFIG_TQM850L
- CONFIG_ERIC CONFIG_MPC8560ADS CONFIG_TQM855L
- CONFIG_ESTEEM192E CONFIG_MUSENKI CONFIG_TQM860L
- CONFIG_ETX094 CONFIG_MVS1 CONFIG_TTTech
- CONFIG_EVB64260 CONFIG_NETPHONE CONFIG_UTX8245
- CONFIG_FADS823 CONFIG_NETTA CONFIG_V37
- CONFIG_FADS850SAR CONFIG_NETVIA CONFIG_W7OLMC
- CONFIG_FADS860T CONFIG_NX823 CONFIG_W7OLMG
- CONFIG_FLAGADM CONFIG_OCRTC CONFIG_WALNUT
- CONFIG_FPS850L CONFIG_ORSG CONFIG_ZPC1900
- CONFIG_FPS860L CONFIG_OXC CONFIG_ZUMA
+ CONFIG_ADCIOP CONFIG_GEN860T CONFIG_PCIPPC2
+ CONFIG_ADS860 CONFIG_GENIETV CONFIG_PCIPPC6
+ CONFIG_AMX860 CONFIG_GTH CONFIG_pcu_e
+ CONFIG_AP1000 CONFIG_gw8260 CONFIG_PIP405
+ CONFIG_AR405 CONFIG_hermes CONFIG_PM826
+ CONFIG_BAB7xx CONFIG_hymod CONFIG_ppmc8260
+ CONFIG_c2mon CONFIG_IAD210 CONFIG_QS823
+ CONFIG_CANBT CONFIG_ICU862 CONFIG_QS850
+ CONFIG_CCM CONFIG_IP860 CONFIG_QS860T
+ CONFIG_CMI CONFIG_IPHASE4539 CONFIG_RBC823
+ CONFIG_cogent_mpc8260 CONFIG_IVML24 CONFIG_RPXClassic
+ CONFIG_cogent_mpc8xx CONFIG_IVML24_128 CONFIG_RPXlite
+ CONFIG_CPCI405 CONFIG_IVML24_256 CONFIG_RPXsuper
+ CONFIG_CPCI4052 CONFIG_IVMS8 CONFIG_rsdproto
+ CONFIG_CPCIISER4 CONFIG_IVMS8_128 CONFIG_sacsng
+ CONFIG_CPU86 CONFIG_IVMS8_256 CONFIG_Sandpoint8240
+ CONFIG_CRAYL1 CONFIG_JSE CONFIG_Sandpoint8245
+ CONFIG_CSB272 CONFIG_LANTEC CONFIG_sbc8260
+ CONFIG_CU824 CONFIG_lwmon CONFIG_sbc8560
+ CONFIG_DASA_SIM CONFIG_MBX CONFIG_SM850
+ CONFIG_DB64360 CONFIG_MBX860T CONFIG_SPD823TS
+ CONFIG_DB64460 CONFIG_MHPC CONFIG_STXGP3
+ CONFIG_DU405 CONFIG_MIP405 CONFIG_SXNI855T
+ CONFIG_DUET_ADS CONFIG_MOUSSE CONFIG_TQM823L
+ CONFIG_EBONY CONFIG_MPC8260ADS CONFIG_TQM8260
+ CONFIG_ELPPC CONFIG_MPC8540ADS CONFIG_TQM850L
+ CONFIG_ELPT860 CONFIG_MPC8540EVAL CONFIG_TQM855L
+ CONFIG_ep8260 CONFIG_MPC8560ADS CONFIG_TQM860L
+ CONFIG_ERIC CONFIG_MUSENKI CONFIG_TTTech
+ CONFIG_ESTEEM192E CONFIG_MVS1 CONFIG_UTX8245
+ CONFIG_ETX094 CONFIG_NETPHONE CONFIG_V37
+ CONFIG_EVB64260 CONFIG_NETTA CONFIG_W7OLMC
+ CONFIG_FADS823 CONFIG_NETVIA CONFIG_W7OLMG
+ CONFIG_FADS850SAR CONFIG_NX823 CONFIG_WALNUT
+ CONFIG_FADS860T CONFIG_OCRTC CONFIG_ZPC1900
+ CONFIG_FLAGADM CONFIG_ORSG CONFIG_ZUMA
+ CONFIG_FPS850L CONFIG_OXC
+ CONFIG_FPS860L CONFIG_PCI405
ARM based boards:
-----------------
- CONFIG_AT91RM9200DK, CONFIG_CERF250, CONFIG_DNP1110,
- CONFIG_EP7312, CONFIG_H2_OMAP1610, CONFIG_HHP_CRADLE,
- CONFIG_IMPA7, CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610,
- CONFIG_LART, CONFIG_LPD7A400 CONFIG_LUBBOCK,
+ CONFIG_ARMADILLO, CONFIG_AT91RM9200DK, CONFIG_CERF250,
+ CONFIG_CSB637, CONFIG_DNP1110, CONFIG_EP7312,
+ CONFIG_H2_OMAP1610, CONFIG_HHP_CRADLE, CONFIG_IMPA7,
+ CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610, CONFIG_KB9202,
+ CONFIG_LART, CONFIG_LPD7A400, CONFIG_LUBBOCK,
CONFIG_OSK_OMAP5912, CONFIG_OMAP2420H4, CONFIG_SHANNON,
CONFIG_P2_OMAP730, CONFIG_SMDK2400, CONFIG_SMDK2410,
CONFIG_TRAB, CONFIG_VCMA9
expect it to be in bytes, others in MB.
Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes.
+ CONFIG_OF_FLAT_TREE
+
+ New kernel versions are expecting firmware settings to be
+ passed using flat open firmware trees.
+ The environment variable "disable_of", when set, disables this
+ functionality.
+
+ CONFIG_OF_FLAT_TREE_MAX_SIZE
+
+ The maximum size of the constructed OF tree.
+
+ OF_CPU - The proper name of the cpus node.
+ OF_TBCLK - The timebase frequency.
+
- Serial Ports:
CFG_PL010_SERIAL
- Console UART Number:
CONFIG_UART1_CONSOLE
- IBM PPC4xx only.
+ AMCC PPC4xx only.
If defined internal UART1 (and not UART0) is used
as default U-Boot console.
allows for a "silent" boot where a splash screen is
loaded very quickly after power-on.
+- Gzip compressed BMP image support: CONFIG_VIDEO_BMP_GZIP
+
+ If this option is set, additionally to standard BMP
+ images, gzipped BMP images can be displayed via the
+ splashscreen support or the bmp command.
+
- Compression support:
CONFIG_BZIP2
remaining RAM in a form that can be passed as boot
argument to Linux, for instance like that:
- setenv bootargs ... mem=\$(mem)
+ setenv bootargs ... mem=\${mem}
saveenv
This way you can tell Linux not to use this memory,
When SystemACE support is added, the "ace" device type
becomes available to the fat commands, i.e. fatls.
+- TFTP Fixed UDP Port:
+ CONFIG_TFTP_PORT
+
+ If this is defined, the environment variable tftpsrcp
+ is used to supply the TFTP UDP source port value.
+ If tftpsrcp isn't defined, the normal pseudo-random port
+ number generator is used.
+
+ Also, the environment variable tftpdstp is used to supply
+ the TFTP UDP destination port value. If tftpdstp isn't
+ defined, the normal port 69 is used.
+
+ The purpose for tftpsrcp is to allow a TFTP server to
+ blindly start the TFTP transfer using the pre-configured
+ target IP address and UDP port. This has the effect of
+ "punching through" the (Windows XP) firewall, allowing
+ the remainder of the TFTP transfer to proceed normally.
+ A better solution is to properly configure the firewall,
+ but sometimes that is not allowed.
+
- Show boot progress:
CONFIG_SHOW_BOOT_PROGRESS
This option also enables the building of the cfi_flash driver
in the drivers directory
+- CFG_FLASH_QUIET_TEST
+ If this option is defined, the common CFI flash doesn't
+ print it's warning upon not recognized FLASH banks. This
+ is useful, if some of the configured banks are only
+ optionally available.
+
- CFG_RX_ETH_BUFFER:
Defines the number of ethernet receive buffers. On some
ethernet controllers it is recommended to set this value
Useful on scripts which control the retry operation
themselves.
+ tftpsrcport - If this is set, the value is used for TFTP's
+ UDP source port.
+
+ tftpdstport - If this is set, the value is used for TFTP's UDP
+ destination port instead of the Well Know Port 69.
+
vlan - When set to a value < 4095 the traffic over
ethernet is encapsulated/received over 802.1q
VLAN tagged frames.
- supports environment variables (through setenv / saveenv commands)
- several commands on one line, separated by ';'
-- variable substitution using "... $(name) ..." syntax
+- variable substitution using "... ${name} ..." syntax
- special characters ('$', ';') can be escaped by prefixing with '\',
for example:
- setenv bootcmd bootm \$(address)
+ setenv bootcmd bootm \${address}
- You can also escape text by enclosing in single apostrophes, for example:
setenv addip 'setenv bootargs $bootargs ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off'
.u_boot_cmd ALIGN(0x4):
{
+ . = .;
__u_boot_cmd_start = .;
*(.u_boot_cmd)
__u_boot_cmd_end = .;
preboot=echo;echo Type "run nfsboot" to mount root filesystem over NFS;echo
gatewayip=192.168.0.1
ramargs=setenv bootargs root=/dev/ram rw
-rootargs=setenv rootpath /tftp/$(ipaddr)
-nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(nfsserverip):$(rootpath)
-addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(nfsserverip):$(gatewayip):$(netmask):$(hostname):eth0:
+rootargs=setenv rootpath /tftp/${ipaddr}
+nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${nfsserverip}:${rootpath}
+addip=setenv bootargs ${bootargs} ip=${ipaddr}:${nfsserverip}:${gatewayip}:${netmask}:${hostname}:eth0:
ramboot=tftp 400000 /home/leox/pMulti;run ramargs;bootm
nfsboot=tftp 400000 /home/leox/uImage;run rootargs;run nfsargs;run addip;bootm
bootcmd=run ramboot
int checkboard (void)
{
- unsigned char *s = getenv ("serial#");
+ char *s = getenv ("serial#");
if (!s || strncmp (s, "ELPT860", 7))
printf ("### No HW ID - assuming ELPT860\n");
* try 8 column mode
*/
size8 = dram_size (CFG_MAMR_8COL,
- (ulong *) SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
+ SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
udelay (1000);
* try 9 column mode
*/
size9 = dram_size (CFG_MAMR_9COL,
- (ulong *) SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
+ SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
size_b0 = size9;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
| KBD_MODE_DISABLE_MOUSE
| KBD_MODE_KCC);
- /* ibm powerpc portables need this to use scan-code set 1 -- Cort */
+ /* AMCC powerpc portables need this to use scan-code set 1 -- Cort */
kbd_write_command_w(KBD_CCMD_READ_MODE);
if (!(kbd_wait_for_input() & KBD_MODE_KCC)) {
/*
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
- volatile unsigned char *addr = (char *) (info->start[0]);
+ volatile unsigned char *addr = (uchar *) (info->start[0]);
int flag, prot, sect, l_sect;
ulong start, now, last;
for (sect = s_first; sect <= s_last; sect++) {
int sector_size = info->size / info->sector_count;
- addr = (char *) (info->start[sect]);
+ addr = (uchar *) (info->start[sect]);
memset ((void *) addr, 0, sector_size);
}
return 0;
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
- addr = (char *) (info->start[sect]);
+ addr = (uchar *) (info->start[sect]);
flash_cmd (info->portwidth, addr, 0, 0x30);
l_sect = sect;
}
/* broken for 2x16: TODO */
static int write_word (flash_info_t * info, ulong dest, ulong data)
{
- volatile unsigned char *addr = (char *) (info->start[0]);
+ volatile unsigned char *addr = (uchar *) (info->start[0]);
ulong start;
int flag, i;
ulong mask;
CHIP_CMD_RST);
/* 1st cycle of word/byte program */
/* write 0x40 to the location to program */
- flash_cmd (info->portwidth, (char *) dest, 0,
+ flash_cmd (info->portwidth, (uchar *) dest, 0,
CHIP_CMD_PROG);
/* 2nd cycle of word/byte program */
/* write the data to the destination address */
static uchar i2c_get_data (uchar * return_data, int len)
{
- unsigned int data, status;
+ unsigned int data, status = 0;
int count = 0;
DP (puts ("i2c_get_data\n"));
int mem_test_data (void)
{
unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
- unsigned long long temp64;
+ unsigned long long temp64 = 0;
int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
int i;
unsigned int hi, lo;
unsigned long long wmask, short read, short write)
{
unsigned int i;
- unsigned long long temp;
+ unsigned long long temp = 0;
unsigned int hitemp, lotemp, himask, lomask;
for (i = 0; i < size; i++) {
dev->send = (void *) db64360_eth_transmit;
dev->recv = (void *) db64360_eth_poll;
- dev->priv = (void *) ethernet_private =
- calloc (sizeof (*ethernet_private), 1);
+ ethernet_private = calloc (sizeof (*ethernet_private), 1);
+ dev->priv = (void *) ethernet_private;
+
if (!ethernet_private) {
printf ("%s: %s allocation failure, %s\n",
__FUNCTION__, dev->name,
memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
/* set pointer to memory for stats data structure etc... */
- ethernet_private->port_private = (void *) port_private =
- calloc (sizeof (*ethernet_private), 1);
+ port_private = calloc (sizeof (*ethernet_private), 1);
+ ethernet_private->port_private = (void *)port_private;
if (!port_private) {
printf ("%s: %s allocation failure, %s\n",
__FUNCTION__, dev->name,
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
int mem_test_data (void)
{
unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
- unsigned long long temp64;
+ unsigned long long temp64 = 0;
int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
int i;
unsigned int hi, lo;
unsigned long long wmask, short read, short write)
{
unsigned int i;
- unsigned long long temp;
+ unsigned long long temp = 0;
unsigned int hitemp, lotemp, himask, lomask;
for (i = 0; i < size; i++) {
dev->send = (void *) db64460_eth_transmit;
dev->recv = (void *) db64460_eth_poll;
- dev->priv = (void *) ethernet_private =
- calloc (sizeof (*ethernet_private), 1);
+ ethernet_private = calloc (sizeof (*ethernet_private), 1);
+ dev->priv = (void *)ethernet_private;
if (!ethernet_private) {
printf ("%s: %s allocation failure, %s\n",
__FUNCTION__, dev->name,
memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
/* set pointer to memory for stats data structure etc... */
- ethernet_private->port_private = (void *) port_private =
- calloc (sizeof (*ethernet_private), 1);
+ port_private = calloc (sizeof (*ethernet_private), 1);
+ ethernet_private->port_private = (void *)port_private;
if (!port_private) {
printf ("%s: %s allocation failure, %s\n",
__FUNCTION__, dev->name,
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
/* Read 256 bytes in EEPROM */
- i2c_read (0x54, 0, 1, buff, 128);
- i2c_read (0x54, 128, 1, buff + 128, 128);
+ i2c_read (0x54, 0, 1, (uchar *)buff, 128);
+ i2c_read (0x54, 128, 1, (uchar *)buff + 128, 128);
/* Retrieve MAC address in buffer (key EA) */
for (cp = buff;;) {
cp += 3;
/* Read MAC address */
for (i = 0; i < 6; i++, cp += 2) {
- enet[i] = aschex_to_byte (cp);
+ enet[i] = aschex_to_byte ((unsigned char *)cp);
}
}
/* Scan to the end of the record */
* try 10 column mode
*/
- size10 = dram_size (CFG_MAMR_10COL, (ulong *) SDRAM_BASE_PRELIM,
+ size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE_PRELIM,
SDRAM_MAX_SIZE);
return (size10);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
* try 10 column mode
*/
- size10 = dram_size (CFG_MAMR_10COL, (ulong *) SDRAM_BASE_PRELIM,
+ size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE_PRELIM,
SDRAM_MAX_SIZE);
return (size10);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
#define CONFIG_BOOTCOMMAND \
"bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
This is enough for kernel NFS test. But as debug process goes on, you would expect
* try 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
+ size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
/*
* Final mapping:
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
int checkboard (void)
{
- unsigned char *s = getenv ("serial#");
+ char *s = getenv ("serial#");
puts ("Board: RRvision ");
* try 8 column mode
*/
size8 = dram_size (CFG_MAMR_8COL,
- (ulong *)SDRAM_BASE2_PRELIM,
+ SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
udelay (1000);
* try 9 column mode
*/
size9 = dram_size (CFG_MAMR_9COL,
- (ulong *) SDRAM_BASE2_PRELIM,
+ SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(16);
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4);
__data_end = .;
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd :
{
. = ALIGN(4);
__data_end = .;
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd :
{
void configure_ppc440ep_pins(void);
int is_nand_selected(void);
+unsigned char cfg_simulate_spd_eeprom[128];
+
gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
#if 0
{ /* GPIO Alternate1 Alternate2 Alternate3 */
int checkboard(void)
{
- sys_info_t sysinfo;
- unsigned char *s = getenv("serial#");
-
- get_sys_info(&sysinfo);
+ char *s = getenv("serial#");
printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
if (s != NULL) {
}
putc('\n');
- printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
- printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
- printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
- printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
- printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
-
return (0);
}
/*************************************************************************
*
- * fixed_sdram_init -- Bamboo has one bank onboard sdram (plus DIMM)
+ * init_spd_array -- Bamboo has one bank onboard sdram (plus DIMM)
*
* Fixed memory is composed of :
* MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
* PLB @ 133 MHz
*
************************************************************************/
-void fixed_sdram_init(void)
+static void init_spd_array(void)
{
- /*
- * clear this first, if the DDR is enabled by a debugger
- * then you can not make changes.
- */
- mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
+ cfg_simulate_spd_eeprom[8] = 0x04; /* 2.5 Volt */
+ cfg_simulate_spd_eeprom[2] = 0x07; /* DDR ram */
- /*--------------------------------------------------------------------
- * Setup for board-specific specific mem
- *------------------------------------------------------------------*/
- /*
- * Following for CAS Latency = 2.5 @ 133 MHz PLB
- */
- mtsdram(mem_b0cr, 0x00082001);
- mtsdram(mem_b1cr, 0x00000000);
- mtsdram(mem_b2cr, 0x00000000);
- mtsdram(mem_b3cr, 0x00000000);
+#ifdef CONFIG_DDR_ECC
+ cfg_simulate_spd_eeprom[11] = 0x02; /* ECC ON : 02 OFF : 00 */
+ cfg_simulate_spd_eeprom[31] = 0x08; /* bankSizeID: 32MB */
+ cfg_simulate_spd_eeprom[3] = 0x0C; /* num Row Addr: 12 */
+#else
+ cfg_simulate_spd_eeprom[11] = 0x00; /* ECC ON : 02 OFF : 00 */
+ cfg_simulate_spd_eeprom[31] = 0x10; /* bankSizeID: 64MB */
+ cfg_simulate_spd_eeprom[3] = 0x0D; /* num Row Addr: 13 */
+#endif
+
+ cfg_simulate_spd_eeprom[4] = 0x09; /* numColAddr: 9 */
+ cfg_simulate_spd_eeprom[5] = 0x01; /* numBanks: 1 */
+ cfg_simulate_spd_eeprom[0] = 0x80; /* number of SPD bytes used: 128 */
+ cfg_simulate_spd_eeprom[1] = 0x08; /* total number bytes in SPD device = 256 */
+ cfg_simulate_spd_eeprom[21] = 0x00; /* not registered: 0 registered : 0x02*/
+ cfg_simulate_spd_eeprom[6] = 0x20; /* Module data width: 32 bits */
+ cfg_simulate_spd_eeprom[7] = 0x00; /* Module data width continued: +0 */
+ cfg_simulate_spd_eeprom[15] = 0x01; /* wcsbc = 1 */
+ cfg_simulate_spd_eeprom[27] = 0x50; /* tRpNs = 20 ns */
+ cfg_simulate_spd_eeprom[29] = 0x50; /* tRcdNs = 20 ns */
+
+ cfg_simulate_spd_eeprom[30] = 45; /* tRasNs */
+
+ cfg_simulate_spd_eeprom[18] = 0x0C; /* casBit (2,2.5) */
+
+ cfg_simulate_spd_eeprom[9] = 0x75; /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
+ cfg_simulate_spd_eeprom[23] = 0xA0; /* SDRAM Cycle Time (cas latency 2) = 10 ns */
+ cfg_simulate_spd_eeprom[25] = 0x00; /* SDRAM Cycle Time (cas latency 1.5) = N.A */
+ cfg_simulate_spd_eeprom[12] = 0x82; /* refresh Rate Type: Normal (15.625us) + Self refresh */
}
long int initdram (int board_type)
long dram_size = 0;
/*
- * First init bank0 (onboard sdram) and then configure the DIMM-slots
+ * First write simulated values in eeprom array for onboard bank 0
*/
- fixed_sdram_init();
+ init_spd_array();
+
dram_size = spd_sdram (0);
return dram_size;
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
int pci_pre_init(struct pci_controller *hose)
{
- unsigned long strap;
unsigned long addr;
- /*--------------------------------------------------------------------------+
- * Bamboo is always configured as the host & requires the
- * PCI arbiter to be enabled.
- *--------------------------------------------------------------------------*/
- mfsdr(sdr_sdstp1, strap);
- if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
- printf("PCI: SDR0_STRP1[PAE] not set.\n");
- printf("PCI: Configuration aborted.\n");
- return 0;
- }
-
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/440gx_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*/
int checkboard(void)
{
- unsigned char *s = getenv("serial#");
+ char *s = getenv("serial#");
puts("Board: Bubinga - AMCC PPC405EP Evaluation Board");
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
int checkboard(void)
{
- sys_info_t sysinfo;
- unsigned char *s = getenv("serial#");
-
- get_sys_info(&sysinfo);
+ char *s = getenv("serial#");
printf("Board: Ebony - AMCC PPC440GP Evaluation Board");
if (s != NULL) {
}
putc('\n');
- printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
- printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
- printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
- printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
- printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
return (0);
}
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
--- /dev/null
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o
+OBJS += flash.o
+SOBJS = init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ADCIOP boards
+#
+
+#TEXT_BASE = 0x00001000
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0xFBD00000
+else
+TEXT_BASE = 0xFFFC0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
--- /dev/null
+#define EPLD0_FSEL_FB2 0x80
+#define EPLD0_BOOT_SMALL_FLASH 0x40 /* 0 boot from large flash, 1 from small flash */
+#define EPLD0_RAW_CARD_BIT0 0x20 /* raw card EC level */
+#define EPLD0_RAW_CARD_BIT1 0x10
+#define EPLD0_RAW_CARD_BIT2 0x08
+#define EPLD0_EXT_ARB_SEL_N 0x04 /* 0 select on-board ext PCI-X, 1 internal arbiter */
+#define EPLD0_FLASH_ONBRD_N 0x02 /* 0 small flash/SRAM active, 1 block access */
+#define EPLD0_FLASH_SRAM_SEL_N 0x01 /* 0 SRAM at mem top, 1 small flash at mem top */
+
+#define EPLD1_CLK_CNTL0 0x80 /* FSEL-FB1 of MPC9772 */
+#define EPLD1_PCIX0_CNTL1 0x40 /* S*0 of 9531 */
+#define EPLD1_PCIX0_CNTL2 0x20 /* S*1 of 9531 */
+#define EPLD1_CLK_CNTL3 0x10 /* FSEL-B1 of MPC9772 */
+#define EPLD1_CLK_CNTL4 0x08 /* FSEL-B0 of MPC9772 */
+#define EPLD1_MASTER_CLOCK6 0x04 /* clock source select 6 */
+#define EPLD1_MASTER_CLOCK7 0x02 /* clock source select 7 */
+#define EPLD1_MASTER_CLOCK8 0x01 /* clock source select 8 */
+
+#define EPLD2_ETH_MODE_10 0x80 /* Ethernet mode 10 (default = 1) */
+#define EPLD2_ETH_MODE_100 0x40 /* Ethernet mode 100 (default = 1) */
+#define EPLD2_ETH_MODE_1000 0x20 /* Ethernet mode 1000 (default = 1) */
+#define EPLD2_ETH_DUPLEX_MODE 0x10 /* Ethernet force full duplex mode */
+#define EPLD2_RESET_ETH_N 0x08 /* Ethernet reset (default = 1) */
+#define EPLD2_ETH_AUTO_NEGO 0x04 /* Ethernet auto negotiation */
+#define EPLD2_DEFAULT_UART_N 0x01 /* 0 select DSR DTR for UART1 */
+
+#define EPLD3_STATUS_LED4 0x08 /* status LED 8 (1 = LED on) */
+#define EPLD3_STATUS_LED3 0x04 /* status LED 4 (1 = LED on) */
+#define EPLD3_STATUS_LED2 0x02 /* status LED 2 (1 = LED on) */
+#define EPLD3_STATUS_LED1 0x01 /* status LED 1 (1 = LED on) */
+
+#define EPLD4_PCIX0_VTH1 0x80 /* PCI-X 0 VTH1 status */
+#define EPLD4_PCIX0_VTH2 0x40 /* PCI-X 0 VTH2 status */
+#define EPLD4_PCIX0_VTH3 0x20 /* PCI-X 0 VTH3 status */
+#define EPLD4_PCIX0_VTH4 0x10 /* PCI-X 0 VTH4 status */
+#define EPLD4_PCIX1_VTH1 0x08 /* PCI-X 1 VTH1 status */
+#define EPLD4_PCIX1_VTH2 0x04 /* PCI-X 1 VTH2 status */
+#define EPLD4_PCIX1_VTH3 0x02 /* PCI-X 1 VTH3 status */
+#define EPLD4_PCIX1_VTH4 0x01 /* PCI-X 1 VTH4 status */
+
+#define EPLD5_PCIX0_INT0 0x80 /* PCIX0 INT0 status, write 0 to reset */
+#define EPLD5_PCIX0_INT1 0x40 /* PCIX0 INT1 status, write 0 to reset */
+#define EPLD5_PCIX0_INT2 0x20 /* PCIX0 INT2 status, write 0 to reset */
+#define EPLD5_PCIX0_INT3 0x10 /* PCIX0 INT3 status, write 0 to reset */
+#define EPLD5_PCIX1_INT0 0x08 /* PCIX1 INT0 status, write 0 to reset */
+#define EPLD5_PCIX1_INT1 0x04 /* PCIX1 INT1 status, write 0 to reset */
+#define EPLD5_PCIX1_INT2 0x02 /* PCIX1 INT2 status, write 0 to reset */
+#define EPLD5_PCIX1_INT3 0x01 /* PCIX1 INT3 status, write 0 to reset */
+
+#define EPLD6_PCIX0_RESET_CTL 0x80 /* 0=enable slot reset, 1=disable slot reset */
+#define EPLD6_PCIX1_RESET_CTL 0x40 /* 0=enable slot reset, 1=disable slot reset */
+#define EPLD6_ETH_INT_MODE 0x20 /* 0=IRQ5 recv's external eth int */
+#define EPLD6_PCIX2_RESET_CTL 0x10 /* 0=enable slot reset, 1=disable slot reset */
+#define EPLD6_PCI1_CLKCNTL1 0x80 /* PCI1 clock control S*0 of 9531 */
+#define EPLD6_PCI1_CLKCNTL2 0x40 /* PCI1 clock control S*1 of 9531 */
+#define EPLD6_PCI2_CLKCNTL1 0x20 /* PCI2 clock control S*0 of 9531 */
+#define EPLD6_PCI2_CLKCNTL2 0x10 /* PCI2 clock control S*1 of 9531 */
+
+#define EPLD7_VTH1 0x80 /* PCI2 VTH1 status */
+#define EPLD7_VTH2 0x40 /* PCI2 VTH2 status */
+#define EPLD7_VTH3 0x20 /* PCI2 VTH3 status */
+#define EPLD7_VTH4 0x10 /* PCI2 VTH4 status */
+#define EPLD7_INTA_MODE 0x80 /* see S5 on SW2 for details */
+#define EPLD7_PCI_INT_MODE_N 0x40 /* see S1 on SW2 for details */
+#define EPLD7_WRITE_ENABLE_GPIO 0x20 /* see S2 on SW2 for details */
+#define EPLD7_WRITE_ENABLE_INT 0x10 /* see S3 on SW2 for details */
+
+
+typedef struct {
+ unsigned char status; /* misc status */
+ unsigned char clock; /* clock status, PCI-X clock control */
+ unsigned char ethuart; /* Ethernet, UART status */
+ unsigned char leds; /* LED register */
+ unsigned char vth01; /* PCI0, PCI1 VTH register */
+ unsigned char pciints; /* PCI0, PCI1 interrupts */
+ unsigned char pci2; /* PCI2 interrupts, clock control */
+ unsigned char vth2; /* PCI2 VTH register */
+ unsigned char filler1[4096-8];
+ unsigned char gpio00; /* GPIO bits 0-7 */
+ unsigned char gpio08; /* GPIO bits 8-15 */
+ unsigned char gpio16; /* GPIO bits 16-23 */
+ unsigned char gpio24; /* GPIO bits 24-31 */
+ unsigned char filler2[4096-4];
+ unsigned char version; /* EPLD version */
+} epld_t;
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+static unsigned long flash_addr_table[1][CFG_MAX_FLASH_BANKS] = {
+ {0xff900000, 0xff980000, 0xffc00000}, /* 0:000: configuraton 3 */
+};
+
+/*
+ * include common flash code (for amcc boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+
+unsigned long flash_init(void)
+{
+ unsigned long total_b = 0;
+ unsigned long size_b[CFG_MAX_FLASH_BANKS];
+ unsigned short index = 0;
+ int i;
+
+ /* read FPGA base register FPGA_REG0 */
+
+ DEBUGF("\n");
+ DEBUGF("FLASH: Index: %d\n", index);
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+
+ /* check whether the address is 0 */
+ if (flash_addr_table[index][i] == 0) {
+ continue;
+ }
+
+ /* call flash_get_size() to initialize sector address */
+ size_b[i] = flash_get_size((vu_long *)
+ flash_addr_table[index][i],
+ &flash_info[i]);
+ flash_info[i].size = size_b[i];
+ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+ printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+ i, size_b[i], size_b[i] << 20);
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+ }
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+ &flash_info[2]);
+#ifdef CFG_ENV_IS_IN_FLASH
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[2]);
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[2]);
+#endif
+
+ total_b += flash_info[i].size;
+ }
+
+ return total_b;
+}
--- /dev/null
+/*
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID 0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K 0x00000000
+#define SZ_4K 0x00000010
+#define SZ_16K 0x00000020
+#define SZ_64K 0x00000030
+#define SZ_256K 0x00000040
+#define SZ_1M 0x00000050
+#define SZ_16M 0x00000070
+#define SZ_256M 0x00000090
+
+/* Storage attributes */
+#define SA_W 0x00000800 /* Write-through */
+#define SA_I 0x00000400 /* Caching inhibited */
+#define SA_M 0x00000200 /* Memory coherence */
+#define SA_G 0x00000100 /* Guarded */
+#define SA_E 0x00000080 /* Endian */
+
+/* Access control */
+#define AC_X 0x00000024 /* Execute */
+#define AC_W 0x00000012 /* Write */
+#define AC_R 0x00000009 /* Read */
+
+/* Some handy macros */
+
+#define EPN(e) ((e) & 0xfffffc00)
+#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a) ( (a)&0x00000fbf )
+
+#define tlbtab_start\
+ mflr r1 ;\
+ bl 0f ;
+
+#define tlbtab_end\
+ .long 0, 0, 0 ; \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+ .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+#if (CFG_LARGE_FLASH == 0xffc00000) /* if booting from large flash */
+ /* large flash */
+ tlbentry( 0xffc00000, SZ_1M, 0xffc00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
+ tlbentry( 0xffd00000, SZ_1M, 0xffd00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
+ tlbentry( 0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
+ tlbentry( 0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
+
+ tlbentry( 0xff800000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
+ tlbentry( 0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
+#else /* else booting from small flash */
+ tlbentry( 0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
+ tlbentry( 0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
+
+ tlbentry( 0xff800000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
+ tlbentry( 0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
+ tlbentry( 0xffa00000, SZ_1M, 0xffa00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
+ tlbentry( 0xffb00000, SZ_1M, 0xffb00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
+#endif
+
+ tlbentry( CFG_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I )
+
+#if (CFG_SRAM_BASE != 0) /* if SRAM up high and SDRAM at zero */
+ tlbentry( 0x00000000, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+#elif (CFG_SMALL_FLASH == 0xff900000) /* else SRAM at 0 */
+ tlbentry( 0x00000000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
+#elif (CFG_SMALL_FLASH == 0xfff00000)
+ tlbentry( 0x00000000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
+#else
+ #error DONT KNOW SRAM LOCATION
+#endif
+
+ /* internal ram (l2 cache) */
+ tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I )
+
+ /* peripherals at f0000000 */
+ tlbentry( CFG_PERIPHERAL_BASE, SZ_4K, CFG_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I )
+
+ /* PCI */
+#if (CONFIG_COMMANDS & CFG_CMD_PCI)
+ tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I )
+#endif
+ tlbtab_end
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * John Otken, jotken@softadvances.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+#include "epld.h"
+
+
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+
+/*************************************************************************
+ * int board_early_init_f()
+ *
+ ************************************************************************/
+int board_early_init_f(void)
+{
+ volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
+
+ mtebc( pb0ap, 0x03800000 ); /* set chip selects */
+ mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
+ mtebc( pb1ap, 0x03800000 );
+ mtebc( pb1cr, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */
+ mtebc( pb2ap, 0x03800000 );
+ mtebc( pb2cr, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */
+
+ mtdcr( uic1sr, 0xffffffff ); /* Clear all interrupts */
+ mtdcr( uic1er, 0x00000000 ); /* disable all interrupts */
+ mtdcr( uic1cr, 0x00000000 ); /* Set Critical / Non Critical interrupts */
+ mtdcr( uic1pr, 0x7fff83ff ); /* Set Interrupt Polarities */
+ mtdcr( uic1tr, 0x001f8000 ); /* Set Interrupt Trigger Levels */
+ mtdcr( uic1vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr( uic1sr, 0x00000000 ); /* clear all interrupts */
+ mtdcr( uic1sr, 0xffffffff );
+
+ mtdcr( uic0sr, 0xffffffff ); /* Clear all interrupts */
+ mtdcr( uic0er, 0x00000000 ); /* disable all interrupts excepted cascade */
+ mtdcr( uic0cr, 0x00000001 ); /* Set Critical / Non Critical interrupts */
+ mtdcr( uic0pr, 0xffffffff ); /* Set Interrupt Polarities */
+ mtdcr( uic0tr, 0x01000004 ); /* Set Interrupt Trigger Levels */
+ mtdcr( uic0vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */
+ mtdcr( uic0sr, 0xffffffff );
+
+ x->ethuart &= ~EPLD2_RESET_ETH_N; /* put Ethernet+PHY in reset */
+
+ return 0;
+}
+
+
+/*************************************************************************
+ * int misc_init_r()
+ *
+ ************************************************************************/
+int misc_init_r(void)
+{
+ volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
+ x->ethuart |= EPLD2_RESET_ETH_N; /* take Ethernet+PHY out of reset */
+
+ return 0;
+}
+
+
+/*************************************************************************
+ * int checkboard()
+ *
+ ************************************************************************/
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+
+ printf("Board: Luan - AMCC PPC440SP Evaluation Board");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ putc('\n');
+
+ return 0;
+}
+
+
+/*************************************************************************
+ * long int fixed_sdram()
+ *
+ ************************************************************************/
+static long int fixed_sdram(void)
+{ /* DDR2 init from BDI2000 script */
+ mtdcr( 0x10, 0x00000021 ); /* MCIF0_MCOPT2 - zero DCEN bit */
+ mtdcr( 0x11, 0x84000000 );
+ mtdcr( 0x10, 0x00000020 ); /* MCIF0_MCOPT1 - no ECC, 64 bits, 4 banks, DDR2 */
+ mtdcr( 0x11, 0x2D122000 );
+ mtdcr( 0x10, 0x00000026 ); /* MCIF0_CODT - die termination on */
+ mtdcr( 0x11, 0x00800026 );
+ mtdcr( 0x10, 0x00000081 ); /* MCIF0_WRDTR - Write DQS Adv 90 + Fractional DQS Delay */
+ mtdcr( 0x11, 0x82000800 );
+ mtdcr( 0x10, 0x00000080 ); /* MCIF0_CLKTR - advance addr clock by 180 deg */
+ mtdcr( 0x11, 0x80000000 );
+ mtdcr( 0x10, 0x00000040 ); /* MCIF0_MB0CF - turn on CS0, N x 10 coll */
+ mtdcr( 0x11, 0x00000201 );
+ mtdcr( 0x10, 0x00000044 ); /* MCIF0_MB1CF - turn on CS0, N x 10 coll */
+ mtdcr( 0x11, 0x00000201 );
+ mtdcr( 0x10, 0x00000030 ); /* MCIF0_RTR - refresh every 7.8125uS */
+ mtdcr( 0x11, 0x08200000 );
+ mtdcr( 0x10, 0x00000085 ); /* MCIF0_SDTR1 - timing register 1 */
+ mtdcr( 0x11, 0x80201000 );
+ mtdcr( 0x10, 0x00000086 ); /* MCIF0_SDTR2 - timing register 2 */
+ mtdcr( 0x11, 0x42103242 );
+ mtdcr( 0x10, 0x00000087 ); /* MCIF0_SDTR3 - timing register 3 */
+ mtdcr( 0x11, 0x0C100D14 );
+ mtdcr( 0x10, 0x00000088 ); /* MCIF0_MMODE - CAS is 4 cycles */
+ mtdcr( 0x11, 0x00000642 );
+ mtdcr( 0x10, 0x00000089 ); /* MCIF0_MEMODE - diff DQS disabled */
+ mtdcr( 0x11, 0x00000400 ); /* ODT term disabled */
+
+ mtdcr( 0x10, 0x00000050 ); /* MCIF0_INITPLR0 - NOP */
+ mtdcr( 0x11, 0x81b80000 );
+ mtdcr( 0x10, 0x00000051 ); /* MCIF0_INITPLR1 - PRE */
+ mtdcr( 0x11, 0x82100400 );
+ mtdcr( 0x10, 0x00000052 ); /* MCIF0_INITPLR2 - EMR2 */
+ mtdcr( 0x11, 0x80820000 );
+ mtdcr( 0x10, 0x00000053 ); /* MCIF0_INITPLR3 - EMR3 */
+ mtdcr( 0x11, 0x80830000 );
+ mtdcr( 0x10, 0x00000054 ); /* MCIF0_INITPLR4 - EMR DLL ENABLE */
+ mtdcr( 0x11, 0x80810000 );
+ mtdcr( 0x10, 0x00000055 ); /* MCIF0_INITPLR5 - MR DLL RESET */
+ mtdcr( 0x11, 0x80800542 );
+ mtdcr( 0x10, 0x00000056 ); /* MCIF0_INITPLR6 - PRE */
+ mtdcr( 0x11, 0x82100400 );
+ mtdcr( 0x10, 0x00000057 ); /* MCIF0_INITPLR7 - refresh */
+ mtdcr( 0x11, 0x99080000 );
+ mtdcr( 0x10, 0x00000058 ); /* MCIF0_INITPLR8 */
+ mtdcr( 0x11, 0x99080000 );
+ mtdcr( 0x10, 0x00000059 ); /* MCIF0_INITPLR9 */
+ mtdcr( 0x11, 0x99080000 );
+ mtdcr( 0x10, 0x0000005A ); /* MCIF0_INITPLR10 */
+ mtdcr( 0x11, 0x99080000 );
+ mtdcr( 0x10, 0x0000005B ); /* MCIF0_INITPLR11 - MR */
+ mtdcr( 0x11, 0x80800442 );
+ mtdcr( 0x10, 0x0000005C ); /* MCIF0_INITPLR12 - EMR OCD Default */
+ mtdcr( 0x11, 0x80810380 );
+ mtdcr( 0x10, 0x0000005D ); /* MCIF0_INITPLR13 - EMR OCD exit */
+ mtdcr( 0x11, 0x80810000 );
+ udelay( 10*1000 );
+
+ mtdcr( 0x10, 0x00000021 ); /* MCIF0_MCOPT2 - execute preloaded init */
+ mtdcr( 0x11, 0x28000000 ); /* set DC_EN */
+ udelay( 100*1000 );
+
+ mtdcr( 0x40, 0x0000F800 ); /* MQ0_B0BAS: base addr 00000000 / 256MB */
+ mtdcr( 0x41, 0x1000F800 ); /* MQ0_B1BAS: base addr 10000000 / 256MB */
+
+ mtdcr( 0x10, 0x00000078 ); /* MCIF0_RDCC - auto set read stage */
+ mtdcr( 0x11, 0x00000000 );
+ mtdcr( 0x10, 0x00000070 ); /* MCIF0_RQDC - read DQS delay control */
+ mtdcr( 0x11, 0x8000003A ); /* enabled, frac DQS delay */
+ mtdcr( 0x10, 0x00000074 ); /* MCIF0_RFDC - two clock feedback delay */
+ mtdcr( 0x11, 0x00000200 );
+
+ return 512 << 20;
+}
+
+
+/*************************************************************************
+ * long int initdram
+ *
+ ************************************************************************/
+long int initdram( int board_type )
+{
+ long dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+ dram_size = spd_sdram (0);
+#else
+ dram_size = fixed_sdram ();
+#endif
+
+ return dram_size;
+}
+
+
+/*************************************************************************
+ * int testdram()
+ *
+ ************************************************************************/
+#if defined(CFG_DRAM_TEST)
+int testdram(void)
+{
+ unsigned long *mem = (unsigned long *) 0;
+ const unsigned long kend = (1024 / sizeof(unsigned long));
+ unsigned long k, n;
+
+ mtmsr(0);
+
+ for (k = 0; k < CFG_KBYTES_SDRAM;
+ ++k, mem += (1024 / sizeof(unsigned long))) {
+ if ((k & 1023) == 0) {
+ printf("%3d MB\r", k / 1024);
+ }
+
+ memset(mem, 0xaaaaaaaa, 1024);
+ for (n = 0; n < kend; ++n) {
+ if (mem[n] != 0xaaaaaaaa) {
+ printf("SDRAM test fails at: %08x\n",
+ (uint) & mem[n]);
+ return 1;
+ }
+ }
+
+ memset(mem, 0x55555555, 1024);
+ for (n = 0; n < kend; ++n) {
+ if (mem[n] != 0x55555555) {
+ printf("SDRAM test fails at: %08x\n",
+ (uint) & mem[n]);
+ return 1;
+ }
+ }
+ }
+ printf("SDRAM test passes\n");
+
+ return 0;
+}
+#endif
+
+
+/*************************************************************************
+ * pci_pre_init
+ *
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
+ *
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init( struct pci_controller *hose )
+{
+ unsigned long strap;
+
+ /*--------------------------------------------------------------------------+
+ * The luan board is always configured as the host & requires the
+ * PCI arbiter to be enabled.
+ *--------------------------------------------------------------------------*/
+ mfsdr(sdr_sdstp1, strap);
+ if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
+ printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
+
+ return 0;
+ }
+
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+
+/*************************************************************************
+ * pci_target_init
+ *
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ /*--------------------------------------------------------------------------+
+ * Disable everything
+ *--------------------------------------------------------------------------*/
+ out32r( PCIX0_PIM0SA, 0 ); /* disable */
+ out32r( PCIX0_PIM1SA, 0 ); /* disable */
+ out32r( PCIX0_PIM2SA, 0 ); /* disable */
+ out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+
+ /*--------------------------------------------------------------------------+
+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
+ * options to not support sizes such as 128/256 MB.
+ *--------------------------------------------------------------------------*/
+ out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+ out32r( PCIX0_PIM0LAH, 0 );
+ out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+
+ out32r( PCIX0_BAR0, 0 );
+
+ /*--------------------------------------------------------------------------+
+ * Program the board's subsystem id/vendor id
+ *--------------------------------------------------------------------------*/
+ out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
+ out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+
+ out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+
+/*************************************************************************
+ * is_pci_host
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) */
+
+
+/*************************************************************************
+ * hw_watchdog_reset
+ *
+ * This routine is called to reset (keep alive) the watchdog timer
+ *
+ ************************************************************************/
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+}
+#endif
+
+
+/*************************************************************************
+ * int on_off()
+ *
+ ************************************************************************/
+static int on_off( const char *s )
+{
+ if (strcmp(s, "on") == 0) {
+ return 1;
+ } else if (strcmp(s, "off") == 0) {
+ return 0;
+ }
+ return -1;
+}
+
+
+/*************************************************************************
+ * void l2cache_disable()
+ *
+ ************************************************************************/
+static void l2cache_disable(void)
+{
+ mtdcr( l2_cache_cfg, 0 );
+}
+
+
+/*************************************************************************
+ * void l2cache_enable()
+ *
+ ************************************************************************/
+static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */
+{
+ mtdcr( l2_cache_cfg, 0x80000000 ); /* enable L2_MODE L2_CFG[L2M] */
+
+ mtdcr( l2_cache_addr, 0 ); /* set L2_ADDR with all zeros */
+
+ mtdcr( l2_cache_cmd, 0x80000000 ); /* issue HCLEAR command via L2_CMD */
+
+ while (!(mfdcr( l2_cache_stat ) & 0x80000000 )) ;; /* poll L2_SR for completion */
+
+ mtdcr( l2_cache_cmd, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */
+
+ mtdcr( l2_cache_cmd, 0x08000000 ); /* clear tag errors L2_CMD[CTE] */
+
+ mtdcr( l2_cache_snp0, 0 ); /* snoop registers */
+ mtdcr( l2_cache_snp1, 0 );
+
+ __asm__ volatile ("sync"); /* msync */
+
+ mtdcr( l2_cache_cfg, 0xe0000000 ); /* inst and data use L2 */
+
+ __asm__ volatile ("sync");
+}
+
+
+/*************************************************************************
+ * int l2cache_status()
+ *
+ ************************************************************************/
+static int l2cache_status(void)
+{
+ return (mfdcr( l2_cache_cfg ) & 0x60000000) != 0;
+}
+
+
+/*************************************************************************
+ * int do_l2cache()
+ *
+ ************************************************************************/
+int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
+{
+ switch (argc) {
+ case 2: /* on / off */
+ switch (on_off(argv[1])) {
+ case 0: l2cache_disable();
+ break;
+ case 1: l2cache_enable();
+ break;
+ }
+ /* FALL TROUGH */
+ case 1: /* get status */
+ printf ("L2 Cache is %s\n",
+ l2cache_status() ? "ON" : "OFF");
+ return 0;
+ default:
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
+ return 0;
+}
+
+
+U_BOOT_CMD(
+ l2cache, 2, 1, do_l2cache,
+ "l2cache - enable or disable L2 cache\n",
+ "[on, off]\n"
+ " - enable or disable L2 cache\n"
+ );
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ board/amcc/luan/init.o (.text)
+ cpu/ppc4xx/kgdb.o (.text)
+ cpu/ppc4xx/traps.o (.text)
+ cpu/ppc4xx/interrupts.o (.text)
+ cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/cpu_init.o (.text)
+ cpu/ppc4xx/speed.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+
+/* . = env_offset;*/
+/* common/environment.o(.text)*/
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
#
#
-# IBM 440GX Reference Platform (Ocotea) board
+# AMCC 440GX Reference Platform (Ocotea) board
#
#TEXT_BASE = 0xFFFE0000
#include "ocotea.h"
#include <asm/processor.h>
#include <spd_sdram.h>
-#include <440gx_enet.h>
+#include <ppc4xx_enet.h>
#define BOOT_SMALL_FLASH 32 /* 00100000 */
#define FLASH_ONBD_N 2 /* 00000010 */
int checkboard (void)
{
- sys_info_t sysinfo;
- unsigned char *s = getenv ("serial#");
-
- get_sys_info (&sysinfo);
+ char *s = getenv ("serial#");
printf ("Board: Ocotea - AMCC PPC440GX Evaluation Board");
if (s != NULL) {
}
putc ('\n');
- printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
- printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
- printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
- printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
- printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
return (0);
}
}
}
+ /*
+ * new Ocotea with Rev. F (pass 3) chips has SMII PHY reset
+ */
+ if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER2) {
+ out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_SMII_RESET_DISABLE);
+ udelay(10000);
+ out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_SMII_RESET_DISABLE);
+ }
+
/* Turn off the LED's */
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) |
FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB |
#define FPGA_REG2_EXT_INTFACE_MASK 0x04
#define FPGA_REG2_EXT_INTFACE_ENABLE 0x00
#define FPGA_REG2_EXT_INTFACE_DISABLE 0x04
+#define FPGA_REG2_SMII_RESET_DISABLE 0x02 /*Use on Ocotea pass 3 boards*/
#define FPGA_REG2_DEFAULT_UART1_N 0x01
#define FPGA_REG3 (CFG_FPGA_BASE + 0x03)
#define FPGA_REG3_GIGABIT_RESET_DISABLE 0x80 /*Use on Ocotea pass 1 boards*/
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/440gx_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*/
int checkboard(void)
{
- unsigned char *s = getenv("serial#");
+ char *s = getenv("serial#");
uint pvr = get_pvr();
if (pvr == PVR_405GPR_RB) {
LIB = lib$(BOARD).a
OBJS = $(BOARD).o
-OBJS += flash.o
SOBJS = init.o
$(LIB): $(OBJS) $(SOBJS)
+++ /dev/null
-/*
- * (C) Copyright 2002-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
- * Add support for Am29F016D and dynamic switch setting.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Modified 4/5/2001
- * Wait for completion of each sector erase command issued
- * 4/5/2001
- * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
- */
-
-/*
- * Ported to XPedite1000, 1/2 mb boot flash only
- * Travis B. Sawyer, <travis.sawyer@sandburst.com>
- */
-
-#include <common.h>
-#include <ppc4xx.h>
-#include <asm/processor.h>
-
-#undef DEBUG
-#ifdef DEBUG
-#define DEBUGF(x...) printf(x)
-#else
-#define DEBUGF(x...)
-#endif /* DEBUG */
-
-#define BOOT_SMALL_FLASH 32 /* 00100000 */
-#define FLASH_ONBD_N 2 /* 00000010 */
-#define FLASH_SRAM_SEL 1 /* 00000001 */
-
-#define BOOT_SMALL_FLASH_VAL 4
-#define FLASH_ONBD_N_VAL 2
-#define FLASH_SRAM_SEL_VAL 1
-
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-unsigned long flash_addr_table[512][CFG_MAX_FLASH_BANKS] = {
- {0xfe000000}
-
-};
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(vu_long * addr, flash_info_t * info);
-static int write_word(flash_info_t * info, ulong dest, ulong data);
-
-#define ADDR0 0xaaaa
-#define ADDR1 0x5554
-#define FLASH_WORD_SIZE unsigned short
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init(void)
-{
- unsigned long total_b = 0;
- unsigned long size_b[CFG_MAX_FLASH_BANKS];
- unsigned short index = 0;
- int i;
-
- DEBUGF("\n");
- DEBUGF("FLASH: Index: %d\n", index);
-
- /* Init: no FLASHes known */
- for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- flash_info[i].sector_count = -1;
- flash_info[i].size = 0;
-
- /* check whether the address is 0 */
- if (flash_addr_table[index][i] == 0) {
- continue;
- }
-
- /* call flash_get_size() to initialize sector address */
- size_b[i] = flash_get_size((vu_long *)
- flash_addr_table[index][i],
- &flash_info[i]);
- flash_info[i].size = size_b[i];
- if (flash_info[i].flash_id == FLASH_UNKNOWN) {
- printf
- ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
- i, size_b[i], size_b[i] << 20);
- flash_info[i].sector_count = -1;
- flash_info[i].size = 0;
- }
-
- total_b += flash_info[i].size;
- }
-
- /* FLASH protect Monitor */
- flash_protect(FLAG_PROTECT_SET,
- CFG_MONITOR_BASE, 0xFFFFFFFF, &flash_info[0]);
-
- return total_b;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info(flash_info_t * info)
-{
- int i;
- int k;
- int size;
- int erased;
- volatile unsigned long *flash;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- printf("AMD ");
- break;
- case FLASH_MAN_FUJ:
- printf("FUJITSU ");
- break;
- case FLASH_MAN_SST:
- printf("SST ");
- break;
- default:
- printf("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AMD016:
- printf("AM29F016D (16 Mbit, uniform sector size)\n");
- break;
- case FLASH_AM040:
- printf("AM29F040 (512 Kbit, uniform sector size)\n");
- break;
- case FLASH_AM400B:
- printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T:
- printf("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B:
- printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T:
- printf("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B:
- printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T:
- printf("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B:
- printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T:
- printf("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- case FLASH_SST800A:
- printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
- break;
- case FLASH_SST160A:
- printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
- break;
- default:
- printf("Unknown Chip Type\n");
- break;
- }
-
- printf(" Size: %ld KB in %d Sectors\n",
- info->size >> 10, info->sector_count);
-
- printf(" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- /*
- * Check if whole sector is erased
- */
- if (i != (info->sector_count - 1))
- size = info->start[i + 1] - info->start[i];
- else
- size = info->start[0] + info->size - info->start[i];
- erased = 1;
- flash = (volatile unsigned long *)info->start[i];
- size = size >> 2; /* divide by 4 for longword access */
- for (k = 0; k < size; k++) {
- if (*flash++ != 0xffffffff) {
- erased = 0;
- break;
- }
- }
-
- if ((i % 5) == 0)
- printf("\n ");
- printf(" %08lX%s%s",
- info->start[i],
- erased ? " E" : " ", info->protect[i] ? "RO " : " ");
- }
- printf("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size(vu_long * addr, flash_info_t * info)
-{
- short i;
- FLASH_WORD_SIZE value;
- ulong base = (ulong) addr;
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
-
- DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
-
- /* Write auto select command: read Manufacturer ID */
- udelay(10000);
- *(FLASH_WORD_SIZE *) ((int)addr + ADDR0) = (FLASH_WORD_SIZE) 0x00AA;
- udelay(1000);
- *(FLASH_WORD_SIZE *) ((int)addr + ADDR1) = (FLASH_WORD_SIZE) 0x0055;
- udelay(1000);
- *(FLASH_WORD_SIZE *) ((int)addr + ADDR0) = (FLASH_WORD_SIZE) 0x0090;
- udelay(1000);
-
- value = addr2[0];
-
- DEBUGF("FLASH MANUFACT: %x\n", value);
-
- switch (value) {
- case (FLASH_WORD_SIZE) AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FLASH_WORD_SIZE) FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (FLASH_WORD_SIZE) SST_MANUFACT:
- info->flash_id = FLASH_MAN_SST;
- break;
- case (FLASH_WORD_SIZE) STM_MANUFACT:
- info->flash_id = FLASH_MAN_STM;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
-#ifdef CONFIG_ADCIOP
- value = addr2[0]; /* device ID */
- debug("\ndev_code=%x\n", value);
-#else
- value = addr2[1]; /* device ID */
-#endif
-
- DEBUGF("\nFLASH DEVICEID: %x\n", value);
-
- info->flash_id = 0;
- info->sector_count = CFG_MAX_FLASH_SECT;
- info->size = 0x02000000;
-
- /* set up sector start address table */
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = (int)base + (i * 0x00020000);
- info->protect[i] = 0;
- }
-
- *(FLASH_WORD_SIZE *) ((int)addr) = (FLASH_WORD_SIZE) 0x00F0; /* reset bank */
-
- return (info->size);
-}
-
-int wait_for_DQ7(flash_info_t * info, int sect)
-{
- ulong start, now, last;
- volatile FLASH_WORD_SIZE *addr =
- (FLASH_WORD_SIZE *) (info->start[sect]);
-
- start = get_timer(0);
- last = start;
- while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
- (FLASH_WORD_SIZE) 0x00800080) {
- if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
- printf("Timeout\n");
- return -1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc('.');
- last = now;
- }
- }
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-{
- volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
- volatile FLASH_WORD_SIZE *addr2;
- int flag, prot, sect, l_sect;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("- missing\n");
- } else {
- printf("- no sectors to erase\n");
- }
- return 1;
- }
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
- printf("Erasing sector %p\n", addr2);
- *(FLASH_WORD_SIZE *) ((int)addr + ADDR0) =
- (FLASH_WORD_SIZE) 0x00AA;
- asm("sync");
- asm("isync");
- *(FLASH_WORD_SIZE *) ((int)addr + ADDR1) =
- (FLASH_WORD_SIZE) 0x0055;
- asm("sync");
- asm("isync");
- *(FLASH_WORD_SIZE *) ((int)addr + ADDR0) =
- (FLASH_WORD_SIZE) 0x0080;
- asm("sync");
- asm("isync");
- *(FLASH_WORD_SIZE *) ((int)addr + ADDR0) =
- (FLASH_WORD_SIZE) 0x00AA;
- asm("sync");
- asm("isync");
- *(FLASH_WORD_SIZE *) ((int)addr + ADDR1) =
- (FLASH_WORD_SIZE) 0x0055;
- asm("sync");
- asm("isync");
- addr2[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */
- asm("sync");
- asm("isync");
-
- l_sect = sect;
- /*
- * Wait for each sector to complete, it's more
- * reliable. According to AMD Spec, you must
- * issue all erase commands within a specified
- * timeout. This has been seen to fail, especially
- * if printf()s are included (for debug)!!
- */
- wait_for_DQ7(info, sect);
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay(1000);
-
-#if 0
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
- wait_for_DQ7(info, l_sect);
-
- DONE:
-#endif
- /* reset to read mode */
- addr = (FLASH_WORD_SIZE *) info->start[0];
- addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
-
- printf(" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
- ulong status_value = 0;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < 4 && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
-
- /*print status if needed */
- if ((wp >= (status_value + 0x20000))
- && (status_value < 0xFFFE0000)) {
- status_value = wp;
- printf("writing to sector 0x%X\n", status_value);
- }
-
- data = 0;
- for (i = 0; i < 4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word(flash_info_t * info, ulong dest, ulong data)
-{
- vu_long *addr2 = (vu_long *) (info->start[0]);
- volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
- volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
- ulong start;
- int i;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((volatile FLASH_WORD_SIZE *)dest) &
- (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
- return (2);
- }
-
- for (i = 0; i < 4 / sizeof(FLASH_WORD_SIZE); i++) {
- int flag;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- *(FLASH_WORD_SIZE *) ((int)addr2 + ADDR0) =
- (FLASH_WORD_SIZE) 0x00AA;
- asm("sync");
- asm("isync");
- *(FLASH_WORD_SIZE *) ((int)addr2 + ADDR1) =
- (FLASH_WORD_SIZE) 0x0055;
- asm("sync");
- asm("isync");
- *(FLASH_WORD_SIZE *) ((int)addr2 + ADDR0) =
- (FLASH_WORD_SIZE) 0x00A0;
- asm("sync");
- asm("isync");
-
- dest2[i] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer(0);
- while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
- (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
-
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- }
-
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
tlbtab:
tlbtab_start
- /*
- 0xf0000000 must be first, before relocation SA_I must be off to use the
- dcache as stack. It is patched after relocation to enable SA_I
- */
- tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
- tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CFG_PCI_BASE, SZ_256M, 0xE0000000, 0, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_NVRAM_BASE_ADDR, SZ_16K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
+
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+
+ tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
/* PCI */
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*/
#include <common.h>
+#include <ppc4xx.h>
#include <asm/processor.h>
#include <spd_sdram.h>
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
int board_early_init_f(void)
{
register uint reg;
mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
- mtebc(pb0cr, 0xfe0ba000); /* BAS=0xfe0 32MB r/w 16-bit */
+ mtebc(pb0cr, 0xfc0da000); /* BAS=0xfc0 64MB r/w 16-bit */
mtebc(pb1ap, 0x00000000);
mtebc(pb1cr, 0x00000000);
mtebc(pb5cr, 0x00000000);
/*--------------------------------------------------------------------
- * Setup the interrupt controller polarities, triggers, etc.
- *-------------------------------------------------------------------*/
- mtdcr(uic0sr, 0xffffffff); /* clear all */
- mtdcr(uic0er, 0x00000000); /* disable all */
- mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
- mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
- mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
- mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr(uic0sr, 0xffffffff); /* clear all */
-
- mtdcr(uic1sr, 0xffffffff); /* clear all */
- mtdcr(uic1er, 0x00000000); /* disable all */
- mtdcr(uic1cr, 0x00000000); /* all non-critical */
- mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
- mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
- mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr(uic1sr, 0xffffffff); /* clear all */
-
- /*--------------------------------------------------------------------
* Setup the GPIO pins
*-------------------------------------------------------------------*/
/*CPLD cs */
- /*setup Address lines for flash sizes larger than 16Meg. */
- out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000);
- out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000);
- out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000);
+ /*setup Address lines for flash size 64Meg. */
+ out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
+ out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
+ out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);
/*setup emac */
out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
+ /* external interrupts IRQ0...3 */
+ out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x0f000000);
+ out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500);
+ out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
+
+#if 0 /* test-only */
/*setup USB 2.0 */
out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
+#endif
+
+ /*--------------------------------------------------------------------
+ * Setup the interrupt controller polarities, triggers, etc.
+ *-------------------------------------------------------------------*/
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+ mtdcr(uic0er, 0x00000000); /* disable all */
+ mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
+ mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
+ mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
+ mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+ mtdcr(uic1er, 0x00000000); /* disable all */
+ mtdcr(uic1cr, 0x00000000); /* all non-critical */
+ mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
+ mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
+ mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
/*--------------------------------------------------------------------
* Setup other serial configuration
/*enable ethernet */
*(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
+#if 0 /* test-only */
/*enable usb 1.1 fs device and remove usb 2.0 reset */
*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
+#endif
/*get rid of flash write protect */
- *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;
+ *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
+
+ return 0;
+}
+
+int misc_init_r (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ uint pbcr;
+ int size_val = 0;
+
+ /* Re-do sizing to get full correct info */
+ mtdcr(ebccfga, pb0cr);
+ pbcr = mfdcr(ebccfgd);
+ switch (gd->bd->bi_flashsize) {
+ case 1 << 20:
+ size_val = 0;
+ break;
+ case 2 << 20:
+ size_val = 1;
+ break;
+ case 4 << 20:
+ size_val = 2;
+ break;
+ case 8 << 20:
+ size_val = 3;
+ break;
+ case 16 << 20:
+ size_val = 4;
+ break;
+ case 32 << 20:
+ size_val = 5;
+ break;
+ case 64 << 20:
+ size_val = 6;
+ break;
+ case 128 << 20:
+ size_val = 7;
+ break;
+ }
+ pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+ mtdcr(ebccfga, pb0cr);
+ mtdcr(ebccfgd, pbcr);
+
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -CFG_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
return 0;
}
int checkboard(void)
{
- sys_info_t sysinfo;
+ char *s = getenv("serial#");
- get_sys_info(&sysinfo);
+ printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ putc('\n');
- printf("Board: AMCC YELLOWSTONE\n");
- printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
- printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
- printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
- printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
- printf("\tPER: %lu MHz\n", sysinfo.freqEPB / 1000000);
- printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
return (0);
}
* PLB @ 133 MHz
*
************************************************************************/
+#define NUM_TRIES 64
+#define NUM_READS 10
+
+void sdram_tr1_set(int ram_address, int* tr1_value)
+{
+ int i;
+ int j, k;
+ volatile unsigned int* ram_pointer = (unsigned int*)ram_address;
+ int first_good = -1, last_bad = 0x1ff;
+
+ unsigned long test[NUM_TRIES] = {
+ 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+ 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+ 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+ 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+ 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+ 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+ 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+ 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+ 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+ 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+ 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+ 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
+ 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
+
+ /* go through all possible SDRAM0_TR1[RDCT] values */
+ for (i=0; i<=0x1ff; i++) {
+ /* set the current value for TR1 */
+ mtsdram(mem_tr1, (0x80800800 | i));
+
+ /* write values */
+ for (j=0; j<NUM_TRIES; j++) {
+ ram_pointer[j] = test[j];
+
+ /* clear any cache at ram location */
+ __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
+ }
+
+ /* read values back */
+ for (j=0; j<NUM_TRIES; j++) {
+ for (k=0; k<NUM_READS; k++) {
+ /* clear any cache at ram location */
+ __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
+
+ if (ram_pointer[j] != test[j])
+ break;
+ }
+
+ /* read error */
+ if (k != NUM_READS) {
+ break;
+ }
+ }
+
+ /* we have a SDRAM0_TR1[RDCT] that is part of the window */
+ if (j == NUM_TRIES) {
+ if (first_good == -1)
+ first_good = i; /* found beginning of window */
+ } else { /* bad read */
+ /* if we have not had a good read then don't care */
+ if(first_good != -1) {
+ /* first failure after a good read */
+ last_bad = i-1;
+ break;
+ }
+ }
+ }
+
+ /* return the current value for TR1 */
+ *tr1_value = (first_good + last_bad) / 2;
+}
+
void sdram_init(void)
{
register uint reg;
+ int tr1_bank1, tr1_bank2;
/*--------------------------------------------------------------------
* Setup some default
mtsdram(mem_wddctr, 0x40000000); /* ?? */
/*clear this first, if the DDR is enabled by a debugger
- then you can not make changes. */
+ then you can not make changes. */
mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
/*--------------------------------------------------------------------
*/
mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
+
mtsdram(mem_tr0, 0x410a4012); /* ?? */
- mtsdram(mem_tr1, 0x8080080b); /* ?? */
mtsdram(mem_rtr, 0x04080000); /* ?? */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
if (reg & 0x80000000)
break;
}
+
+ sdram_tr1_set(0x00000000, &tr1_bank1);
+ sdram_tr1_set(0x08000000, &tr1_bank2);
+ mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800) );
}
/*************************************************************************
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
int pci_pre_init(struct pci_controller *hose)
{
- unsigned long strap;
unsigned long addr;
- /*--------------------------------------------------------------------------+
- * Bamboo is always configured as the host & requires the
- * PCI arbiter to be enabled.
- *--------------------------------------------------------------------------*/
- mfsdr(sdr_sdstp1, strap);
- if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
- printf("PCI: SDR0_STRP1[PAE] not set.\n");
- printf("PCI: Configuration aborted.\n");
- return 0;
- }
-
- /*-------------------------------------------------------------------------+
- | Set priority for all PLB3 devices to 0.
- | Set PLB3 arbiter to fair mode.
- +-------------------------------------------------------------------------*/
+ /*-------------------------------------------------------------------------+
+ | Set priority for all PLB3 devices to 0.
+ | Set PLB3 arbiter to fair mode.
+ +-------------------------------------------------------------------------*/
mfsdr(sdr_amp1, addr);
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb3_acr);
mtdcr(plb3_acr, addr | 0x80000000);
- /*-------------------------------------------------------------------------+
- | Set priority for all PLB4 devices to 0.
- +-------------------------------------------------------------------------*/
+ /*-------------------------------------------------------------------------+
+ | Set priority for all PLB4 devices to 0.
+ +-------------------------------------------------------------------------*/
mfsdr(sdr_amp0, addr);
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
mtdcr(plb4_acr, addr);
- /*-------------------------------------------------------------------------+
- | Set Nebula PLB4 arbiter to fair mode.
- +-------------------------------------------------------------------------*/
- /* Segment0 */
+ /*-------------------------------------------------------------------------+
+ | Set Nebula PLB4 arbiter to fair mode.
+ +-------------------------------------------------------------------------*/
+ /* Segment0 */
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
/*--------------------------------------------------------------------------+
* Set up Direct MMIO registers
*--------------------------------------------------------------------------*/
- /*--------------------------------------------------------------------------+
- | PowerPC440 EP PCI Master configuration.
- | Map one 1Gig range of PLB/processor addresses to PCI memory space.
- | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
- | Use byte reversed out routines to handle endianess.
- | Make this region non-prefetchable.
- +--------------------------------------------------------------------------*/
+ /*--------------------------------------------------------------------------+
+ | PowerPC440 EP PCI Master configuration.
+ | Map one 1Gig range of PLB/processor addresses to PCI memory space.
+ | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
+ | Use byte reversed out routines to handle endianess.
+ | Make this region non-prefetchable.
+ +--------------------------------------------------------------------------*/
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
{
unsigned short temp_short;
- /*--------------------------------------------------------------------------+
- | Write the PowerPC440 EP PCI Configuration regs.
- | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
- | Enable PowerPC440 EP to act as a PCI memory target (PTM).
- +--------------------------------------------------------------------------*/
+ /*--------------------------------------------------------------------------+
+ | Write the PowerPC440 EP PCI Configuration regs.
+ | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
+ | Enable PowerPC440 EP to act as a PCI memory target (PTM).
+ +--------------------------------------------------------------------------*/
pci_read_config_word(0, PCI_COMMAND, &temp_short);
pci_write_config_word(0, PCI_COMMAND,
temp_short | PCI_COMMAND_MASTER |
#if defined(CONFIG_HW_WATCHDOG)
void hw_watchdog_reset(void)
{
+
}
#endif
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
mtebc(pb5cr, 0x00000000);
/*--------------------------------------------------------------------
- * Setup the interrupt controller polarities, triggers, etc.
- *-------------------------------------------------------------------*/
- mtdcr(uic0sr, 0xffffffff); /* clear all */
- mtdcr(uic0er, 0x00000000); /* disable all */
- mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
- mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
- mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
- mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr(uic0sr, 0xffffffff); /* clear all */
-
- mtdcr(uic1sr, 0xffffffff); /* clear all */
- mtdcr(uic1er, 0x00000000); /* disable all */
- mtdcr(uic1cr, 0x00000000); /* all non-critical */
- mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
- mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
- mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr(uic1sr, 0xffffffff); /* clear all */
-
- /*--------------------------------------------------------------------
* Setup the GPIO pins
*-------------------------------------------------------------------*/
/*CPLD cs */
- /*setup Address lines for flash sizes larger than 16Meg. */
- out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000);
- out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000);
- out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000);
+ /*setup Address lines for flash size 64Meg. */
+ out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
+ out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
+ out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);
/*setup emac */
out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
+ /* external interrupts IRQ0...3 */
+ out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x0f000000);
+ out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500);
+ out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
+
/*setup USB 2.0 */
out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
/*--------------------------------------------------------------------
+ * Setup the interrupt controller polarities, triggers, etc.
+ *-------------------------------------------------------------------*/
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+ mtdcr(uic0er, 0x00000000); /* disable all */
+ mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
+ mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
+ mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
+ mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+ mtdcr(uic1er, 0x00000000); /* disable all */
+ mtdcr(uic1cr, 0x00000000); /* all non-critical */
+ mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
+ mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
+ mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+
+ /*--------------------------------------------------------------------
* Setup other serial configuration
*-------------------------------------------------------------------*/
mfsdr(sdr_pci0, reg);
*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
/*get rid of flash write protect */
- *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;
+ *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
return 0;
}
mtdcr(ebccfga, pb0cr);
mtdcr(ebccfgd, pbcr);
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
-CFG_MONITOR_LEN,
int checkboard(void)
{
- sys_info_t sysinfo;
-
- get_sys_info(&sysinfo);
-
- printf("Board: AMCC YOSEMITE\n");
- printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
- printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
- printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
- printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
- printf("\tPER: %lu MHz\n", sysinfo.freqEPB / 1000000);
- printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
+ char *s = getenv("serial#");
+ printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ putc('\n');
return (0);
}
* PLB @ 133 MHz
*
************************************************************************/
+#define NUM_TRIES 64
+#define NUM_READS 10
+
+void sdram_tr1_set(int ram_address, int* tr1_value)
+{
+ int i;
+ int j, k;
+ volatile unsigned int* ram_pointer = (unsigned int*)ram_address;
+ int first_good = -1, last_bad = 0x1ff;
+
+ unsigned long test[NUM_TRIES] = {
+ 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+ 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+ 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+ 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+ 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+ 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+ 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+ 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+ 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+ 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+ 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+ 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
+ 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
+
+ /* go through all possible SDRAM0_TR1[RDCT] values */
+ for (i=0; i<=0x1ff; i++) {
+ /* set the current value for TR1 */
+ mtsdram(mem_tr1, (0x80800800 | i));
+
+ /* write values */
+ for (j=0; j<NUM_TRIES; j++) {
+ ram_pointer[j] = test[j];
+
+ /* clear any cache at ram location */
+ __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
+ }
+
+ /* read values back */
+ for (j=0; j<NUM_TRIES; j++) {
+ for (k=0; k<NUM_READS; k++) {
+ /* clear any cache at ram location */
+ __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
+
+ if (ram_pointer[j] != test[j])
+ break;
+ }
+
+ /* read error */
+ if (k != NUM_READS) {
+ break;
+ }
+ }
+
+ /* we have a SDRAM0_TR1[RDCT] that is part of the window */
+ if (j == NUM_TRIES) {
+ if (first_good == -1)
+ first_good = i; /* found beginning of window */
+ } else { /* bad read */
+ /* if we have not had a good read then don't care */
+ if(first_good != -1) {
+ /* first failure after a good read */
+ last_bad = i-1;
+ break;
+ }
+ }
+ }
+
+ /* return the current value for TR1 */
+ *tr1_value = (first_good + last_bad) / 2;
+}
+
void sdram_init(void)
{
register uint reg;
+ int tr1_bank1, tr1_bank2;
/*--------------------------------------------------------------------
* Setup some default
mtsdram(mem_wddctr, 0x40000000); /* ?? */
/*clear this first, if the DDR is enabled by a debugger
- then you can not make changes. */
+ then you can not make changes. */
mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
/*--------------------------------------------------------------------
mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
mtsdram(mem_tr0, 0x410a4012); /* ?? */
- mtsdram(mem_tr1, 0x8080080b); /* ?? */
mtsdram(mem_rtr, 0x04080000); /* ?? */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
if (reg & 0x80000000)
break;
}
+
+ sdram_tr1_set(0x00000000, &tr1_bank1);
+ sdram_tr1_set(0x08000000, &tr1_bank2);
+ mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800) );
}
/*************************************************************************
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
int pci_pre_init(struct pci_controller *hose)
{
- unsigned long strap;
unsigned long addr;
- /*--------------------------------------------------------------------------+
- * Bamboo is always configured as the host & requires the
- * PCI arbiter to be enabled.
- *--------------------------------------------------------------------------*/
- mfsdr(sdr_sdstp1, strap);
- if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
- printf("PCI: SDR0_STRP1[PAE] not set.\n");
- printf("PCI: Configuration aborted.\n");
- return 0;
- }
-
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o serial.o pci.o powerspan.o
+SOBJS = init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $^
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+/*
+ * amirix.c: ppcboot platform support for AMIRIX board
+ *
+ * Copyright 2002 Mind NV
+ * Copyright 2003 AMIRIX Systems Inc.
+ *
+ * http://www.mind.be/
+ * http://www.amirix.com/
+ *
+ * Author : Peter De Schrijver (p2@mind.be)
+ * Frank Smith (smith@amirix.com)
+ *
+ * Derived from : Other platform support files in this tree, ml2
+ *
+ * This software may be used and distributed according to the terms of
+ * the GNU General Public License (GPL) version 2, incorporated herein by
+ * reference. Drivers based on or derived from this code fall under the GPL
+ * and must retain the authorship, copyright and this license notice. This
+ * file is not a complete program and may only be used when the entire
+ * program is licensed under the GPL.
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+
+#include "powerspan.h"
+#include "ap1000.h"
+
+int board_pre_init (void)
+{
+ return 0;
+}
+
+/** serial number and platform display at startup */
+int checkboard (void)
+{
+ char *s = getenv ("serial#");
+ char *e;
+
+ /* After a loadace command, the SystemAce control register is left in a wonky state. */
+ /* this code did not work in board_pre_init */
+ unsigned char *p = (unsigned char *) AP1000_SYSACE_REGBASE;
+
+ p[SYSACE_CTRLREG0] = 0x0;
+
+ /* add platform and device to banner */
+ switch (get_device ()) {
+ case AP1xx_AP107_TARGET:
+ puts (AP1xx_AP107_TARGET_STR);
+ break;
+ case AP1xx_AP120_TARGET:
+ puts (AP1xx_AP120_TARGET_STR);
+ break;
+ case AP1xx_AP130_TARGET:
+ puts (AP1xx_AP130_TARGET_STR);
+ break;
+ case AP1xx_AP1070_TARGET:
+ puts (AP1xx_AP1070_TARGET_STR);
+ break;
+ case AP1xx_AP1100_TARGET:
+ puts (AP1xx_AP1100_TARGET_STR);
+ break;
+ default:
+ puts (AP1xx_UNKNOWN_STR);
+ break;
+ }
+ puts (AP1xx_TARGET_STR);
+ puts (" with ");
+
+ switch (get_platform ()) {
+ case AP100_BASELINE_PLATFORM:
+ case AP1000_BASELINE_PLATFORM:
+ puts (AP1xx_BASELINE_PLATFORM_STR);
+ break;
+ case AP1xx_QUADGE_PLATFORM:
+ puts (AP1xx_QUADGE_PLATFORM_STR);
+ break;
+ case AP1xx_MGT_REF_PLATFORM:
+ puts (AP1xx_MGT_REF_PLATFORM_STR);
+ break;
+ case AP1xx_STANDARD_PLATFORM:
+ puts (AP1xx_STANDARD_PLATFORM_STR);
+ break;
+ case AP1xx_DUAL_PLATFORM:
+ puts (AP1xx_DUAL_PLATFORM_STR);
+ break;
+ case AP1xx_BASE_SRAM_PLATFORM:
+ puts (AP1xx_BASE_SRAM_PLATFORM_STR);
+ break;
+ case AP1xx_PCI_PCB_TESTPLATFORM:
+ case AP1000_PCI_PCB_TESTPLATFORM:
+ puts (AP1xx_PCI_PCB_TESTPLATFORM_STR);
+ break;
+ case AP1xx_DUAL_GE_MEZZ_TESTPLATFORM:
+ puts (AP1xx_DUAL_GE_MEZZ_TESTPLATFORM_STR);
+ break;
+ case AP1xx_SFP_MEZZ_TESTPLATFORM:
+ puts (AP1xx_SFP_MEZZ_TESTPLATFORM_STR);
+ break;
+ default:
+ puts (AP1xx_UNKNOWN_STR);
+ break;
+ }
+
+ if ((get_platform () & AP1xx_TESTPLATFORM_MASK) != 0) {
+ puts (AP1xx_TESTPLATFORM_STR);
+ } else {
+ puts (AP1xx_PLATFORM_STR);
+ }
+
+ putc ('\n');
+
+ puts ("Serial#: ");
+
+ if (!s) {
+ printf ("### No HW ID - assuming AMIRIX");
+ } else {
+ for (e = s; *e; ++e) {
+ if (*e == ' ')
+ break;
+ }
+
+ for (; s < e; ++s) {
+ putc (*s);
+ }
+ }
+
+ putc ('\n');
+
+ return (0);
+}
+
+
+long int initdram (int board_type)
+{
+ char *s = getenv ("dramsize");
+
+ if (s != NULL) {
+ if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X'))) {
+ s += 2;
+ }
+ return (long int)simple_strtoul (s, NULL, 16);
+ } else {
+ /* give all 64 MB */
+ return 64 * 1024 * 1024;
+ }
+}
+
+unsigned int get_platform (void)
+{
+ unsigned int *revision_reg_ptr = (unsigned int *) AP1xx_FPGA_REV_ADDR;
+
+ return (*revision_reg_ptr & AP1xx_PLATFORM_MASK);
+}
+
+unsigned int get_device (void)
+{
+ unsigned int *revision_reg_ptr = (unsigned int *) AP1xx_FPGA_REV_ADDR;
+
+ return (*revision_reg_ptr & AP1xx_TARGET_MASK);
+}
+
+#if 0 /* loadace is not working; it appears to be a hardware issue with the system ace. */
+/*
+ This function loads FPGA configurations from the SystemACE CompactFlash
+*/
+int do_loadace (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned char *p = (unsigned char *) AP1000_SYSACE_REGBASE;
+ int cfg;
+
+ if ((p[SYSACE_STATREG0] & 0x10) == 0) {
+ p[SYSACE_CTRLREG0] = 0x80;
+ printf ("\nNo CompactFlash Detected\n\n");
+ p[SYSACE_CTRLREG0] = 0x00;
+ return 1;
+ }
+
+ /* reset configuration controller: | 0x80 */
+ /* select cpflash & ~0x40 */
+ /* cfg start | 0x20 */
+ /* wait for cfgstart & ~0x10 */
+ /* force cfgmode: | 0x08 */
+ /* do no force cfgaddr: & ~0x04 */
+ /* clear mpulock: & ~0x02 */
+ /* do not force lock request & ~0x01 */
+
+ p[SYSACE_CTRLREG0] = 0x80 | 0x20 | 0x08;
+ p[SYSACE_CTRLREG1] = 0x00;
+
+ /* force config address if arg2 exists */
+ if (argc == 2) {
+ cfg = simple_strtoul (argv[1], NULL, 10);
+
+ if (cfg > 7) {
+ printf ("\nInvalid Configuration\n\n");
+ p[SYSACE_CTRLREG0] = 0x00;
+ return 1;
+ }
+ /* Set config address */
+ p[SYSACE_CTRLREG1] = (cfg << 5);
+ /* force cfgaddr */
+ p[SYSACE_CTRLREG0] |= 0x04;
+
+ } else {
+ cfg = (p[SYSACE_STATREG1] & 0xE0) >> 5;
+ }
+
+ /* release configuration controller */
+ printf ("\nLoading V2PRO with config %d...\n", cfg);
+ p[SYSACE_CTRLREG0] &= ~0x80;
+
+
+ while ((p[SYSACE_STATREG1] & 0x01) == 0) {
+
+ if (p[SYSACE_ERRREG0] & 0x80) {
+ /* attempting to load an invalid configuration makes the cpflash */
+ /* appear to be removed. Reset here to avoid that problem */
+ p[SYSACE_CTRLREG0] = 0x80;
+ printf ("\nConfiguration %d Read Error\n\n", cfg);
+ p[SYSACE_CTRLREG0] = 0x00;
+ return 1;
+ }
+ }
+
+ p[SYSACE_CTRLREG0] |= 0x20;
+
+ return 0;
+}
+#endif
+
+/** Console command to display and set the software reconfigure byte
+ * <pre>
+ * swconfig - display the current value of the software reconfigure byte
+ * swconfig [#] - change the software reconfigure byte to #
+ * </pre>
+ * @param *cmdtp [IN] as passed by run_command (ignored)
+ * @param flag [IN] as passed by run_command (ignored)
+ * @param argc [IN] as passed by run_command if 1, display, if 2 change
+ * @param *argv[] [IN] contains the parameters to use
+ * @return
+ * <pre>
+ * 0 if passed
+ * -1 if failed
+ * </pre>
+ */
+int do_swconfigbyte (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned char *sector_buffer = NULL;
+ unsigned char input_char;
+ int write_result;
+ unsigned int input_uint;
+
+ /* display value if no argument */
+ if (argc < 2) {
+ printf ("Software configuration byte is currently: 0x%02x\n",
+ *((unsigned char *) (SW_BYTE_SECTOR_ADDR +
+ SW_BYTE_SECTOR_OFFSET)));
+ return 0;
+ } else if (argc > 3) {
+ printf ("Too many arguments\n");
+ return -1;
+ }
+
+ /* if 3 arguments, 3rd argument is the address to use */
+ if (argc == 3) {
+ input_uint = simple_strtoul (argv[1], NULL, 16);
+ sector_buffer = (unsigned char *) input_uint;
+ } else {
+ sector_buffer = (unsigned char *) DEFAULT_TEMP_ADDR;
+ }
+
+ input_char = simple_strtoul (argv[1], NULL, 0);
+ if ((input_char & ~SW_BYTE_MASK) != 0) {
+ printf ("Input of 0x%02x will be masked to 0x%02x\n",
+ input_char, (input_char & SW_BYTE_MASK));
+ input_char = input_char & SW_BYTE_MASK;
+ }
+
+ memcpy (sector_buffer, (void *) SW_BYTE_SECTOR_ADDR,
+ SW_BYTE_SECTOR_SIZE);
+ sector_buffer[SW_BYTE_SECTOR_OFFSET] = input_char;
+
+
+ printf ("Erasing Flash...");
+ if (flash_sect_erase
+ (SW_BYTE_SECTOR_ADDR,
+ (SW_BYTE_SECTOR_ADDR + SW_BYTE_SECTOR_OFFSET))) {
+ return -1;
+ }
+
+ printf ("Writing to Flash... ");
+ write_result =
+ flash_write ((char *)sector_buffer, SW_BYTE_SECTOR_ADDR,
+ SW_BYTE_SECTOR_SIZE);
+ if (write_result != 0) {
+ flash_perror (write_result);
+ return -1;
+ } else {
+ printf ("done\n");
+ printf ("Software configuration byte is now: 0x%02x\n",
+ *((unsigned char *) (SW_BYTE_SECTOR_ADDR +
+ SW_BYTE_SECTOR_OFFSET)));
+ }
+
+ return 0;
+}
+
+#define ONE_SECOND 1000000
+
+int do_pause (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ int pause_time;
+ unsigned int delay_time;
+ int break_loop = 0;
+
+ /* display value if no argument */
+ if (argc < 2) {
+ pause_time = 1;
+ }
+
+ else if (argc > 2) {
+ printf ("Too many arguments\n");
+ return -1;
+ } else {
+ pause_time = simple_strtoul (argv[1], NULL, 0);
+ }
+
+ printf ("Pausing with a poll time of %d, press any key to reactivate\n", pause_time);
+ delay_time = pause_time * ONE_SECOND;
+ while (break_loop == 0) {
+ udelay (delay_time);
+ if (serial_tstc () != 0) {
+ break_loop = 1;
+ /* eat user key presses */
+ while (serial_tstc () != 0) {
+ serial_getc ();
+ }
+ }
+ }
+
+ return 0;
+}
+
+int do_swreconfig (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ printf ("Triggering software reconfigure (software config byte is 0x%02x)...\n",
+ *((unsigned char *) (SW_BYTE_SECTOR_ADDR + SW_BYTE_SECTOR_OFFSET)));
+ udelay (1000);
+ *((unsigned char *) AP1000_CPLD_BASE) = 1;
+
+ return 0;
+}
+
+#define GET_DECIMAL(low_byte) ((low_byte >> 5) * 125)
+#define TEMP_BUSY_BIT 0x80
+#define TEMP_LHIGH_BIT 0x40
+#define TEMP_LLOW_BIT 0x20
+#define TEMP_EHIGH_BIT 0x10
+#define TEMP_ELOW_BIT 0x08
+#define TEMP_OPEN_BIT 0x04
+#define TEMP_ETHERM_BIT 0x02
+#define TEMP_LTHERM_BIT 0x01
+
+int do_temp_sensor (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ char cmd;
+ int ret_val = 0;
+ unsigned char temp_byte;
+ int temp;
+ int temp_low;
+ int low;
+ int low_low;
+ int high;
+ int high_low;
+ int therm;
+ unsigned char user_data[4] = { 0 };
+ int user_data_count = 0;
+ int ii;
+
+ if (argc > 1) {
+ cmd = argv[1][0];
+ } else {
+ cmd = 's'; /* default to status */
+ }
+
+ user_data_count = argc - 2;
+ for (ii = 0; ii < user_data_count; ii++) {
+ user_data[ii] = simple_strtoul (argv[2 + ii], NULL, 0);
+ }
+ switch (cmd) {
+ case 's':
+ if (I2CAccess
+ (0x2, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+ &temp_byte, I2C_READ) != 0) {
+ goto fail;
+ }
+ printf ("Status : 0x%02x ", temp_byte);
+ if (temp_byte & TEMP_BUSY_BIT)
+ printf ("BUSY ");
+
+ if (temp_byte & TEMP_LHIGH_BIT)
+ printf ("LHIGH ");
+
+ if (temp_byte & TEMP_LLOW_BIT)
+ printf ("LLOW ");
+
+ if (temp_byte & TEMP_EHIGH_BIT)
+ printf ("EHIGH ");
+
+ if (temp_byte & TEMP_ELOW_BIT)
+ printf ("ELOW ");
+
+ if (temp_byte & TEMP_OPEN_BIT)
+ printf ("OPEN ");
+
+ if (temp_byte & TEMP_ETHERM_BIT)
+ printf ("ETHERM ");
+
+ if (temp_byte & TEMP_LTHERM_BIT)
+ printf ("LTHERM");
+
+ printf ("\n");
+
+ if (I2CAccess
+ (0x3, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+ &temp_byte, I2C_READ) != 0) {
+ goto fail;
+ }
+ printf ("Config : 0x%02x ", temp_byte);
+
+ if (I2CAccess
+ (0x4, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+ &temp_byte, I2C_READ) != 0) {
+ printf ("\n");
+ goto fail;
+ }
+ printf ("Conversion: 0x%02x\n", temp_byte);
+ if (I2CAccess
+ (0x22, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+ &temp_byte, I2C_READ) != 0) {
+ goto fail;
+ }
+ printf ("Cons Alert: 0x%02x ", temp_byte);
+
+ if (I2CAccess
+ (0x21, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+ &temp_byte, I2C_READ) != 0) {
+ printf ("\n");
+ goto fail;
+ }
+ printf ("Therm Hyst: %d\n", temp_byte);
+
+ if (I2CAccess
+ (0x0, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+ &temp_byte, I2C_READ) != 0) {
+ goto fail;
+ }
+ temp = temp_byte;
+ if (I2CAccess
+ (0x6, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+ &temp_byte, I2C_READ) != 0) {
+ goto fail;
+ }
+ low = temp_byte;
+ if (I2CAccess
+ (0x5, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+ &temp_byte, I2C_READ) != 0) {
+ goto fail;
+ }
+ high = temp_byte;
+ if (I2CAccess
+ (0x20, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+ &temp_byte, I2C_READ) != 0) {
+ goto fail;
+ }
+ therm = temp_byte;
+ printf ("Local Temp: %2d Low: %2d High: %2d THERM: %2d\n", temp, low, high, therm);
+
+ if (I2CAccess
+ (0x1, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+ &temp_byte, I2C_READ) != 0) {
+ goto fail;
+ }
+ temp = temp_byte;
+ if (I2CAccess
+ (0x10, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+ &temp_byte, I2C_READ) != 0) {
+ goto fail;
+ }
+ temp_low = temp_byte;
+ if (I2CAccess
+ (0x8, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+ &temp_byte, I2C_READ) != 0) {
+ goto fail;
+ }
+ low = temp_byte;
+ if (I2CAccess
+ (0x14, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+ &temp_byte, I2C_READ) != 0) {
+ goto fail;
+ }
+ low_low = temp_byte;
+ if (I2CAccess
+ (0x7, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+ &temp_byte, I2C_READ) != 0) {
+ goto fail;
+ }
+ high = temp_byte;
+ if (I2CAccess
+ (0x13, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+ &temp_byte, I2C_READ) != 0) {
+ goto fail;
+ }
+ high_low = temp_byte;
+ if (I2CAccess
+ (0x19, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+ &temp_byte, I2C_READ) != 0) {
+ goto fail;
+ }
+ therm = temp_byte;
+ if (I2CAccess
+ (0x11, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+ &temp_byte, I2C_READ) != 0) {
+ goto fail;
+ }
+ printf ("Ext Temp : %2d.%03d Low: %2d.%03d High: %2d.%03d THERM: %2d Offset: %2d\n", temp, GET_DECIMAL (temp_low), low, GET_DECIMAL (low_low), high, GET_DECIMAL (high_low), therm, temp_byte);
+ break;
+ case 'l': /* alter local limits : low, high, therm */
+ if (argc < 3) {
+ goto usage;
+ }
+
+ /* low */
+ if (I2CAccess
+ (0xC, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+ &user_data[0], I2C_WRITE) != 0) {
+ goto fail;
+ }
+
+ if (user_data_count > 1) {
+ /* high */
+ if (I2CAccess
+ (0xB, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+ &user_data[1], I2C_WRITE) != 0) {
+ goto fail;
+ }
+ }
+
+ if (user_data_count > 2) {
+ /* therm */
+ if (I2CAccess
+ (0x20, I2C_SENSOR_DEV,
+ I2C_SENSOR_CHIP_SEL, &user_data[2],
+ I2C_WRITE) != 0) {
+ goto fail;
+ }
+ }
+ break;
+ case 'e': /* alter external limits: low, high, therm, offset */
+ if (argc < 3) {
+ goto usage;
+ }
+
+ /* low */
+ if (I2CAccess
+ (0xE, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+ &user_data[0], I2C_WRITE) != 0) {
+ goto fail;
+ }
+
+ if (user_data_count > 1) {
+ /* high */
+ if (I2CAccess
+ (0xD, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+ &user_data[1], I2C_WRITE) != 0) {
+ goto fail;
+ }
+ }
+
+ if (user_data_count > 2) {
+ /* therm */
+ if (I2CAccess
+ (0x19, I2C_SENSOR_DEV,
+ I2C_SENSOR_CHIP_SEL, &user_data[2],
+ I2C_WRITE) != 0) {
+ goto fail;
+ }
+ }
+
+ if (user_data_count > 3) {
+ /* offset */
+ if (I2CAccess
+ (0x11, I2C_SENSOR_DEV,
+ I2C_SENSOR_CHIP_SEL, &user_data[3],
+ I2C_WRITE) != 0) {
+ goto fail;
+ }
+ }
+ break;
+ case 'c': /* alter config settings: config, conv, cons alert, therm hyst */
+ if (argc < 3) {
+ goto usage;
+ }
+
+ /* config */
+ if (I2CAccess
+ (0x9, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+ &user_data[0], I2C_WRITE) != 0) {
+ goto fail;
+ }
+
+ if (user_data_count > 1) {
+ /* conversion */
+ if (I2CAccess
+ (0xA, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+ &user_data[1], I2C_WRITE) != 0) {
+ goto fail;
+ }
+ }
+
+ if (user_data_count > 2) {
+ /* cons alert */
+ if (I2CAccess
+ (0x22, I2C_SENSOR_DEV,
+ I2C_SENSOR_CHIP_SEL, &user_data[2],
+ I2C_WRITE) != 0) {
+ goto fail;
+ }
+ }
+
+ if (user_data_count > 3) {
+ /* therm hyst */
+ if (I2CAccess
+ (0x21, I2C_SENSOR_DEV,
+ I2C_SENSOR_CHIP_SEL, &user_data[3],
+ I2C_WRITE) != 0) {
+ goto fail;
+ }
+ }
+ break;
+ default:
+ goto usage;
+ }
+
+ goto done;
+fail:
+ printf ("Access to sensor failed\n");
+ ret_val = -1;
+ goto done;
+usage:
+ printf ("Usage:\n%s\n", cmdtp->help);
+
+done:
+ return ret_val;
+}
+
+U_BOOT_CMD (temp, 6, 0, do_temp_sensor,
+ "temp - interact with the temperature sensor\n",
+ "temp [s]\n"
+ " - Show status.\n"
+ "temp l LOW [HIGH] [THERM]\n"
+ " - Set local limits.\n"
+ "temp e LOW [HIGH] [THERM] [OFFSET]\n"
+ " - Set external limits.\n"
+ "temp c CONFIG [CONVERSION] [CONS. ALERT] [THERM HYST]\n"
+ " - Set config options.\n"
+ "\n"
+ "All values can be decimal or hex (hex preceded with 0x).\n"
+ "Only whole numbers are supported for external limits.\n");
+
+#if 0
+U_BOOT_CMD (loadace, 2, 0, do_loadace,
+ "loadace - load fpga configuration from System ACE compact flash\n",
+ "N\n"
+ " - Load configuration N (0-7) from System ACE compact flash\n"
+ "loadace\n" " - loads default configuration\n");
+#endif
+
+U_BOOT_CMD (swconfig, 2, 0, do_swconfigbyte,
+ "swconfig- display or modify the software configuration byte\n",
+ "N [ADDRESS]\n"
+ " - set software configuration byte to N, optionally use ADDRESS as\n"
+ " location of buffer for flash copy\n"
+ "swconfig\n" " - display software configuration byte\n");
+
+U_BOOT_CMD (pause, 2, 0, do_pause,
+ "pause - sleep processor until any key is pressed with poll time of N seconds\n",
+ "N\n"
+ " - sleep processor until any key is pressed with poll time of N seconds\n"
+ "pause\n"
+ " - sleep processor until any key is pressed with poll time of 1 second\n");
+
+U_BOOT_CMD (swrecon, 1, 0, do_swreconfig,
+ "swrecon - trigger a board reconfigure to the software selected configuration\n",
+ "\n"
+ " - trigger a board reconfigure to the software selected configuration\n");
--- /dev/null
+/*
+ * ap1000.h: AP1000 (e.g. AP1070, AP1100) board specific definitions and functions that are needed globally
+ *
+ * Author : James MacAulay
+ *
+ * This software may be used and distributed according to the terms of
+ * the GNU General Public License (GPL) version 2, incorporated herein by
+ * reference. Drivers based on or derived from this code fall under the GPL
+ * and must retain the authorship, copyright and this license notice. This
+ * file is not a complete program and may only be used when the entire
+ * program is licensed under the GPL.
+ *
+ */
+
+#ifndef __AP1000_H
+#define __AP1000_H
+
+/*
+ * Revision Register stuff
+ */
+#define AP1xx_FPGA_REV_ADDR 0x29000000
+
+#define AP1xx_PLATFORM_MASK 0xFF000000
+#define AP100_BASELINE_PLATFORM 0x01000000
+#define AP1xx_QUADGE_PLATFORM 0x02000000
+#define AP1xx_MGT_REF_PLATFORM 0x03000000
+#define AP1xx_STANDARD_PLATFORM 0x04000000
+#define AP1xx_DUAL_PLATFORM 0x05000000
+#define AP1xx_BASE_SRAM_PLATFORM 0x06000000
+
+#define AP1000_BASELINE_PLATFORM 0x21000000
+
+#define AP1xx_TESTPLATFORM_MASK 0xC0000000
+#define AP1xx_PCI_PCB_TESTPLATFORM 0xC0000000
+#define AP1xx_DUAL_GE_MEZZ_TESTPLATFORM 0xC1000000
+#define AP1xx_SFP_MEZZ_TESTPLATFORM 0xC2000000
+
+#define AP1000_PCI_PCB_TESTPLATFORM 0xC3000000
+
+#define AP1xx_TARGET_MASK 0x00FF0000
+#define AP1xx_AP107_TARGET 0x00010000
+#define AP1xx_AP120_TARGET 0x00020000
+#define AP1xx_AP130_TARGET 0x00030000
+#define AP1xx_AP1070_TARGET 0x00040000
+#define AP1xx_AP1100_TARGET 0x00050000
+
+#define AP1xx_UNKNOWN_STR "Unknown"
+
+#define AP1xx_PLATFORM_STR " Platform"
+#define AP1xx_BASELINE_PLATFORM_STR "Baseline"
+#define AP1xx_QUADGE_PLATFORM_STR "Quad GE"
+#define AP1xx_MGT_REF_PLATFORM_STR "MGT Reference"
+#define AP1xx_STANDARD_PLATFORM_STR "Standard"
+#define AP1xx_DUAL_PLATFORM_STR "Dual"
+#define AP1xx_BASE_SRAM_PLATFORM_STR "Baseline with SRAM"
+
+#define AP1xx_TESTPLATFORM_STR " Test Platform"
+#define AP1xx_PCI_PCB_TESTPLATFORM_STR "Base"
+#define AP1xx_DUAL_GE_MEZZ_TESTPLATFORM_STR "Dual GE Mezzanine"
+#define AP1xx_SFP_MEZZ_TESTPLATFORM_STR "SFP Mezzanine"
+
+#define AP1xx_TARGET_STR " Board"
+#define AP1xx_AP107_TARGET_STR "AP107"
+#define AP1xx_AP120_TARGET_STR "AP120"
+#define AP1xx_AP130_TARGET_STR "AP130"
+
+#define AP1xx_AP1070_TARGET_STR "AP1070"
+#define AP1xx_AP1100_TARGET_STR "AP1100"
+
+/*
+ * Flash Stuff
+ */
+#define AP1xx_PROGRAM_FLASH_INDEX 0
+#define AP1xx_CONFIG_FLASH_INDEX 1
+
+/*
+ * System Ace Stuff
+ */
+#define AP1000_SYSACE_REGBASE 0x28000000
+
+#define SYSACE_STATREG0 0x04 /* 7:0 */
+#define SYSACE_STATREG1 0x05 /* 15:8 */
+#define SYSACE_STATREG2 0x06 /* 23:16 */
+#define SYSACE_STATREG3 0x07 /* 31:24 */
+
+#define SYSACE_ERRREG0 0x08 /* 7:0 */
+#define SYSACE_ERRREG1 0x09 /* 15:8 */
+#define SYSACE_ERRREG2 0x0a /* 23:16 */
+#define SYSACE_ERRREG3 0x0b /* 31:24 */
+
+#define SYSACE_CTRLREG0 0x18 /* 7:0 */
+#define SYSACE_CTRLREG1 0x19 /* 15:8 */
+#define SYSACE_CTRLREG2 0x1A /* 23:16 */
+#define SYSACE_CTRLREG3 0x1B /* 31:24 */
+
+/*
+ * Software reconfig thing
+ */
+#define SW_BYTE_SECTOR_ADDR 0x24FE0000
+#define SW_BYTE_SECTOR_OFFSET 0x0001FFFF
+#define SW_BYTE_SECTOR_SIZE 0x00020000
+#define SW_BYTE_MASK 0x00000003
+
+#define DEFAULT_TEMP_ADDR 0x00100000
+
+#define AP1000_CPLD_BASE 0x26000000
+
+/* PowerSpan II Stuff */
+#define PSII_SYNC() asm("eieio")
+#define PSPAN_BASEADDR 0x30000000
+#define EEPROM_DEFAULT { 0x01, /* Byte 0 - Long Load = 0x02, short = 01, use 0xff for try no load */ \
+ 0x0,0x0,0x0, /* Bytes 1 - 3 Power span reserved */ \
+ 0x0, /* Byte 4 - Powerspan reserved - start of short load */ \
+ 0x0F, /* Byte 5 - Enable PCI 1 & 2 as Bus masters and Memory targets. */ \
+ 0x0E, /* Byte 6 - PCI 1 Target image prefetch - on for image 0,1,2, off for i20 & 3. */ \
+ 0x00, 0x00, /* Byte 7,8 - PCI-1 Subsystem ID - */ \
+ 0x00, 0x00, /* Byte 9,10 - PCI-1 Subsystem Vendor Id - */ \
+ 0x00, /* Byte 11 - No PCI interrupt generation on PCI-1 PCI-2 int A */ \
+ 0x1F, /* Byte 12 - PCI-1 enable bridge registers, all target images */ \
+ 0xBA, /* Byte 13 - Target 0 image 128 Meg(Ram), Target 1 image 64 Meg. (config Flash/CPLD )*/ \
+ 0xA0, /* Byte 14 - Target 2 image 64 Meg(program Flash), target 3 64k. */ \
+ 0x00, /* Byte 15 - Vital Product Data Disabled. */ \
+ 0x88, /* Byte 16 - PCI arbiter config complete, all requests routed through PCI-1, Unlock PCI-1 */ \
+ 0x40, /* Byte 17 - Interrupt direction control - PCI-1 Int A out, everything else in. */ \
+ 0x00, /* Byte 18 - I2O disabled */ \
+ 0x00, /* Byte 19 - PCI-2 Target image prefetch - off for all images. */ \
+ 0x00,0x00, /* Bytes 20,21 - PCI 2 Subsystem Id */ \
+ 0x00,0x00, /* Bytes 22,23 - PCI 2 Subsystem Vendor id */ \
+ 0x0C, /* Byte 24 - PCI-2 BAR enables, target image 0, & 1 */ \
+ 0xBB, /* Byte 25 - PCI-2 target 0 - 128 Meg(Ram), target 1 - 128 Meg (program/config flash) */ \
+ 0x00, /* Byte 26 - PCI-2 target 2 & 3 unused. */ \
+ 0x00,0x00,0x00,0x00,0x00, /* Bytes 27,28,29,30, 31 - Reserved */ \
+ /* Long Load Information */ \
+ 0x82,0x60, /* Bytes 32,33 - PCI-1 Device ID - Powerspan II */ \
+ 0x10,0xE3, /* Bytes 24,35 - PCI-1 Vendor ID - Tundra */ \
+ 0x06, /* Byte 36 - PCI-1 Class Base - Bridge device. */ \
+ 0x80, /* Byte 37 - PCI-1 Class sub class - Other bridge. */ \
+ 0x00, /* Byte 38 - PCI-1 Class programing interface - Other bridge */ \
+ 0x01, /* Byte 39 - Power span revision 1. */ \
+ 0x6E, /* Byte 40 - PB SI0 enabled, translation enabled, decode enabled, 64 Meg */ \
+ 0x40, /* Byte 41 - PB SI0 memory command mode, PCI-1 dest */ \
+ 0x22, /* Byte 42 - Prefetch discard after read, PCI-little endian conversion, 32 byte prefetch */ \
+ 0x00,0x00, /* Bytes 43, 44 - Translation address for SI0, set to zero for now. */ \
+ 0x0E, /* Byte 45 - Translation address (0) and PB bus master enables - all. */ \
+ 0x2c,00,00, /* Bytes 46,47,48 - PB SI0 processor base address - 0x2C000000 */ \
+ 0x30,00,00, /* Bytes 49,50,51 - PB Address for Powerspan registers - 0x30000000, big Endian */ \
+ 0x82,0x60, /* Bytes 52, 53 - PCI-2 Device ID - Powerspan II */ \
+ 0x10,0xE3, /* Bytes 54,55 - PCI 2 Vendor Id - Tundra */ \
+ 0x06, /* Byte 56 - PCI-2 Class Base - Bridge device */ \
+ 0x80, /* Byte 57 - PCI-2 Class sub class - Other Bridge. */ \
+ 0x00, /* Byte 58 - PCI-2 class programming interface - Other bridge */ \
+ 0x01, /* Byte 59 - PCI-2 class revision 1 */ \
+ 0x00,0x00,0x00,0x00 }; /* Bytes 60,61, 62, 63 - Powerspan reserved */
+
+
+#define EEPROM_LENGTH 64 /* Long Load */
+
+#define I2C_SENSOR_DEV 0x9
+#define I2C_SENSOR_CHIP_SEL 0x4
+
+/*
+ * Board Functions
+ */
+void set_eat_machine_checks(int a_flag);
+int get_eat_machine_checks(void);
+unsigned int get_platform(void);
+unsigned int get_device(void);
+void* memcpyb(void * dest,const void *src,size_t count);
+int process_bootflag(ulong bootflag);
+void user_led_on(void);
+void user_led_off(void);
+
+#endif /* __COMMON_H_ */
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# Start at bottom of RAM, but at an aliased address so that it looks
+# like it's not in RAM. This is a bit of voodoo to allow it to be
+# run from RAM instead of Flash.
+TEXT_BASE = 0x08000000
--- /dev/null
+/**
+ * @file flash.c
+ */
+
+/*
+ * (C) Copyright 2003
+ * AMIRIX Systems Inc.
+ *
+ * Originated from ppcboot-2.0.0/board/esd/cpci440/strataflash.c
+ *
+ * (C) Copyright 2002
+ * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#undef DEBUG_FLASH
+/*
+ * This file implements a Common Flash Interface (CFI) driver for ppcboot.
+ * The width of the port and the width of the chips are determined at initialization.
+ * These widths are used to calculate the address for access CFI data structures.
+ * It has been tested on an Intel Strataflash implementation.
+ *
+ * References
+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
+ *
+ * TODO
+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
+ * Add support for other command sets Use the PRI and ALT to determine command set
+ * Verify erase and program timeouts.
+ */
+
+#define FLASH_CMD_CFI 0x98
+#define FLASH_CMD_READ_ID 0x90
+#define FLASH_CMD_RESET 0xff
+#define FLASH_CMD_BLOCK_ERASE 0x20
+#define FLASH_CMD_ERASE_CONFIRM 0xD0
+#define FLASH_CMD_WRITE 0x40
+#define FLASH_CMD_PROTECT 0x60
+#define FLASH_CMD_PROTECT_SET 0x01
+#define FLASH_CMD_PROTECT_CLEAR 0xD0
+#define FLASH_CMD_CLEAR_STATUS 0x50
+#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
+#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
+
+#define FLASH_STATUS_DONE 0x80
+#define FLASH_STATUS_ESS 0x40
+#define FLASH_STATUS_ECLBS 0x20
+#define FLASH_STATUS_PSLBS 0x10
+#define FLASH_STATUS_VPENS 0x08
+#define FLASH_STATUS_PSS 0x04
+#define FLASH_STATUS_DPS 0x02
+#define FLASH_STATUS_R 0x01
+#define FLASH_STATUS_PROTECT 0x01
+
+#define FLASH_OFFSET_CFI 0x55
+#define FLASH_OFFSET_CFI_RESP 0x10
+#define FLASH_OFFSET_WTOUT 0x1F
+#define FLASH_OFFSET_WBTOUT 0x20
+#define FLASH_OFFSET_ETOUT 0x21
+#define FLASH_OFFSET_CETOUT 0x22
+#define FLASH_OFFSET_WMAX_TOUT 0x23
+#define FLASH_OFFSET_WBMAX_TOUT 0x24
+#define FLASH_OFFSET_EMAX_TOUT 0x25
+#define FLASH_OFFSET_CEMAX_TOUT 0x26
+#define FLASH_OFFSET_SIZE 0x27
+#define FLASH_OFFSET_INTERFACE 0x28
+#define FLASH_OFFSET_BUFFER_SIZE 0x2A
+#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
+#define FLASH_OFFSET_ERASE_REGIONS 0x2D
+#define FLASH_OFFSET_PROTECT 0x02
+#define FLASH_OFFSET_USER_PROTECTION 0x85
+#define FLASH_OFFSET_INTEL_PROTECTION 0x81
+
+#define FLASH_MAN_CFI 0x01000000
+
+typedef union {
+ unsigned char c;
+ unsigned short w;
+ unsigned long l;
+} cfiword_t;
+
+typedef union {
+ unsigned char *cp;
+ unsigned short *wp;
+ unsigned long *lp;
+} cfiptr_t;
+
+#define NUM_ERASE_REGIONS 4
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c);
+static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf);
+static void flash_write_cmd (flash_info_t * info, int sect, uchar offset,
+ uchar cmd);
+static int flash_isequal (flash_info_t * info, int sect, uchar offset,
+ uchar cmd);
+static int flash_isset (flash_info_t * info, int sect, uchar offset,
+ uchar cmd);
+static int flash_detect_cfi (flash_info_t * info);
+static ulong flash_get_size (ulong base, int banknum);
+static int flash_write_cfiword (flash_info_t * info, ulong dest,
+ cfiword_t cword);
+static int flash_full_status_check (flash_info_t * info, ulong sector,
+ ulong tout, char *prompt);
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
+ int len);
+#endif
+/*-----------------------------------------------------------------------
+ * create an address based on the offset and the port width
+ */
+uchar *flash_make_addr (flash_info_t * info, int sect, int offset)
+{
+ return ((uchar *) (info->start[sect] + (offset * info->chipwidth)));
+}
+
+/*-----------------------------------------------------------------------
+ * read a character at a port width address
+ */
+uchar flash_read_uchar (flash_info_t * info, uchar offset)
+{
+ if (info->portwidth == FLASH_CFI_8BIT) {
+ volatile uchar *cp;
+ uchar c;
+
+ cp = flash_make_addr (info, 0, offset);
+ c = *cp;
+#ifdef DEBUG_FLASH
+ printf ("flash_read_uchar offset=%04x ptr=%08x c=%02x\n",
+ offset, (unsigned int) cp, c);
+#endif
+ return (c);
+
+ } else if (info->portwidth == FLASH_CFI_16BIT) {
+ volatile ushort *sp;
+ ushort s;
+ uchar c;
+
+ sp = (ushort *) flash_make_addr (info, 0, offset);
+ s = *sp;
+ c = (uchar) s;
+#ifdef DEBUG_FLASH
+ printf ("flash_read_uchar offset=%04x ptr=%08x s=%04x c=%02x\n", offset, (unsigned int) sp, s, c);
+#endif
+ return (c);
+
+ }
+
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * read a short word by swapping for ppc format.
+ */
+ushort flash_read_ushort (flash_info_t * info, int sect, uchar offset)
+{
+ if (info->portwidth == FLASH_CFI_8BIT) {
+ volatile uchar *cp;
+ uchar c0, c1;
+ ushort s;
+
+ cp = flash_make_addr (info, 0, offset);
+ c1 = cp[2];
+ c0 = cp[0];
+ s = c1 << 8 | c0;
+#ifdef DEBUG_FLASH
+ printf ("flash_read_ushort offset=%04x ptr=%08x c1=%02x c0=%02x s=%04x\n", offset, (unsigned int) cp, c1, c0, s);
+#endif
+ return (s);
+
+ } else if (info->portwidth == FLASH_CFI_16BIT) {
+ volatile ushort *sp;
+ ushort s;
+ uchar c0, c1;
+
+ sp = (ushort *) flash_make_addr (info, 0, offset);
+ s = *sp;
+ c1 = (uchar) sp[1];
+ c0 = (uchar) sp[0];
+ s = c1 << 8 | c0;
+#ifdef DEBUG_FLASH
+ printf ("flash_read_ushort offset=%04x ptr=%08x c1=%02x c0=%02x s=%04x\n", offset, (unsigned int) sp, c1, c0, s);
+#endif
+ return (s);
+
+ }
+
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * read a long word by picking the least significant byte of each maiximum
+ * port size word. Swap for ppc format.
+ */
+ulong flash_read_long (flash_info_t * info, int sect, uchar offset)
+{
+ if (info->portwidth == FLASH_CFI_8BIT) {
+ volatile uchar *cp;
+ uchar c0, c1, c2, c3;
+ ulong l;
+
+ cp = flash_make_addr (info, 0, offset);
+ c3 = cp[6];
+ c2 = cp[4];
+ c1 = cp[2];
+ c0 = cp[0];
+ l = c3 << 24 | c2 << 16 | c1 << 8 | c0;
+#ifdef DEBUG_FLASH
+ printf ("flash_read_long offset=%04x ptr=%08x c3=%02x c2=%02x c1=%02x c0=%02x l=%08x\n", offset, (unsigned int) cp, c3, c2, c1, c0, l);
+#endif
+ return (l);
+
+ } else if (info->portwidth == FLASH_CFI_16BIT) {
+ volatile ushort *sp;
+ uchar c0, c1, c2, c3;
+ ulong l;
+
+ sp = (ushort *) flash_make_addr (info, 0, offset);
+ c3 = (uchar) sp[3];
+ c2 = (uchar) sp[2];
+ c1 = (uchar) sp[1];
+ c0 = (uchar) sp[0];
+ l = c3 << 24 | c2 << 16 | c1 << 8 | c0;
+#ifdef DEBUG_FLASH
+ printf ("flash_read_long offset=%04x ptr=%08x c3=%02x c2=%02x c1=%02x c0=%02x l=%08x\n", offset, (unsigned int) sp, c3, c2, c1, c0, l);
+#endif
+ return (l);
+
+ }
+
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+ unsigned long size;
+
+ size = 0;
+
+ flash_info[0].flash_id = FLASH_UNKNOWN;
+ flash_info[0].portwidth = FLASH_CFI_16BIT;
+ flash_info[0].chipwidth = FLASH_CFI_16BIT;
+ size += flash_info[0].size = flash_get_size (CFG_PROGFLASH_BASE, 0);
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", 1, flash_info[0].size, flash_info[0].size << 20);
+ };
+
+ flash_info[1].flash_id = FLASH_UNKNOWN;
+ flash_info[1].portwidth = FLASH_CFI_8BIT;
+ flash_info[1].chipwidth = FLASH_CFI_16BIT;
+ size += flash_info[1].size = flash_get_size (CFG_CONFFLASH_BASE, 1);
+ if (flash_info[1].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", 2, flash_info[1].size, flash_info[1].size << 20);
+ };
+
+ return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+ int rcode = 0;
+ int prot;
+ int sect;
+
+ if (info->flash_id != FLASH_MAN_CFI) {
+ printf ("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+ if ((s_first < 0) || (s_first > s_last)) {
+ printf ("- no sectors to erase\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+ } else {
+ printf ("\n");
+ }
+
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ flash_write_cmd (info, sect, 0,
+ FLASH_CMD_CLEAR_STATUS);
+ flash_write_cmd (info, sect, 0,
+ FLASH_CMD_BLOCK_ERASE);
+ flash_write_cmd (info, sect, 0,
+ FLASH_CMD_ERASE_CONFIRM);
+
+ if (flash_full_status_check
+ (info, sect, info->erase_blk_tout, "erase")) {
+ rcode = 1;
+ } else
+ printf (".");
+ }
+ }
+ printf (" done\n");
+ return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+ int i;
+
+ if (info->flash_id != FLASH_MAN_CFI) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ printf ("CFI conformant FLASH (x%d device in x%d mode)",
+ (info->chipwidth << 3), (info->portwidth << 3));
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+ printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
+
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n");
+ printf (" %08lX%5s",
+ info->start[i], info->protect[i] ? " (RO)" : " ");
+ }
+ printf ("\n");
+ return;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong wp;
+ ulong cp;
+ int aln;
+ cfiword_t cword;
+ int i, rc;
+
+ /* get lower aligned address */
+ wp = (addr & ~(info->portwidth - 1));
+
+ /* handle unaligned start */
+ if ((aln = addr - wp) != 0) {
+ cword.l = 0;
+ cp = wp;
+ for (i = 0; i < aln; ++i, ++cp)
+ flash_add_byte (info, &cword, (*(uchar *) cp));
+
+ for (; (i < info->portwidth) && (cnt > 0); i++) {
+ flash_add_byte (info, &cword, *src++);
+ cnt--;
+ cp++;
+ }
+ for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
+ flash_add_byte (info, &cword, (*(uchar *) cp));
+ if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
+ return rc;
+ wp = cp;
+ }
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+ while (cnt >= info->portwidth) {
+ i = info->buffer_size > cnt ? cnt : info->buffer_size;
+ if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
+ return rc;
+ wp += i;
+ src += i;
+ cnt -= i;
+ }
+#else
+ /* handle the aligned part */
+ while (cnt >= info->portwidth) {
+ cword.l = 0;
+ for (i = 0; i < info->portwidth; i++) {
+ flash_add_byte (info, &cword, *src++);
+ }
+ if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
+ return rc;
+ wp += info->portwidth;
+ cnt -= info->portwidth;
+ }
+#endif /* CFG_FLASH_USE_BUFFER_WRITE */
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ cword.l = 0;
+ for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) {
+ flash_add_byte (info, &cword, *src++);
+ --cnt;
+ }
+ for (; i < info->portwidth; ++i, ++cp) {
+ flash_add_byte (info, &cword, (*(uchar *) cp));
+ }
+
+ return flash_write_cfiword (info, wp, cword);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect (flash_info_t * info, long sector, int prot)
+{
+ int retcode = 0;
+
+ flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+ flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT);
+ if (prot)
+ flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET);
+ else
+ flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
+
+ if ((retcode =
+ flash_full_status_check (info, sector, info->erase_blk_tout,
+ prot ? "protect" : "unprotect")) == 0) {
+
+ info->protect[sector] = prot;
+ /* Intel's unprotect unprotects all locking */
+ if (prot == 0) {
+ int i;
+
+ for (i = 0; i < info->sector_count; i++) {
+ if (info->protect[i])
+ flash_real_protect (info, i, 1);
+ }
+ }
+ }
+
+ return retcode;
+}
+
+/*-----------------------------------------------------------------------
+ * wait for XSR.7 to be set. Time out with an error if it does not.
+ * This routine does not set the flash to read-array mode.
+ */
+static int flash_status_check (flash_info_t * info, ulong sector, ulong tout,
+ char *prompt)
+{
+ ulong start;
+
+ /* Wait for command completion */
+ start = get_timer (0);
+ while (!flash_isset (info, sector, 0, FLASH_STATUS_DONE)) {
+ if (get_timer (start) > info->erase_blk_tout) {
+ printf ("Flash %s timeout at address %lx\n", prompt,
+ info->start[sector]);
+ flash_write_cmd (info, sector, 0, FLASH_CMD_RESET);
+ return ERR_TIMOUT;
+ }
+ }
+ return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
+ * This routine sets the flash to read-array mode.
+ */
+static int flash_full_status_check (flash_info_t * info, ulong sector,
+ ulong tout, char *prompt)
+{
+ int retcode;
+
+ retcode = flash_status_check (info, sector, tout, prompt);
+ if ((retcode == ERR_OK)
+ && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
+ retcode = ERR_INVAL;
+ printf ("Flash %s error at address %lx\n", prompt,
+ info->start[sector]);
+ if (flash_isset
+ (info, sector, 0,
+ FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
+ printf ("Command Sequence Error.\n");
+ } else if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS)) {
+ printf ("Block Erase Error.\n");
+ retcode = ERR_NOT_ERASED;
+ } else if (flash_isset (info, sector, 0, FLASH_STATUS_PSLBS)) {
+ printf ("Locking Error\n");
+ }
+ if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) {
+ printf ("Block locked.\n");
+ retcode = ERR_PROTECTED;
+ }
+ if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS))
+ printf ("Vpp Low Error.\n");
+ }
+ flash_write_cmd (info, sector, 0, FLASH_CMD_RESET);
+ return retcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
+{
+ switch (info->portwidth) {
+ case FLASH_CFI_8BIT:
+ cword->c = c;
+ break;
+ case FLASH_CFI_16BIT:
+ cword->w = (cword->w << 8) | c;
+ break;
+ case FLASH_CFI_32BIT:
+ cword->l = (cword->l << 8) | c;
+ }
+}
+
+/*-----------------------------------------------------------------------
+ * make a proper sized command based on the port and chip widths
+ */
+static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf)
+{
+ /*int i; */
+ uchar *cp = (uchar *) cmdbuf;
+
+ /* for(i=0; i< info->portwidth; i++) */
+ /* *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; */
+ if (info->portwidth == FLASH_CFI_8BIT
+ && info->chipwidth == FLASH_CFI_16BIT) {
+ cp[0] = cmd;
+ } else if (info->portwidth == FLASH_CFI_16BIT
+ && info->chipwidth == FLASH_CFI_16BIT) {
+ cp[0] = '\0';
+ cp[1] = cmd;
+ };
+}
+
+/*
+ * Write a proper sized command to the correct address
+ */
+static void flash_write_cmd (flash_info_t * info, int sect, uchar offset,
+ uchar cmd)
+{
+
+ volatile cfiptr_t addr;
+ cfiword_t cword;
+
+ addr.cp = flash_make_addr (info, sect, offset);
+ flash_make_cmd (info, cmd, &cword);
+ switch (info->portwidth) {
+ case FLASH_CFI_8BIT:
+ *addr.cp = cword.c;
+ break;
+ case FLASH_CFI_16BIT:
+ *addr.wp = cword.w;
+ break;
+ case FLASH_CFI_32BIT:
+ *addr.lp = cword.l;
+ break;
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isequal (flash_info_t * info, int sect, uchar offset,
+ uchar cmd)
+{
+ cfiptr_t cptr;
+ cfiword_t cword;
+ int retval;
+
+ cptr.cp = flash_make_addr (info, sect, offset);
+ flash_make_cmd (info, cmd, &cword);
+ switch (info->portwidth) {
+ case FLASH_CFI_8BIT:
+ retval = (cptr.cp[0] == cword.c);
+ break;
+ case FLASH_CFI_16BIT:
+ retval = (cptr.wp[0] == cword.w);
+ break;
+ case FLASH_CFI_32BIT:
+ retval = (cptr.lp[0] == cword.l);
+ break;
+ default:
+ retval = 0;
+ break;
+ }
+ return retval;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isset (flash_info_t * info, int sect, uchar offset,
+ uchar cmd)
+{
+ cfiptr_t cptr;
+ cfiword_t cword;
+ int retval;
+
+ cptr.cp = flash_make_addr (info, sect, offset);
+ flash_make_cmd (info, cmd, &cword);
+ switch (info->portwidth) {
+ case FLASH_CFI_8BIT:
+ retval = ((cptr.cp[0] & cword.c) == cword.c);
+ break;
+ case FLASH_CFI_16BIT:
+ retval = ((cptr.wp[0] & cword.w) == cword.w);
+ break;
+ case FLASH_CFI_32BIT:
+ retval = ((cptr.lp[0] & cword.l) == cword.l);
+ break;
+ default:
+ retval = 0;
+ break;
+ }
+ return retval;
+}
+
+/*-----------------------------------------------------------------------
+ * detect if flash is compatible with the Common Flash Interface (CFI)
+ * http://www.jedec.org/download/search/jesd68.pdf
+ *
+*/
+static int flash_detect_cfi (flash_info_t * info)
+{
+
+#if 0
+ for (info->portwidth = FLASH_CFI_8BIT;
+ info->portwidth <= FLASH_CFI_32BIT; info->portwidth <<= 1) {
+ for (info->chipwidth = FLASH_CFI_BY8;
+ info->chipwidth <= info->portwidth;
+ info->chipwidth <<= 1) {
+ flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
+ flash_write_cmd (info, 0, FLASH_OFFSET_CFI,
+ FLASH_CMD_CFI);
+ if (flash_isequal
+ (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
+ && flash_isequal (info, 0,
+ FLASH_OFFSET_CFI_RESP + 1, 'R')
+ && flash_isequal (info, 0,
+ FLASH_OFFSET_CFI_RESP + 2, 'Y'))
+ return 1;
+ }
+ }
+#endif
+ flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
+ flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
+ if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') &&
+ flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
+ flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
+ return 1;
+ } else {
+ return 0;
+ };
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ *
+ */
+static ulong flash_get_size (ulong base, int banknum)
+{
+ flash_info_t *info = &flash_info[banknum];
+ int i, j;
+ int sect_cnt;
+ unsigned long sector;
+ unsigned long tmp;
+ int size_ratio;
+ uchar num_erase_regions;
+ int erase_region_size;
+ int erase_region_count;
+
+ info->start[0] = base;
+
+ if (flash_detect_cfi (info)) {
+#ifdef DEBUG_FLASH
+ printf ("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
+#endif
+ size_ratio = 1; /* info->portwidth / info->chipwidth; */
+ num_erase_regions =
+ flash_read_uchar (info,
+ FLASH_OFFSET_NUM_ERASE_REGIONS);
+#ifdef DEBUG_FLASH
+ printf ("found %d erase regions\n", num_erase_regions);
+#endif
+ sect_cnt = 0;
+ sector = base;
+ for (i = 0; i < num_erase_regions; i++) {
+ if (i > NUM_ERASE_REGIONS) {
+ printf ("%d erase regions found, only %d used\n", num_erase_regions, NUM_ERASE_REGIONS);
+ break;
+ }
+ tmp = flash_read_long (info, 0,
+ FLASH_OFFSET_ERASE_REGIONS);
+ erase_region_count = (tmp & 0xffff) + 1;
+ tmp >>= 16;
+ erase_region_size =
+ (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
+ for (j = 0; j < erase_region_count; j++) {
+ info->start[sect_cnt] = sector;
+ sector += (erase_region_size * size_ratio);
+ info->protect[sect_cnt] =
+ flash_isset (info, sect_cnt,
+ FLASH_OFFSET_PROTECT,
+ FLASH_STATUS_PROTECT);
+ sect_cnt++;
+ }
+ }
+
+ info->sector_count = sect_cnt;
+ /* multiply the size by the number of chips */
+ info->size =
+ (1 << flash_read_uchar (info, FLASH_OFFSET_SIZE)) *
+ size_ratio;
+ info->buffer_size =
+ (1 <<
+ flash_read_ushort (info, 0,
+ FLASH_OFFSET_BUFFER_SIZE));
+ tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT);
+ info->erase_blk_tout =
+ (tmp *
+ (1 <<
+ flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT)));
+ tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT);
+ info->buffer_write_tout =
+ (tmp *
+ (1 <<
+ flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT)));
+ tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT);
+ info->write_tout =
+ (tmp *
+ (1 <<
+ flash_read_uchar (info,
+ FLASH_OFFSET_WMAX_TOUT))) / 1000;
+ info->flash_id = FLASH_MAN_CFI;
+ }
+
+ flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
+ return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_write_cfiword (flash_info_t * info, ulong dest,
+ cfiword_t cword)
+{
+
+ cfiptr_t ctladdr;
+ cfiptr_t cptr;
+ int flag;
+
+ ctladdr.cp = flash_make_addr (info, 0, 0);
+ cptr.cp = (uchar *) dest;
+
+ /* Check if Flash is (sufficiently) erased */
+ switch (info->portwidth) {
+ case FLASH_CFI_8BIT:
+ flag = ((cptr.cp[0] & cword.c) == cword.c);
+ break;
+ case FLASH_CFI_16BIT:
+ flag = ((cptr.wp[0] & cword.w) == cword.w);
+ break;
+ case FLASH_CFI_32BIT:
+ flag = ((cptr.lp[0] & cword.l) == cword.l);
+ break;
+ default:
+ return 2;
+ }
+ if (!flag)
+ return 2;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts ();
+
+ flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS);
+ flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE);
+
+ switch (info->portwidth) {
+ case FLASH_CFI_8BIT:
+ cptr.cp[0] = cword.c;
+ break;
+ case FLASH_CFI_16BIT:
+ cptr.wp[0] = cword.w;
+ break;
+ case FLASH_CFI_32BIT:
+ cptr.lp[0] = cword.l;
+ break;
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts ();
+
+ return flash_full_status_check (info, 0, info->write_tout, "write");
+}
+
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+
+/* loop through the sectors from the highest address
+ * when the passed address is greater or equal to the sector address
+ * we have a match
+ */
+static int find_sector (flash_info_t * info, ulong addr)
+{
+ int sector;
+
+ for (sector = info->sector_count - 1; sector >= 0; sector--) {
+ if (addr >= info->start[sector])
+ break;
+ }
+ return sector;
+}
+
+static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
+ int len)
+{
+
+ int sector;
+ int cnt;
+ int retcode;
+ volatile cfiptr_t src;
+ volatile cfiptr_t dst;
+
+ src.cp = cp;
+ dst.cp = (uchar *) dest;
+ sector = find_sector (info, dest);
+ flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+ flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
+ if ((retcode =
+ flash_status_check (info, sector, info->buffer_write_tout,
+ "write to buffer")) == ERR_OK) {
+ switch (info->portwidth) {
+ case FLASH_CFI_8BIT:
+ cnt = len;
+ break;
+ case FLASH_CFI_16BIT:
+ cnt = len >> 1;
+ break;
+ case FLASH_CFI_32BIT:
+ cnt = len >> 2;
+ break;
+ default:
+ return ERR_INVAL;
+ break;
+ }
+ flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
+ while (cnt-- > 0) {
+ switch (info->portwidth) {
+ case FLASH_CFI_8BIT:
+ *dst.cp++ = *src.cp++;
+ break;
+ case FLASH_CFI_16BIT:
+ *dst.wp++ = *src.wp++;
+ break;
+ case FLASH_CFI_32BIT:
+ *dst.lp++ = *src.lp++;
+ break;
+ default:
+ return ERR_INVAL;
+ break;
+ }
+ }
+ flash_write_cmd (info, sector, 0,
+ FLASH_CMD_WRITE_BUFFER_CONFIRM);
+ retcode =
+ flash_full_status_check (info, sector,
+ info->buffer_write_tout,
+ "buffer write");
+ }
+ flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+ return retcode;
+}
+#endif /* CFG_USE_FLASH_BUFFER_WRITE */
--- /dev/null
+/*
+ * init.S: Stubs for ppcboot initialization
+ *
+ * Copyright 2002 Mind NV
+ *
+ * http://www.mind.be/
+ *
+ * Author : Peter De Schrijver (p2@mind.be)
+ *
+ * This software may be used and distributed according to the terms of
+ * the GNU General Public License (GPL) version 2, incorporated herein by
+ * reference. Drivers based on or derived from this code fall under the GPL
+ * and must retain the authorship, copyright and this license notice. This
+ * file is not a complete program and may only be used when the entire
+ * program is licensed under the GPL.
+ *
+ */
+
+#include <ppc4xx.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+
+ .globl ext_bus_cntlr_init
+ext_bus_cntlr_init:
+ blr
+
+ .globl sdram_init
+sdram_init:
+ blr
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * AMIRIX Systems Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <pci.h>
+
+#define PCI_MEM_82559ER_CSR_BASE 0x30200000
+#define PCI_IO_82559ER_CSR_BASE 0x40000200
+
+/** AP1100 specific values */
+#define PSII_BASE 0x30000000 /**< PowerSpan II dual bridge local bus register address */
+#define PSII_CONFIG_ADDR 0x30000290 /**< PowerSpan II Configuration Cycle Address configuration register */
+#define PSII_CONFIG_DATA 0x30000294 /**< PowerSpan II Configuration Cycle Data register. */
+#define PSII_CONFIG_DEST_PCI2 0x01000000 /**< PowerSpan II configuration cycle destination selection, set for PCI2 bus */
+#define PSII_PCI_MEM_BASE 0x30200000 /**< Local Bus address for start of PCI memory space on PCI2 bus. */
+#define PSII_PCI_MEM_SIZE 0x1BE00000 /**< PCI Memory space about 510 Meg. */
+#define AP1000_SYS_MEM_START 0x00000000 /**< System memory starts at 0. */
+#define AP1000_SYS_MEM_SIZE 0x08000000 /**< System memory is 128 Meg. */
+
+/* static int G_verbosity_level = 1; */
+#define G_verbosity_level 1
+
+void write1 (unsigned long addr, unsigned char val)
+{
+ volatile unsigned char *p = (volatile unsigned char *) addr;
+
+ if (G_verbosity_level > 1)
+ printf ("write1: addr=%08x val=%02x\n", (unsigned int) addr,
+ val);
+ *p = val;
+ asm ("eieio");
+}
+
+unsigned char read1 (unsigned long addr)
+{
+ unsigned char val;
+ volatile unsigned char *p = (volatile unsigned char *) addr;
+
+ if (G_verbosity_level > 1)
+ printf ("read1: addr=%08x ", (unsigned int) addr);
+ val = *p;
+ asm ("eieio");
+ if (G_verbosity_level > 1)
+ printf ("val=%08x\n", val);
+ return val;
+}
+
+void write2 (unsigned long addr, unsigned short val)
+{
+ volatile unsigned short *p = (volatile unsigned short *) addr;
+
+ if (G_verbosity_level > 1)
+ printf ("write2: addr=%08x val=%04x -> *p=%04x\n",
+ (unsigned int) addr, val,
+ ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8));
+
+ *p = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
+ asm ("eieio");
+}
+
+unsigned short read2 (unsigned long addr)
+{
+ unsigned short val;
+ volatile unsigned short *p = (volatile unsigned short *) addr;
+
+ if (G_verbosity_level > 1)
+ printf ("read2: addr=%08x ", (unsigned int) addr);
+ val = *p;
+ val = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
+ asm ("eieio");
+ if (G_verbosity_level > 1)
+ printf ("*p=%04x -> val=%04x\n",
+ ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8), val);
+ return val;
+}
+
+void write4 (unsigned long addr, unsigned long val)
+{
+ volatile unsigned long *p = (volatile unsigned long *) addr;
+
+ if (G_verbosity_level > 1)
+ printf ("write4: addr=%08x val=%08x -> *p=%08x\n",
+ (unsigned int) addr, (unsigned int) val,
+ (unsigned int) (((val & 0xFF000000) >> 24) |
+ ((val & 0x000000FF) << 24) |
+ ((val & 0x00FF0000) >> 8) |
+ ((val & 0x0000FF00) << 8)));
+
+ *p = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
+ ((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
+ asm ("eieio");
+}
+
+unsigned long read4 (unsigned long addr)
+{
+ unsigned long val;
+ volatile unsigned long *p = (volatile unsigned long *) addr;
+
+ if (G_verbosity_level > 1)
+ printf ("read4: addr=%08x", (unsigned int) addr);
+
+ val = *p;
+ val = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
+ ((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
+ asm ("eieio");
+
+ if (G_verbosity_level > 1)
+ printf ("*p=%04x -> val=%04x\n",
+ (unsigned int) (((val & 0xFF000000) >> 24) |
+ ((val & 0x000000FF) << 24) |
+ ((val & 0x00FF0000) >> 8) |
+ ((val & 0x0000FF00) << 8)),
+ (unsigned int) val);
+ return val;
+}
+
+void write4be (unsigned long addr, unsigned long val)
+{
+ volatile unsigned long *p = (volatile unsigned long *) addr;
+
+ if (G_verbosity_level > 1)
+ printf ("write4: addr=%08x val=%08x\n", (unsigned int) addr,
+ (unsigned int) val);
+ *p = val;
+ asm ("eieio");
+}
+
+/** One byte configuration write on PSII.
+ * Currently fixes destination PCI bus to PCI2, onboard
+ * pci.
+ * @param hose PCI Host controller information. Ignored.
+ * @param dev Encoded PCI device/Bus and Function value.
+ * @param reg PCI Configuration register number.
+ * @param val Address of location for received byte.
+ * @return Always Zero.
+ */
+static int psII_read_config_byte (struct pci_controller *hose,
+ pci_dev_t dev, int reg, u8 * val)
+{
+ write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
+ (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
+
+ *val = read1 (PSII_CONFIG_DATA + (reg & 0x03));
+ return (0);
+}
+
+/** One byte configuration write on PSII.
+ * Currently fixes destination bus to PCI2, onboard
+ * pci.
+ * @param hose PCI Host controller information. Ignored.
+ * @param dev Encoded PCI device/Bus and Function value.
+ * @param reg PCI Configuration register number.
+ * @param val Output byte.
+ * @return Always Zero.
+ */
+static int psII_write_config_byte (struct pci_controller *hose,
+ pci_dev_t dev, int reg, u8 val)
+{
+ write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
+ (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
+
+ write1 (PSII_CONFIG_DATA + (reg & 0x03), (unsigned char) val);
+
+ return (0);
+}
+
+/** One word (16 bit) configuration read on PSII.
+ * Currently fixes destination PCI bus to PCI2, onboard
+ * pci.
+ * @param hose PCI Host controller information. Ignored.
+ * @param dev Encoded PCI device/Bus and Function value.
+ * @param reg PCI Configuration register number.
+ * @param val Address of location for received word.
+ * @return Always Zero.
+ */
+static int psII_read_config_word (struct pci_controller *hose,
+ pci_dev_t dev, int reg, u16 * val)
+{
+ write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
+ (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
+
+ *val = read2 (PSII_CONFIG_DATA + (reg & 0x03));
+ return (0);
+}
+
+/** One word (16 bit) configuration write on PSII.
+ * Currently fixes destination bus to PCI2, onboard
+ * pci.
+ * @param hose PCI Host controller information. Ignored.
+ * @param dev Encoded PCI device/Bus and Function value.
+ * @param reg PCI Configuration register number.
+ * @param val Output word.
+ * @return Always Zero.
+ */
+static int psII_write_config_word (struct pci_controller *hose,
+ pci_dev_t dev, int reg, u16 val)
+{
+ write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
+ (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
+
+ write2 (PSII_CONFIG_DATA + (reg & 0x03), (unsigned short) val);
+
+ return (0);
+}
+
+/** One DWord (32 bit) configuration read on PSII.
+ * Currently fixes destination PCI bus to PCI2, onboard
+ * pci.
+ * @param hose PCI Host controller information. Ignored.
+ * @param dev Encoded PCI device/Bus and Function value.
+ * @param reg PCI Configuration register number.
+ * @param val Address of location for received byte.
+ * @return Always Zero.
+ */
+static int psII_read_config_dword (struct pci_controller *hose,
+ pci_dev_t dev, int reg, u32 * val)
+{
+ write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
+ (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
+
+ *val = read4 (PSII_CONFIG_DATA);
+ return (0);
+}
+
+/** One DWord (32 bit) configuration write on PSII.
+ * Currently fixes destination bus to PCI2, onboard
+ * pci.
+ * @param hose PCI Host controller information. Ignored.
+ * @param dev Encoded PCI device/Bus and Function value.
+ * @param reg PCI Configuration register number.
+ * @param val Output Dword.
+ * @return Always Zero.
+ */
+static int psII_write_config_dword (struct pci_controller *hose,
+ pci_dev_t dev, int reg, u32 val)
+{
+ write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
+ (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
+
+ write4 (PSII_CONFIG_DATA, (unsigned long) val);
+
+ return (0);
+}
+
+static struct pci_config_table ap1000_config_table[] = {
+#ifdef CONFIG_AP1000
+ {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+ PCI_BUS (CFG_ETH_DEV_FN), PCI_DEV (CFG_ETH_DEV_FN),
+ PCI_FUNC (CFG_ETH_DEV_FN),
+ pci_cfgfunc_config_device,
+ {CFG_ETH_IOBASE, CFG_ETH_MEMBASE,
+ PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
+#endif
+ {}
+};
+
+static struct pci_controller psII_hose = {
+ config_table:ap1000_config_table,
+};
+
+void pci_init_board (void)
+{
+ struct pci_controller *hose = &psII_hose;
+
+ /*
+ * Register the hose
+ */
+ hose->first_busno = 0;
+ hose->last_busno = 0xff;
+
+ /* System memory space */
+ pci_set_region (hose->regions + 0,
+ AP1000_SYS_MEM_START, AP1000_SYS_MEM_START,
+ AP1000_SYS_MEM_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* PCI Memory space */
+ pci_set_region (hose->regions + 1,
+ PSII_PCI_MEM_BASE, PSII_PCI_MEM_BASE,
+ PSII_PCI_MEM_SIZE, PCI_REGION_MEM);
+
+ /* No IO Memory space - for now */
+
+ pci_set_ops (hose,
+ psII_read_config_byte,
+ psII_read_config_word,
+ psII_read_config_dword,
+ psII_write_config_byte,
+ psII_write_config_word, psII_write_config_dword);
+
+ hose->region_count = 2;
+
+ pci_register_hose (hose);
+
+ hose->last_busno = pci_hose_scan (hose);
+}
--- /dev/null
+/**
+ * @file powerspan.c Source file for PowerSpan II code.
+ */
+
+/*
+ * (C) Copyright 2005
+ * AMIRIX Systems Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include "powerspan.h"
+#define tolower(x) x
+#include "ap1000.h"
+
+#ifdef INCLUDE_PCI
+
+/** Write one byte with byte swapping.
+ * @param addr [IN] the address to write to
+ * @param val [IN] the value to write
+ */
+void write1 (unsigned long addr, unsigned char val)
+{
+ volatile unsigned char *p = (volatile unsigned char *) addr;
+
+#ifdef VERBOSITY
+ if (gVerbosityLevel > 1) {
+ printf ("write1: addr=%08x val=%02x\n", addr, val);
+ }
+#endif
+ *p = val;
+ PSII_SYNC ();
+}
+
+/** Read one byte with byte swapping.
+ * @param addr [IN] the address to read from
+ * @return the value at addr
+ */
+unsigned char read1 (unsigned long addr)
+{
+ unsigned char val;
+ volatile unsigned char *p = (volatile unsigned char *) addr;
+
+ val = *p;
+ PSII_SYNC ();
+#ifdef VERBOSITY
+ if (gVerbosityLevel > 1) {
+ printf ("read1: addr=%08x val=%02x\n", addr, val);
+ }
+#endif
+ return val;
+}
+
+/** Write one 2-byte word with byte swapping.
+ * @param addr [IN] the address to write to
+ * @param val [IN] the value to write
+ */
+void write2 (unsigned long addr, unsigned short val)
+{
+ volatile unsigned short *p = (volatile unsigned short *) addr;
+
+#ifdef VERBOSITY
+ if (gVerbosityLevel > 1) {
+ printf ("write2: addr=%08x val=%04x -> *p=%04x\n", addr, val,
+ ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8));
+ }
+#endif
+ *p = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
+ PSII_SYNC ();
+}
+
+/** Read one 2-byte word with byte swapping.
+ * @param addr [IN] the address to read from
+ * @return the value at addr
+ */
+unsigned short read2 (unsigned long addr)
+{
+ unsigned short val;
+ volatile unsigned short *p = (volatile unsigned short *) addr;
+
+ val = *p;
+ val = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
+ PSII_SYNC ();
+#ifdef VERBOSITY
+ if (gVerbosityLevel > 1) {
+ printf ("read2: addr=%08x *p=%04x -> val=%04x\n", addr, *p,
+ val);
+ }
+#endif
+ return val;
+}
+
+/** Write one 4-byte word with byte swapping.
+ * @param addr [IN] the address to write to
+ * @param val [IN] the value to write
+ */
+void write4 (unsigned long addr, unsigned long val)
+{
+ volatile unsigned long *p = (volatile unsigned long *) addr;
+
+#ifdef VERBOSITY
+ if (gVerbosityLevel > 1) {
+ printf ("write4: addr=%08x val=%08x -> *p=%08x\n", addr, val,
+ ((val & 0xFF000000) >> 24) |
+ ((val & 0x000000FF) << 24) |
+ ((val & 0x00FF0000) >> 8) |
+ ((val & 0x0000FF00) << 8));
+ }
+#endif
+ *p = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
+ ((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
+ PSII_SYNC ();
+}
+
+/** Read one 4-byte word with byte swapping.
+ * @param addr [IN] the address to read from
+ * @return the value at addr
+ */
+unsigned long read4 (unsigned long addr)
+{
+ unsigned long val;
+ volatile unsigned long *p = (volatile unsigned long *) addr;
+
+ val = *p;
+ val = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
+ ((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
+ PSII_SYNC ();
+#ifdef VERBOSITY
+ if (gVerbosityLevel > 1) {
+ printf ("read4: addr=%08x *p=%08x -> val=%08x\n", addr, *p,
+ val);
+ }
+#endif
+ return val;
+}
+
+int PCIReadConfig (int bus, int dev, int fn, int reg, int width,
+ unsigned long *val)
+{
+ unsigned int conAdrVal;
+ unsigned int conDataReg = REG_CONFIG_DATA;
+ unsigned int status;
+ int ret_val = 0;
+
+
+ /* DEST bit hardcoded to 1: local pci is PCI-2 */
+ /* TYPE bit is hardcoded to 1: all config cycles are local */
+ conAdrVal = (1 << 24)
+ | ((bus & 0xFF) << 16)
+ | ((dev & 0xFF) << 11)
+ | ((fn & 0x07) << 8)
+ | (reg & 0xFC);
+
+ /* clear any pending master aborts */
+ write4 (REG_P1_CSR, CLEAR_MASTER_ABORT);
+
+ /* Load the conAdrVal value first, then read from pb_conf_data */
+ write4 (REG_CONFIG_ADDRESS, conAdrVal);
+ PSII_SYNC ();
+
+
+ /* Note: documentation does not match the pspan library code */
+ /* Note: *pData comes back as -1 if device is not present */
+ switch (width) {
+ case 4:
+ *(unsigned int *) val = read4 (conDataReg);
+ break;
+ case 2:
+ *(unsigned short *) val = read2 (conDataReg);
+ break;
+ case 1:
+ *(unsigned char *) val = read1 (conDataReg);
+ break;
+ default:
+ ret_val = ILLEGAL_REG_OFFSET;
+ break;
+ }
+ PSII_SYNC ();
+
+ /* clear any pending master aborts */
+ status = read4 (REG_P1_CSR);
+ if (status & CLEAR_MASTER_ABORT) {
+ ret_val = NO_DEVICE_FOUND;
+ write4 (REG_P1_CSR, CLEAR_MASTER_ABORT);
+ }
+
+ return ret_val;
+}
+
+
+int PCIWriteConfig (int bus, int dev, int fn, int reg, int width,
+ unsigned long val)
+{
+ unsigned int conAdrVal;
+ unsigned int conDataReg = REG_CONFIG_DATA;
+ unsigned int status;
+ int ret_val = 0;
+
+
+ /* DEST bit hardcoded to 1: local pci is PCI-2 */
+ /* TYPE bit is hardcoded to 1: all config cycles are local */
+ conAdrVal = (1 << 24)
+ | ((bus & 0xFF) << 16)
+ | ((dev & 0xFF) << 11)
+ | ((fn & 0x07) << 8)
+ | (reg & 0xFC);
+
+ /* clear any pending master aborts */
+ write4 (REG_P1_CSR, CLEAR_MASTER_ABORT);
+
+ /* Load the conAdrVal value first, then read from pb_conf_data */
+ write4 (REG_CONFIG_ADDRESS, conAdrVal);
+ PSII_SYNC ();
+
+
+ /* Note: documentation does not match the pspan library code */
+ /* Note: *pData comes back as -1 if device is not present */
+ switch (width) {
+ case 4:
+ write4 (conDataReg, val);
+ break;
+ case 2:
+ write2 (conDataReg, val);
+ break;
+ case 1:
+ write1 (conDataReg, val);
+ break;
+ default:
+ ret_val = ILLEGAL_REG_OFFSET;
+ break;
+ }
+ PSII_SYNC ();
+
+ /* clear any pending master aborts */
+ status = read4 (REG_P1_CSR);
+ if (status & CLEAR_MASTER_ABORT) {
+ ret_val = NO_DEVICE_FOUND;
+ write4 (REG_P1_CSR, CLEAR_MASTER_ABORT);
+ }
+
+ return ret_val;
+}
+
+
+int pci_read_config_byte (int bus, int dev, int fn, int reg,
+ unsigned char *val)
+{
+ unsigned long read_val;
+ int ret_val;
+
+ ret_val = PCIReadConfig (bus, dev, fn, reg, 1, &read_val);
+ *val = read_val & 0xFF;
+
+ return ret_val;
+}
+
+int pci_write_config_byte (int bus, int dev, int fn, int reg,
+ unsigned char val)
+{
+ return PCIWriteConfig (bus, dev, fn, reg, 1, val);
+}
+
+int pci_read_config_word (int bus, int dev, int fn, int reg,
+ unsigned short *val)
+{
+ unsigned long read_val;
+ int ret_val;
+
+ ret_val = PCIReadConfig (bus, dev, fn, reg, 2, &read_val);
+ *val = read_val & 0xFFFF;
+
+ return ret_val;
+}
+
+int pci_write_config_word (int bus, int dev, int fn, int reg,
+ unsigned short val)
+{
+ return PCIWriteConfig (bus, dev, fn, reg, 2, val);
+}
+
+int pci_read_config_dword (int bus, int dev, int fn, int reg,
+ unsigned long *val)
+{
+ return PCIReadConfig (bus, dev, fn, reg, 4, val);
+}
+
+int pci_write_config_dword (int bus, int dev, int fn, int reg,
+ unsigned long val)
+{
+ return PCIWriteConfig (bus, dev, fn, reg, 4, val);
+}
+
+#endif /* INCLUDE_PCI */
+
+int I2CAccess (unsigned char theI2CAddress, unsigned char theDevCode,
+ unsigned char theChipSel, unsigned char *theValue, int RWFlag)
+{
+ int ret_val = 0;
+ unsigned int reg_value;
+
+ reg_value = PowerSpanRead (REG_I2C_CSR);
+
+ if (reg_value & I2C_CSR_ACT) {
+ printf ("Error: I2C busy\n");
+ ret_val = I2C_BUSY;
+ } else {
+ reg_value = ((theI2CAddress & 0xFF) << 24)
+ | ((theDevCode & 0x0F) << 12)
+ | ((theChipSel & 0x07) << 9)
+ | I2C_CSR_ERR;
+ if (RWFlag == I2C_WRITE) {
+ reg_value |= I2C_CSR_RW | ((*theValue & 0xFF) << 16);
+ }
+
+ PowerSpanWrite (REG_I2C_CSR, reg_value);
+ udelay (1);
+
+ do {
+ reg_value = PowerSpanRead (REG_I2C_CSR);
+
+ if ((reg_value & I2C_CSR_ACT) == 0) {
+ if (reg_value & I2C_CSR_ERR) {
+ ret_val = I2C_ERR;
+ } else {
+ *theValue =
+ (reg_value & I2C_CSR_DATA) >>
+ 16;
+ }
+ }
+ } while (reg_value & I2C_CSR_ACT);
+ }
+
+ return ret_val;
+}
+
+int EEPROMRead (unsigned char theI2CAddress, unsigned char *theValue)
+{
+ return I2CAccess (theI2CAddress, I2C_EEPROM_DEV, I2C_EEPROM_CHIP_SEL,
+ theValue, I2C_READ);
+}
+
+int EEPROMWrite (unsigned char theI2CAddress, unsigned char theValue)
+{
+ return I2CAccess (theI2CAddress, I2C_EEPROM_DEV, I2C_EEPROM_CHIP_SEL,
+ &theValue, I2C_WRITE);
+}
+
+int do_eeprom (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ char cmd;
+ int ret_val = 0;
+ unsigned int address = 0;
+ unsigned char value = 1;
+ unsigned char read_value;
+ int ii;
+ int error = 0;
+ unsigned char *mem_ptr;
+ unsigned char default_eeprom[] = EEPROM_DEFAULT;
+
+ if (argc < 2) {
+ goto usage;
+ }
+
+ cmd = argv[1][0];
+ if (argc > 2) {
+ address = simple_strtoul (argv[2], NULL, 16);
+ if (argc > 3) {
+ value = simple_strtoul (argv[3], NULL, 16) & 0xFF;
+ }
+ }
+
+ switch (cmd) {
+ case 'r':
+ if (address > 256) {
+ printf ("Illegal Address\n");
+ goto usage;
+ }
+ printf ("@0x%x: ", address);
+ for (ii = 0; ii < value; ii++) {
+ if (EEPROMRead (address + ii, &read_value) !=
+ 0) {
+ printf ("Read Error\n");
+ } else {
+ printf ("0x%02x ", read_value);
+ }
+
+ if (((ii + 1) % 16) == 0) {
+ printf ("\n");
+ }
+ }
+ printf ("\n");
+ break;
+ case 'w':
+ if (address > 256) {
+ printf ("Illegal Address\n");
+ goto usage;
+ }
+ if (argc < 4) {
+ goto usage;
+ }
+ if (EEPROMWrite (address, value) != 0) {
+ printf ("Write Error\n");
+ }
+ break;
+ case 'g':
+ if (argc != 3) {
+ goto usage;
+ }
+ mem_ptr = (unsigned char *) address;
+ for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0));
+ ii++) {
+ if (EEPROMRead (ii, &read_value) != 0) {
+ printf ("Read Error\n");
+ error = 1;
+ } else {
+ *mem_ptr = read_value;
+ mem_ptr++;
+ }
+ }
+ break;
+ case 'p':
+ if (argc != 3) {
+ goto usage;
+ }
+ mem_ptr = (unsigned char *) address;
+ for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0));
+ ii++) {
+ if (EEPROMWrite (ii, *mem_ptr) != 0) {
+ printf ("Write Error\n");
+ error = 1;
+ }
+
+ mem_ptr++;
+ }
+ break;
+ case 'd':
+ if (argc != 2) {
+ goto usage;
+ }
+ for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0));
+ ii++) {
+ if (EEPROMWrite (ii, default_eeprom[ii]) != 0) {
+ printf ("Write Error\n");
+ error = 1;
+ }
+ }
+ break;
+ default:
+ goto usage;
+ }
+
+ goto done;
+ usage:
+ printf ("Usage:\n%s\n", cmdtp->help);
+
+ done:
+ return ret_val;
+
+}
+
+U_BOOT_CMD (eeprom, 4, 0, do_eeprom,
+ "eeprom - read/write/copy to/from the PowerSpan II eeprom\n",
+ "eeprom r OFF [NUM]\n"
+ " - read NUM words starting at OFF\n"
+ "eeprom w OFF VAL\n"
+ " - write word VAL at offset OFF\n"
+ "eeprom g ADD\n"
+ " - store contents of eeprom at address ADD\n"
+ "eeprom p ADD\n"
+ " - put data stored at address ADD into the eeprom\n"
+ "eeprom d\n" " - return eeprom to default contents\n");
+
+unsigned int PowerSpanRead (unsigned int theOffset)
+{
+ volatile unsigned int *ptr =
+ (volatile unsigned int *) (PSPAN_BASEADDR + theOffset);
+ unsigned int ret_val;
+
+#ifdef VERBOSITY
+ if (gVerbosityLevel > 1) {
+ printf ("PowerSpanRead: offset=%08x ", theOffset);
+ }
+#endif
+ ret_val = *ptr;
+ PSII_SYNC ();
+
+#ifdef VERBOSITY
+ if (gVerbosityLevel > 1) {
+ printf ("value=%08x\n", ret_val);
+ }
+#endif
+
+ return ret_val;
+}
+
+void PowerSpanWrite (unsigned int theOffset, unsigned int theValue)
+{
+ volatile unsigned int *ptr =
+ (volatile unsigned int *) (PSPAN_BASEADDR + theOffset);
+#ifdef VERBOSITY
+ if (gVerbosityLevel > 1) {
+ printf ("PowerSpanWrite: offset=%08x val=%02x\n", theOffset,
+ theValue);
+ }
+#endif
+ *ptr = theValue;
+ PSII_SYNC ();
+}
+
+/**
+ * Sets the indicated bits in the indicated register.
+ * @param theOffset [IN] the register to access.
+ * @param theMask [IN] bits set in theMask will be set in the register.
+ */
+void PowerSpanSetBits (unsigned int theOffset, unsigned int theMask)
+{
+ volatile unsigned int *ptr =
+ (volatile unsigned int *) (PSPAN_BASEADDR + theOffset);
+ unsigned int register_value;
+
+#ifdef VERBOSITY
+ if (gVerbosityLevel > 1) {
+ printf ("PowerSpanSetBits: offset=%08x mask=%02x\n",
+ theOffset, theMask);
+ }
+#endif
+ register_value = *ptr;
+ PSII_SYNC ();
+
+ register_value |= theMask;
+ *ptr = register_value;
+ PSII_SYNC ();
+}
+
+/**
+ * Clears the indicated bits in the indicated register.
+ * @param theOffset [IN] the register to access.
+ * @param theMask [IN] bits set in theMask will be cleared in the register.
+ */
+void PowerSpanClearBits (unsigned int theOffset, unsigned int theMask)
+{
+ volatile unsigned int *ptr =
+ (volatile unsigned int *) (PSPAN_BASEADDR + theOffset);
+ unsigned int register_value;
+
+#ifdef VERBOSITY
+ if (gVerbosityLevel > 1) {
+ printf ("PowerSpanClearBits: offset=%08x mask=%02x\n",
+ theOffset, theMask);
+ }
+#endif
+ register_value = *ptr;
+ PSII_SYNC ();
+
+ register_value &= ~theMask;
+ *ptr = register_value;
+ PSII_SYNC ();
+}
+
+/**
+ * Configures a slave image on the local bus, based on the parameters and some hardcoded system values.
+ * Slave Images are images that cause the PowerSpan II to be a master on the PCI bus. Thus, they
+ * are outgoing from the standpoint of the local bus.
+ * @param theImageIndex [IN] the PowerSpan II image to set (assumed to be 0-7).
+ * @param theBlockSize [IN] the block size of the image (as used by PowerSpan II: PB_SIx_CTL[BS]).
+ * @param theMemIOFlag [IN] if PX_TGT_USE_MEM_IO, this image will have the MEM_IO bit set.
+ * @param theEndianness [IN] the endian bits for the image (already shifted, use defines).
+ * @param theLocalBaseAddr [IN] the Local address for the image (assumed to be valid with provided block size).
+ * @param thePCIBaseAddr [IN] the PCI address for the image (assumed to be valid with provided block size).
+ */
+int SetSlaveImage (int theImageIndex, unsigned int theBlockSize,
+ int theMemIOFlag, int theEndianness,
+ unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr)
+{
+ unsigned int reg_offset = theImageIndex * PB_SLAVE_IMAGE_OFF;
+ unsigned int reg_value = 0;
+
+ /* Make sure that the Slave Image is disabled */
+ PowerSpanClearBits ((REGS_PB_SLAVE_CSR + reg_offset),
+ PB_SLAVE_CSR_IMG_EN);
+
+ /* Setup the mask required for requested PB Slave Image configuration */
+ reg_value = PB_SLAVE_CSR_TA_EN | theEndianness | (theBlockSize << 24);
+ if (theMemIOFlag == PB_SLAVE_USE_MEM_IO) {
+ reg_value |= PB_SLAVE_CSR_MEM_IO;
+ }
+
+ /* hardcoding the following:
+ TA_EN = 1
+ MD_EN = 0
+ MODE = 0
+ PRKEEP = 0
+ RD_AMT = 0
+ */
+ PowerSpanWrite ((REGS_PB_SLAVE_CSR + reg_offset), reg_value);
+
+ /* these values are not checked by software */
+ PowerSpanWrite ((REGS_PB_SLAVE_BADDR + reg_offset), theLocalBaseAddr);
+ PowerSpanWrite ((REGS_PB_SLAVE_TADDR + reg_offset), thePCIBaseAddr);
+
+ /* Enable the Slave Image */
+ PowerSpanSetBits ((REGS_PB_SLAVE_CSR + reg_offset),
+ PB_SLAVE_CSR_IMG_EN);
+
+ return 0;
+}
+
+/**
+ * Configures a target image on the local bus, based on the parameters and some hardcoded system values.
+ * Target Images are used when the PowerSpan II is acting as a target for an access. Thus, they
+ * are incoming from the standpoint of the local bus.
+ * In order to behave better on the host PCI bus, if thePCIBaseAddr is NULL (0x00000000), then the PCI
+ * base address will not be updated; makes sense given that the hosts own memory should be mapped to
+ * PCI address 0x00000000.
+ * @param theImageIndex [IN] the PowerSpan II image to set.
+ * @param theBlockSize [IN] the block size of the image (as used by PowerSpan II: Px_TIx_CTL[BS]).
+ * @param theMemIOFlag [IN] if PX_TGT_USE_MEM_IO, this image will have the MEM_IO bit set.
+ * @param theEndianness [IN] the endian bits for the image (already shifted, use defines).
+ * @param theLocalBaseAddr [IN] the Local address for the image (assumed to be valid with provided block size).
+ * @param thePCIBaseAddr [IN] the PCI address for the image (assumed to be valid with provided block size).
+ */
+int SetTargetImage (int theImageIndex, unsigned int theBlockSize,
+ int theMemIOFlag, int theEndianness,
+ unsigned int theLocalBaseAddr,
+ unsigned int thePCIBaseAddr)
+{
+ unsigned int csr_reg_offset = theImageIndex * P1_TGT_IMAGE_OFF;
+ unsigned int pci_reg_offset = theImageIndex * P1_BST_OFF;
+ unsigned int reg_value = 0;
+
+ /* Make sure that the Slave Image is disabled */
+ PowerSpanClearBits ((REGS_P1_TGT_CSR + csr_reg_offset),
+ PB_SLAVE_CSR_IMG_EN);
+
+ /* Setup the mask required for requested PB Slave Image configuration */
+ reg_value =
+ PX_TGT_CSR_TA_EN | PX_TGT_CSR_BAR_EN | (theBlockSize << 24) |
+ PX_TGT_CSR_RTT_READ | PX_TGT_CSR_WTT_WFLUSH | theEndianness;
+ if (theMemIOFlag == PX_TGT_USE_MEM_IO) {
+ reg_value |= PX_TGT_MEM_IO;
+ }
+
+ /* hardcoding the following:
+ TA_EN = 1
+ BAR_EN = 1
+ MD_EN = 0
+ MODE = 0
+ DEST = 0
+ RTT = 01010
+ GBL = 0
+ CI = 0
+ WTT = 00010
+ PRKEEP = 0
+ MRA = 0
+ RD_AMT = 0
+ */
+ PowerSpanWrite ((REGS_P1_TGT_CSR + csr_reg_offset), reg_value);
+
+ PowerSpanWrite ((REGS_P1_TGT_TADDR + csr_reg_offset),
+ theLocalBaseAddr);
+
+ if (thePCIBaseAddr != (unsigned int) NULL) {
+ PowerSpanWrite ((REGS_P1_BST + pci_reg_offset),
+ thePCIBaseAddr);
+ }
+
+ /* Enable the Slave Image */
+ PowerSpanSetBits ((REGS_P1_TGT_CSR + csr_reg_offset),
+ PB_SLAVE_CSR_IMG_EN);
+
+ return 0;
+}
+
+int do_bridge (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ char cmd;
+ int ret_val = 1;
+ unsigned int image_index;
+ unsigned int block_size;
+ unsigned int mem_io;
+ unsigned int local_addr;
+ unsigned int pci_addr;
+ int endianness;
+
+ if (argc != 8) {
+ goto usage;
+ }
+
+ cmd = argv[1][0];
+ image_index = simple_strtoul (argv[2], NULL, 16);
+ block_size = simple_strtoul (argv[3], NULL, 16);
+ mem_io = simple_strtoul (argv[4], NULL, 16);
+ endianness = argv[5][0];
+ local_addr = simple_strtoul (argv[6], NULL, 16);
+ pci_addr = simple_strtoul (argv[7], NULL, 16);
+
+
+ switch (cmd) {
+ case 'i':
+ if (tolower (endianness) == 'b') {
+ endianness = PX_TGT_CSR_BIG_END;
+ } else if (tolower (endianness) == 'l') {
+ endianness = PX_TGT_CSR_TRUE_LEND;
+ } else {
+ goto usage;
+ }
+ SetTargetImage (image_index, block_size, mem_io,
+ endianness, local_addr, pci_addr);
+ break;
+ case 'o':
+ if (tolower (endianness) == 'b') {
+ endianness = PB_SLAVE_CSR_BIG_END;
+ } else if (tolower (endianness) == 'l') {
+ endianness = PB_SLAVE_CSR_TRUE_LEND;
+ } else {
+ goto usage;
+ }
+ SetSlaveImage (image_index, block_size, mem_io,
+ endianness, local_addr, pci_addr);
+ break;
+ default:
+ goto usage;
+ }
+
+ goto done;
+usage:
+ printf ("Usage:\n%s\n", cmdtp->help);
+
+done:
+ return ret_val;
+}
--- /dev/null
+/**
+ * @file powerspan.h Header file for PowerSpan II code.
+ */
+
+/*
+ * (C) Copyright 2005
+ * AMIRIX Systems Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef POWERSPAN_H
+#define POWERSPAN_H
+
+#define CLEAR_MASTER_ABORT 0xdeadbeef
+#define NO_DEVICE_FOUND -1
+#define ILLEGAL_REG_OFFSET -2
+#define I2C_BUSY -3
+#define I2C_ERR -4
+
+#define REG_P1_CSR 0x004
+#define REGS_P1_BST 0x018
+#define REG_P1_ERR_CSR 0x150
+#define REG_P1_MISC_CSR 0x160
+#define REGS_P1_TGT_CSR 0x100
+#define REGS_P1_TGT_TADDR 0x104
+#define REGS_PB_SLAVE_CSR 0x200
+#define REGS_PB_SLAVE_TADDR 0x204
+#define REGS_PB_SLAVE_BADDR 0x208
+#define REG_CONFIG_ADDRESS 0x290
+#define REG_CONFIG_DATA 0x294
+#define REG_PB_ERR_CSR 0x2B0
+#define REG_PB_MISC_CSR 0x2C0
+#define REG_MISC_CSR 0x400
+#define REG_I2C_CSR 0x408
+#define REG_RESET_CSR 0x40C
+#define REG_ISR0 0x410
+#define REG_ISR1 0x414
+#define REG_IER0 0x418
+#define REG_MBOX_MAP 0x420
+#define REG_HW_MAP 0x42C
+#define REG_IDR 0x444
+
+#define CSR_MEMORY_SPACE_ENABLE 0x00000002
+#define CSR_PCI_MASTER_ENABLE 0x00000004
+
+#define P1_BST_OFF 0x04
+
+#define PX_ERR_ERR_STATUS 0x01000000
+
+#define PX_MISC_CSR_MAX_RETRY_MASK 0x00000F00
+#define PX_MISC_CSR_MAX_RETRY 0x00000F00
+#define PX_MISC_REG_BAR_ENABLE 0x00008000
+#define PB_MISC_TEA_ENABLE 0x00000010
+#define PB_MISC_MAC_TEA 0x00000040
+
+#define P1_TGT_IMAGE_OFF 0x010
+#define PX_TGT_CSR_IMG_EN 0x80000000
+#define PX_TGT_CSR_TA_EN 0x40000000
+#define PX_TGT_CSR_BAR_EN 0x20000000
+#define PX_TGT_CSR_MD_EN 0x10000000
+#define PX_TGT_CSR_MODE 0x00800000
+#define PX_TGT_CSR_DEST 0x00400000
+#define PX_TGT_CSR_MEM_IO 0x00200000
+#define PX_TGT_CSR_GBL 0x00080000
+#define PX_TGT_CSR_CL 0x00040000
+#define PX_TGT_CSR_PRKEEP 0x00000080
+
+#define PX_TGT_CSR_BS_MASK 0x0F000000
+#define PX_TGT_MEM_IO 0x00200000
+#define PX_TGT_CSR_RTT_MASK 0x001F0000
+#define PX_TGT_CSR_RTT_READ 0x000A0000
+#define PX_TGT_CSR_WTT_MASK 0x00001F00
+#define PX_TGT_CSR_WTT_WFLUSH 0x00000200
+#define PX_TGT_CSR_END_MASK 0x00000060
+#define PX_TGT_CSR_BIG_END 0x00000040
+#define PX_TGT_CSR_TRUE_LEND 0x00000060
+#define PX_TGT_CSR_RDAMT_MASK 0x00000007
+
+#define PX_TGT_CSR_BS_64MB 0xa
+#define PX_TGT_CSR_BS_16MB 0x8
+
+#define PX_TGT_USE_MEM_IO 1
+#define PX_TGT_NOT_MEM_IO 0
+
+#define PB_SLAVE_IMAGE_OFF 0x010
+#define PB_SLAVE_CSR_IMG_EN 0x80000000
+#define PB_SLAVE_CSR_TA_EN 0x40000000
+#define PB_SLAVE_CSR_MD_EN 0x20000000
+#define PB_SLAVE_CSR_MODE 0x00800000
+#define PB_SLAVE_CSR_DEST 0x00400000
+#define PB_SLAVE_CSR_MEM_IO 0x00200000
+#define PB_SLAVE_CSR_PRKEEP 0x00000080
+
+#define PB_SLAVE_CSR_BS_MASK 0x1F000000
+#define PB_SLAVE_CSR_END_MASK 0x00000060
+#define PB_SLAVE_CSR_BIG_END 0x00000040
+#define PB_SLAVE_CSR_TRUE_LEND 0x00000060
+#define PB_SLAVE_CSR_RDAMT_MASK 0x00000007
+
+#define PB_SLAVE_USE_MEM_IO 1
+#define PB_SLAVE_NOT_MEM_IO 0
+
+
+#define MISC_CSR_PCI1_LOCK 0x00000080
+
+#define I2C_CSR_ADDR 0xFF000000 /* Specifies I2C Device Address to be Accessed */
+#define I2C_CSR_DATA 0x00FF0000 /* Specifies the Required Data for a Write */
+#define I2C_CSR_DEV_CODE 0x0000F000 /* Device Select. I2C 4-bit Device Code */
+#define I2C_CSR_CS 0x00000E00 /* Chip Select */
+#define I2C_CSR_RW 0x00000100 /* Read/Write */
+#define I2C_CSR_ACT 0x00000080 /* I2C Interface Active */
+#define I2C_CSR_ERR 0x00000040 /* Error */
+
+#define I2C_EEPROM_DEV 0xa
+#define I2C_EEPROM_CHIP_SEL 0
+
+#define I2C_READ 0
+#define I2C_WRITE 1
+
+#define RESET_CSR_EEPROM_LOAD 0x00000010
+
+#define ISR_CLEAR_ALL 0xFFFFFFFF
+
+#define IER0_DMA_INTS_EN 0x0F000000
+#define IER0_PCI_1_EN 0x00400000
+#define IER0_HW_INTS_EN 0x003F0000
+#define IER0_MB_INTS_EN 0x000000FF
+#define IER0_DEFAULT (IER0_DMA_INTS_EN | IER0_PCI_1_EN | IER0_HW_INTS_EN | IER0_MB_INTS_EN)
+
+#define MBOX_MAP_TO_INT4 0xCCCCCCCC
+
+#define HW_MAP_HW4_TO_INT4 0x000C0000
+
+#define IDR_PCI_A_OUT 0x40000000
+#define IDR_MBOX_OUT 0x10000000
+
+
+int pci_read_config_byte(int bus, int dev, int fn, int reg, unsigned char* val);
+int pci_write_config_byte(int bus, int dev, int fn, int reg, unsigned char val);
+int pci_read_config_word(int bus, int dev, int fn, int reg, unsigned short* val);
+int pci_write_config_word(int bus, int dev, int fn, int reg, unsigned short val);
+int pci_read_config_dword(int bus, int dev, int fn, int reg, unsigned long* val);
+int pci_write_config_dword(int bus, int dev, int fn, int reg, unsigned long val);
+
+unsigned int PowerSpanRead(unsigned int theOffset);
+void PowerSpanWrite(unsigned int theOffset, unsigned int theValue);
+
+int I2CAccess(unsigned char theI2CAddress, unsigned char theDevCode, unsigned char theChipSel, unsigned char* theValue, int RWFlag);
+
+int PCIWriteConfig(int bus, int dev, int fn, int reg, int width, unsigned long val);
+int PCIReadConfig(int bus, int dev, int fn, int reg, int width, unsigned long* val);
+
+int SetSlaveImage(int theImageIndex, unsigned int theBlockSize, int theMemIOFlag, int theEndianness, unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr);
+int SetTargetImage(int theImageIndex, unsigned int theBlockSize, int theMemIOFlag, int theEndianness, unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr);
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Peter De Schrijver (p2@mind.be), Mind Linux Solutions, NV.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <asm/u-boot.h>
+#include <asm/processor.h>
+#include <common.h>
+#include <command.h>
+#include <config.h>
+
+#include <ns16550.h>
+
+#if 0
+#include "serial.h"
+#endif
+
+const NS16550_t COM_PORTS[] =
+ { (NS16550_t) CFG_NS16550_COM1, (NS16550_t) CFG_NS16550_COM2 };
+
+#undef CFG_DUART_CHAN
+#define CFG_DUART_CHAN gComPort
+static int gComPort = 0;
+
+int serial_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
+
+ (void) NS16550_init (COM_PORTS[0], clock_divisor);
+ gComPort = 0;
+
+ return 0;
+}
+
+void serial_putc (const char c)
+{
+ if (c == '\n') {
+ NS16550_putc (COM_PORTS[CFG_DUART_CHAN], '\r');
+ }
+
+ NS16550_putc (COM_PORTS[CFG_DUART_CHAN], c);
+}
+
+int serial_getc (void)
+{
+ return NS16550_getc (COM_PORTS[CFG_DUART_CHAN]);
+}
+
+int serial_tstc (void)
+{
+ return NS16550_tstc (COM_PORTS[CFG_DUART_CHAN]);
+}
+
+void serial_setbrg (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
+
+#ifdef CFG_INIT_CHAN1
+ NS16550_reinit (COM_PORTS[0], clock_divisor);
+#endif
+#ifdef CFG_INIT_CHAN2
+ NS16550_reinit (COM_PORTS[1], clock_divisor);
+#endif
+}
+
+void serial_puts (const char *s)
+{
+ while (*s) {
+ serial_putc (*s++);
+ }
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+void kgdb_serial_init (void)
+{
+}
+
+void putDebugChar (int c)
+{
+ serial_putc (c);
+}
+
+void putDebugStr (const char *str)
+{
+ serial_puts (str);
+}
+
+int getDebugChar (void)
+{
+ return serial_getc ();
+}
+
+void kgdb_interruptible (int yes)
+{
+ return;
+}
+#endif /* CFG_CMD_KGDB */
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ board/amirix/ap1000/init.o (.text)
+ cpu/ppc4xx/kgdb.o (.text)
+ cpu/ppc4xx/traps.o (.text)
+ cpu/ppc4xx/interrupts.o (.text)
+ cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/cpu_init.o (.text)
+ cpu/ppc4xx/speed.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+
+/* . = env_offset;*/
+/* common/environment.o(.text)*/
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+#
+# (C) Copyright 2002
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := armadillo.o flash.o
+SOBJS := lowlevel_init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2005 Rowel Atienza <rowel@diwalabs.com>
+ * Armadillo board HT1070
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <clps7111.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ /* Activate LED flasher */
+ IO_LEDFLSH = 0x40;
+
+ /* arch number MACH_TYPE_ARMADILLO - not official*/
+ gd->bd->bi_arch_number = 83;
+
+ /* location of boot parameters */
+ gd->bd->bi_boot_params = 0xc0000100;
+
+ return 0;
+}
+
+int dram_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return (0);
+}
--- /dev/null
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#address where u-boot will be relocated
+TEXT_BASE = 0xc0f80000
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2005 Rowel Atienza <rowel@diwalabs.com>
+ * Flash driver for armadillo board HT1070
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#define FLASH_BANK_SIZE 0x400000
+
+/*value used by hermit is 0x200*/
+/*document says sector size is either 64k in low mem reg and 8k in high mem reg*/
+#define MAIN_SECT_SIZE 0x10000
+
+#define UNALIGNED_MASK (3)
+#define FL_WORD(addr) (*(volatile unsigned short*)(addr))
+#define FLASH_TIMEOUT 20000000
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init (void)
+{
+ int i, j;
+ ulong size = 0;
+
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+ ulong flashbase = 0;
+
+ flash_info[i].flash_id = (FUJ_MANUFACT & FLASH_VENDMASK);
+ /*(INTEL_ID_28F128J3 & FLASH_TYPEMASK); */
+ flash_info[i].size = FLASH_BANK_SIZE;
+ flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+ memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+ if (i == 0)
+ flashbase = PHYS_FLASH_1;
+ else
+ panic ("configured too many flash banks!\n");
+ for (j = 0; j < flash_info[i].sector_count; j++) {
+ flash_info[i].start[j] =
+ flashbase + j * MAIN_SECT_SIZE;
+ }
+ size += flash_info[i].size;
+ }
+
+ /* Protect monitor and environment sectors
+ */
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_FLASH_BASE,
+ CFG_FLASH_BASE + monitor_flash_len - 1,
+ &flash_info[0]);
+
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+ return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+ int i;
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case (FUJ_MANUFACT & FLASH_VENDMASK):
+ printf ("Fujitsu: ");
+ break;
+ default:
+ printf ("Unknown Vendor ");
+ break;
+ }
+/*
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
+ printf ("28F128J3 (128Mbit)\n");
+ break;
+ default:
+ printf ("Unknown Chip Type\n");
+ goto Done;
+ break;
+ }
+*/
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; i++) {
+ if ((i % 5) == 0) {
+ printf ("\n ");
+ }
+ printf (" %08lX%s", info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+ }
+ printf ("\n");
+
+/*
+Done: ;
+*/
+}
+
+/*
+ * * Loop until both write state machines complete.
+ * */
+static unsigned short flash_status_wait (unsigned long addr,
+ unsigned short value)
+{
+ unsigned short status;
+ long timeout = FLASH_TIMEOUT;
+
+ while (((status = (FL_WORD (addr))) != value) && timeout > 0) {
+ timeout--;
+ }
+ return status;
+}
+
+/*
+ * Loop until the Write State machine is ready, then do a full error
+ * check. Clear status and leave the flash in Read Array mode; return
+ * 0 for no error, -1 for error.
+ */
+static int flash_status_full_check (unsigned long addr, unsigned short value1,
+ unsigned short value2)
+{
+ unsigned short status1, status2;
+
+ status1 = flash_status_wait (addr, value1);
+ status2 = flash_status_wait (addr + 2, value2);
+ return (status1 != value1 || status2 != value2) ? -1 : 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+ int flag, prot, sect;
+ int rc = ERR_OK;
+ unsigned long base;
+ unsigned long addr;
+
+ if ((info->flash_id & FLASH_VENDMASK) !=
+ (FUJ_MANUFACT & FLASH_VENDMASK)) {
+ return ERR_UNKNOWN_FLASH_VENDOR;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+ if (prot)
+ return ERR_PROTECTED;
+
+ /*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+ flag = disable_interrupts ();
+
+ printf ("Erasing %d sectors starting at sector %2d.\n"
+ "This make take some time ... ",
+ s_last - s_first, sect);
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+ /* ARM simple, non interrupt dependent timer */
+ reset_timer_masked ();
+
+ if (info->protect[sect] == 0) { /* not protected */
+
+ addr = sect * MAIN_SECT_SIZE;
+ addr &= ~(unsigned long) UNALIGNED_MASK; /* word align */
+ base = addr & 0xF0000000;
+
+ FL_WORD (base + (0x555 << 1)) = 0xAA;
+ FL_WORD (base + (0x2AA << 1)) = 0x55;
+ FL_WORD (base + (0x555 << 1)) = 0x80;
+ FL_WORD (base + (0x555 << 1)) = 0xAA;
+ FL_WORD (base + (0x2AA << 1)) = 0x55;
+ FL_WORD (addr) = 0x30;
+ if (flash_status_full_check (addr, 0xFFFF, 0xFFFF))
+ return ERR_PROTECTED;
+ }
+ }
+ printf ("\nDone.\n");
+ if (ctrlc ())
+ printf ("User Interrupt!\n");
+
+ /* allow flash to settle - wait 10 ms */
+ udelay_masked (10000);
+
+ if (flag)
+ enable_interrupts ();
+
+ return rc;
+}
+
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+static int write_word (flash_info_t * info, ulong dest, ushort data)
+{
+ int flag;
+ unsigned long base;
+
+ /* Check if Flash is (sufficiently) erased
+ */
+ if ((FL_WORD (dest) & data) != data)
+ return ERR_NOT_ERASED;
+
+ /*if(dest & UNALIGNED_MASK) return ERR_ALIGN; */
+
+ /*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+ flag = disable_interrupts ();
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked ();
+
+ base = dest & 0xF0000000;
+ FL_WORD (base + (0x555 << 1)) = 0xAA;
+ FL_WORD (base + (0x2AA << 1)) = 0x55;
+ FL_WORD (base + (0x555 << 1)) = 0xA0;
+ FL_WORD (dest) = data;
+ /*printf("writing 0x%p = 0x%x\n",dest,data); */
+ if (flash_status_wait (dest, data) != data)
+ return ERR_PROG_ERROR;
+
+ if (flag)
+ enable_interrupts ();
+
+ return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong cp, wp;
+ ushort data;
+ int l;
+ int i, rc;
+
+ wp = (addr & ~1); /* get lower word aligned address */
+ printf ("Writing %d short data to 0x%p from 0x%p.\n ", cnt, wp, src);
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i = 0, cp = wp; i < l; ++i, ++cp) {
+ data = (data >> 8) | (*(uchar *) cp << 8);
+ }
+ for (; i < 2 && cnt > 0; ++i) {
+ data = (data >> 8) | (*src++ << 8);
+ --cnt;
+ ++cp;
+ }
+ for (; cnt == 0 && i < 2; ++i, ++cp) {
+ data = (data >> 8) | (*(uchar *) cp << 8);
+ }
+
+ if ((rc = write_word (info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 2;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 2) {
+ data = *((vu_short *) src);
+ if ((rc = write_word (info, wp, data)) != 0) {
+ return (rc);
+ }
+ src += 2;
+ wp += 2;
+ cnt -= 2;
+ }
+
+ if (cnt == 0) {
+ printf ("\nDone.\n");
+ return ERR_OK;
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
+ data = (data >> 8) | (*src++ << 8);
+ --cnt;
+ }
+ for (; i < 2; ++i, ++cp) {
+ data = (data >> 8) | (*(uchar *) cp << 8);
+ }
+
+ return write_word (info, wp, data);
+}
--- /dev/null
+/*
+ * Initialization stuff - taken from hermit
+ * (C) Copyright 2005 Rowel Atienza <rowel@diwalabs.com>
+ * Armadillo board HT1070
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+/* setting up the memory */
+#define SRAM_START 0x60000000
+#define SRAM_SIZE 0x0000c000
+
+.globl lowlevel_init
+lowlevel_init:
+ mov r0, #0x70 /* 32-bit code + data, MMU mandatory */
+ mcr p15, 0, r0, c1, c0, 0 /* MMU init */
+
+ mov r0, #0
+ mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
+ mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
+
+ mov r0, #0x80000000 /* I/O base */
+
+ mov r1, #0x6 /* CLKCTL_73 in SYSCON3 */
+ add r2, r0, #0x2200 /* address of SYSCON3 in r2 */
+ str r1, [r2] /* set clock speed to 73.728 MHz */
+
+ mov r1, #0x81 /* 64KHz DRAM refresh period */
+ str r1, [r0, #0x200] /* set DRFPR */
+
+ mov r1, #0x500 /* permanent enable, 16bits wide */
+ add r1, r1, #0x42 /* 128Mbit, CAS lat = 2 SDRAM */
+ add r2, r0, #0x2300 /* load address in r2 */
+ str r1, [r2]
+
+ mov r1, #0x100 /* SDRAM refresh rate */
+ add r2, r0, #0x2340 /* load address in r2 */
+ str r1, [r2]
+
+ mov sp, #SRAM_START /* init stack pointer */
+ add sp, sp, #SRAM_SIZE
+
+ /* everything is fine now */
+ mov pc, lr
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm720t/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
LIB = lib$(BOARD).a
-OBJS := at91rm9200dk.o at45.o dm9161.o flash.o
+OBJS := at91rm9200dk.o at45.o flash.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
#include <common.h>
#include <asm/arch/AT91RM9200.h>
+#include <at91rm9200_net.h>
+#include <dm9161.h>
/* ------------------------------------------------------------------------- */
/*
/* Correct IRDA resistor problem */
/* Set PA23_TXD in Output */
- (AT91PS_PIO) AT91C_BASE_PIOA->PIO_OER = AT91C_PA23_TXD2;
+ ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_OER = AT91C_PA23_TXD2;
/* memory and cpu-speed are setup before relocation */
/* so we do _nothing_ here */
return 0;
}
+#ifdef CONFIG_DRIVER_ETHER
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+
+/*
+ * Name:
+ * at91rm9200_GetPhyInterface
+ * Description:
+ * Initialise the interface functions to the PHY
+ * Arguments:
+ * None
+ * Return value:
+ * None
+ */
+void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
+{
+ p_phyops->Init = dm9161_InitPhy;
+ p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
+ p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
+ p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
+}
+
+#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
+#endif /* CONFIG_DRIVER_ETHER */
+
/*
* Disk On Chip (NAND) Millenium initialization.
* The NAND lives in the CS2* space
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
int i;
uchar *boottype;
uchar *bootletter;
- uchar *fmt;
+ char *fmt;
uchar botbootletter[] = "B";
uchar topbootletter[] = "T";
uchar botboottype[] = "bottom boot sector";
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o
+
+$(LIB): .depend $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend: Makefile $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+This port of U-Boot is tuned to run on a range of Barco Control Rooms
+Streaming Video Solutions, including:
+
+ - Streaming Video Card (SVC)
+ - Sample Compress Network (SCN)
+
+For more information, see http://www.barcocontrolrooms.com/
+
+Code and configuration are originally based on the Sandpoint board
+
+Marc Leeman <marc.leeman@barco.com>
--- /dev/null
+/********************************************************************
+ *
+ * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms
+ *
+ * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/board/barco/barco.c,v $
+ * $Revision: 1.4 $
+ * $Author: mleeman $
+ * $Date: 2005/03/02 16:40:20 $
+ *
+ * Last ChangeLog Entry
+ * $Log: barco.c,v $
+ * Revision 1.4 2005/03/02 16:40:20 mleeman
+ * remove empty labels (3.4 complains)
+ *
+ * Revision 1.3 2005/02/21 12:48:58 mleeman
+ * update of copyright years (feedback wd)
+ *
+ * Revision 1.2 2005/02/21 10:10:53 mleeman
+ * - split up switch statement to a function call (Linux kernel coding guidelines)
+ * ( feedback wd)
+ *
+ * Revision 1.1 2005/02/14 09:31:07 mleeman
+ * renaming of files
+ *
+ * Revision 1.1 2005/02/14 09:23:46 mleeman
+ * - moved 'barcohydra' directory to a more generic barco; since we will be
+ * supporting and adding multiple boards
+ *
+ * Revision 1.3 2005/02/10 13:57:32 mleeman
+ * fixed flash corruption: I should exit from the moment I find the correct value
+ *
+ * Revision 1.2 2005/02/09 12:56:23 mleeman
+ * add generic header to track changes in sources
+ *
+ *
+ *******************************************************************/
+
+/*
+ * (C) Copyright 2004
+ * Marc Leeman <marc.leeman@barco.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <pci.h>
+#include <malloc.h>
+#include <command.h>
+
+#include "config.h"
+#include "barco_svc.h"
+
+#define TRY_WORKING (3)
+#define BOOT_DEFAULT (2)
+#define BOOT_WORKING (1)
+
+int checkboard (void)
+{
+ /*TODO: Check processor type */
+
+ puts ( "Board: Streaming Video Card for Hydra systems "
+#ifdef CONFIG_MPC8240
+ "8240"
+#endif
+#ifdef CONFIG_MPC8245
+ "8245"
+#endif
+ " Unity ##Test not implemented yet##\n");
+ return 0;
+}
+
+long int initdram (int board_type)
+{
+ long size;
+ long new_bank0_end;
+ long mear1;
+ long emear1;
+
+ size = get_ram_size (CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+
+ new_bank0_end = size - 1;
+ mear1 = mpc824x_mpc107_getreg (MEAR1);
+ emear1 = mpc824x_mpc107_getreg (EMEAR1);
+ mear1 = (mear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+ emear1 = (emear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+ mpc824x_mpc107_setreg (MEAR1, mear1);
+ mpc824x_mpc107_setreg (EMEAR1, emear1);
+
+ return (size);
+}
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_barcohydra_config_table[] = {
+ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
+ pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } },
+ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
+ pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
+ PCI_ENET1_MEMADDR,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } },
+ { }
+};
+#endif
+
+struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+ config_table: pci_barcohydra_config_table,
+#endif
+};
+
+void pci_init_board (void)
+{
+ pci_mpc824x_init (&hose);
+}
+
+int write_flash (char *addr, char value)
+{
+ char *adr = (char *)0xFF800000;
+ int cnt = 0;
+ char status,oldstatus;
+
+ *(adr+0x55) = 0xAA; udelay (1);
+ *(adr+0xAA) = 0x55; udelay (1);
+ *(adr+0x55) = 0xA0; udelay (1);
+ *addr = value;
+
+ status = *addr;
+ do {
+ oldstatus = status;
+ status = *addr;
+
+ if ((oldstatus & 0x40) == (status & 0x40)) {
+ return 4;
+ }
+ cnt++;
+ if (cnt > 10000) {
+ return 2;
+ }
+ } while ( (status & 0x20) == 0 );
+
+ oldstatus = *addr;
+ status = *addr;
+
+ if ((oldstatus & 0x40) == (status & 0x40)) {
+ return 0;
+ } else {
+ *(adr+0x55) = 0xF0;
+ return 1;
+ }
+}
+
+unsigned update_flash (unsigned char *buf)
+{
+ switch ((*buf) & 0x3) {
+ case TRY_WORKING:
+ printf ("found 3 and converted it to 2\n");
+ write_flash ((char *)buf, (*buf) & 0xFE);
+ *((unsigned char *)0xFF800000) = 0xF0;
+ udelay (100);
+ printf ("buf [%#010x] %#010x\n", buf, (*buf));
+ /* XXX - fall through??? */
+ case BOOT_WORKING :
+ return BOOT_WORKING;
+ }
+ return BOOT_DEFAULT;
+}
+
+unsigned scan_flash (void)
+{
+ char section[] = "kernel";
+ int cfgFileLen = (CFG_FLASH_ERASE_SECTOR_LENGTH >> 1);
+ int sectionPtr = 0;
+ int foundItem = 0; /* 0: None, 1: section found, 2: "=" found */
+ int bufPtr;
+ unsigned char *buf;
+
+ buf = (unsigned char*)(CFG_FLASH_RANGE_BASE + CFG_FLASH_RANGE_SIZE \
+ - CFG_FLASH_ERASE_SECTOR_LENGTH);
+ for (bufPtr = 0; bufPtr < cfgFileLen; ++bufPtr) {
+ if ((buf[bufPtr]==0xFF) && (*(int*)(buf+bufPtr)==0xFFFFFFFF)) {
+ return BOOT_DEFAULT;
+ }
+ /* This is the scanning loop, we try to find a particular
+ * quoted value
+ */
+ switch (foundItem) {
+ case 0:
+ if ((section[sectionPtr] == 0)) {
+ ++foundItem;
+ } else if (buf[bufPtr] == section[sectionPtr]) {
+ ++sectionPtr;
+ } else {
+ sectionPtr = 0;
+ }
+ break;
+ case 1:
+ ++foundItem;
+ break;
+ case 2:
+ ++foundItem;
+ break;
+ case 3:
+ default:
+ return update_flash (&buf[bufPtr - 1]);
+ }
+ }
+
+ printf ("Failed to read %s\n",section);
+ return BOOT_DEFAULT;
+}
+
+TSBootInfo* find_boot_info (void)
+{
+ unsigned bootimage = scan_flash ();
+ TSBootInfo* info = (TSBootInfo*)malloc (sizeof(TSBootInfo));
+
+ switch (bootimage) {
+ case TRY_WORKING:
+ info->address = CFG_WORKING_KERNEL_ADDRESS;
+ break;
+ case BOOT_WORKING :
+ info->address = CFG_WORKING_KERNEL_ADDRESS;
+ break;
+ case BOOT_DEFAULT:
+ default:
+ info->address= CFG_DEFAULT_KERNEL_ADDRESS;
+
+ }
+ info->size = *((unsigned int *)(info->address ));
+
+ return info;
+}
+
+void barcobcd_boot (void)
+{
+ TSBootInfo* start;
+ char *bootm_args[2];
+ char *buf;
+ int cnt;
+ extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
+
+ buf = (char *)(0x00800000);
+ /* make certain there are enough chars to print the command line here!
+ */
+ bootm_args[0] = (char *)malloc (16*sizeof(char));
+ bootm_args[1] = (char *)malloc (16*sizeof(char));
+
+ start = find_boot_info ();
+
+ printf ("Booting kernel at address %#10x with size %#10x\n",
+ start->address, start->size);
+
+ /* give length of the kernel image to bootm */
+ sprintf (bootm_args[0],"%x",start->size);
+ /* give address of the kernel image to bootm */
+ sprintf (bootm_args[1],"%x",buf);
+
+ printf ("flash address: %#10x\n",start->address+8);
+ printf ("buf address: %#10x\n",buf);
+
+ /* aha, we reserve 8 bytes here... */
+ for (cnt = 0; cnt < start->size ; cnt++) {
+ buf[cnt] = ((char *)start->address)[cnt+8];
+ }
+
+ /* initialise RAM memory */
+ *((unsigned int *)0xFEC00000) = 0x00141A98;
+ do_bootm (NULL,0,2,bootm_args);
+}
+
+int barcobcd_boot_image (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+#if 0
+ if (argc > 1) {
+ printf ("Usage:\n (%d) %s\n", argc, cmdtp->usage);
+ return 1;
+ }
+#endif
+ barcobcd_boot ();
+
+ return 0;
+}
+
+/* Currently, boot_working and boot_default are the same command. This is
+ * left in here to see what we'll do in the future */
+
+U_BOOT_CMD (
+ try_working, 1, 1, barcobcd_boot_image,
+ " try_working - check flash value and boot the appropriate image\n",
+ "\n"
+ );
+
+U_BOOT_CMD (
+ boot_working, 1, 1, barcobcd_boot_image,
+ " boot_working - check flash value and boot the appropriate image\n",
+ "\n"
+ );
+
+U_BOOT_CMD (
+ boot_default, 1, 1, barcobcd_boot_image,
+ " boot_default - check flash value and boot the appropriate image\n",
+ "\n"
+ );
+/*
+ * We are not using serial communication, so just provide empty functions
+ */
+int serial_init (void)
+{
+ return 0;
+}
+void serial_setbrg (void)
+{
+ return;
+}
+void serial_putc (const char c)
+{
+ return;
+}
+void serial_puts (const char *c)
+{
+ return;
+}
+void serial_addr (unsigned int i)
+{
+ return;
+}
+int serial_getc (void)
+{
+ return 0;
+}
+int serial_tstc (void)
+{
+ return 0;
+}
+
+unsigned long post_word_load (void)
+{
+ return 0l;
+}
+void post_word_store (unsigned long val)
+{
+ return;
+}
--- /dev/null
+/********************************************************************
+ *
+ * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms
+ *
+ * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/board/barco/barco_svc.h,v $
+ * $Revision: 1.2 $
+ * $Author: mleeman $
+ * $Date: 2005/02/21 12:48:58 $
+ *
+ * Last ChangeLog Entry
+ * $Log: barco_svc.h,v $
+ * Revision 1.2 2005/02/21 12:48:58 mleeman
+ * update of copyright years (feedback wd)
+ *
+ * Revision 1.1 2005/02/14 09:31:07 mleeman
+ * renaming of files
+ *
+ * Revision 1.1 2005/02/14 09:23:46 mleeman
+ * - moved 'barcohydra' directory to a more generic barco; since we will be
+ * supporting and adding multiple boards
+ *
+ * Revision 1.1 2005/02/08 15:40:19 mleeman
+ * modified and added platform files
+ *
+ * Revision 1.2 2005/01/25 08:05:04 mleeman
+ * more cleanup of the code
+ *
+ * Revision 1.1 2004/07/20 08:49:55 mleeman
+ * Working version of the default and nfs kernel booting.
+ *
+ *
+ *******************************************************************/
+
+#ifndef _LOCAL_BARCOHYDRA_H_
+#define _LOCAL_BARCOHYDRA_H_
+
+#include <flash.h>
+#include <asm/io.h>
+
+/* Defines for the barcohydra board */
+#ifndef CFG_FLASH_ERASE_SECTOR_LENGTH
+#define CFG_FLASH_ERASE_SECTOR_LENGTH (0x10000)
+#endif
+
+#ifndef CFG_DEFAULT_KERNEL_ADDRESS
+#define CFG_DEFAULT_KERNEL_ADDRESS (CFG_FLASH_BASE + 0x30000)
+#endif
+
+#ifndef CFG_WORKING_KERNEL_ADDRESS
+#define CFG_WORKING_KERNEL_ADDRESS (0xFFE00000)
+#endif
+
+
+typedef struct SBootInfo {
+ unsigned int address;
+ unsigned int size;
+ unsigned char state;
+}TSBootInfo;
+
+/* barcohydra.c */
+int checkboard(void);
+long int initdram(int board_type);
+void pci_init_board(void);
+void check_flash(void);
+int write_flash(char *addr, char value);
+TSBootInfo* find_boot_info(void);
+void final_boot(void);
+#endif
-# Copyright 2004 Freescale Semiconductor.
-# Modified by Xianghua Xiao, X.Xiao@motorola.com
-# (C) Copyright 2002,Motorola Inc.
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
#
-# tqm8540 board
-# default CCARBAR is at 0xff700000
-# assume U-Boot is less than 256k
+# Barco Hydra/SCN boards
#
-TEXT_BASE = 0xfffc0000
+
+TEXT_BASE = 0xFFF00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Thomas Koeller, tkoeller@gmx.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__ 1
+#endif
+
+#include <config.h>
+#include <asm/processor.h>
+#include <mpc824x.h>
+#include <ppc_asm.tmpl>
+
+#if defined(USE_DINK32)
+ /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */
+ #define MCCR1VAL ((CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO)
+#else
+ #define MCCR1VAL (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT)
+#endif
+
+ .text
+
+ /* Values to program into memory controller registers */
+tbl: .long MCCR1, MCCR1VAL
+ .long MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT
+ .long MCCR3
+ .long (((CFG_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \
+ (CFG_REFREC << MCCR3_REFREC_SHIFT) | \
+ (CFG_RDLAT << MCCR3_RDLAT_SHIFT)
+ .long MCCR4
+ .long (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \
+ (CFG_REGISTERD_TYPE_BUFFER << 20) | \
+ (((CFG_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \
+ ((CFG_SDMODE_CAS_LAT << 4) | (CFG_SDMODE_WRAP << 3) | \
+ (CFG_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \
+ (CFG_ACTTORW << MCCR4_ACTTORW_SHIFT) | \
+ ((CFG_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT )
+ .long MSAR1
+ .long (((CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
+ (((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
+ (((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+ (((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+ .long EMSAR1
+ .long (((CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
+ (((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
+ (((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+ (((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+ .long MSAR2
+ .long (((CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
+ (((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
+ (((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+ (((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+ .long EMSAR2
+ .long (((CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
+ (((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
+ (((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+ (((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+ .long MEAR1
+ .long (((CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
+ (((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
+ (((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+ (((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+ .long EMEAR1
+ .long (((CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
+ (((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
+ (((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+ (((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+ .long MEAR2
+ .long (((CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
+ (((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
+ (((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+ (((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+ .long EMEAR2
+ .long (((CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
+ (((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
+ (((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+ (((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+ .long 0
+
+
+ /*
+ * Early CPU initialization. Set up memory controller, so we can access any RAM at all. This
+ * must be done in assembly, since we have no stack at this point.
+ */
+ .global early_init_f
+early_init_f:
+ mflr r10
+
+ /* basic memory controller configuration */
+ lis r3, CONFIG_ADDR_HIGH
+ lis r4, CONFIG_DATA_HIGH
+ bl lab
+lab: mflr r5
+ lwzu r0, tbl - lab(r5)
+loop: lwz r1, 4(r5)
+ stwbrx r0, 0, r3
+ eieio
+ stwbrx r1, 0, r4
+ eieio
+ lwzu r0, 8(r5)
+ cmpli cr0, 0, r0, 0
+ bne cr0, loop
+
+ /* set bank enable bits */
+ lis r0, MBER@h
+ ori r0, 0, MBER@l
+ li r1, CFG_BANK_ENABLE
+ stwbrx r0, 0, r3
+ eieio
+ stb r1, 0(r4)
+ eieio
+
+ /* delay loop */
+ lis r0, 0x0003
+ mtctr r0
+delay: bdnz delay
+
+ /* enable memory controller */
+ lis r0, MCCR1@h
+ ori r0, 0, MCCR1@l
+ stwbrx r0, 0, r3
+ eieio
+ lwbrx r0, 0, r4
+ oris r0, 0, MCCR1_MEMGO@h
+ stwbrx r0, 0, r4
+ eieio
+
+ /* set up stack pointer */
+ lis r1, CFG_INIT_SP_OFFSET@h
+ ori r1, r1, CFG_INIT_SP_OFFSET@l
+
+ mtlr r10
+ blr
--- /dev/null
+/********************************************************************
+ *
+ * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms
+ *
+ * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/board/barco/flash.c,v $
+ * $Revision: 1.3 $
+ * $Author: mleeman $
+ * $Date: 2005/02/21 12:48:58 $
+ *
+ * Last ChangeLog Entry
+ * $Log: flash.c,v $
+ * Revision 1.3 2005/02/21 12:48:58 mleeman
+ * update of copyright years (feedback wd)
+ *
+ * Revision 1.2 2005/02/21 11:04:04 mleeman
+ * remove dead code and Coding style (feedback wd)
+ *
+ * Revision 1.1 2005/02/14 09:23:46 mleeman
+ * - moved 'barcohydra' directory to a more generic barco; since we will be
+ * supporting and adding multiple boards
+ *
+ * Revision 1.2 2005/02/09 12:56:23 mleeman
+ * add generic header to track changes in sources
+ *
+ *
+ *******************************************************************/
+
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+#include <flash.h>
+
+#define ROM_CS0_START 0xFF800000
+#define ROM_CS1_START 0xFF000000
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef CFG_ENV_ADDR
+# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef CFG_ENV_SIZE
+# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
+# endif
+# ifndef CFG_ENV_SECT_SIZE
+# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*flash command address offsets*/
+
+#define ADDR0 (0xAAA)
+#define ADDR1 (0x555)
+#define ADDR3 (0x001)
+
+#define FLASH_WORD_SIZE unsigned char
+
+/*-----------------------------------------------------------------------
+ */
+
+static unsigned long flash_id(unsigned char mfct, unsigned char chip) __attribute__ ((const));
+
+typedef struct{
+ FLASH_WORD_SIZE extval;
+ unsigned short intval;
+} map_entry;
+
+static unsigned long flash_id(unsigned char mfct, unsigned char chip)
+{
+ static const map_entry mfct_map[] = {
+ {(FLASH_WORD_SIZE) AMD_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)},
+ {(FLASH_WORD_SIZE) FUJ_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)},
+ {(FLASH_WORD_SIZE) STM_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)},
+ {(FLASH_WORD_SIZE) MT_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)},
+ {(FLASH_WORD_SIZE) INTEL_MANUFACT,(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)},
+ {(FLASH_WORD_SIZE) INTEL_ALT_MANU,(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}
+ };
+
+ static const map_entry chip_map[] = {
+ {AMD_ID_F040B, FLASH_AM040},
+ {AMD_ID_F033C, FLASH_AM033},
+ {AMD_ID_F065D, FLASH_AM065},
+ {ATM_ID_LV040, FLASH_AT040},
+ {(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB}
+ };
+
+ const map_entry *p;
+ unsigned long result = FLASH_UNKNOWN;
+
+ /* find chip id */
+ for(p = &chip_map[0]; p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++){
+ if(p->extval == chip){
+ result = FLASH_VENDMASK | p->intval;
+ break;
+ }
+ }
+
+ /* find vendor id */
+ for(p = &mfct_map[0]; p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++){
+ if(p->extval == mfct){
+ result &= ~FLASH_VENDMASK;
+ result |= (unsigned long) p->intval << 16;
+ break;
+ }
+ }
+
+ return result;
+}
+
+
+unsigned long flash_init(void)
+{
+ unsigned long i;
+ unsigned char j;
+ static const ulong flash_banks[] = CFG_FLASH_BANKS;
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++){
+ flash_info_t * const pflinfo = &flash_info[i];
+ pflinfo->flash_id = FLASH_UNKNOWN;
+ pflinfo->size = 0;
+ pflinfo->sector_count = 0;
+ }
+
+ /* Enable writes to Hydra/Argus flash */
+ {
+ register unsigned int temp;
+ CONFIG_READ_WORD(PICR1,temp);
+ temp |= PICR1_FLASH_WR_EN;
+ CONFIG_WRITE_WORD(PICR1,temp);
+ }
+
+ for(i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++){
+ flash_info_t * const pflinfo = &flash_info[i];
+ const unsigned long base_address = flash_banks[i];
+ volatile FLASH_WORD_SIZE * const flash = (FLASH_WORD_SIZE *) base_address;
+
+ /* write autoselect sequence */
+ flash[0x5555] = 0xaa;
+ flash[0x2aaa] = 0x55;
+ flash[0x5555] = 0x90;
+ __asm__ __volatile__("sync");
+
+ pflinfo->flash_id = flash_id(flash[0x0], flash[0x1]);
+
+ switch(pflinfo->flash_id & FLASH_TYPEMASK){
+ case FLASH_AM033:
+ pflinfo->size = 0x00200000;
+ pflinfo->sector_count = 64;
+ for(j = 0; j < 64; j++){
+ pflinfo->start[j] = base_address + 0x00010000 * j;
+ pflinfo->protect[j] = flash[(j << 16) | 0x2];
+ }
+ break;
+ case FLASH_AM065:
+ pflinfo->size = 0x00800000;
+ pflinfo->sector_count =128;
+ for(j = 0; j < 128; j++){
+ pflinfo->start[j] = base_address + 0x00010000 * j;
+ pflinfo->protect[j] = flash[(j << 16) | 0x2];
+ }
+ break;
+ case FLASH_AT040:
+ pflinfo->size = 0x00080000;
+ pflinfo->sector_count = 2;
+ pflinfo->start[0] = base_address ;
+ pflinfo->start[1] = base_address + 0x00004000;
+ pflinfo->protect[0] = ((flash[0x02] & 0X01)==0) ? 0X02 : 0X01;
+ pflinfo->protect[1] = 0X02;
+ break;
+ case FLASH_AM040:
+ pflinfo->size = 0x00080000;
+ pflinfo->sector_count = 8;
+ for(j = 0; j < 8; j++){
+ pflinfo->start[j] = base_address + 0x00010000 * j;
+ pflinfo->protect[j] = flash[(j << 16) | 0x2];
+ }
+ break;
+ case FLASH_STM800AB:
+ pflinfo->size = 0x00100000;
+ pflinfo->sector_count = 19;
+ pflinfo->start[0] = base_address;
+ pflinfo->start[1] = base_address + 0x4000;
+ pflinfo->start[2] = base_address + 0x6000;
+ pflinfo->start[3] = base_address + 0x8000;
+ for(j = 1; j < 16; j++){
+ pflinfo->start[j+3] = base_address + 0x00010000 * j;
+ }
+ break;
+ }
+ /* Protect monitor and environment sectors */
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + monitor_flash_len - 1,
+ &flash_info[0]);
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+ &flash_info[0]);
+#endif
+
+ /* reset device to read mode */
+ flash[0x0000] = 0xf0;
+ __asm__ __volatile__("sync");
+ }
+
+ return flash_info[0].size + flash_info[1].size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t *info)
+{
+ static const char unk[] = "Unknown";
+ const char *mfct = unk, *type = unk;
+ unsigned int i;
+
+ if(info->flash_id != FLASH_UNKNOWN){
+ switch(info->flash_id & FLASH_VENDMASK){
+ case FLASH_MAN_ATM:
+ mfct = "Atmel";
+ break;
+ case FLASH_MAN_AMD:
+ mfct = "AMD";
+ break;
+ case FLASH_MAN_FUJ:
+ mfct = "FUJITSU";
+ break;
+ case FLASH_MAN_STM:
+ mfct = "STM";
+ break;
+ case FLASH_MAN_SST:
+ mfct = "SST";
+ break;
+ case FLASH_MAN_BM:
+ mfct = "Bright Microelectonics";
+ break;
+ case FLASH_MAN_INTEL:
+ mfct = "Intel";
+ break;
+ }
+
+ switch(info->flash_id & FLASH_TYPEMASK){
+ case FLASH_AT040:
+ type = "AT49LV040 (512K * 8, uniform sector size)";
+ break;
+ case FLASH_AM033:
+ type = "AM29F033C (4 Mbit * 8, uniform sector size)";
+ break;
+ case FLASH_AM040:
+ type = "AM29F040B (512K * 8, uniform sector size)";
+ break;
+ case FLASH_AM065:
+ type = "AM29F0465D ( 8 MBit * 8, uniform sector size) or part of AM29F652D( 16 MB)";
+ break;
+ case FLASH_AM400B:
+ type = "AM29LV400B (4 Mbit, bottom boot sect)";
+ break;
+ case FLASH_AM400T:
+ type = "AM29LV400T (4 Mbit, top boot sector)";
+ break;
+ case FLASH_AM800B:
+ type = "AM29LV800B (8 Mbit, bottom boot sect)";
+ break;
+ case FLASH_AM800T:
+ type = "AM29LV800T (8 Mbit, top boot sector)";
+ break;
+ case FLASH_AM160T:
+ type = "AM29LV160T (16 Mbit, top boot sector)";
+ break;
+ case FLASH_AM320B:
+ type = "AM29LV320B (32 Mbit, bottom boot sect)";
+ break;
+ case FLASH_AM320T:
+ type = "AM29LV320T (32 Mbit, top boot sector)";
+ break;
+ case FLASH_STM800AB:
+ type = "M29W800AB (8 Mbit, bottom boot sect)";
+ break;
+ case FLASH_SST800A:
+ type = "SST39LF/VF800 (8 Mbit, uniform sector size)";
+ break;
+ case FLASH_SST160A:
+ type = "SST39LF/VF160 (16 Mbit, uniform sector size)";
+ break;
+ }
+ }
+
+ printf(
+ "\n Brand: %s Type: %s\n"
+ " Size: %lu KB in %d Sectors\n",
+ mfct,
+ type,
+ info->size >> 10,
+ info->sector_count
+ );
+
+ printf (" Sector Start Addresses:");
+
+ for (i = 0; i < info->sector_count; i++){
+ unsigned long size;
+ unsigned int erased;
+ unsigned long * flash = (unsigned long *) info->start[i];
+
+ /*
+ * Check if whole sector is erased
+ */
+ size =
+ (i != (info->sector_count - 1)) ?
+ (info->start[i + 1] - info->start[i]) >> 2 :
+ (info->start[0] + info->size - info->start[i]) >> 2;
+
+ for(
+ flash = (unsigned long *) info->start[i], erased = 1;
+ (flash != (unsigned long *) info->start[i] + size) && erased;
+ flash++
+ ){
+ erased = *flash == ~0x0UL;
+ }
+
+ printf(
+ "%s %08lX %s %s",
+ (i % 5) ? "" : "\n ",
+ info->start[i],
+ erased ? "E" : " ",
+ info->protect[i] ? "RO" : " "
+ );
+ }
+
+ puts("\n");
+ return;
+}
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+ volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
+ int flag, prot, sect, l_sect;
+ ulong start, now, last;
+ unsigned char sh8b;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if ((info->flash_id == FLASH_UNKNOWN) ||
+ (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) {
+ printf ("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ l_sect = -1;
+
+ /* Check the ROM CS */
+ if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START)){
+ sh8b = 3;
+ }
+ else{
+ sh8b = 0;
+ }
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
+ addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080;
+ addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr = (FLASH_WORD_SIZE *)(info->start[0] + (
+ (info->start[sect] - info->start[0]) << sh8b));
+ if (info->flash_id & FLASH_MAN_SST){
+ addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
+ addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080;
+ addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
+ addr[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */
+ udelay(30000); /* wait 30 ms */
+ }
+ else
+ addr[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
+ l_sect = sect;
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag){
+ enable_interrupts();
+ }
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ /*
+ * We wait for the last triggered sector
+ */
+ if (l_sect < 0){
+ goto DONE;
+ }
+
+ start = get_timer (0);
+ last = start;
+ addr = (FLASH_WORD_SIZE *)(info->start[0] + (
+ (info->start[l_sect] - info->start[0]) << sh8b));
+ while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ return 1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ serial_putc ('.');
+ last = now;
+ }
+ }
+
+DONE:
+ /* reset to read mode */
+ addr = (FLASH_WORD_SIZE *)info->start[0];
+ addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
+
+ printf (" done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+ for (; i<4 && cnt>0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i=0; i<4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+ volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)info->start[0];
+ volatile FLASH_WORD_SIZE *dest2;
+ volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
+ ulong start;
+ int flag;
+ int i;
+ unsigned char sh8b;
+
+ /* Check the ROM CS */
+ if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START)){
+ sh8b = 3;
+ }
+ else{
+ sh8b = 0;
+ }
+
+ dest2 = (FLASH_WORD_SIZE *)(((dest - info->start[0]) << sh8b) +
+ info->start[0]);
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*dest2 & (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++){
+ addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
+ addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00A000A0;
+
+ dest2[i << sh8b] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag){
+ enable_interrupts();
+ }
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ while ((dest2[i << sh8b] & (FLASH_WORD_SIZE)0x00800080) !=
+ (data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ }
+
+ return (0);
+}
+
+/*----------------------------------------------------------------------- */
--- /dev/null
+/********************************************************************
+ *
+ * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms
+ *
+ * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/board/barco/speed.h,v $
+ * $Revision: 1.2 $
+ * $Author: mleeman $
+ * $Date: 2005/02/21 12:48:58 $
+ *
+ * Last ChangeLog Entry
+ * $Log: speed.h,v $
+ * Revision 1.2 2005/02/21 12:48:58 mleeman
+ * update of copyright years (feedback wd)
+ *
+ * Revision 1.1 2005/02/14 09:23:46 mleeman
+ * - moved 'barcohydra' directory to a more generic barco; since we will be
+ * supporting and adding multiple boards
+ *
+ * Revision 1.2 2005/02/09 12:56:23 mleeman
+ * add generic header to track changes in sources
+ *
+ *
+ *******************************************************************/
+
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*-----------------------------------------------------------------------
+ * Timer value for timer 2, ICLK = 10
+ *
+ * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1))
+ * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
+ *
+ * SPEED_FCOUNT2 timer 2 counting frequency
+ * GCLK CPU clock
+ * SPEED_TMR2_PS prescaler
+ */
+#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */
+
+/*-----------------------------------------------------------------------
+ * Timer value for PIT
+ *
+ * PIT_TIME = SPEED_PITC / PITRTCLK
+ * PITRTCLK = 8192
+ */
+#define SPEED_PITC (82 << 16) /* start counting from 82 */
+
+/*
+ * The new value for PTA is calculated from
+ *
+ * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
+ *
+ * gclk CPU clock (not bus clock !)
+ * Trefresh Refresh cycle * 4 (four word bursts used)
+ * DFBRG For normal mode (no clock reduction) always 0
+ * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
+ * NCS Number of SDRAM banks (chip selects) on this UPM.
+ */
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc824x/start.o (.text)
+ lib_ppc/board.o (.text)
+ lib_ppc/ppcstring.o (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/environment.o (.text)
+
+ *(.text)
+
+ *(.fixup)
+ *(.got1)
+ . = ALIGN(16);
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+
+ _end = . ;
+ PROVIDE (end = .);
+}
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
int checkboard (void)
{
- unsigned char *s = getenv ("serial#");
+ unsigned char *s = (unsigned char *)getenv ("serial#");
puts ("Board: TTTech C2MON ");
* try 8 column mode
*/
size8 = dram_size (CFG_MAMR_8COL,
- (ulong *)SDRAM_BASE2_PRELIM,
+ SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
udelay (1000);
* try 9 column mode
*/
size9 = dram_size (CFG_MAMR_9COL,
- (ulong *) SDRAM_BASE2_PRELIM,
+ SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
LIB = lib$(BOARD).a
-OBJS := cmc_pu2.o at45.o dm9161.o flash.o
+OBJS := cmc_pu2.o at45.o flash.o load_sernum_ethaddr.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
#include <common.h>
#include <asm/mach-types.h>
#include <asm/arch/AT91RM9200.h>
+#include <at91rm9200_net.h>
+#include <dm9161.h>
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
-#define CMC_BASIC 1
+#define CMC_HP_BASIC 1
#define CMC_PU2 2
+#define CMC_BASIC 4
int hw_detect (void);
/*
* On CMC-PU2 board configure PB3-PB6 to input without pull ups to
* clear the duo LEDs (the external pull downs assure a proper
- * signal). On CMC-BASIC set PB3-PB6 to output and drive it
- * high, to configure current meassurement on AINx.
+ * signal). On CMC-BASIC and CMC-HP-BASIC set PB3-PB6 to output and
+ * drive it high, to configure current measurement on AINx.
*/
if (hw_detect() & CMC_PU2) {
piob->PIO_ODR = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
AT91C_PIO_PB5 | AT91C_PIO_PB6;
}
- else if (hw_detect() & CMC_BASIC) {
+ else if ((hw_detect() & CMC_BASIC) || (hw_detect() & CMC_HP_BASIC)) {
piob->PIO_SODR = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
AT91C_PIO_PB5 | AT91C_PIO_PB6;
piob->PIO_OER = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
puts ("Board: CMC-PU2 (Rittal GmbH)\n");
else if (hw_detect() & CMC_BASIC)
puts ("Board: CMC-BASIC (Rittal GmbH)\n");
+ else if (hw_detect() & CMC_HP_BASIC)
+ puts ("Board: CMC-HP-BASIC (Rittal GmbH)\n");
else
puts ("Board: unknown\n");
return 0;
pio->PIO_PPUDR = AT91C_PIO_PB12;
pio->PIO_PER = AT91C_PIO_PB12;
+ /* configure PB13 as input without pull up */
+ pio->PIO_ODR = AT91C_PIO_PB13;
+ pio->PIO_PPUDR = AT91C_PIO_PB13;
+ pio->PIO_PER = AT91C_PIO_PB13;
+
/* read board identification pin */
- return ((pio->PIO_PDSR & AT91C_PIO_PB12) ? CMC_PU2 : CMC_BASIC);
+ if (pio->PIO_PDSR & AT91C_PIO_PB12)
+ return ((pio->PIO_PDSR & AT91C_PIO_PB13)
+ ? CMC_PU2 : 0);
+ else
+ return ((pio->PIO_PDSR & AT91C_PIO_PB13)
+ ? CMC_HP_BASIC : CMC_BASIC);
}
+
+#ifdef CONFIG_DRIVER_ETHER
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+
+/*
+ * Name:
+ * at91rm9200_GetPhyInterface
+ * Description:
+ * Initialise the interface functions to the PHY
+ * Arguments:
+ * None
+ * Return value:
+ * None
+ */
+void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
+{
+ p_phyops->Init = dm9161_InitPhy;
+ p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
+ p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
+ p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
+}
+
+#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
+#endif /* CONFIG_DRIVER_ETHER */
--- /dev/null
+/*
+ * (C) Copyright 2000, 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* #define DEBUG */
+
+#include <common.h>
+
+#define I2C_CHIP 0x50 /* I2C bus address of onboard EEPROM */
+#define I2C_ALEN 1 /* length of EEPROM addresses in bytes */
+#define I2C_OFFSET 0x0 /* start address of manufacturere data block
+ * in EEPROM */
+
+/* 64 Byte manufacturer data block in EEPROM */
+struct manufacturer_data {
+ unsigned int serial_number; /* serial number (0...999999) */
+ unsigned short hardware; /* hardware version (e.g. V1.02) */
+ unsigned short manuf_date; /* manufacture date (e.g. 25/02) */
+ unsigned char name[20]; /* device name (in CHIP.INI) */
+ unsigned char macadr[6]; /* MAC address */
+ signed char a_kal[4]; /* calibration value for U */
+ signed char i_kal[4]; /* calibration value for I */
+ unsigned char reserve[18]; /* reserved */
+ unsigned short save_nr; /* save count */
+ unsigned short chksum; /* checksum */
+};
+
+
+int i2c_read (unsigned char chip, unsigned int addr, int alen,
+ unsigned char *buffer, int len);
+
+/*-----------------------------------------------------------------------
+ * Process manufacturer data block in EEPROM:
+ *
+ * If we boot on a system fresh from factory, check if the manufacturer data
+ * in the EEPROM is valid and save some information it contains.
+ *
+ * CMC manufacturer data is defined as follows:
+ *
+ * - located in the onboard EEPROM
+ * - starts at offset 0x0
+ * - size 0x00000040
+ *
+ * Internal structure: see struct definition
+ */
+
+void load_sernum_ethaddr (void)
+{
+ struct manufacturer_data data;
+ unsigned char serial [9];
+ unsigned char ethaddr[18];
+ unsigned short chksum;
+ unsigned char *p;
+ unsigned short i, is, id;
+
+#if !defined(CONFIG_HARD_I2C) && !defined(CONFIG_SOFT_I2C)
+#error you must define some I2C support (CONFIG_HARD_I2C or CONFIG_SOFT_I2C)
+#endif
+ if (i2c_read(I2C_CHIP, I2C_OFFSET, I2C_ALEN, (unsigned char *)&data,
+ sizeof(data)) != 0) {
+ puts ("Error reading manufacturer data from EEPROM\n");
+ return;
+ }
+
+ /* check if manufacturer data block is valid */
+ p = (unsigned char *)&data;
+ chksum = 0;
+ for (i = 0; i < (sizeof(data) - sizeof(data.chksum)); i++)
+ chksum += *p++;
+
+ debug ("checksum of manufacturer data block: %#.4x\n", chksum);
+
+ if (chksum != data.chksum) {
+ puts ("Error: manufacturer data block has invalid checksum\n");
+ return;
+ }
+
+ /* copy MAC address */
+ is = 0;
+ id = 0;
+ for (i = 0; i < 6; i++) {
+ sprintf (ðaddr[id], "%02x", data.macadr[is++]);
+ id += 2;
+ if (is < 6)
+ ethaddr[id++] = ':';
+ }
+ ethaddr[id] = '\0'; /* just to be sure */
+
+ /* copy serial number */
+ sprintf (serial, "%d", data.serial_number);
+
+ /* set serial# and ethaddr if not yet defined */
+ if (getenv("serial#") == NULL) {
+ setenv ("serial#", serial);
+ }
+
+ if (getenv("ethaddr") == NULL) {
+ setenv ("ethaddr", ethaddr);
+ }
+}
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
/* ------------------------------------------------------------------------- */
int misc_init_r (void)
{
- unsigned char *s, *e;
+ char *s, *e;
image_header_t *hdr;
time_t timestamp;
struct rtc_time tm;
#define FACTORY_SETTINGS 0xFFFC0000
if ((s = getenv ("ethaddr")) == NULL) {
- e = (unsigned char *) (FACTORY_SETTINGS);
+ e = (char *) (FACTORY_SETTINGS);
if (*(e + 0) != '0'
|| *(e + 1) != '0'
|| *(e + 2) != ':'
{
setenv (Things[thing].envname, Things[thing].dhcpvalue);
}
- return (Things[thing].dhcpvalue);
+ return ((u8 *)(Things[thing].dhcpvalue));
}
/* ------------------------------------------------------------------------- */
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
+ cpu/ppc4xx/4xx_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
#include <asm/processor.h>
#include <i2c.h>
#include <miiphy.h>
-#include <405gp_enet.h>
+#include <ppc4xx_enet.h>
/*
* Configuration data for AMIS FS6377-01 Programmable 3-PLL Clock Generator
int last_stage_init(void)
{
/* initialize the PHY */
- miiphy_reset(CONFIG_PHY_ADDR);
- miiphy_write(CONFIG_PHY_ADDR, PHY_BMCR,
- PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); /* AUTO neg */
- miiphy_write(CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08); /* LEDs */
+ miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
+
+ /* AUTO neg */
+ miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_BMCR,
+ PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+
+ /* LEDs */
+ miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08);
+
return 0; /* success */
}
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
+ cpu/ppc4xx/4xx_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
#include <asm/processor.h>
#include <i2c.h>
#include <miiphy.h>
-#include <405gp_enet.h>
+#include <ppc4xx_enet.h>
/*
* board_early_init_f: do early board initialization
int last_stage_init(void)
{
/* initialize the PHY */
- miiphy_reset(CONFIG_PHY_ADDR);
- miiphy_write(CONFIG_PHY_ADDR, PHY_BMCR,
- PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); /* AUTO neg */
- miiphy_write(CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08); /* LEDs */
+ miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
+
+ /* AUTO neg */
+ miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_BMCR,
+ PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+
+ /* LEDs */
+ miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08);
return 0; /* success */
}
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
+ cpu/ppc4xx/4xx_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
--- /dev/null
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := csb637.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+TEXT_BASE = 0x23fc0000
--- /dev/null
+/*
+ * (C) Copyright 2005 REA Elektronik GmbH <www.rea.de>
+ * Anders Larsen <alarsen@rea.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/AT91RM9200.h>
+#include <at91rm9200_net.h>
+#include <bcm5221.h>
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ /* Enable Ctrlc */
+ console_init_f ();
+
+ /* memory and cpu-speed are setup before relocation */
+ /* so we do _nothing_ here */
+
+ /* arch number of CSB637-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_CSB637;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int dram_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_ETHER
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+
+/*
+ * Name:
+ * at91rm9200_GetPhyInterface
+ * Description:
+ * Initialise the interface functions to the PHY
+ * Arguments:
+ * None
+ * Return value:
+ * None
+ */
+void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
+{
+ p_phyops->Init = bcm5221_InitPhy;
+ p_phyops->IsPhyConnected = bcm5221_IsPhyConnected;
+ p_phyops->GetLinkSpeed = bcm5221_GetLinkSpeed;
+ p_phyops->AutoNegotiate = bcm5221_AutoNegotiate;
+}
+
+#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
+#endif /* CONFIG_DRIVER_ETHER */
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
+
. = ALIGN(4);
- .text :
+ .text :
{
- cpu/arm926ejs/start.o (.text)
+ cpu/arm920t/start.o (.text)
*(.text)
}
+
+ . = ALIGN(4);
.rodata : { *(.rodata) }
+
. = ALIGN(4);
.data : { *(.data) }
+
. = ALIGN(4);
.got : { *(.got) }
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
LIB = lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+OBJS = $(BOARD).o flash.o nand.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
puts ("Board: ");
/* ------------------------------------------------------------------------- */
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-extern ulong
-nand_probe(ulong physadr);
-
-void
-nand_init(void)
-{
- ulong totlen = 0;
-
-/*
- The HI model is equipped with a large block NAND chip not supported yet
- by U-Boot
- (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
-*/
-
-#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
- debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE);
- totlen += nand_probe (CFG_NAND0_BASE);
-#endif /* CONFIG_PPCHAMELEON_MODULE_ME, CONFIG_PPCHAMELEON_MODULE_HI */
-
- debug ("Probing at 0x%.8x\n", CFG_NAND1_BASE);
- totlen += nand_probe (CFG_NAND1_BASE);
-
- printf ("%3lu MB\n", totlen >>20);
-}
-#endif
-
#ifdef CONFIG_CFB_CONSOLE
# ifdef CONFIG_CONSOLE_EXTRA_INFO
# include <video_fb.h>
case 1:
switch (pvr) {
case PVR_405EP_RB:
- sprintf (info, " IBM PowerPC 405EP Rev. B");
+ sprintf (info, " AMCC PowerPC 405EP Rev. B");
break;
default:
- sprintf (info, " IBM PowerPC 405EP Rev. <unknown>");
+ sprintf (info, " AMCC PowerPC 405EP Rev. <unknown>");
break;
}
return;
#
-# (C) Copyright 2000
+# (C) Copyright 2000, 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
# Reserve 256 kB for Monitor
-TEXT_BASE = 0xFFFC0000
+#TEXT_BASE = 0xFFFC0000
# Reserve 320 kB for Monitor
-#TEXT_BASE = 0xFFFB0000
+TEXT_BASE = 0xFFFB0000
+
+# Compile the new NAND code (needed iff #ifdef CONFIG_NEW_NAND_CODE)
+BOARDLIBS = drivers/nand/libnand.a
--- /dev/null
+/*
+ * (C) Copyright 2006 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#ifdef CONFIG_NEW_NAND_CODE
+/* new NAND handling */
+
+#include <nand.h>
+
+/*
+ * hardware specific access to control-lines
+ * function borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c)
+ */
+static void ppchameleonevb_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+{
+ struct nand_chip *this = mtdinfo->priv;
+ ulong base = (ulong) this->IO_ADDR_W;
+
+ switch(cmd) {
+ case NAND_CTL_SETCLE:
+ MACRO_NAND_CTL_SETCLE((unsigned long)base);
+ break;
+ case NAND_CTL_CLRCLE:
+ MACRO_NAND_CTL_CLRCLE((unsigned long)base);
+ break;
+ case NAND_CTL_SETALE:
+ MACRO_NAND_CTL_SETALE((unsigned long)base);
+ break;
+ case NAND_CTL_CLRALE:
+ MACRO_NAND_CTL_CLRALE((unsigned long)base);
+ break;
+ case NAND_CTL_SETNCE:
+ MACRO_NAND_ENABLE_CE((unsigned long)base);
+ break;
+ case NAND_CTL_CLRNCE:
+ MACRO_NAND_DISABLE_CE((unsigned long)base);
+ break;
+ }
+}
+
+
+/*
+ * read device ready pin
+ * function +/- borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c)
+ */
+static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo)
+{
+ struct nand_chip *this = mtdinfo->priv;
+ ulong rb_gpio_pin;
+
+ /* use the base addr to find out which chip are we dealing with */
+ switch((ulong) this->IO_ADDR_W) {
+ case CFG_NAND0_BASE:
+ rb_gpio_pin = CFG_NAND0_RDY;
+ break;
+ case CFG_NAND1_BASE:
+ rb_gpio_pin = CFG_NAND1_RDY;
+ break;
+ default: /* this should never happen */
+ return 0;
+ break;
+ }
+
+ if (in32(GPIO0_IR) & rb_gpio_pin)
+ return 1;
+ return 0;
+}
+
+
+/*
+ * Board-specific NAND initialization. The following members of the
+ * argument are board-specific (per include/linux/mtd/nand_new.h):
+ * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
+ * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
+ * - hwcontrol: hardwarespecific function for accesing control-lines
+ * - dev_ready: hardwarespecific function for accesing device ready/busy line
+ * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
+ * only be provided if a hardware ECC is available
+ * - eccmode: mode of ecc, see defines
+ * - chip_delay: chip dependent delay for transfering data from array to
+ * read regs (tR)
+ * - options: various chip options. They can partly be set to inform
+ * nand_scan about special functionality. See the defines for further
+ * explanation
+ * Members with a "?" were not set in the merged testing-NAND branch,
+ * so they are not set here either.
+ */
+void board_nand_init(struct nand_chip *nand)
+{
+
+ nand->hwcontrol = ppchameleonevb_hwcontrol;
+ nand->dev_ready = ppchameleonevb_device_ready;
+ nand->eccmode = NAND_ECC_SOFT;
+ nand->chip_delay = NAND_BIG_DELAY_US;
+ nand->options = NAND_SAMSUNG_LP_OPTIONS;
+}
+
+#else
+
+/* old NAND handling */
+extern ulong
+nand_probe(ulong physadr);
+
+void
+nand_init(void)
+{
+ ulong totlen = 0;
+
+/*
+ The HI model is equipped with a large block NAND chip not supported yet
+ by U-Boot
+ (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
+*/
+
+#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
+ debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE);
+ totlen += nand_probe (CFG_NAND0_BASE);
+#endif /* CONFIG_PPCHAMELEON_MODULE_ME, CONFIG_PPCHAMELEON_MODULE_HI */
+
+ debug ("Probing at 0x%.8x\n", CFG_NAND1_BASE);
+ totlen += nand_probe (CFG_NAND1_BASE);
+
+ printf ("%3lu MB\n", totlen >>20);
+}
+#endif
+#endif
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
+ cpu/ppc4xx/4xx_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
.sdata : { *(.sdata) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
int misc_init_r (void)
{
revinfo eerev;
- u_char *ptr;
+ char *ptr;
u_int i, l, initSrom, copyNv;
char buf[256];
char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
if (strcmp (eerev.magic, "ELTEC") != 0)
{
/* srom is not initialized -> create a default revision info */
- for (i = 0, ptr = (u_char *)&eerev; i < sizeof(revinfo); i++)
+ for (i = 0, ptr = (char *)&eerev; i < sizeof(revinfo); i++)
*ptr++ = 0x00;
strcpy(eerev.magic, "ELTEC");
eerev.revrev[0] = 1;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
/* get onboard network iobase */
pci_read_config_dword(PCI_BDF(0,0x10,0), PCI_BASE_ADDRESS_0,
- &onboard_dev.iobase);
+ (unsigned int *)&onboard_dev.iobase);
onboard_dev.iobase &= ~0xf;
source[63] = eepro100_srom_checksum (source);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
int i;
/* check revision data */
- eeprom_read (CFG_I2C_EEPROM_ADDR, 480, (char *) &mhpcRevInfo, 32);
+ eeprom_read (CFG_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo, 32);
if (strncmp ((char *) &mhpcRevInfo.board[2], "MHPC", 4) != 0) {
printf ("Enter revision number (0-9): %c ",
}
/* setup new revision data */
- eeprom_write (CFG_I2C_EEPROM_ADDR, 480, (char *) &mhpcRevInfo,
+ eeprom_write (CFG_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo,
32);
}
immap_t *immr = (immap_t *) CFG_IMMR;
/* enable video only on CLUT value */
- if ((penv = getenv ("clut")) != NULL)
- clut = (u_int) simple_strtoul (penv, NULL, 10);
+ if ((penv = (uchar *)getenv ("clut")) != NULL)
+ clut = (u_int) simple_strtoul ((char *)penv, NULL, 10);
else
return NULL;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
int i;
uchar *boottype;
uchar *bootletter;
- uchar *fmt;
+ char *fmt;
uchar botbootletter[] = "B";
uchar topbootletter[] = "T";
uchar botboottype[] = "bottom boot sector";
/*printf ("%s\n", buf); */
/* search for our specific entry */
if (!strncmp ((char *) buf, "[RLA/lan/Ethernet] ", 19)) {
- setenv ("ethaddr", buf + 19);
+ setenv ("ethaddr", (char *)(buf + 19));
} else if (!strncmp ((char *) buf, "[BOARD/SERIAL] ", 15)) {
- setenv ("serial#", buf + 15);
+ setenv ("serial#", (char *)(buf + 15));
} else if (!strncmp ((char *) buf, "[BOARD/TYPE] ", 13)) {
- setenv ("board_id", buf + 13);
+ setenv ("board_id", (char *)(buf + 13));
}
}
}
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
#include "eric.h"
#include <asm/processor.h>
-#define IBM405GP_GPIO0_OR 0xef600700 /* GPIO Output */
-#define IBM405GP_GPIO0_TCR 0xef600704 /* GPIO Three-State Control */
-#define IBM405GP_GPIO0_ODR 0xef600718 /* GPIO Open Drain */
-#define IBM405GP_GPIO0_IR 0xef60071c /* GPIO Input */
+#define PPC405GP_GPIO0_OR 0xef600700 /* GPIO Output */
+#define PPC405GP_GPIO0_TCR 0xef600704 /* GPIO Three-State Control */
+#define PPC405GP_GPIO0_ODR 0xef600718 /* GPIO Open Drain */
+#define PPC405GP_GPIO0_IR 0xef60071c /* GPIO Input */
int board_early_init_f (void)
{
| IRQ 30 (EXT IRQ 5) PCI INTB#; active low; level sensitive
| IRQ 31 (EXT IRQ 6) PCI INTA#; active low; level sensitive
| -> IRQ6 Pin is NOW GPIO23 and can be activateted by setting
- | IBM405GP_GPIO0_TCR Bit 0 = 1 (driving the output as defined in IBM405GP_GPIO0_OR,
+ | PPC405GP_GPIO0_TCR Bit 0 = 1 (driving the output as defined in PPC405GP_GPIO0_OR,
| else tristate)
| Note for ERIC board:
| An interrupt taken for the HOST (IRQ 28) indicates that
mtdcr (cntrl0, 0x00002000); /* set IRQ6 as GPIO23 to generate an interrupt request to the PCP2PCI bridge */
- out32 (IBM405GP_GPIO0_OR, 0x60000000); /*fixme is SMB_INT high or low active??; IRQ6 is GPIO23 output */
- out32 (IBM405GP_GPIO0_TCR, 0x7E400000);
+ out32 (PPC405GP_GPIO0_OR, 0x60000000); /*fixme is SMB_INT high or low active??; IRQ6 is GPIO23 output */
+ out32 (PPC405GP_GPIO0_TCR, 0x7E400000);
return 0;
}
int checkboard (void)
{
- unsigned char *s = getenv ("serial#");
- unsigned char *e;
+ char *s = getenv ("serial#");
+ char *e;
puts ("Board: ");
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
+ cpu/ppc4xx/4xx_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof (str));
puts ("Board: ");
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
int index;
int len;
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof (str));
const unsigned char *fpga;
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
+ cpu/ppc4xx/4xx_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
puts ("Board: ");
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
int index;
int len;
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof (str));
puts ("Board: ");
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
common/dlmalloc.o (.text)
lib_ppc/extable.o (.text)
lib_ppc/board.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+# Objects for Xilinx JTAG programming (CPLD)
+CPLD = ../common/xilinx_jtag/lenval.o \
+ ../common/xilinx_jtag/micro.o \
+ ../common/xilinx_jtag/ports.o
+
+OBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD)
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+
+
+extern void lxt971_no_sleep(void);
+
+
+/* fpga configuration data - not compressed, generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+int filesize = sizeof(fpgadata);
+
+
+int board_early_init_f (void)
+{
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+ * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+ * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+ */
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(uicer, 0x00000000); /* disable all ints */
+ mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
+ mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
+ mtdcr(uictr, 0x10000000); /* set int trigger levels */
+ mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+
+ /*
+ * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+ */
+ mtebc (epcr, 0xa8400000); /* ebc always driven */
+
+ /*
+ * Reset CPLD via GPIO12 (CS3) pin
+ */
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_PLD_RESET);
+ udelay(1000); /* wait 1ms */
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_PLD_RESET);
+ udelay(1000); /* wait 1ms */
+
+ return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_f (void)
+{
+ return 0; /* dummy implementation */
+}
+
+
+int misc_init_r (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+ /*
+ * Setup and enable EEPROM write protection
+ */
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
+
+ /*
+ * Set NAND-FLASH GPIO signals to default
+ */
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
+
+ return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+ char str[64];
+ int flashcnt;
+ int delay;
+ volatile unsigned char *led_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1000);
+ volatile unsigned char *ver_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1001);
+
+ puts ("Board: ");
+
+ if (getenv_r("serial#", str, sizeof(str)) == -1) {
+ puts ("### No HW ID - assuming CMS700");
+ } else {
+ puts(str);
+ }
+
+ printf(" (PLD-Version=%02d)\n", *ver_reg);
+
+ /*
+ * Flash LEDs
+ */
+ for (flashcnt = 0; flashcnt < 3; flashcnt++) {
+ *led_reg = 0x00; /* LEDs off */
+ for (delay = 0; delay < 100; delay++)
+ udelay(1000);
+ *led_reg = 0x0f; /* LEDs on */
+ for (delay = 0; delay < 50; delay++)
+ udelay(1000);
+ }
+ *led_reg = 0x70;
+
+ return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+ unsigned long val;
+
+ mtdcr(memcfga, mem_mb0cf);
+ val = mfdcr(memcfgd);
+
+#if 0
+ printf("\nmb0cf=%x\n", val); /* test-only */
+ printf("strap=%x\n", mfdcr(strap)); /* test-only */
+#endif
+
+ return (4*1024*1024 << ((val & 0x000e0000) >> 17));
+}
+
+/* ------------------------------------------------------------------------- */
+
+#if defined(CFG_EEPROM_WREN)
+/* Input: <dev_addr> I2C address of EEPROM device to enable.
+ * <state> -1: deliver current state
+ * 0: disable write
+ * 1: enable write
+ * Returns: -1: wrong device address
+ * 0: dis-/en- able done
+ * 0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+ if (CFG_I2C_EEPROM_ADDR != dev_addr) {
+ return -1;
+ } else {
+ switch (state) {
+ case 1:
+ /* Enable write access, clear bit GPIO_SINT2. */
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
+ state = 0;
+ break;
+ case 0:
+ /* Disable write access, set bit GPIO_SINT2. */
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
+ state = 0;
+ break;
+ default:
+ /* Read current status back. */
+ state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
+ break;
+ }
+ }
+ return state;
+}
+
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int query = argc == 1;
+ int state = 0;
+
+ if (query) {
+ /* Query write access state. */
+ state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
+ if (state < 0) {
+ puts ("Query of write access state failed.\n");
+ } else {
+ printf ("Write access for device 0x%0x is %sabled.\n",
+ CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+ state = 0;
+ }
+ } else {
+ if ('0' == argv[1][0]) {
+ /* Disable write access. */
+ state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
+ } else {
+ /* Enable write access. */
+ state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
+ }
+ if (state < 0) {
+ puts ("Setup of write access state failed.\n");
+ }
+ }
+
+ return state;
+}
+
+U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
+ "eepwren - Enable / disable / query EEPROM write access\n",
+ NULL);
+#endif /* #if defined(CFG_EEPROM_WREN) */
+
+/* ------------------------------------------------------------------------- */
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#include <linux/mtd/nand.h>
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+
+void nand_init(void)
+{
+ nand_probe(CFG_NAND_BASE);
+ if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
+ print_size(nand_dev_desc[0].totlen, "\n");
+ }
+}
+#endif
+
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+ /*
+ * Disable sleep mode in LXT971
+ */
+ lxt971_no_sleep();
+#endif
+}
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd CMS405 boards
+#
+
+TEXT_BASE = 0xFFFC0000
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size_b0;
+ int i;
+ uint pbcr;
+ unsigned long base_b0;
+ int size_val = 0;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0<<20);
+ }
+
+ /* Setup offsets */
+ flash_get_offsets (-size_b0, &flash_info[0]);
+
+ /* Re-do sizing to get full correct info */
+ mtdcr(ebccfga, pb0cr);
+ pbcr = mfdcr(ebccfgd);
+ mtdcr(ebccfga, pb0cr);
+ base_b0 = -size_b0;
+ switch (size_b0) {
+ case 1 << 20:
+ size_val = 0;
+ break;
+ case 2 << 20:
+ size_val = 1;
+ break;
+ case 4 << 20:
+ size_val = 2;
+ break;
+ case 8 << 20:
+ size_val = 3;
+ break;
+ case 16 << 20:
+ size_val = 4;
+ break;
+ }
+ pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+ mtdcr(ebccfgd, pbcr);
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -CFG_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+
+ flash_info[0].size = size_b0;
+
+ return (size_b0);
+}
--- /dev/null
+ 0x07,0x20,0x12,0x00,0x12,0x01,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x02,0x08,
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+ 0x00,0x00,0x01,0x09,0x00,0x01,0x40,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
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+ 0x01,0x09,0x00,0x01,0x48,0x0c,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,
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+ 0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x03,0x09,0x00,0x01,0x80,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
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+ 0x00,0x01,0x84,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
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+ 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x8c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x90,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x01,0x09,0x00,0x01,0xa0,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
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+ 0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x33,0x84,0x00,
+ 0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x09,0x00,0x33,0x88,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x01,0x09,0x00,0x33,0x8c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,
+ 0x09,0x00,0x33,0x90,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,
+ 0x00,0x33,0xa0,0x00,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+ 0x33,0xa4,0x00,0x00,0x00,0x11,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,
+ 0xa8,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0xac,
+ 0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0xb0,0x00,
+ 0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0xc0,0x00,0x00,
+ 0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0xc4,0x00,0x00,0x00,
+ 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0xc8,0x00,0x00,0x00,0x01,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0xcc,0x00,0x00,0x00,0x01,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x09,0x00,0x33,0xd0,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x34,0x00,0x00,0x00,
+ 0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x34,0x04,0x00,0x00,0x00,0x01,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x34,
+ 0x08,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x0c,
+ 0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x10,0x00,
+ 0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x20,0x00,0x00,
+ 0x00,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x24,0x00,0x00,0x00,
+ 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x28,0x00,0x00,0x00,0x01,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x2c,0x00,0x00,0x00,0x01,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x30,0x00,0x00,0x00,0x01,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x40,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x44,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x01,0x09,0x00,0x34,0x48,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x01,0x09,0x00,0x34,0x4c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,
+ 0x34,0x50,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x34,0x80,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,
+ 0x00,0x09,0x00,0x34,0x84,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x34,0x88,0x00,0x00,0x00,0x01,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x8c,0x00,0x00,0x00,0x01,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x90,0x00,0x00,0x00,0x01,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0xa0,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x01,0x09,0x00,0x34,0xa4,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x01,0x09,0x00,0x34,0xa8,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x01,0x09,0x00,0x34,0xac,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x01,0x09,0x00,0x34,0xb0,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,
+ 0x09,0x00,0x34,0xc0,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,
+ 0x00,0x34,0xc4,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+ 0x34,0xc8,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,
+ 0xcc,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,
+ 0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x34,0xd0,0x00,0x00,0x00,
+ 0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x03,
+ 0x09,0x00,0x35,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x35,0x04,
+ 0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x09,0x00,0x35,0x08,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x01,0x09,0x00,0x35,0x0c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x01,0x09,0x00,0x35,0x10,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,
+ 0x09,0x00,0x35,0x20,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,
+ 0x00,0x35,0x24,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+ 0x35,0x28,0x00,0x00,0x08,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,
+ 0x2c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x30,
+ 0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x40,0x00,
+ 0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x44,0x00,0x00,
+ 0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x48,0x00,0x00,0x00,
+ 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x4c,0x00,0x00,0x00,0x01,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x09,0x00,0x35,0x50,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x35,0x80,0x00,
+ 0x00,0x40,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x35,0x84,0x00,0x00,0x00,0x01,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,
+ 0x35,0x88,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,
+ 0x8c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x90,
+ 0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xa0,0x00,
+ 0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xa4,0x00,0x1c,
+ 0x00,0x81,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xa8,0x00,0x00,0x00,
+ 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xac,0x00,0x00,0x00,0x01,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xb0,0x00,0x00,0x00,0x01,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xc0,0x00,0x00,0x00,0x01,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xc4,0x00,0x14,0x00,0x61,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xc8,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x01,0x09,0x00,0x35,0xcc,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,
+ 0x00,0x35,0xd0,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x35,0xd0,0x00,0x00,0x00,0x01,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x04,0x00,0x00,
+ 0x00,0x64,0x02,0x08,0xf0,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x02,0x08,0xff,
+ 0x08,0x00,0x00,0x00,0x01,0x01,0x00,0x09,0x00,0x00,0x00,
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ cpu/ppc4xx/traps.o (.text)
+ cpu/ppc4xx/interrupts.o (.text)
+ cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/cpu_init.o (.text)
+ cpu/ppc4xx/speed.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+
+/* . = env_offset;*/
+/* common/environment.o(.text)*/
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
#endif
extern int flash_sect_erase(ulong, ulong);
extern int flash_sect_protect (int, ulong, ulong);
-extern int flash_write (uchar *, ulong, ulong);
+extern int flash_write (char *, ulong, ulong);
/* change char* to void* to shutup the compiler */
extern block_dev_desc_t *get_dev (char*, int);
/* check the data CRC */
checksum = ntohl(hdr->ih_dcrc);
- if (crc32 (0, (char *)(LOAD_ADDR + sizeof(*hdr)), ntohl(hdr->ih_size))
+ if (crc32 (0, (uchar *)(LOAD_ADDR + sizeof(*hdr)), ntohl(hdr->ih_size))
!= checksum) {
printf ("Image %s bad data checksum\n", au_image[i].name);
return -1;
checksum = ntohl(hdr->ih_hcrc);
hdr->ih_hcrc = 0;
- if (crc32 (0, (char *)hdr, sizeof(*hdr)) != checksum) {
+ if (crc32 (0, (uchar *)hdr, sizeof(*hdr)) != checksum) {
printf ("Image %s bad header checksum\n", au_image[i].name);
return -1;
}
*/
if (au_image[i].type != AU_NAND) {
debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes);
- rc = flash_write(addr, start, nbytes);
+ rc = flash_write((char *)addr, start, nbytes);
} else {
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
debug ("nand_rw(%p, %lx %x)\n", addr, start, nbytes);
rc = nand_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2,
- start, nbytes, &total, addr);
+ start, nbytes, (size_t *)&total, (uchar *)addr);
debug ("nand_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes);
#endif
}
* check the dcrc of the copy
*/
if (au_image[i].type != AU_NAND) {
- rc = crc32 (0, (char *)(start + off), ntohl(hdr->ih_size));
+ rc = crc32 (0, (uchar *)(start + off), ntohl(hdr->ih_size));
} else {
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
rc = nand_rw(nand_dev_desc, NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP,
- start, nbytes, &total, addr);
- rc = crc32 (0, (char *)(addr + off), ntohl(hdr->ih_size));
+ start, nbytes, (size_t *)&total, (uchar *)addr);
+ rc = crc32 (0, (uchar *)(addr + off), ntohl(hdr->ih_size));
#endif
}
if (rc != ntohl(hdr->ih_dcrc)) {
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Matthias Fuchs, esd GmbH Germany, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+
+extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
+extern int do_autoscript (cmd_tbl_t *, int, int, char *[]);
+
+#define ADDRMASK 0xfffff000
+
+/*
+ * Command loadpci: wait for signal from host and boot image.
+ */
+int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned int *ptr = 0;
+ int count = 0;
+ int count2 = 0;
+ char addr[16];
+ char str[] = "\\|/-";
+ char *local_args[2];
+
+ while(1) {
+ /*
+ * Mark sync address
+ */
+ ptr = 0;
+ memset(ptr, 0, 0x20);
+
+ *ptr = 0xffffffff;
+ puts("\nWaiting for action from pci host -");
+
+ /*
+ * Wait for host to write the start address
+ */
+ while (*ptr == 0xffffffff) {
+ count++;
+ if (!(count % 100)) {
+ count2++;
+ putc(0x08); /* backspace */
+ putc(str[count2 % 4]);
+ }
+
+ /* Abort if ctrl-c was pressed */
+ if (ctrlc()) {
+ puts("\nAbort\n");
+ return 0;
+ }
+
+ udelay(1000);
+ }
+
+ printf("\nGot bootcode %08x: ", *ptr);
+ sprintf(addr, "%08x", *ptr & ADDRMASK);
+
+ switch (*ptr & ~ADDRMASK) {
+ case 0:
+ /*
+ * Boot image via bootm
+ */
+ printf("booting image at addr 0x%s ...\n", addr);
+ setenv("loadaddr", addr);
+
+ do_bootm (cmdtp, 0, 0, NULL);
+ break;
+
+ case 1:
+ /*
+ * Boot image via autoscr
+ */
+ printf("executing script at addr 0x%s ...\n", addr);
+
+ local_args[0] = addr;
+ local_args[1] = NULL;
+ do_autoscript(cmdtp, 0, 1, local_args);
+ break;
+
+ case 2:
+ /*
+ * Call run_cmd
+ */
+ printf("running command at addr 0x%s ...\n", addr);
+ run_command ((char*)(*ptr & ADDRMASK), 0);
+ break;
+
+ default:
+ printf("unhandled boot method\n");
+ break;
+ }
+ }
+}
+
+U_BOOT_CMD(
+ loadpci, 1, 1, do_loadpci,
+ "loadpci - Wait for pci bootcmd and boot it\n",
+ NULL
+ );
+
+#endif
+
* (C) Copyright 2003-2004
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
#include "lcd.h"
+extern int video_display_bitmap (ulong, int, int);
+
+
int palette_index;
int palette_value;
-
+int lcd_depth;
+unsigned char *glob_lcd_reg;
+unsigned char *glob_lcd_mem;
#ifdef CFG_LCD_ENDIAN
void lcd_setup(int lcd, int config)
#endif /* #ifdef CFG_LCD_ENDIAN */
-void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
- uchar *logo_bmp, ulong len)
+void lcd_bmp(uchar *logo_bmp)
{
int i;
- ushort s1dReg;
- uchar s1dValue;
uchar *ptr;
ushort *ptr2;
ushort val;
- unsigned char *dst;
+ unsigned char *dst = NULL;
int x, y;
int width, height, bpp, colors, line_size;
int header_size;
unsigned char *bmp;
unsigned char r, g, b;
BITMAPINFOHEADER *bm_info;
- int reg_byte_swap;
+ ulong len;
/*
- * Detect epson
+ * Check for bmp mark 'BM'
*/
- if (lcd_reg[0] == 0x1c) {
+ if (*(ushort *)logo_bmp != 0x424d) {
+
/*
- * Big epson detected
+ * Decompress bmp image
*/
- reg_byte_swap = FALSE;
- palette_index = 0x1e2;
- palette_value = 0x1e4;
- puts("LCD: S1D13806");
- } else if (lcd_reg[1] == 0x1c) {
- /*
- * Big epson detected (with register swap bug)
- */
- reg_byte_swap = TRUE;
- palette_index = 0x1e3;
- palette_value = 0x1e5;
- puts("LCD: S1D13806S");
- } else if (lcd_reg[0] == 0x18) {
+ len = CFG_VIDEO_LOGO_MAX_SIZE;
+ dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE);
+ if (dst == NULL) {
+ printf("Error: malloc in gunzip failed!\n");
+ return;
+ }
+ if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)logo_bmp, &len) != 0) {
+ return;
+ }
+ if (len == CFG_VIDEO_LOGO_MAX_SIZE) {
+ printf("Image could be truncated (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n");
+ }
+
/*
- * Small epson detected (704)
+ * Check for bmp mark 'BM'
*/
- reg_byte_swap = FALSE;
- palette_index = 0x15;
- palette_value = 0x17;
- puts("LCD: S1D13704");
- } else if (lcd_reg[0x10000] == 0x24) {
+ if (*(ushort *)dst != 0x424d) {
+ printf("LCD: Unknown image format!\n");
+ free(dst);
+ return;
+ }
+ } else {
/*
- * Small epson detected (705)
+ * Uncompressed BMP image, just use this pointer
*/
- reg_byte_swap = FALSE;
- palette_index = 0x15;
- palette_value = 0x17;
- lcd_reg += 0x10000; /* add offset for 705 regs */
- puts("LCD: S1D13705");
- } else {
- puts("LCD: No controller detected!\n");
- return;
- }
-
- for (i = 0; i<reg_count; i++) {
- s1dReg = regs[i].Index;
- if (reg_byte_swap) {
- if ((s1dReg & 0x0001) == 0)
- s1dReg |= 0x0001;
- else
- s1dReg &= ~0x0001;
- }
- s1dValue = regs[i].Value;
- lcd_reg[s1dReg] = s1dValue;
- }
-
- /*
- * Decompress bmp image
- */
- dst = malloc(CFG_LCD_LOGO_MAX_SIZE);
- if (gunzip(dst, CFG_LCD_LOGO_MAX_SIZE, (uchar *)logo_bmp, &len) != 0) {
- return;
- }
-
- /*
- * Check for bmp mark 'BM'
- */
- if (*(ushort *)dst != 0x424d) {
- printf("LCD: Unknown image format!\n");
- free(dst);
- return;
+ dst = (uchar *)logo_bmp;
}
/*
break;
default:
printf("LCD: Unknown bpp (%d) im image!\n", bpp);
- free(dst);
+ if ((dst != NULL) && (dst != (uchar *)logo_bmp)) {
+ free(dst);
+ }
return;
}
printf(" (%d*%d, %dbpp)\n", width, height, bpp);
/*
* Write color palette
*/
- if (colors <= 256) {
+ if ((colors <= 256) && (lcd_depth <= 8)) {
ptr = (unsigned char *)(dst + 14 + 40);
for (i=0; i<colors; i++) {
b = *ptr++;
g = *ptr++;
r = *ptr++;
ptr++;
- S1D_WRITE_PALETTE(lcd_reg, i, r, g, b);
+ S1D_WRITE_PALETTE(glob_lcd_reg, i, r, g, b);
}
}
/*
* Write bitmap data into framebuffer
*/
- ptr = lcd_mem;
- ptr2 = (ushort *)lcd_mem;
+ ptr = glob_lcd_mem;
+ ptr2 = (ushort *)glob_lcd_mem;
header_size = 14 + 40 + 4*colors; /* skip bmp header */
for (y=0; y<height; y++) {
bmp = &dst[(height-1-y)*line_size + header_size];
- if (bpp == 24) {
- for (x=0; x<width; x++) {
- /*
- * Generate epson 16bpp fb-format from 24bpp image
- */
- b = *bmp++ >> 3;
- g = *bmp++ >> 2;
- r = *bmp++ >> 3;
- val = ((r & 0x1f) << 11) | ((g & 0x3f) << 5) | (b & 0x1f);
- *ptr2++ = val;
+ if (lcd_depth == 16) {
+ if (bpp == 24) {
+ for (x=0; x<width; x++) {
+ /*
+ * Generate epson 16bpp fb-format from 24bpp image
+ */
+ b = *bmp++ >> 3;
+ g = *bmp++ >> 2;
+ r = *bmp++ >> 3;
+ val = ((r & 0x1f) << 11) | ((g & 0x3f) << 5) | (b & 0x1f);
+ *ptr2++ = val;
+ }
+ } else if (bpp == 8) {
+ for (x=0; x<line_size; x++) {
+ /* query rgb value from palette */
+ ptr = (unsigned char *)(dst + 14 + 40) ;
+ ptr += (*bmp++) << 2;
+ b = *ptr++ >> 3;
+ g = *ptr++ >> 2;
+ r = *ptr++ >> 3;
+ val = ((r & 0x1f) << 11) | ((g & 0x3f) << 5) | (b & 0x1f);
+ *ptr2++ = val;
+ }
}
} else {
for (x=0; x<line_size; x++) {
}
}
- free(dst);
+ if ((dst != NULL) && (dst != (uchar *)logo_bmp)) {
+ free(dst);
+ }
}
+
+
+void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
+ uchar *logo_bmp, ulong len)
+{
+ int i;
+ ushort s1dReg;
+ uchar s1dValue;
+ int reg_byte_swap;
+
+ /*
+ * Detect epson
+ */
+ if (lcd_reg[0] == 0x1c) {
+ /*
+ * Big epson detected
+ */
+ reg_byte_swap = FALSE;
+ palette_index = 0x1e2;
+ palette_value = 0x1e4;
+ lcd_depth = 16;
+ puts("LCD: S1D13806");
+ } else if (lcd_reg[1] == 0x1c) {
+ /*
+ * Big epson detected (with register swap bug)
+ */
+ reg_byte_swap = TRUE;
+ palette_index = 0x1e3;
+ palette_value = 0x1e5;
+ lcd_depth = 16;
+ puts("LCD: S1D13806S");
+ } else if (lcd_reg[0] == 0x18) {
+ /*
+ * Small epson detected (704)
+ */
+ reg_byte_swap = FALSE;
+ palette_index = 0x15;
+ palette_value = 0x17;
+ lcd_depth = 8;
+ puts("LCD: S1D13704");
+ } else if (lcd_reg[0x10000] == 0x24) {
+ /*
+ * Small epson detected (705)
+ */
+ reg_byte_swap = FALSE;
+ palette_index = 0x15;
+ palette_value = 0x17;
+ lcd_depth = 8;
+ lcd_reg += 0x10000; /* add offset for 705 regs */
+ puts("LCD: S1D13705");
+ } else {
+ puts("LCD: No controller detected!\n");
+ return;
+ }
+
+ /*
+ * Setup lcd controller regs
+ */
+ for (i = 0; i<reg_count; i++) {
+ s1dReg = regs[i].Index;
+ if (reg_byte_swap) {
+ if ((s1dReg & 0x0001) == 0)
+ s1dReg |= 0x0001;
+ else
+ s1dReg &= ~0x0001;
+ }
+ s1dValue = regs[i].Value;
+ lcd_reg[s1dReg] = s1dValue;
+ }
+
+ /*
+ * Save reg & mem pointer for later usage (e.g. bmp command)
+ */
+ glob_lcd_reg = lcd_reg;
+ glob_lcd_mem = lcd_mem;
+
+ /*
+ * Display bmp image
+ */
+ lcd_bmp(logo_bmp);
+}
+
+#ifdef CONFIG_VIDEO_SM501
+int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ ulong addr;
+ char *str;
+
+ if (argc != 2) {
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
+ addr = simple_strtoul(argv[1], NULL, 16);
+
+ str = getenv("bd_type");
+ if ((strcmp(str, "ppc221") == 0) || (strcmp(str, "ppc231") == 0)) {
+ /*
+ * SM501 available, use standard bmp command
+ */
+ return (video_display_bitmap(addr, 0, 0));
+ } else {
+ /*
+ * No SM501 available, use esd epson bmp command
+ */
+ lcd_bmp((uchar *)addr);
+ return 0;
+ }
+}
+
+U_BOOT_CMD(
+ esdbmp, 2, 1, do_esdbmp,
+ "esdbmp - display BMP image\n",
+ "<imageAddr> - display image\n"
+);
+#endif
{
unsigned short reg;
- miiphy_read(CONFIG_PHY_ADDR, 0x10, ®);
+ miiphy_read("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, ®);
reg &= ~0x0040; /* disable sleep mode */
- miiphy_write(CONFIG_PHY_ADDR, 0x10, reg);
+ miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, reg);
}
#endif /* CONFIG_LXT971_NO_SLEEP */
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o ../common/misc.o ../common/cmd_loadpci.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd CPCI2DP board
+#
+
+TEXT_BASE = 0xFFFC0000
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+
+int board_early_init_f (void)
+{
+ unsigned long cntrl0Reg;
+
+ /*
+ * Setup GPIO pins
+ */
+ cntrl0Reg = mfdcr(cntrl0);
+ mtdcr(cntrl0, cntrl0Reg | ((CFG_EEPROM_WP | CFG_PB_LED | CFG_SELF_RST | CFG_INTA_FAKE) << 5));
+
+ /* set output pins to high */
+ out32(GPIO0_OR, CFG_EEPROM_WP);
+ /* setup for output (LED=off) */
+ out32(GPIO0_TCR, CFG_EEPROM_WP | CFG_PB_LED);
+
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive
+ * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
+ * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) unused
+ */
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(uicer, 0x00000000); /* disable all ints */
+ mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
+ mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
+
+ mtdcr(uictr, 0x10000000); /* set int trigger levels */
+ mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+
+ return 0;
+}
+
+
+int misc_init_f (void)
+{
+ return 0; /* dummy implementation */
+}
+
+
+int misc_init_r (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ unsigned long cntrl0Reg;
+
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+ /*
+ * Select cts (and not dsr) on uart1
+ */
+ cntrl0Reg = mfdcr(cntrl0);
+ mtdcr(cntrl0, cntrl0Reg | 0x00001000);
+
+ return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+ char str[64];
+ int i = getenv_r ("serial#", str, sizeof(str));
+
+ puts ("Board: ");
+
+ if (i == -1) {
+ puts ("### No HW ID - assuming CPCI2DP");
+ } else {
+ puts(str);
+ }
+
+ printf(" (Ver 1.0)");
+
+ putc ('\n');
+
+ return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+ unsigned long val;
+
+ mtdcr(memcfga, mem_mb0cf);
+ val = mfdcr(memcfgd);
+
+ return (4*1024*1024 << ((val & 0x000e0000) >> 17));
+}
+
+/* ------------------------------------------------------------------------- */
+
+#if defined(CFG_EEPROM_WREN)
+/* Input: <dev_addr> I2C address of EEPROM device to enable.
+ * <state> -1: deliver current state
+ * 0: disable write
+ * 1: enable write
+ * Returns: -1: wrong device address
+ * 0: dis-/en- able done
+ * 0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state) {
+ if (CFG_I2C_EEPROM_ADDR != dev_addr) {
+ return -1;
+ } else {
+ switch (state) {
+ case 1:
+ /* Enable write access, clear bit GPIO_SINT2. */
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
+ state = 0;
+ break;
+ case 0:
+ /* Disable write access, set bit GPIO_SINT2. */
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
+ state = 0;
+ break;
+ default:
+ /* Read current status back. */
+ state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
+ break;
+ }
+ }
+ return state;
+}
+#endif
+
+#if defined(CFG_EEPROM_WREN)
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int query = argc == 1;
+ int state = 0;
+
+ if (query) {
+ /* Query write access state. */
+ state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
+ if (state < 0) {
+ puts ("Query of write access state failed.\n");
+ } else {
+ printf ("Write access for device 0x%0x is %sabled.\n",
+ CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+ state = 0;
+ }
+ } else {
+ if ('0' == argv[1][0]) {
+ /* Disable write access. */
+ state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
+ } else {
+ /* Enable write access. */
+ state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
+ }
+ if (state < 0) {
+ puts ("Setup of write access state failed.\n");
+ }
+ }
+
+ return state;
+}
+
+U_BOOT_CMD(
+ eepwren, 2, 0, do_eep_wren,
+ "eepwren - Enable / disable / query EEPROM write access\n",
+ NULL
+ );
+#endif /* #if defined(CFG_EEPROM_WREN) */
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size_b0;
+ int i;
+ uint pbcr;
+ unsigned long base_b0;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0<<20);
+ }
+
+ /* Setup offsets */
+ flash_get_offsets (-size_b0, &flash_info[0]);
+
+ /* Re-do sizing to get full correct info */
+ mtdcr(ebccfga, pb0cr);
+ pbcr = mfdcr(ebccfgd);
+ mtdcr(ebccfga, pb0cr);
+ base_b0 = -size_b0;
+ pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
+ mtdcr(ebccfgd, pbcr);
+ /* printf("pb1cr = %x\n", pbcr); */
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -monitor_flash_len,
+ 0xffffffff,
+ &flash_info[0]);
+
+ flash_info[0].size = size_b0;
+
+ return (size_b0);
+}
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ cpu/ppc4xx/traps.o (.text)
+ cpu/ppc4xx/interrupts.o (.text)
+ cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/cpu_init.o (.text)
+ cpu/ppc4xx/speed.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+
+/* . = env_offset;*/
+/* common/environment.o(.text)*/
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
int index;
int len;
#endif
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
unsigned short ver;
#endif
if (ctermm2()) {
- unsigned char str[4];
+ char str[4];
/*
* Read board-id and save in env-variable
int result;
int i;
unsigned char ow_id[6];
- unsigned char str[32];
+ char str[32];
unsigned char ow_crc;
/*
IPaddr_t ipaddr;
buf = malloc(CFG_ENV_SIZE_2);
- if (eeprom_read(CFG_I2C_EEPROM_ADDR_2, 0, buf, CFG_ENV_SIZE_2)) {
+ if (eeprom_read(CFG_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CFG_ENV_SIZE_2)) {
puts("\nError reading backplane EEPROM!\n");
} else {
- crc = crc32(0, buf+4, CFG_ENV_SIZE_2-4);
+ crc = crc32(0, (uchar *)(buf+4), CFG_ENV_SIZE_2-4);
if (crc != *(ulong *)buf) {
printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(ulong *)buf);
return -1;
int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
char *buf;
- unsigned char str[32];
+ char str[32];
ulong crc;
if (argc < 2) {
memset(buf, 0, CFG_ENV_SIZE_2);
sprintf(str, "bp_ip=%s", argv[1]);
strcpy(buf+4, str);
- crc = crc32(0, buf+4, CFG_ENV_SIZE_2-4);
+ crc = crc32(0, (uchar *)(buf+4), CFG_ENV_SIZE_2-4);
*(ulong *)buf = crc;
- if (eeprom_write(CFG_I2C_EEPROM_ADDR_2, 0, buf, CFG_ENV_SIZE_2)) {
+ if (eeprom_write(CFG_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CFG_ENV_SIZE_2)) {
puts("\nError writing backplane EEPROM!\n");
}
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
--- /dev/null
+
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+# Objects for Xilinx JTAG programming (CPLD)
+# CPLD = ../common/xilinx_jtag/lenval.o \
+# ../common/xilinx_jtag/micro.o \
+# ../common/xilinx_jtag/ports.o
+
+# OBJS = $(BOARD).o flash.o $(CPLD)
+OBJS = $(BOARD).o strataflash.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# IceCube board:
+#
+# Valid values for TEXT_BASE are:
+#
+# 0xFFF00000 boot high (standard configuration)
+# 0xFF000000 boot low for 16 MiB boards
+# 0xFF800000 boot low for 8 MiB boards
+# 0x00100000 boot from RAM (for testing only)
+#
+
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+## Standard: boot high
+TEXT_BASE = 0xFFF00000
+## For testing: boot from RAM
+# TEXT_BASE = 0x00100000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * cpci5200.c - main board support/init for the esd cpci5200.
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <command.h>
+
+#include "mt46v16m16-75.h"
+
+void init_ata_reset(void);
+
+static void sdram_start(int hi_addr)
+{
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+ /* unlock mode register */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL =
+ SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* precharge all banks */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL =
+ SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* set mode register: extended mode */
+ *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+ __asm__ volatile ("sync");
+
+ /* set mode register: reset DLL */
+ *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+ __asm__ volatile ("sync");
+
+ /* precharge all banks */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL =
+ SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* auto refresh */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL =
+ SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* set mode register */
+ *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+ __asm__ volatile ("sync");
+
+ /* normal operation */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+ __asm__ volatile ("sync");
+}
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ * is something else than 0x00000000.
+ */
+
+long int initdram(int board_type)
+{
+ ulong dramsize = 0;
+ ulong test1, test2;
+
+ /* setup SDRAM chip selects */
+ *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
+ __asm__ volatile ("sync");
+
+ /* setup config registers */
+ *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+ *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+ __asm__ volatile ("sync");
+
+ /* set tap delay */
+ *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+ __asm__ volatile ("sync");
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start(0);
+ test1 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000);
+ sdram_start(1);
+ test2 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000);
+
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else {
+ dramsize = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20)) {
+ dramsize = 0;
+ }
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0) {
+ *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+ 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+ /* let SDRAM CS1 start right after CS0 */
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
+ } else {
+#if 0
+ *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+ /* let SDRAM CS1 start right after CS0 */
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
+#else
+ *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+ 0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
+ /* let SDRAM CS1 start right after CS0 */
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */
+#endif
+ }
+
+#if 0
+ /* find RAM size using SDRAM CS1 only */
+ sdram_start(0);
+ get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+ sdram_start(1);
+ get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+ sdram_start(0);
+#endif
+ /* set SDRAM CS1 size according to the amount of RAM found */
+
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+
+ init_ata_reset();
+ return (dramsize);
+}
+
+int checkboard(void)
+{
+ puts("Board: esd CPCI5200 (cpci5200)\n");
+ return 0;
+}
+
+void flash_preinit(void)
+{
+ /*
+ * Now, when we are in RAM, enable flash write
+ * access for detection process.
+ * Note that CS_BOOT cannot be cleared when
+ * executing in flash.
+ */
+ *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+}
+
+void flash_afterinit(ulong size)
+{
+ if (size == 0x02000000) {
+ /* adjust mapping */
+ *(vu_long *) MPC5XXX_BOOTCS_START =
+ *(vu_long *) MPC5XXX_CS0_START =
+ START_REG(CFG_BOOTCS_START | size);
+ *(vu_long *) MPC5XXX_BOOTCS_STOP =
+ *(vu_long *) MPC5XXX_CS0_STOP =
+ STOP_REG(CFG_BOOTCS_START | size, size);
+ }
+}
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void
+ ) {
+ pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+
+#define GPIO_PSC1_4 0x01000000UL
+
+void init_ide_reset(void)
+{
+ debug("init_ide_reset\n");
+
+ /* Configure PSC1_4 as GPIO output for ATA reset */
+ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
+}
+
+void ide_set_reset(int idereset)
+{
+ debug("ide_reset(%d)\n", idereset);
+
+ if (idereset) {
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
+ } else {
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
+ }
+}
+#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
+
+#define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004)
+#define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014)
+
+#define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020)
+#define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028)
+#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
+#define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C)
+
+#define GPIO_WU6 0x40000000UL
+#define GPIO_USB0 0x00010000UL
+#define GPIO_USB9 0x08000000UL
+#define GPIO_USB9S 0x00080000UL
+
+void init_ata_reset(void)
+{
+ debug("init_ata_reset\n");
+
+ /* Configure GPIO_WU6 as GPIO output for ATA reset */
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_WU6;
+ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
+ *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
+ __asm__ volatile ("sync");
+
+ *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
+ *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
+ *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
+ __asm__ volatile ("sync");
+
+ *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
+ *(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
+ __asm__ volatile ("sync");
+
+ if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
+ *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
+ __asm__ volatile ("sync");
+ }
+}
+
+int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned int addr;
+ unsigned int size;
+ int i;
+ volatile unsigned long *ptr;
+
+ addr = simple_strtol(argv[1], NULL, 16);
+ size = simple_strtol(argv[2], NULL, 16);
+
+ printf("\nWriting at addr %08x, size %08x.\n", addr, size);
+
+ while (1) {
+ ptr = (volatile unsigned long *)addr;
+ for (i = 0; i < (size >> 2); i++) {
+ *ptr++ = i;
+ }
+
+ /* Abort if ctrl-c was pressed */
+ if (ctrlc()) {
+ puts("\nAbort\n");
+ return 0;
+ }
+ putc('.');
+ }
+ return 0;
+}
+
+U_BOOT_CMD(writepci, 3, 1, do_writepci,
+ "writepci- Write some data to pcibus\n",
+ "<addr> <size>\n" " - Write some data to pcibus.\n");
--- /dev/null
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR 1 /* is DDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x705f0f00
+#define SDRAM_CONFIG1 0x73722930
+#define SDRAM_CONFIG2 0x47770000
+#define SDRAM_TAPDELAY 0x10000000
+
+#else
+#error CONFIG_MPC5200 not defined
+#endif
#include <common.h>
#include <asm/processor.h>
+#include <asm/cache.h>
#undef DEBUG_FLASH
/*
- * This file implements a Common Flash Interface (CFI) driver for ppcboot.
+ * This file implements a Common Flash Interface (CFI) driver for U-Boot.
* The width of the port and the width of the chips are determined at initialization.
* These widths are used to calculate the address for access CFI data structures.
* It has been tested on an Intel Strataflash implementation.
} cfiword_t;
typedef union {
- unsigned char * cp;
+ unsigned char *cp;
unsigned short *wp;
unsigned long *lp;
} cfiptr_t;
#define NUM_ERASE_REGIONS 4
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
*/
-static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c);
-static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
-static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd);
-static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static void flash_add_byte(flash_info_t * info, cfiword_t * cword, uchar c);
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void *cmdbuf);
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset,
+ uchar cmd);
+static int flash_isequal(flash_info_t * info, int sect, uchar offset,
+ uchar cmd);
static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
static int flash_detect_cfi(flash_info_t * info);
-static ulong flash_get_size (ulong base, int banknum);
-static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
-static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
+static ulong flash_get_size(ulong base, int banknum);
+static int flash_write_cfiword(flash_info_t * info, ulong dest,
+ cfiword_t cword);
+static int flash_full_status_check(flash_info_t * info, ulong sector,
+ ulong tout, char *prompt);
#ifdef CFG_FLASH_USE_BUFFER_WRITE
-static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp,
+ int len);
#endif
/*-----------------------------------------------------------------------
* create an address based on the offset and the port width
*/
-inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset)
+inline uchar *flash_make_addr(flash_info_t * info, int sect, int offset)
{
- return ((uchar *)(info->start[sect] + (offset * info->portwidth)));
+ return ((uchar *) (info->start[sect] + (offset * info->portwidth)));
}
+
/*-----------------------------------------------------------------------
* read a character at a port width address
*/
/*-----------------------------------------------------------------------
* read a short word by swapping for ppc format.
*/
-ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset)
+ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset)
{
- uchar * addr;
+ uchar *addr;
- addr = flash_make_addr(info, sect, offset);
- return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]);
+ addr = flash_make_addr(info, sect, offset);
+ return ((addr[(2 * info->portwidth) - 1] << 8) |
+ addr[info->portwidth - 1]);
}
* read a long word by picking the least significant byte of each maiximum
* port size word. Swap for ppc format.
*/
-ulong flash_read_long(flash_info_t * info, int sect, uchar offset)
+ulong flash_read_long(flash_info_t * info, int sect, uchar offset)
{
- uchar * addr;
+ uchar *addr;
- addr = flash_make_addr(info, sect, offset);
- return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) |
- (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]);
+ addr = flash_make_addr(info, sect, offset);
+ return ((addr[(2 * info->portwidth) - 1] << 24) |
+ (addr[(info->portwidth) - 1] << 16) |
+ (addr[(4 * info->portwidth) - 1] << 8) |
+ addr[(3 * info->portwidth) - 1]);
}
/*-----------------------------------------------------------------------
*/
-unsigned long flash_init (void)
+unsigned long flash_init(void)
{
unsigned long size;
int i;
- unsigned long address;
-
+ unsigned long address;
/* The flash is positioned back to back, with the demultiplexing of the chip
* based on the A24 address line.
size = 0;
/* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
size += flash_info[i].size = flash_get_size(address, i);
address += CFG_FLASH_INCREMENT;
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
- flash_info[0].size, flash_info[i].size<<20);
+ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+ printf
+ ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+ i, flash_info[0].size, flash_info[i].size << 20);
}
}
-#if 0 /* test-only */
+#if 0 /* test-only */
/* Monitor protection ON by default */
#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
- for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+CFG_MONITOR_LEN-1; i++)
+ for (i = 0;
+ flash_info[0].start[i] < CFG_MONITOR_BASE + monitor_flash_len - 1;
+ i++)
(void)flash_real_protect(&flash_info[0], i, 1);
#endif
-#else
- /* monitor protection ON by default */
- flash_protect (FLAG_PROTECT_SET,
- - CFG_MONITOR_LEN,
- - 1, &flash_info[1]);
#endif
return (size);
/*-----------------------------------------------------------------------
*/
-int flash_erase (flash_info_t *info, int s_first, int s_last)
+int flash_erase(flash_info_t * info, int s_first, int s_last)
{
int rcode = 0;
int prot;
int sect;
- if( info->flash_id != FLASH_MAN_CFI) {
- printf ("Can't erase unknown flash type - aborted\n");
+ if (info->flash_id != FLASH_MAN_CFI) {
+ printf("Can't erase unknown flash type - aborted\n");
return 1;
}
if ((s_first < 0) || (s_first > s_last)) {
- printf ("- no sectors to erase\n");
+ printf("- no sectors to erase\n");
return 1;
}
prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
+ for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
} else {
- printf ("\n");
+ printf("\n");
}
-
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
- if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
+ if (flash_full_status_check
+ (info, sect, info->erase_blk_tout, "erase")) {
rcode = 1;
} else
printf(".");
}
}
- printf (" done\n");
+ printf(" done\n");
return rcode;
}
/*-----------------------------------------------------------------------
*/
-void flash_print_info (flash_info_t *info)
+void flash_print_info(flash_info_t * info)
{
int i;
if (info->flash_id != FLASH_MAN_CFI) {
- printf ("missing or unknown FLASH type\n");
+ printf("missing or unknown FLASH type\n");
return;
}
printf("CFI conformant FLASH (%d x %d)",
- (info->portwidth << 3 ), (info->chipwidth << 3 ));
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
- printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
- info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
-#ifdef CFG_FLASH_EMPTY_INFO
- int k;
- int size;
- int erased;
- volatile unsigned long *flash;
-
- /*
- * Check if whole sector is erased
- */
- if (i != (info->sector_count-1))
- size = info->start[i+1] - info->start[i];
- else
- size = info->start[0] + info->size - info->start[i];
- erased = 1;
- flash = (volatile unsigned long *)info->start[i];
- size = size >> 2; /* divide by 4 for longword access */
- for (k=0; k<size; k++)
- {
- if (*flash++ != 0xffffffff)
- {
- erased = 0;
- break;
- }
- }
-
- if ((i % 5) == 0)
- printf ("\n ");
- /* print empty and read-only info */
- printf (" %08lX%s%s",
- info->start[i],
- erased ? " E" : " ",
- info->protect[i] ? "RO " : " ");
-#else
+ (info->portwidth << 3), (info->chipwidth << 3));
+ printf(" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+ printf
+ (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
+ info->erase_blk_tout, info->write_tout, info->buffer_write_tout,
+ info->buffer_size);
+
+ printf(" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " ");
-#endif
+ printf("\n");
+ printf(" %08lX%5s",
+ info->start[i], info->protect[i] ? " (RO)" : " ");
}
- printf ("\n");
+ printf("\n");
return;
}
* 1 - write timeout
* 2 - Flash not erased
*/
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong wp;
ulong cp;
wp = (addr & ~(info->portwidth - 1));
/* handle unaligned start */
- if((aln = addr - wp) != 0) {
+ if ((aln = addr - wp) != 0) {
cword.l = 0;
cp = wp;
- for(i=0;i<aln; ++i, ++cp)
- flash_add_byte(info, &cword, (*(uchar *)cp));
+ for (i = 0; i < aln; ++i, ++cp)
+ flash_add_byte(info, &cword, (*(uchar *) cp));
- for(; (i< info->portwidth) && (cnt > 0) ; i++) {
+ for (; (i < info->portwidth) && (cnt > 0); i++) {
flash_add_byte(info, &cword, *src++);
cnt--;
cp++;
}
- for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
- flash_add_byte(info, &cword, (*(uchar *)cp));
- if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+ for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
+ flash_add_byte(info, &cword, (*(uchar *) cp));
+ if ((rc = flash_write_cfiword(info, wp, cword)) != 0)
return rc;
wp = cp;
}
-
#ifdef CFG_FLASH_USE_BUFFER_WRITE
- while(cnt >= info->portwidth) {
- i = info->buffer_size > cnt? cnt: info->buffer_size;
- if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
+ while (cnt >= info->portwidth) {
+ i = info->buffer_size > cnt ? cnt : info->buffer_size;
+ if ((rc = flash_write_cfibuffer(info, wp, src, i)) != ERR_OK)
return rc;
wp += i;
src += i;
- cnt -=i;
+ cnt -= i;
}
#else
/* handle the aligned part */
- while(cnt >= info->portwidth) {
+ while (cnt >= info->portwidth) {
cword.l = 0;
- for(i = 0; i < info->portwidth; i++) {
+ for (i = 0; i < info->portwidth; i++) {
flash_add_byte(info, &cword, *src++);
}
- if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+ if ((rc = flash_write_cfiword(info, wp, cword)) != 0)
return rc;
wp += info->portwidth;
cnt -= info->portwidth;
}
-#endif /* CFG_FLASH_USE_BUFFER_WRITE */
+#endif /* CFG_FLASH_USE_BUFFER_WRITE */
if (cnt == 0) {
return (0);
}
* handle unaligned tail bytes
*/
cword.l = 0;
- for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) {
+ for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) {
flash_add_byte(info, &cword, *src++);
--cnt;
}
- for (; i<info->portwidth; ++i, ++cp) {
- flash_add_byte(info, & cword, (*(uchar *)cp));
+ for (; i < info->portwidth; ++i, ++cp) {
+ flash_add_byte(info, &cword, (*(uchar *) cp));
}
return flash_write_cfiword(info, wp, cword);
/*-----------------------------------------------------------------------
*/
-int flash_real_protect(flash_info_t *info, long sector, int prot)
+int flash_real_protect(flash_info_t * info, long sector, int prot)
{
int retcode = 0;
flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
- if(prot)
+ if (prot)
flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
else
flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
- if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
- prot?"protect":"unprotect")) == 0) {
+ if ((retcode =
+ flash_full_status_check(info, sector, info->erase_blk_tout,
+ prot ? "protect" : "unprotect")) == 0) {
info->protect[sector] = prot;
/* Intel's unprotect unprotects all locking */
- if(prot == 0) {
+ if (prot == 0) {
int i;
- for(i = 0 ; i<info->sector_count; i++) {
- if(info->protect[i])
+ for (i = 0; i < info->sector_count; i++) {
+ if (info->protect[i])
flash_real_protect(info, i, 1);
}
}
return retcode;
}
+
/*-----------------------------------------------------------------------
* wait for XSR.7 to be set. Time out with an error if it does not.
* This routine does not set the flash to read-array mode.
*/
-static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+static int flash_status_check(flash_info_t * info, ulong sector, ulong tout,
+ char *prompt)
{
ulong start;
/* Wait for command completion */
- start = get_timer (0);
- while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
+ start = get_timer(0);
+ while (!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
if (get_timer(start) > info->erase_blk_tout) {
- printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]);
+ printf("Flash %s timeout at address %lx\n", prompt,
+ info->start[sector]);
flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
return ERR_TIMOUT;
}
}
return ERR_OK;
}
+
/*-----------------------------------------------------------------------
* Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
* This routine sets the flash to read-array mode.
*/
-static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+static int flash_full_status_check(flash_info_t * info, ulong sector,
+ ulong tout, char *prompt)
{
int retcode;
retcode = flash_status_check(info, sector, tout, prompt);
- if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
+ if ((retcode == ERR_OK)
+ && !flash_isequal(info, sector, 0, FLASH_STATUS_DONE)) {
retcode = ERR_INVAL;
- printf("Flash %s error at address %lx\n", prompt,info->start[sector]);
- if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){
+ printf("Flash %s error at address %lx\n", prompt,
+ info->start[sector]);
+ if (flash_isset
+ (info, sector, 0,
+ FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
printf("Command Sequence Error.\n");
- } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
+ } else if (flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)) {
printf("Block Erase Error.\n");
retcode = ERR_NOT_ERASED;
} else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
printf("Locking Error\n");
}
- if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){
+ if (flash_isset(info, sector, 0, FLASH_STATUS_DPS)) {
printf("Block locked.\n");
retcode = ERR_PROTECTED;
}
- if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
+ if (flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
printf("Vpp Low Error.\n");
}
flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
return retcode;
}
+
/*-----------------------------------------------------------------------
*/
-static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c)
+static void flash_add_byte(flash_info_t * info, cfiword_t * cword, uchar c)
{
- switch(info->portwidth) {
+ switch (info->portwidth) {
case FLASH_CFI_8BIT:
cword->c = c;
break;
}
}
-
/*-----------------------------------------------------------------------
* make a proper sized command based on the port and chip widths
*/
-static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void *cmdbuf)
{
int i;
- uchar *cp = (uchar *)cmdbuf;
- for(i=0; i< info->portwidth; i++)
- *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
+ uchar *cp = (uchar *) cmdbuf;
+ for (i = 0; i < info->portwidth; i++)
+ *cp++ = ((i + 1) % info->chipwidth) ? '\0' : cmd;
}
/*
* Write a proper sized command to the correct address
*/
-static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd)
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset,
+ uchar cmd)
{
volatile cfiptr_t addr;
cfiword_t cword;
addr.cp = flash_make_addr(info, sect, offset);
flash_make_cmd(info, cmd, &cword);
- switch(info->portwidth) {
+ switch (info->portwidth) {
case FLASH_CFI_8BIT:
*addr.cp = cword.c;
break;
int retval;
cptr.cp = flash_make_addr(info, sect, offset);
flash_make_cmd(info, cmd, &cword);
- switch(info->portwidth) {
+ switch (info->portwidth) {
case FLASH_CFI_8BIT:
retval = (cptr.cp[0] == cword.c);
break;
}
return retval;
}
+
/*-----------------------------------------------------------------------
*/
static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
int retval;
cptr.cp = flash_make_addr(info, sect, offset);
flash_make_cmd(info, cmd, &cword);
- switch(info->portwidth) {
+ switch (info->portwidth) {
case FLASH_CFI_8BIT:
retval = ((cptr.cp[0] & cword.c) == cword.c);
break;
* detect if flash is compatible with the Common Flash Interface (CFI)
* http://www.jedec.org/download/search/jesd68.pdf
*
-*/
+ */
static int flash_detect_cfi(flash_info_t * info)
{
- for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT;
- info->portwidth <<= 1) {
- for(info->chipwidth =FLASH_CFI_BY8;
- info->chipwidth <= info->portwidth;
- info->chipwidth <<= 1) {
+ for (info->portwidth = FLASH_CFI_8BIT;
+ info->portwidth <= FLASH_CFI_32BIT; info->portwidth <<= 1) {
+ for (info->chipwidth = FLASH_CFI_BY8;
+ info->chipwidth <= info->portwidth;
+ info->chipwidth <<= 1) {
flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
- flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
- if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
- flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
- flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y'))
+ flash_write_cmd(info, 0, FLASH_OFFSET_CFI,
+ FLASH_CMD_CFI);
+ if (flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
+ && flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1,
+ 'R')
+ && flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2,
+ 'Y'))
return 1;
}
}
return 0;
}
+
/*
* The following code cannot be run from FLASH!
*
*/
-static ulong flash_get_size (ulong base, int banknum)
+static ulong flash_get_size(ulong base, int banknum)
{
- flash_info_t * info = &flash_info[banknum];
+ flash_info_t *info = &flash_info[banknum];
int i, j;
int sect_cnt;
unsigned long sector;
unsigned long tmp;
- int size_ratio;
+ int size_ratio = 0;
uchar num_erase_regions;
- int erase_region_size;
- int erase_region_count;
+ int erase_region_size;
+ int erase_region_count;
info->start[0] = base;
-
- if(flash_detect_cfi(info)){
-#ifdef DEBUG_FLASH
- printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
+#if 0
+ invalidate_dcache_range(base, base + 0x400);
#endif
+ if (flash_detect_cfi(info)) {
+
size_ratio = info->portwidth / info->chipwidth;
- num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
-#ifdef DEBUG_FLASH
- printf("found %d erase regions\n", num_erase_regions);
-#endif
+ num_erase_regions =
+ flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
+
sect_cnt = 0;
sector = base;
- for(i = 0 ; i < num_erase_regions; i++) {
- if(i > NUM_ERASE_REGIONS) {
+ for (i = 0; i < num_erase_regions; i++) {
+ if (i > NUM_ERASE_REGIONS) {
printf("%d erase regions found, only %d used\n",
num_erase_regions, NUM_ERASE_REGIONS);
break;
}
- tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS);
- erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
+ tmp =
+ flash_read_long(info, 0,
+ FLASH_OFFSET_ERASE_REGIONS);
+ erase_region_size =
+ (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
tmp >>= 16;
- erase_region_count = (tmp & 0xffff) +1;
- for(j = 0; j< erase_region_count; j++) {
+ erase_region_count = (tmp & 0xffff) + 1;
+ for (j = 0; j < erase_region_count; j++) {
info->start[sect_cnt] = sector;
sector += (erase_region_size * size_ratio);
- info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
+ info->protect[sect_cnt] =
+ flash_isset(info, sect_cnt,
+ FLASH_OFFSET_PROTECT,
+ FLASH_STATUS_PROTECT);
sect_cnt++;
}
}
info->sector_count = sect_cnt;
/* multiply the size by the number of chips */
- info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
- info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
+ info->size =
+ (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) *
+ size_ratio;
+ info->buffer_size =
+ (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
- info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
+ info->erase_blk_tout =
+ (tmp *
+ (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
- info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
+ info->buffer_write_tout =
+ (tmp *
+ (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
- info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
+ info->write_tout =
+ (tmp *
+ (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT))) /
+ 1000;
info->flash_id = FLASH_MAN_CFI;
}
flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
- return(info->size);
+#ifdef DEBUG_FLASH
+ printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
+#endif
+#ifdef DEBUG_FLASH
+ printf("found %d erase regions\n", num_erase_regions);
+#endif
+#ifdef DEBUG_FLASH
+ printf("size=%08x sectors=%08x \n", info->size, info->sector_count);
+#endif
+ return (info->size);
}
-
/*-----------------------------------------------------------------------
*/
-static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
+static int flash_write_cfiword(flash_info_t * info, ulong dest, cfiword_t cword)
{
cfiptr_t ctladdr;
int flag;
ctladdr.cp = flash_make_addr(info, 0, 0);
- cptr.cp = (uchar *)dest;
-
+ cptr.cp = (uchar *) dest;
/* Check if Flash is (sufficiently) erased */
- switch(info->portwidth) {
+ switch (info->portwidth) {
case FLASH_CFI_8BIT:
flag = ((cptr.cp[0] & cword.c) == cword.c);
break;
flag = ((cptr.wp[0] & cword.w) == cword.w);
break;
case FLASH_CFI_32BIT:
- flag = ((cptr.lp[0] & cword.l) == cword.l);
+ flag = ((cptr.lp[0] & cword.l) == cword.l);
break;
default:
return 2;
}
- if(!flag)
+ if (!flag)
return 2;
/* Disable interrupts which might cause a timeout here */
flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
- switch(info->portwidth) {
+ switch (info->portwidth) {
case FLASH_CFI_8BIT:
cptr.cp[0] = cword.c;
break;
}
/* re-enable interrupts if necessary */
- if(flag)
+ if (flag)
enable_interrupts();
return flash_full_status_check(info, 0, info->write_tout, "write");
* when the passed address is greater or equal to the sector address
* we have a match
*/
-static int find_sector(flash_info_t *info, ulong addr)
+static int find_sector(flash_info_t * info, ulong addr)
{
int sector;
- for(sector = info->sector_count - 1; sector >= 0; sector--) {
- if(addr >= info->start[sector])
+ for (sector = info->sector_count - 1; sector >= 0; sector--) {
+ if (addr >= info->start[sector])
break;
}
return sector;
}
-static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp,
+ int len)
{
int sector;
volatile cfiptr_t dst;
src.cp = cp;
- dst.cp = (uchar *)dest;
+ dst.cp = (uchar *) dest;
sector = find_sector(info, dest);
flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
- if((retcode = flash_status_check(info, sector, info->buffer_write_tout,
- "write to buffer")) == ERR_OK) {
- switch(info->portwidth) {
+ if ((retcode = flash_status_check(info, sector, info->buffer_write_tout,
+ "write to buffer")) == ERR_OK) {
+ switch (info->portwidth) {
case FLASH_CFI_8BIT:
cnt = len;
break;
return ERR_INVAL;
break;
}
- flash_write_cmd(info, sector, 0, (uchar)cnt-1);
- while(cnt-- > 0) {
- switch(info->portwidth) {
+ flash_write_cmd(info, sector, 0, (uchar) cnt - 1);
+ while (cnt-- > 0) {
+ switch (info->portwidth) {
case FLASH_CFI_8BIT:
*dst.cp++ = *src.cp++;
break;
break;
}
}
- flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
- retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
- "buffer write");
+ flash_write_cmd(info, sector, 0,
+ FLASH_CMD_WRITE_BUFFER_CONFIRM);
+ retcode =
+ flash_full_status_check(info, sector,
+ info->buffer_write_tout,
+ "buffer write");
}
flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
return retcode;
}
-#endif /* CFG_USE_FLASH_BUFFER_WRITE */
+#endif /* CFG_USE_FLASH_BUFFER_WRITE */
/*
- * (C) Copyright 2002,2003, Motorola,Inc.
- * Xianghua Xiao, X.Xiao@motorola.com.
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
__DYNAMIC = 0; */
SECTIONS
{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/mpc85xx/start.o (.bootpg)
- board/tqm8560/init.o (.bootpg)
- } = 0xffff
-
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
.plt : { *(.plt) }
- .text :
+ .text :
{
- cpu/mpc85xx/start.o (.text)
- board/tqm8560/init.o (.text)
- cpu/mpc85xx/traps.o (.text)
- cpu/mpc85xx/interrupts.o (.text)
- cpu/mpc85xx/cpu_init.o (.text)
- cpu/mpc85xx/cpu.o (.text)
- cpu/mpc85xx/speed.o (.text)
- cpu/mpc85xx/pci.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
+ cpu/mpc5xxx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
+ . = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
- .fini : { *(.fini) } =0
+ .fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
+ . = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
- .data :
+ .data :
{
*(.data)
*(.data1)
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
- . = ALIGN(256);
+ . = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
- . = ALIGN(256);
+ . = ALIGN(4096);
__init_end = .;
__bss_start = .;
- .bss :
+ .bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
int mem_test_data (void)
{
unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
- unsigned long long temp64;
+ unsigned long long temp64 = 0;
int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
int i;
unsigned int hi, lo;
unsigned long long wmask, short read, short write)
{
unsigned int i;
- unsigned long long temp;
+ unsigned long long temp = 0;
unsigned int hitemp, lotemp, himask, lomask;
for (i = 0; i < size; i++) {
dev->send = (void *) db64360_eth_transmit;
dev->recv = (void *) db64360_eth_poll;
- dev->priv = (void *) ethernet_private =
+ ethernet_private =
calloc (sizeof (*ethernet_private), 1);
+ dev->priv = (void *) ethernet_private;
if (!ethernet_private) {
printf ("%s: %s allocation failure, %s\n",
__FUNCTION__, dev->name,
memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
/* set pointer to memory for stats data structure etc... */
- ethernet_private->port_private = (void *) port_private =
+ port_private =
calloc (sizeof (*ethernet_private), 1);
+ ethernet_private->port_private = (void *)port_private;
if (!port_private) {
printf ("%s: %s allocation failure, %s\n",
__FUNCTION__, dev->name,
{0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
};
+#ifdef CONFIG_USE_CPCIDVI
+typedef struct {
+ unsigned int base;
+ unsigned int init;
+} GT_CPCIDVI_ROM_T;
+
+static GT_CPCIDVI_ROM_T gt_cpcidvi_rom = {0, 0};
+#endif
#ifdef DEBUG
static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
unsigned int offset =
(bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
- pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
- 0x0);
- pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
- &bar_response);
+ pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
+ 0x0);
+ pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
+ &bar_response);
pciauto_region_allocate (bar_response &
PCI_BASE_ADDRESS_SPACE_IO ? hose->
pci_io : hose->pci_mem, ide_bar[bar],
&bar_value);
- pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
- bar_value);
+ pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + bar * 4,
+ bar_value);
}
}
+#ifdef CONFIG_USE_CPCIDVI
+static void gt_setup_cpcidvi (struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *entry)
+{
+ u32 bar_value, pci_response;
+
+ pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response);
+ pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
+ pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pci_response);
+ pciauto_region_allocate (hose->pci_mem, 0x01000000, &bar_value);
+ pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, (bar_value & 0xffffff00));
+ pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, 0x0);
+ pciauto_region_allocate (hose->pci_mem, 0x40000, &bar_value);
+ pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, (bar_value & 0xffffff00) | 0x01);
+ gt_cpcidvi_rom.base = bar_value & 0xffffff00;
+ gt_cpcidvi_rom.init = 1;
+}
+
+unsigned char gt_cpcidvi_in8(unsigned int offset)
+{
+ unsigned char data;
+
+ if (gt_cpcidvi_rom.init == 0) {
+ return(0);
+ }
+ data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base);
+ return(data);
+}
+
+void gt_cpcidvi_out8(unsigned int offset, unsigned char data)
+{
+ unsigned int off;
+
+ if (gt_cpcidvi_rom.init == 0) {
+ return;
+ }
+ off = data;
+ off = ((off << 3) & 0x7f8) + (offset & 0x4) + 0x3e000 + gt_cpcidvi_rom.base;
+ in8(off);
+ return;
+}
+#endif
/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */
/* and is curently not called *. */
#endif
struct pci_config_table gt_config_table[] = {
+#ifdef CONFIG_USE_CPCIDVI
+ {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030, PCI_CLASS_DISPLAY_VGA,
+ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_cpcidvi},
+#endif
{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
-
{}
};
#ifdef CONFIG_PCI_PNP
unsigned int bar;
#endif
-
#ifdef DEBUG
gt_pci_bus_mode_display (PCI_HOST0);
#endif
+#ifdef CONFIG_USE_CPCIDVI
+ gt_cpcidvi_rom.init = 0;
+ gt_cpcidvi_rom.base = 0;
+#endif
+
+ pci0_hose.config_table = gt_config_table;
+ pci1_hose.config_table = gt_config_table;
+
+#ifdef CONFIG_USE_CPCIDVI
+ gt_config_table[0].config_device = gt_setup_cpcidvi;
+#endif
+ gt_config_table[1].config_device = gt_setup_ide;
pci0_hose.first_busno = 0;
pci0_hose.last_busno = 0xff;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
int index;
int len;
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof (str));
puts ("Board: ");
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
for (i = 0; i < 4; i++) {
pci_read_config_dword (CFG_PCI9054_DEV_FN,
l * 16 + i * 4,
- &val);
+ (unsigned int *)&val);
printf ("%08x ", val);
}
printf ("\n");
{
int index;
int len;
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof (str));
int fpga;
unsigned short val;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
unsigned char trans[16] = {0x0,0x8,0x4,0xc,0x2,0xa,0x6,0xe,
0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf};
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
+ cpu/ppc4xx/4xx_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
int index;
int len;
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof (str));
puts ("Board: ");
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
- 0x1f,0x8b,0x08,0x08,0x00,0x37,0x39,0x42,0x00,0x03,0x68,0x68,0x34,0x30,0x35,0x5f,
- 0x31,0x5f,0x30,0x34,0x2e,0x62,0x69,0x74,0x00,0xec,0xfd,0x7f,0x7c,0x54,0xe5,0x99,
- 0x37,0x8e,0x5f,0xe7,0x3e,0x27,0xe1,0x64,0xce,0x24,0x73,0x98,0x04,0x1b,0x01,0xf1,
- 0x64,0x12,0x70,0xa0,0x93,0x30,0x4c,0x10,0x31,0xc6,0xc9,0x61,0x12,0xe9,0x08,0x54,
- 0xa6,0xd6,0xed,0xb2,0x5d,0x3f,0xdd,0x81,0xd2,0x6e,0xda,0x8f,0x75,0xa3,0xed,0xb3,
- 0x4b,0x5d,0xd7,0xde,0x99,0x04,0x98,0x10,0x84,0x01,0xa9,0x46,0xcb,0xe3,0x0e,0x31,
- 0x6a,0x54,0xda,0x0e,0x01,0x25,0x28,0xc5,0x13,0x8c,0x1a,0x20,0x62,0x6a,0x69,0x17,
- 0xad,0xd5,0x41,0x83,0x06,0x1b,0x35,0x58,0xb4,0x09,0x3f,0xbf,0xd7,0x75,0x26,0xc9,
- 0x9c,0x09,0xdd,0x7d,0x76,0x3f,0xcf,0xeb,0xf3,0x7d,0xed,0xf7,0xf5,0x7d,0xb2,0x7f,
- 0xec,0xdd,0x33,0x37,0xc7,0x73,0xee,0x73,0xdf,0xd7,0xf5,0xbe,0xde,0xd7,0x2f,0xc8,
- 0x71,0x0c,0xa5,0xfe,0x0f,0x40,0x58,0x09,0x8e,0xda,0xda,0xf9,0xde,0x6b,0xff,0x6e,
- 0xde,0xdf,0x79,0xe7,0x97,0xdd,0xf9,0xed,0xd5,0xb0,0x0a,0x14,0xdf,0x0f,0xaf,0xf5,
- 0x7e,0xe7,0x47,0x77,0xcd,0x9b,0x3f,0x1f,0xbe,0x8d,0xff,0xcb,0xeb,0xbd,0x76,0xae,
- 0xb7,0x7c,0xee,0xbc,0xeb,0x60,0x35,0xe4,0x78,0x17,0x56,0x5c,0x3b,0xaf,0xc2,0x77,
- 0x3d,0x7c,0x07,0x84,0xf2,0xb6,0x4b,0xf8,0xf7,0xf4,0xc3,0x7f,0xf5,0x5d,0x2f,0x70,
- 0x01,0x00,0x26,0x79,0x85,0x30,0xfd,0x7f,0xc5,0x2b,0x68,0x02,0xf0,0xaa,0x52,0x2f,
- 0x18,0xf4,0xbf,0x61,0xf4,0xf7,0x1c,0x2f,0x68,0xd6,0xff,0x2d,0x78,0x41,0x87,0x10,
- 0xe8,0x1b,0x55,0x27,0xfc,0x27,0xfe,0x64,0x89,0x8f,0x0d,0xff,0x53,0xf3,0x61,0x7c,
- 0xfe,0xa5,0xc3,0xfc,0xdf,0x9d,0x94,0xfe,0xab,0xfa,0x2c,0x3e,0x3a,0x52,0x99,0xf7,
- 0x7f,0x3d,0x5d,0x08,0xc2,0xd8,0x5d,0x3f,0x7d,0xeb,0x3f,0x73,0xff,0xeb,0xbe,0x18,
- 0xbb,0xff,0x7f,0x75,0x3e,0xa8,0xff,0x89,0xe9,0xf8,0xbe,0x63,0x83,0x4f,0x55,0x41,
- 0xc7,0x7f,0x93,0x0d,0x02,0x87,0x30,0x14,0xfe,0x3b,0x83,0xeb,0xba,0xc7,0xe6,0x1b,
- 0x6b,0x87,0x4b,0xde,0xee,0xba,0xee,0xe5,0xdc,0x3d,0xa2,0xbf,0xe6,0xc3,0x98,0xaf,
- 0xdb,0xde,0x2b,0xde,0x57,0x73,0x2e,0x56,0xd5,0xbf,0x6c,0xa4,0xf8,0x22,0x0c,0x86,
- 0x77,0x73,0xfb,0x29,0x71,0x48,0xaa,0x1b,0x9b,0x5f,0x78,0x4a,0x8b,0x82,0x2b,0x2a,
- 0x77,0x30,0x0f,0x6f,0xd6,0x5a,0x7b,0x96,0x44,0xf2,0x77,0xf2,0x17,0xb4,0xb2,0x1e,
- 0x9b,0xcf,0x35,0xa8,0x75,0xd6,0xb9,0x22,0xb6,0x56,0x36,0x24,0x8d,0xad,0x62,0x4f,
- 0x56,0x3b,0x9f,0xaa,0x95,0x18,0x39,0x09,0x66,0x6f,0xfc,0xb2,0x6b,0x4e,0x4f,0x90,
- 0x3b,0xed,0xd1,0xdd,0x9a,0xa7,0x47,0xf6,0xb1,0xde,0xc6,0x56,0xd0,0x82,0xb2,0x8b,
- 0x7d,0x26,0x8c,0xdf,0x5f,0x6a,0xaf,0x69,0x06,0x57,0xa3,0xdc,0xce,0x3c,0xd0,0xdc,
- 0x38,0xa7,0x6f,0x2a,0x67,0x3b,0x85,0x17,0xa4,0x32,0xc3,0x96,0x60,0x83,0xf0,0x3c,
- 0xb8,0x16,0xd9,0xe2,0x6c,0x08,0xdf,0x24,0xf5,0xb7,0x68,0x4a,0x2d,0xef,0x93,0x17,
- 0xe8,0xa5,0xfb,0x9b,0x3d,0xf2,0x09,0xa3,0x22,0xbc,0xd1,0x55,0xec,0x91,0xcf,0x49,
- 0x7e,0xc3,0x9e,0x10,0x07,0xd5,0x53,0x89,0x8e,0xf8,0xc6,0x78,0xe0,0x18,0x8c,0xdd,
- 0x3f,0x2e,0x74,0xc0,0x05,0xed,0x46,0xc3,0x91,0x98,0x7c,0x5e,0xbe,0xc0,0xfe,0x29,
- 0xe8,0x30,0xc4,0xf3,0xf2,0x25,0xa8,0x32,0x1c,0x43,0xdf,0x3e,0x0f,0x23,0xf0,0x62,
- 0x70,0x73,0x92,0x0d,0x8c,0xdf,0xdf,0x50,0x77,0xc2,0x59,0x56,0x61,0xe4,0x6e,0x13,
- 0x77,0xe2,0xaf,0xbe,0xbe,0xbc,0x88,0xe2,0xe1,0x7f,0x94,0x7d,0x3d,0x8e,0x84,0xe8,
- 0x81,0x3f,0xc9,0xde,0xad,0x8e,0x56,0x31,0x01,0xda,0xe8,0xfc,0xe3,0x59,0x12,0xec,
- 0x03,0xd7,0x79,0x79,0x26,0x3e,0x7f,0x8b,0xa4,0xdd,0x9e,0xbb,0x91,0x95,0xaa,0xcd,
- 0x30,0x67,0x48,0x49,0x38,0x3d,0xf0,0x02,0xb8,0x74,0xa5,0x7d,0xc3,0x02,0xdc,0xfd,
- 0x63,0xef,0x1b,0x54,0x13,0x93,0xb5,0x64,0x8e,0x37,0x7b,0x27,0xec,0x82,0xb0,0xa1,
- 0x48,0xec,0xfe,0x9a,0x72,0x58,0x35,0xa4,0x78,0x99,0x1d,0x12,0xaa,0xd6,0xa8,0x68,
- 0x6c,0xa1,0x14,0x1a,0x9d,0x3f,0x1c,0xfa,0xa6,0xfe,0x2c,0x2f,0x6a,0x0b,0xae,0xc9,
- 0x9e,0x01,0x57,0xc5,0x1e,0xeb,0x6f,0x5a,0x12,0x39,0x50,0xb3,0x97,0xcf,0x1e,0x58,
- 0xba,0x86,0xcd,0x80,0x3d,0xbc,0x28,0xac,0x9c,0x62,0x95,0xe3,0xf7,0x0f,0xca,0x41,
- 0x78,0x9e,0xf9,0x8c,0xd2,0x85,0xe2,0x46,0x7e,0x3a,0xe9,0x1d,0xc8,0xe3,0xe2,0x2f,
- 0xf8,0x39,0xee,0x7d,0x6f,0x92,0x57,0xb4,0xc3,0x67,0x82,0x37,0xea,0xd0,0xc4,0xad,
- 0x6c,0x6c,0x3f,0xe8,0x53,0x3a,0xd5,0x0b,0xea,0x73,0xdc,0x31,0x24,0x9e,0x87,0x37,
- 0x85,0x1b,0x79,0xde,0xc1,0xa5,0x77,0xf0,0x23,0x2a,0xad,0x8f,0x72,0x5e,0xbf,0xa0,
- 0x56,0xe9,0x9b,0xc3,0x4a,0x5f,0xf6,0xd8,0xfa,0xc8,0x6a,0x1b,0x1c,0x07,0xbf,0xb1,
- 0x2c,0x91,0xef,0x51,0x47,0x20,0xa1,0x4f,0xf7,0x8a,0x3b,0xa5,0x23,0xf5,0xbe,0x2e,
- 0x47,0xa2,0x7a,0x50,0xde,0x07,0x3e,0xee,0x89,0xe7,0xcc,0x19,0x5f,0xff,0x1e,0x75,
- 0x1b,0x64,0xb1,0x52,0xc3,0x5d,0xe7,0x9c,0x0e,0xcf,0x42,0x91,0xfe,0x4d,0x5d,0x38,
- 0xaf,0xae,0x87,0x22,0x43,0xa9,0x63,0x6f,0xc3,0x01,0x98,0xad,0xcb,0x61,0xe6,0x93,
- 0xc6,0xee,0xaf,0xc1,0x3a,0x35,0x9b,0x7b,0x4e,0x04,0x17,0xba,0xbe,0x05,0xbf,0x8a,
- 0xfe,0x7d,0xb2,0xa5,0xc7,0xf5,0x28,0x3c,0xc4,0x67,0x26,0x95,0x35,0xec,0x1d,0x58,
- 0x5f,0x5f,0x14,0x97,0x07,0x9c,0xe1,0xf1,0xf5,0xaf,0x95,0xd6,0xb9,0xea,0xfb,0x3c,
- 0xdd,0xb2,0xd7,0xb6,0x0c,0x76,0x49,0x25,0x49,0x9b,0x68,0xeb,0x85,0x07,0xa0,0xc4,
- 0xc0,0xf5,0xec,0x15,0x76,0xc3,0x9c,0x3b,0x64,0x8d,0xdd,0x3a,0xbe,0x3f,0x07,0x84,
- 0x73,0xfc,0x28,0xab,0x8a,0xdb,0x07,0x26,0xd5,0xc2,0x17,0xea,0x75,0x9d,0xf6,0x81,
- 0x69,0xed,0xec,0x2d,0xf8,0x8c,0x3b,0xe2,0xe2,0xc0,0xe4,0xa3,0x7a,0x39,0xb7,0x27,
- 0xc5,0x8a,0xf1,0xe7,0x09,0x0a,0x78,0x59,0xf3,0x6b,0x57,0xaf,0x9d,0x14,0x87,0x61,
- 0x5c,0x5a,0x5c,0xcf,0xa4,0x3c,0x10,0xa8,0x00,0x07,0x0e,0xb2,0x86,0x6d,0x7e,0xd8,
- 0xcc,0xc5,0xad,0x30,0x76,0x7f,0x19,0xd6,0xc1,0x21,0xb8,0xaf,0xc6,0xde,0x32,0x69,
- 0x96,0x3c,0x02,0xf3,0xf5,0xdc,0x98,0x58,0x42,0x57,0xf4,0x49,0x31,0xb1,0x5f,0x1a,
- 0x11,0x7c,0xb5,0xf6,0x47,0x6c,0x6c,0xfc,0x79,0xb8,0xfa,0xf7,0xc2,0x9b,0x7a,0x59,
- 0xa8,0xf4,0x11,0xe5,0xef,0x71,0xf5,0x5a,0xf5,0xb9,0xdb,0xc4,0xd5,0xf0,0xa6,0xeb,
- 0xbe,0x90,0xb2,0x8d,0x7d,0x08,0xfb,0x74,0x57,0x58,0x56,0x1d,0xe1,0x71,0xb1,0xb0,
- 0x30,0x6b,0xe6,0x4d,0x4f,0xe9,0x1e,0x5d,0x9e,0x3c,0x6b,0xa6,0xbe,0x8f,0xcd,0xd2,
- 0x7f,0x5c,0xe0,0x92,0xa0,0x49,0xb8,0x13,0xe7,0x3b,0x4f,0xde,0xb4,0x43,0x77,0x19,
- 0x72,0x2c,0xfb,0x95,0xf1,0xfd,0xa0,0x15,0x64,0xe5,0xec,0x58,0xe4,0xe9,0x93,0x0b,
- 0xb2,0xb3,0xa4,0x7d,0xba,0x16,0x9a,0x56,0xc0,0x6e,0x12,0xb6,0x04,0x6a,0x43,0x4a,
- 0x01,0x7b,0x59,0xd8,0xa5,0xc7,0x43,0xf2,0xb6,0xec,0x83,0xc2,0xd8,0x7e,0x58,0x93,
- 0x1b,0x66,0xed,0xac,0x0c,0x64,0xce,0x34,0x7c,0xdf,0x05,0x90,0xcb,0x45,0x0d,0x0c,
- 0x28,0x13,0xe8,0x7d,0xf1,0x8a,0x17,0x3c,0x5c,0xdc,0x24,0x8e,0xed,0xcf,0x96,0xac,
- 0xcf,0xe1,0x0f,0x50,0x15,0x72,0x1c,0x13,0xcf,0xe0,0xf7,0x7d,0x31,0xb4,0xbc,0x4f,
- 0xec,0xc7,0x83,0xe3,0xd7,0x1d,0xf8,0xbe,0x70,0xa9,0x06,0x7f,0x0a,0x89,0xb3,0xb2,
- 0xc7,0xf6,0x43,0x61,0x56,0xbf,0x7e,0x08,0x7c,0xcb,0x37,0xe2,0xaf,0xea,0x21,0xdd,
- 0x77,0x93,0x5d,0xc5,0xf5,0x19,0x81,0x7b,0x74,0xfb,0x16,0xb1,0x44,0x3f,0xe2,0xf6,
- 0x2d,0xb6,0xc7,0x26,0xbd,0x32,0xbe,0x7f,0x16,0x16,0x9e,0x60,0x51,0xad,0xb5,0x50,
- 0x6e,0x5c,0x97,0x8c,0x44,0xf1,0x75,0x64,0x6e,0xd3,0x0a,0x3a,0xa1,0x02,0xdc,0x7c,
- 0x69,0x98,0x7e,0x52,0xf3,0x0c,0x76,0x74,0x7c,0x3d,0x83,0x59,0xdb,0x8c,0xb5,0xb3,
- 0x8b,0x83,0xd1,0xaf,0x07,0x8e,0xcd,0xbc,0x1f,0x8a,0x82,0x3d,0xdf,0x6c,0x2d,0x68,
- 0xbf,0xd6,0x5d,0xba,0x44,0x0e,0xb1,0x82,0xc6,0xb5,0xee,0x22,0x3d,0xe7,0xd6,0xc8,
- 0xd6,0x71,0xf9,0xd3,0x22,0x6d,0x73,0xae,0xe5,0xc5,0xba,0x7c,0x9c,0x1d,0x53,0xef,
- 0xd7,0x1f,0x0b,0x15,0xde,0xea,0x9c,0x2f,0xfd,0x0a,0x4a,0xf5,0x60,0x88,0xdd,0x26,
- 0xaf,0xd5,0x8a,0x42,0x4b,0xfa,0x9c,0xaf,0x8c,0xef,0x87,0xf8,0xe4,0xef,0x34,0x1e,
- 0x5a,0xe5,0xd4,0xed,0x0f,0xb2,0x7e,0x38,0x24,0xf8,0xea,0x3c,0xf4,0x7d,0x47,0x84,
- 0xfb,0x74,0x7c,0xa3,0x12,0xa9,0x09,0x7c,0x61,0xfc,0xe2,0x03,0xe3,0xf2,0xb3,0x67,
- 0x51,0x9b,0x36,0x22,0xfb,0x6b,0xe7,0xc6,0xf2,0x71,0x59,0xe4,0xfd,0x4b,0xe6,0xc6,
- 0xcc,0xf5,0xa9,0xa0,0xf5,0x69,0x83,0x11,0xee,0x0f,0x3a,0x62,0x0d,0x67,0xc7,0xe5,
- 0x8f,0xac,0xee,0x10,0x7a,0x74,0x1f,0xd8,0x71,0xd9,0x0b,0x7b,0x60,0x81,0xea,0xe1,
- 0xc5,0x9a,0xd4,0x23,0xf8,0x61,0x19,0xad,0x7f,0x4f,0x8d,0x0f,0x82,0x46,0xfe,0x12,
- 0x69,0x6c,0xff,0xbb,0xb3,0xdc,0xec,0x30,0x68,0xdc,0x16,0x9f,0xe6,0xce,0x8e,0xe8,
- 0xae,0x58,0x5e,0x9c,0xb5,0xc3,0x5b,0x50,0xc6,0xed,0xed,0xce,0x01,0xd8,0x00,0x73,
- 0xf0,0x27,0xd1,0x36,0xbe,0x1f,0xdc,0xd2,0x72,0x78,0xc0,0x70,0x1b,0xb2,0x37,0x7b,
- 0x19,0x0e,0x34,0xa3,0xd0,0x9b,0x6d,0x17,0x1a,0xe0,0x8e,0x64,0x8e,0x9f,0xbd,0xce,
- 0x1b,0xb8,0x66,0xc8,0x0b,0x99,0x0d,0xc6,0xbe,0x2f,0x57,0x6f,0xd7,0xd6,0xd7,0x14,
- 0x73,0xb9,0x36,0x32,0x1d,0x1e,0x5a,0x54,0xd4,0x65,0xeb,0x63,0x0f,0x66,0x3d,0x28,
- 0xff,0xa0,0x4f,0xfe,0x51,0xe0,0x0f,0xb0,0x5e,0x2f,0x32,0x6c,0xf7,0x32,0xf7,0xf8,
- 0xfd,0xa3,0xd1,0xbb,0xe1,0x51,0xbe,0x2f,0xec,0x3e,0x2e,0xfa,0xe0,0x5f,0xf9,0xb3,
- 0x49,0x7b,0x6d,0xb1,0x1f,0x5e,0xe5,0x73,0xe3,0xa5,0xb5,0xe2,0x59,0x76,0x94,0xef,
- 0x0e,0xdb,0x87,0x95,0x39,0xe3,0xf2,0x47,0x16,0xe2,0x70,0x16,0x2a,0xbb,0x70,0x59,
- 0x92,0xf2,0x1f,0x45,0xbf,0x71,0x35,0xad,0xcf,0x39,0xf8,0x47,0x83,0xce,0x23,0xfc,
- 0x11,0x45,0x8d,0x23,0x31,0xe9,0xe0,0xb8,0xfc,0x61,0xd2,0x01,0xf8,0x38,0x72,0x43,
- 0xbf,0xd4,0x59,0xfd,0x89,0xfe,0x36,0x9f,0xbf,0x33,0x6f,0x78,0xda,0x01,0xfd,0x52,
- 0x6c,0x41,0xd8,0x3e,0xc2,0x66,0x49,0x1f,0xf3,0xf2,0xa4,0xbd,0x47,0x80,0xf1,0xf5,
- 0x6f,0x97,0xf7,0x7b,0x51,0xda,0xb4,0xd9,0x07,0x50,0x7e,0xf6,0x6d,0xb9,0x76,0x20,
- 0xf7,0x6b,0xe2,0x62,0xf8,0x82,0x2f,0x4c,0xda,0xce,0xb2,0xe7,0x60,0x3d,0xec,0x30,
- 0x6c,0x06,0x7b,0x7a,0xfc,0xfb,0x02,0xdf,0x0e,0x8f,0xab,0xee,0xa0,0xad,0xce,0x95,
- 0xe0,0x8d,0x50,0xbc,0xf6,0x91,0x24,0xdb,0x6e,0xec,0x2d,0x12,0x20,0xe7,0x2e,0x36,
- 0x1d,0x1a,0x51,0x82,0xc9,0xb5,0x0c,0xc6,0xe5,0x8f,0x26,0x6d,0x84,0x86,0x90,0xd6,
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+ 0xde,0xb9,0xe1,0xb5,0x5d,0x1e,0xfd,0xb5,0xb6,0x0b,0xb0,0x82,0x27,0xd3,0x10,0xb3,
+ 0xbd,0x89,0xcf,0xe6,0xbf,0xf4,0x8e,0x55,0x53,0xf7,0x4d,0xd6,0x9b,0xf0,0xd0,0x39,
+ 0x49,0xeb,0xe7,0xd0,0x69,0x7b,0x13,0x9f,0x25,0x46,0x4f,0xda,0xcb,0xae,0x9c,0x38,
+ 0xe6,0x4d,0x78,0x30,0x27,0xcd,0x9b,0x3c,0x39,0x68,0x9b,0xb6,0x37,0xf1,0xa3,0x6b,
+ 0xf6,0x1f,0xb1,0xeb,0x3f,0x7b,0x7e,0xab,0x37,0xe1,0x71,0xff,0x9d,0xf5,0x7b,0xb5,
+ 0xff,0x91,0xd6,0x71,0x0b,0x9e,0x58,0x32,0xe1,0xdd,0xfe,0x2f,0xc0,0xfc,0xd9,0x0a,
+ 0x5e,0xed,0x7f,0x6d,0xcb,0xd7,0x33,0xf0,0xd0,0x8e,0x2f,0x37,0x7a,0x13,0x1e,0xf7,
+ 0xdf,0x59,0xbf,0x67,0xf9,0xff,0x58,0xdd,0x27,0xbc,0xe6,0x95,0xd1,0x7b,0x7d,0xe6,
+ 0xff,0x7e,0x65,0x4e,0x76,0x62,0xfe,0x1c,0xf4,0x2e,0xff,0x75,0x6d,0x35,0x2c,0x0f,
+ 0x3f,0xec,0x5d,0xfe,0x3b,0xeb,0xf7,0x6a,0xff,0xa3,0x8d,0xe9,0x1e,0x58,0x75,0xbb,
+ 0xc5,0xab,0xfc,0x31,0xe7,0x6c,0xaa,0x9f,0xe6,0x8c,0xed,0x4d,0x7c,0x16,0x1a,0x7a,
+ 0xd3,0x5e,0xfd,0xc5,0xa8,0x67,0xf5,0xdf,0x5d,0xff,0xdf,0xbf,0x99,0xe0,0xc1,0x88,
+ 0x25,0x47,0xcf,0xd8,0xc9,0x25,0x23,0x9e,0xd5,0x9f,0xb9,0x19,0xaa,0x9f,0x33,0x5e,
+ 0xed,0xff,0x82,0x0d,0xbf,0xde,0xb2,0x3b,0x7e,0x7a,0x66,0xd2,0x9b,0xf0,0xb8,0xff,
+ 0xce,0xfa,0x3d,0xdb,0xff,0x0d,0xc7,0xdf,0xb7,0x1e,0x5f,0x72,0x3a,0x7c,0xef,0xa9,
+ 0xf7,0x25,0x73,0x6e,0x92,0xea,0xa7,0x67,0xf9,0x1f,0x6c,0x38,0xf3,0xb2,0xd5,0xf2,
+ 0xed,0xcf,0x69,0x6f,0xc2,0xe3,0xfe,0x3b,0xeb,0xf7,0x6c,0xff,0x97,0xef,0xf8,0x0a,
+ 0x12,0x75,0xef,0x79,0x57,0x7f,0xe6,0xa8,0x7e,0x7a,0x97,0xff,0xcb,0x02,0x8d,0x7c,
+ 0xc3,0xe9,0xe8,0x65,0x6f,0xc2,0xd3,0x97,0x9c,0x88,0xf5,0x7b,0xb3,0xff,0xa6,0xf8,
+ 0x46,0x8a,0x1b,0x3f,0x98,0x60,0xd1,0x67,0x44,0xfc,0x26,0xf0,0x7f,0x7d,0x3f,0xc1,
+ 0x7d,0x6c,0xc0,0x84,0x09,0x4d,0x8a,0xb9,0xfb,0xce,0x79,0x7f,0x01,0xf4,0xb7,0xc1,
+ 0xde,0xf0,0x33,0x01,0x00,
* (C) Copyright 2001-2004
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
#include <asm/processor.h>
#include <command.h>
#include <malloc.h>
+#include <pci.h>
+#include <sm501.h>
+
+
+#ifdef CONFIG_VIDEO_SM501
+
+#define SWAP32(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
+ (((x) & 0x00ff0000) >> 8) | (((x) & 0xff000000) >> 24) )
+
+#ifdef CONFIG_VIDEO_SM501_8BPP
+#error CONFIG_VIDEO_SM501_8BPP not supported.
+#endif /* CONFIG_VIDEO_SM501_8BPP */
+
+#ifdef CONFIG_VIDEO_SM501_16BPP
+#define BPP 16
+
+/*
+ * 800x600 display B084SN03: PCLK = 40MHz
+ * => 2*PCLK = 80MHz
+ * 336/4 = 84MHz
+ * => PCLK = 84MHz
+ */
+static const SMI_REGS init_regs_800x600 [] =
+{
+#if 1 /* test-only */
+ {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
+#else
+ {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
+#endif
+ {0x00004, SWAP32(0x00000000)},
+ /* clocks for pm1... */
+ {0x00048, SWAP32(0x00021807)},
+ {0x0004C, SWAP32(0x221a0a01)},
+ {0x00054, SWAP32(0x00000001)},
+ /* clocks for pm0... */
+ {0x00040, SWAP32(0x00021807)},
+ {0x00044, SWAP32(0x221a0a01)},
+ {0x00054, SWAP32(0x00000000)},
+ /* panel control regs... */
+ {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
+ {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
+ {0x8000C, SWAP32(0x00000000)}, /* panel fb address */
+ {0x80010, SWAP32(0x06400640)}, /* panel fb offset/window width */
+ {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
+ {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
+ {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
+ {0x80020, SWAP32(0x02580320)}, /* panel plane br location */
+ {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
+ {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
+ {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
+ {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
+ {0x80200, SWAP32(0x00010000)}, /* crt display control */
+ {0, 0}
+};
+
+/*
+ * 1024x768 display G150XG02: PCLK = 65MHz
+ * => 2*PCLK = 130MHz
+ * 288/2 = 144MHz
+ * => PCLK = 72MHz
+ */
+static const SMI_REGS init_regs_1024x768 [] =
+{
+ {0x00004, SWAP32(0x00000000)},
+ /* clocks for pm1... */
+ {0x00048, SWAP32(0x00021807)},
+ {0x0004C, SWAP32(0x011a0a01)},
+ {0x00054, SWAP32(0x00000001)},
+ /* clocks for pm0... */
+ {0x00040, SWAP32(0x00021807)},
+ {0x00044, SWAP32(0x011a0a01)},
+ {0x00054, SWAP32(0x00000000)},
+ /* panel control regs... */
+ {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
+ {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
+ {0x8000C, SWAP32(0x00000000)}, /* panel fb address */
+ {0x80010, SWAP32(0x08000800)}, /* panel fb offset/window width */
+ {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
+ {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
+ {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
+ {0x80020, SWAP32(0x03000400)}, /* panel plane br location */
+ {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
+ {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
+ {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
+ {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
+ {0x80200, SWAP32(0x00010000)}, /* crt display control */
+ {0, 0}
+};
-/* ------------------------------------------------------------------------- */
+#endif /* CONFIG_VIDEO_SM501_16BPP */
+
+#ifdef CONFIG_VIDEO_SM501_32BPP
+#define BPP 32
+
+/*
+ * 800x600 display B084SN03: PCLK = 40MHz
+ * => 2*PCLK = 80MHz
+ * 336/4 = 84MHz
+ * => PCLK = 84MHz
+ */
+static const SMI_REGS init_regs_800x600 [] =
+{
+#if 0 /* test-only */
+ {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
+#else
+ {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
+#endif
+ {0x00004, SWAP32(0x00000000)},
+ /* clocks for pm1... */
+ {0x00048, SWAP32(0x00021807)},
+ {0x0004C, SWAP32(0x221a0a01)},
+ {0x00054, SWAP32(0x00000001)},
+ /* clocks for pm0... */
+ {0x00040, SWAP32(0x00021807)},
+ {0x00044, SWAP32(0x221a0a01)},
+ {0x00054, SWAP32(0x00000000)},
+ /* panel control regs... */
+ {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
+ {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
+ {0x8000C, SWAP32(0x00000000)}, /* panel fb address */
+ {0x80010, SWAP32(0x0c800c80)}, /* panel fb offset/window width */
+ {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
+ {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
+ {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
+ {0x80020, SWAP32(0x02580320)}, /* panel plane br location */
+ {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
+ {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
+ {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
+ {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
+ {0x80200, SWAP32(0x00010000)}, /* crt display control */
+ {0, 0}
+};
+
+/*
+ * 1024x768 display G150XG02: PCLK = 65MHz
+ * => 2*PCLK = 130MHz
+ * 288/2 = 144MHz
+ * => PCLK = 72MHz
+ */
+static const SMI_REGS init_regs_1024x768 [] =
+{
+ {0x00004, SWAP32(0x00000000)},
+ /* clocks for pm1... */
+ {0x00048, SWAP32(0x00021807)},
+ {0x0004C, SWAP32(0x011a0a01)},
+ {0x00054, SWAP32(0x00000001)},
+ /* clocks for pm0... */
+ {0x00040, SWAP32(0x00021807)},
+ {0x00044, SWAP32(0x011a0a01)},
+ {0x00054, SWAP32(0x00000000)},
+ /* panel control regs... */
+ {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
+ {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
+ {0x8000C, SWAP32(0x00000000)}, /* panel fb address */
+ {0x80010, SWAP32(0x10001000)}, /* panel fb offset/window width */
+ {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
+ {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
+ {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
+ {0x80020, SWAP32(0x03000400)}, /* panel plane br location */
+ {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
+ {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
+ {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
+ {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
+ {0x80200, SWAP32(0x00010000)}, /* crt display control */
+ {0, 0}
+};
+
+#endif /* CONFIG_VIDEO_SM501_32BPP */
+
+#endif /* CONFIG_VIDEO_SM501 */
#if 0
#define FPGA_DEBUG
au_image_t au_image[] = {
{"hh405/preinst.img", 0, -1, AU_SCRIPT},
{"hh405/u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE},
- {"hh405/pImage_$(bd_type)", 0x00000000, 0x00100000, AU_NAND},
+ {"hh405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND},
{"hh405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND},
{"hh405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND},
{"hh405/postinst.img", 0, 0, AU_SCRIPT},
if (value & 0x80000000) {
/* Revision 1.0 or 1.1 detected */
- return 1;
+ return 0x0101;
} else {
if (value & 0x00400000) {
- /* Revision 1.3 detected */
- return 3;
+ /* unused */
+ return 0x0103;
} else {
- /* Revision 1.2 detected */
- return 2;
+ /* Revision >= 2.0 detected */
+ /* rev. 2.x uses four SM501 GPIOs for revision coding */
+ return 0x0200;
}
}
}
* Write Board revision into FPGA
*/
*fpga_ctrl |= gd->board_type & 0x0003;
- if (gd->board_type >= 2) {
+ if (gd->board_type >= 0x0200) {
*fpga_ctrl |= CFG_FPGA_CTRL_CF_BUS_EN;
}
+ /*
+ * Setup and enable EEPROM write protection
+ */
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
+
/*
* Set NAND-FLASH GPIO signals to default
*/
/*
* Init lcd interface and display logo
*/
+
str = getenv("bd_type");
if (strcmp(str, "ppc230") == 0) {
/*
regs_13704_320_240_4bpp,
sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
logo_bmp_320, sizeof(logo_bmp_320));
+#ifdef CONFIG_VIDEO_SM501
} else {
- printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
- return 0;
+ pci_dev_t devbusfn;
+
+ /*
+ * Is SM501 connected (ppc221/ppc231)?
+ */
+ devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
+ if (devbusfn != -1) {
+ puts("VGA: SM501 with 8 MB ");
+ if (strcmp(str, "ppc221") == 0) {
+ printf("(800*600, %dbpp)\n", BPP);
+ } else if (strcmp(str, "ppc231") == 0) {
+ printf("(1024*768, %dbpp)\n", BPP);
+ } else {
+ printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
+ return 0;
+ }
+ } else {
+ printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
+ return 0;
+ }
+#endif /* CONFIG_VIDEO_SM501 */
}
return (0);
{
DECLARE_GLOBAL_DATA_PTR;
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
puts ("Board: ");
}
gd->board_type = board_revision();
- printf(", Rev 1.%ld)\n", gd->board_type);
+ printf(", Rev %ld.%ld)\n",
+ (gd->board_type >> 8) & 0xff,
+ gd->board_type & 0xff);
/*
* Disable sleep mode in LXT971
return 0;
}
-/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
{
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
-/* ------------------------------------------------------------------------- */
int testdram (void)
{
return (0);
}
-/* ------------------------------------------------------------------------- */
#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
}
}
#endif
+
+
+#if defined(CFG_EEPROM_WREN)
+/* Input: <dev_addr> I2C address of EEPROM device to enable.
+ * <state> -1: deliver current state
+ * 0: disable write
+ * 1: enable write
+ * Returns: -1: wrong device address
+ * 0: dis-/en- able done
+ * 0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+ if (CFG_I2C_EEPROM_ADDR != dev_addr) {
+ return -1;
+ } else {
+ switch (state) {
+ case 1:
+ /* Enable write access, clear bit GPIO_SINT2. */
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
+ state = 0;
+ break;
+ case 0:
+ /* Disable write access, set bit GPIO_SINT2. */
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
+ state = 0;
+ break;
+ default:
+ /* Read current status back. */
+ state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
+ break;
+ }
+ }
+ return state;
+}
+
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int query = argc == 1;
+ int state = 0;
+
+ if (query) {
+ /* Query write access state. */
+ state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
+ if (state < 0) {
+ puts ("Query of write access state failed.\n");
+ } else {
+ printf ("Write access for device 0x%0x is %sabled.\n",
+ CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+ state = 0;
+ }
+ } else {
+ if ('0' == argv[1][0]) {
+ /* Disable write access. */
+ state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
+ } else {
+ /* Enable write access. */
+ state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
+ }
+ if (state < 0) {
+ puts ("Setup of write access state failed.\n");
+ }
+ }
+
+ return state;
+}
+
+U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
+ "eepwren - Enable / disable / query EEPROM write access\n",
+ NULL);
+#endif /* #if defined(CFG_EEPROM_WREN) */
+
+
+#ifdef CONFIG_VIDEO_SM501
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+/*
+ * Return text to be printed besides the logo.
+ */
+void video_get_info_str (int line_number, char *info)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ char str[64];
+ char str2[64];
+ int i = getenv_r("serial#", str2, sizeof(str));
+
+ if (line_number == 1) {
+ sprintf(str, " Board: ");
+
+ if (i == -1) {
+ strcat(str, "### No HW ID - assuming HH405");
+ } else {
+ strcat(str, str2);
+ }
+
+ if (getenv_r("bd_type", str2, sizeof(str2)) != -1) {
+ strcat(str, " (");
+ strcat(str, str2);
+ } else {
+ strcat(str, " (Missing bd_type!");
+ }
+
+ sprintf(str2, ", Rev %ld.%ld)",
+ (gd->board_type >> 8) & 0xff, gd->board_type & 0xff);
+ strcat(str, str2);
+ strcpy(info, str);
+ } else {
+ info [0] = '\0';
+ }
+}
+#endif /* CONFIG_CONSOLE_EXTRA_INFO */
+
+/*
+ * Returns SM501 register base address. First thing called in the driver.
+ */
+unsigned int board_video_init (void)
+{
+ pci_dev_t devbusfn;
+ u32 addr;
+
+ /*
+ * Is SM501 connected (ppc221/ppc231)?
+ */
+ devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
+ if (devbusfn != -1) {
+ pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, (u32 *)&addr);
+ return (addr & 0xfffffffe);
+ }
+
+ return 0;
+}
+
+/*
+ * Returns SM501 framebuffer address
+ */
+unsigned int board_video_get_fb (void)
+{
+ pci_dev_t devbusfn;
+ u32 addr;
+
+ /*
+ * Is SM501 connected (ppc221/ppc231)?
+ */
+ devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
+ if (devbusfn != -1) {
+ pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (u32 *)&addr);
+ return (addr & 0xfffffffe);
+ }
+
+ return 0;
+}
+
+/*
+ * Called after initializing the SM501 and before clearing the screen.
+ */
+void board_validate_screen (unsigned int base)
+{
+}
+
+/*
+ * Return a pointer to the initialization sequence.
+ */
+const SMI_REGS *board_get_regs (void)
+{
+ char *str;
+
+ str = getenv("bd_type");
+ if (strcmp(str, "ppc221") == 0) {
+ return init_regs_800x600;
+ } else {
+ return init_regs_1024x768;
+ }
+}
+
+int board_get_width (void)
+{
+ char *str;
+
+ str = getenv("bd_type");
+ if (strcmp(str, "ppc221") == 0) {
+ return 800;
+ } else {
+ return 1024;
+ }
+}
+
+int board_get_height (void)
+{
+ char *str;
+
+ str = getenv("bd_type");
+ if (strcmp(str, "ppc221") == 0) {
+ return 600;
+ } else {
+ return 768;
+ }
+}
+
+#endif /* CONFIG_VIDEO_SM501 */
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
DECLARE_GLOBAL_DATA_PTR;
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
puts ("Board: ");
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
+ cpu/ppc4xx/4xx_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
#include <common.h>
#include <command.h>
#include <pci.h>
+#include <pci_ids.h>
#include <405gp_pci.h>
#if (CONFIG_COMMANDS & CFG_CMD_BSP)
-#define IBM_VENDOR_ID 0x1014
-#define PPC405_DEVICE_ID 0x0156
-
-
/*
* Set device number on pci board
*/
u32 addr;
while (bdf >= 0) {
- if ((bdf = pci_find_device(IBM_VENDOR_ID, PPC405_DEVICE_ID, idx++)) < 0) {
+ if ((bdf = pci_find_device(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_405GP, idx++)) < 0) {
break;
}
printf("Found device nr %d at %x!\n", idx-1, bdf);
*/
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof (str));
puts ("Board: ");
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
pci_read_config_dword(PCIDEVID_405GP, i, ptr++);
}
ptr = (unsigned int *)PCI_REGS_ADDR;
- *ptr = crc32(0, (char *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4);
+ *ptr = crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4);
printf("\nStoring PCI Configuration Regs...\n");
} else {
pci_read_config_dword(PCIDEVID_405GP, i, ptr++);
}
ptr = (unsigned int *)PCI_REGS_ADDR;
- *ptr = crc32(0, (char *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4);
+ *ptr = crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4);
printf("\nStoring PCI Configuration Regs...\n");
* Rewrite pci config regs (only after soft-reset with magic set)
*/
ptr = (unsigned int *)PCI_REGS_ADDR;
- if (crc32(0, (char *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
+ if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
puts("Restoring PCI Configurations Regs!\n");
ptr = (unsigned int *)PCI_REGS_ADDR + 1;
for (i=0; i<0x40; i+=4) {
* Rewrite pci config regs (only after soft-reset with magic set)
*/
ptr = (unsigned int *)PCI_REGS_ADDR;
- if (crc32(0, (char *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
+ if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
puts("Restoring PCI Configurations Regs!\n");
ptr = (unsigned int *)PCI_REGS_ADDR + 1;
for (i=0; i<0x40; i+=4) {
{
DECLARE_GLOBAL_DATA_PTR;
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
puts ("Board: ");
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
--- /dev/null
+
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+# Objects for Xilinx JTAG programming (CPLD)
+# CPLD = ../common/xilinx_jtag/lenval.o \
+# ../common/xilinx_jtag/micro.o \
+# ../common/xilinx_jtag/ports.o
+
+# OBJS = $(BOARD).o flash.o $(CPLD)
+OBJS = $(BOARD).o flash.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# IceCube board:
+#
+# Valid values for TEXT_BASE are:
+#
+# 0xFFF00000 boot high (standard configuration)
+# 0xFF000000 boot low for 16 MiB boards
+# 0xFF800000 boot low for 8 MiB boards
+# 0x00100000 boot from RAM (for testing only)
+#
+
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+## Standard: boot high
+TEXT_BASE = 0xFFF00000
+## For testing: boot from RAM
+# TEXT_BASE = 0x00100000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+
+#define FLASH_ID_MASK 0x00FF
+
+#define FPW FLASH_PORT_WIDTH
+#define FPWV FLASH_PORT_WIDTHV
+
+#define FLASH_CYCLE1 0x0555
+#define FLASH_CYCLE2 0x0aaa
+#define FLASH_ID1 0x00
+#define FLASH_ID2 0x01
+#define FLASH_ID3 0x0E
+#define FLASH_ID4 0x0F
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPWV * addr, flash_info_t * info);
+static void flash_reset(flash_info_t * info);
+static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data);
+static flash_info_t *flash_get_info(ulong base);
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init(void)
+{
+ unsigned long size = 0;
+ int i = 0;
+ extern void flash_preinit(void);
+ extern void flash_afterinit(uint, ulong, ulong);
+
+ ulong flashbase = CFG_FLASH_BASE;
+
+ flash_preinit();
+
+ /* There is only ONE FLASH device */
+ memset(&flash_info[i], 0, sizeof(flash_info_t));
+ flash_info[i].size = flash_get_size((FPW *) flashbase, &flash_info[i]);
+ size += flash_info[i].size;
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + monitor_flash_len - 1,
+ flash_get_info(CFG_MONITOR_BASE));
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+ /* ENV protection ON by default */
+ flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+ flash_get_info(CFG_ENV_ADDR));
+#endif
+
+ flash_afterinit(i, flash_info[i].start[0], flash_info[i].size);
+ return size ? size : 1;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t * info) {
+ FPWV *base = (FPWV *) (info->start[0]);
+
+ /* Put FLASH back in read mode */
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+ *base = (FPW) 0x00FF00FF; /* Intel Read Mode */
+ } else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
+ *base = (FPW) 0x00F000F0; /* AMD Read Mode */
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static flash_info_t *flash_get_info(ulong base) {
+ int i;
+ flash_info_t *info;
+
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+ info = &flash_info[i];
+ if ((info->size) && (info->start[0] <= base)
+ && (base <= info->start[0] + info->size - 1)) {
+ break;
+ }
+ }
+ return (i == CFG_MAX_FLASH_BANKS ? 0 : info);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info(flash_info_t * info) {
+ int i;
+ char *fmt;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD:
+ printf("AMD ");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AMLV256U:
+ fmt = "29LV256M (256 Mbit)\n";
+ break;
+ default:
+ fmt = "Unknown Chip Type\n";
+ break;
+ }
+
+ printf(fmt);
+ printf(" Size: %ld MB in %d Sectors\n", info->size >> 20,
+ info->sector_count);
+ printf(" Sector Start Addresses:");
+
+ for (i = 0; i < info->sector_count; ++i) {
+ ulong size;
+ int erased;
+ ulong *flash = (unsigned long *)info->start[i];
+
+ if ((i % 5) == 0) {
+ printf("\n ");
+ }
+
+ /*
+ * Check if whole sector is erased
+ */
+ size =
+ (i !=
+ (info->sector_count - 1)) ? (info->start[i + 1] -
+ info->start[i]) >> 2 : (info->
+ start
+ [0] +
+ info->
+ size -
+ info->
+ start
+ [i])
+ >> 2;
+
+ for (flash = (unsigned long *)info->start[i], erased = 1;
+ (flash != (unsigned long *)info->start[i] + size)
+ && erased; flash++) {
+ erased = *flash == ~0x0UL;
+ }
+ printf(" %08lX %s %s", info->start[i], erased ? "E" : " ",
+ info->protect[i] ? "(RO)" : " ");
+ }
+
+ printf("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size(FPWV * addr, flash_info_t * info) {
+ int i;
+
+ /* Write auto select command: read Manufacturer ID */
+ /* Write auto select command sequence and test FLASH answer */
+ addr[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */
+ addr[FLASH_CYCLE2] = (FPW) 0x00550055; /* for AMD, Intel ignores this */
+ addr[FLASH_CYCLE1] = (FPW) 0x00900090; /* selects Intel or AMD */
+
+ /* The manufacturer codes are only 1 byte, so just use 1 byte. */
+ /* This works for any bus width and any FLASH device width. */
+ udelay(100);
+ switch (addr[FLASH_ID1] & 0x00ff) {
+ case (uchar) AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ default:
+ printf("unknown vendor=%x ", addr[FLASH_ID1] & 0xff);
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ break;
+ }
+
+ /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ switch ((FPW) addr[FLASH_ID2]) {
+ case (FPW) AMD_ID_MIRROR:
+ /* MIRROR BIT FLASH, read more ID bytes */
+ if ((FPW) addr[FLASH_ID3] == (FPW) AMD_ID_LV256U_2
+ && (FPW) addr[FLASH_ID4] == (FPW) AMD_ID_LV256U_3) {
+ /* attention: only the first 16 MB will be used in u-boot */
+ info->flash_id += FLASH_AMLV256U;
+ info->sector_count = 512;
+ info->size = 0x02000000;
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] =
+ (ulong) addr + 0x10000 * i;
+ }
+ break;
+ }
+ /* fall thru to here ! */
+ default:
+ printf("unknown AMD device=%x %x %x",
+ (FPW) addr[FLASH_ID2], (FPW) addr[FLASH_ID3],
+ (FPW) addr[FLASH_ID4]);
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0x800000;
+ break;
+ }
+
+ /* Put FLASH back in read mode */
+ flash_reset(info);
+ }
+ return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase(flash_info_t * info, int s_first, int s_last) {
+ FPWV *addr;
+ int flag, prot, sect;
+ int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
+ ulong start, now, last;
+ int rcode = 0;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("- missing\n");
+ } else {
+ printf("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AMLV256U:
+ break;
+ case FLASH_UNKNOWN:
+ default:
+ printf("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf("\n");
+ }
+
+ last = get_timer(0);
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last && rcode == 0; sect++) {
+ if (info->protect[sect] != 0) { /* protected, skip it */
+ continue;
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr = (FPWV *) (info->start[sect]);
+ if (intel) {
+ *addr = (FPW) 0x00500050; /* clear status register */
+ *addr = (FPW) 0x00200020; /* erase setup */
+ *addr = (FPW) 0x00D000D0; /* erase confirm */
+ } else {
+ /* must be AMD style if not Intel */
+ FPWV *base; /* first address in bank */
+
+ base = (FPWV *) (info->start[0]);
+ base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
+ base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
+ base[FLASH_CYCLE1] = (FPW) 0x00800080; /* erase mode */
+ base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
+ base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
+ *addr = (FPW) 0x00300030; /* erase sector */
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag) {
+ enable_interrupts();
+ }
+ start = get_timer(0);
+
+ /* wait at least 50us for AMD, 80us for Intel. */
+ /* Let's wait 1 ms. */
+ udelay(1000);
+
+ while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ if (intel) {
+ /* suspend erase */
+ *addr = (FPW) 0x00B000B0;
+ }
+ flash_reset(info); /* reset to read mode */
+ rcode = 1; /* failed */
+ break;
+ }
+ /* show that we're waiting */
+ if ((get_timer(last)) > CFG_HZ) {
+ /* every second */
+ putc('.');
+ last = get_timer(0);
+ }
+ }
+ /* show that we're waiting */
+ if ((get_timer(last)) > CFG_HZ) {
+ /* every second */
+ putc('.');
+ last = get_timer(0);
+ }
+ flash_reset(info); /* reset to read mode */
+ }
+ printf(" done\n");
+ return (rcode);
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
+ int bytes; /* number of bytes to program in current word */
+ int left; /* number of bytes left to program */
+ int i, res;
+
+ for (left = cnt, res = 0;
+ left > 0 && res == 0;
+ addr += sizeof(data), left -= sizeof(data) - bytes) {
+
+ bytes = addr & (sizeof(data) - 1);
+ addr &= ~(sizeof(data) - 1);
+
+ /* combine source and destination data so can program
+ * an entire word of 16 or 32 bits
+ */
+ for (i = 0; i < sizeof(data); i++) {
+ data <<= 8;
+ if (i < bytes || i - bytes >= left)
+ data += *((uchar *) addr + i);
+ else
+ data += *src++;
+ }
+
+ /* write one word to the flash */
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD:
+ res = write_word_amd(info, (FPWV *) addr, data);
+ break;
+ default:
+ /* unknown flash type, error! */
+ printf("missing or unknown FLASH type\n");
+ res = 1; /* not really a timeout, but gives error */
+ break;
+ }
+ }
+ return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data) {
+ ulong start;
+ int flag;
+ int res = 0; /* result, assume success */
+ FPWV *base; /* first address in flash bank */
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*dest & data) != data) {
+ return (2);
+ }
+
+ base = (FPWV *) (info->start[0]);
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
+ base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
+ base[FLASH_CYCLE1] = (FPW) 0x00A000A0; /* selects program mode */
+
+ *dest = data; /* start programming the data */
+
+ /* re-enable interrupts if necessary */
+ if (flag) {
+ enable_interrupts();
+ }
+ start = get_timer(0);
+
+ /* data polling for D7 */
+ while (res == 0
+ && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ *dest = (FPW) 0x00F000F0; /* reset bank */
+ res = 1;
+ }
+ }
+ return (res);
+}
--- /dev/null
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR 1 /* is DDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x705f0f00
+#define SDRAM_CONFIG1 0x73722930
+#define SDRAM_CONFIG2 0x47770000
+#define SDRAM_TAPDELAY 0x10000000
+
+#else
+#error CONFIG_MPC5200 not defined
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * pf5200.c - main board support/init for the esd pf5200.
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <command.h>
+
+#include "mt46v16m16-75.h"
+
+void init_power_switch(void);
+
+static void sdram_start(int hi_addr)
+{
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+ /* unlock mode register */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL =
+ SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* precharge all banks */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL =
+ SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* set mode register: extended mode */
+ *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+ __asm__ volatile ("sync");
+
+ /* set mode register: reset DLL */
+ *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+ __asm__ volatile ("sync");
+
+ /* precharge all banks */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL =
+ SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* auto refresh */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL =
+ SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* set mode register */
+ *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+ __asm__ volatile ("sync");
+
+ /* normal operation */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+ __asm__ volatile ("sync");
+}
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ * is something else than 0x00000000.
+ */
+
+long int initdram(int board_type)
+{
+ ulong dramsize = 0;
+ ulong test1, test2;
+
+ /* setup SDRAM chip selects */
+ *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
+ __asm__ volatile ("sync");
+
+ /* setup config registers */
+ *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+ *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+ __asm__ volatile ("sync");
+
+ /* set tap delay */
+ *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+ __asm__ volatile ("sync");
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start(0);
+ test1 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000);
+ sdram_start(1);
+ test2 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000);
+
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else {
+ dramsize = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20)) {
+ dramsize = 0;
+ }
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0) {
+ *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+ 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+ /* let SDRAM CS1 start right after CS0 */
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
+ } else {
+#if 0
+ *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+ /* let SDRAM CS1 start right after CS0 */
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
+#else
+ *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+ 0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
+ /* let SDRAM CS1 start right after CS0 */
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */
+#endif
+ }
+
+#if 0
+ /* find RAM size using SDRAM CS1 only */
+ sdram_start(0);
+ get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+ sdram_start(1);
+ get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+ sdram_start(0);
+#endif
+ /* set SDRAM CS1 size according to the amount of RAM found */
+
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+
+ init_power_switch();
+ return (dramsize);
+}
+
+int checkboard(void)
+{
+ puts("Board: esd ParaFinder (pf5200)\n");
+ return 0;
+}
+
+void flash_preinit(void)
+{
+ /*
+ * Now, when we are in RAM, enable flash write
+ * access for detection process.
+ * Note that CS_BOOT cannot be cleared when
+ * executing in flash.
+ */
+ *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+}
+
+void flash_afterinit(ulong size)
+{
+ if (size == 0x02000000) {
+ /* adjust mapping */
+ *(vu_long *) MPC5XXX_BOOTCS_START =
+ *(vu_long *) MPC5XXX_CS0_START =
+ START_REG(CFG_BOOTCS_START | size);
+ *(vu_long *) MPC5XXX_BOOTCS_STOP =
+ *(vu_long *) MPC5XXX_CS0_STOP =
+ STOP_REG(CFG_BOOTCS_START | size, size);
+ }
+}
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void
+ ) {
+ pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+
+#define GPIO_PSC1_4 0x01000000UL
+
+void init_ide_reset(void)
+{
+ debug("init_ide_reset\n");
+
+ /* Configure PSC1_4 as GPIO output for ATA reset */
+ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
+}
+
+void ide_set_reset(int idereset)
+{
+ debug("ide_reset(%d)\n", idereset);
+
+ if (idereset) {
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
+ } else {
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
+ }
+}
+#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
+
+#define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004)
+#define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014)
+
+#define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020)
+#define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028)
+#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
+#define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C)
+
+#define GPIO_WU6 0x40000000UL
+#define GPIO_USB0 0x00010000UL
+#define GPIO_USB9 0x08000000UL
+#define GPIO_USB9S 0x00080000UL
+
+void init_power_switch(void)
+{
+ debug("init_power_switch\n");
+
+ /* Configure GPIO_WU6 as GPIO output for ATA reset */
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_WU6;
+ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
+ *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
+ __asm__ volatile ("sync");
+
+ *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
+ *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
+ *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
+ __asm__ volatile ("sync");
+
+ *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
+ *(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
+ __asm__ volatile ("sync");
+
+ if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
+ *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
+ __asm__ volatile ("sync");
+ }
+ *(vu_char *) CFG_CS1_START = 0x02; /* Red Power LED on */
+ __asm__ volatile ("sync");
+
+ *(vu_char *) (CFG_CS1_START + 1) = 0x02; /* Disable driver for KB11 */
+ __asm__ volatile ("sync");
+}
+
+void power_set_reset(int power)
+{
+ debug("ide_set_reset(%d)\n", power);
+
+ if (power) {
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_WU6;
+ *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
+ } else {
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_WU6;
+ if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) ==
+ 0) {
+ *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |=
+ GPIO_USB0;
+ }
+
+ }
+}
+
+int do_poweroff(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ power_set_reset(1);
+ return (0);
+}
+
+U_BOOT_CMD(poweroff, 1, 1, do_poweroff, "poweroff- Switch off power\n", NULL);
+
+int phypower(int flag)
+{
+ u32 addr;
+ vu_long *reg;
+ int status;
+ pci_dev_t dev;
+
+ dev = PCI_BDF(0, 0x18, 0);
+ status = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &addr);
+ if (status == 0) {
+ reg = (vu_long *) (addr + 0x00000040);
+ *reg |= 0x40000000;
+ __asm__ volatile ("sync");
+
+ reg = (vu_long *) (addr + 0x001000c);
+ *reg |= 0x20000000;
+ __asm__ volatile ("sync");
+
+ reg = (vu_long *) (addr + 0x0010004);
+ if (flag != 0) {
+ *reg &= ~0x20000000;
+ } else {
+ *reg |= 0x20000000;
+ }
+ __asm__ volatile ("sync");
+ }
+ return (status);
+}
+
+int do_phypower(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ int status;
+
+ if (argv[1][0] == '0') {
+ status = phypower(0);
+ } else {
+ status = phypower(1);
+ }
+ return (0);
+}
+
+U_BOOT_CMD(phypower, 2, 2, do_phypower,
+ "phypower- Switch power of ethernet phy\n", NULL);
+
+int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned int addr;
+ unsigned int size;
+ int i;
+ volatile unsigned long *ptr;
+
+ addr = simple_strtol(argv[1], NULL, 16);
+ size = simple_strtol(argv[2], NULL, 16);
+
+ printf("\nWriting at addr %08x, size %08x.\n", addr, size);
+
+ while (1) {
+ ptr = (volatile unsigned long *)addr;
+ for (i = 0; i < (size >> 2); i++) {
+ *ptr++ = i;
+ }
+
+ /* Abort if ctrl-c was pressed */
+ if (ctrlc()) {
+ puts("\nAbort\n");
+ return 0;
+ }
+ putc('.');
+ }
+ return 0;
+}
+
+U_BOOT_CMD(writepci, 3, 1, do_writepci,
+ "writepci- Write some data to pcibus\n",
+ "<addr> <size>\n" " - Write some data to pcibus.\n");
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc5xxx/start.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ . = ALIGN(16);
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
au_image_t au_image[] = {
{"plu405/preinst.img", 0, -1, AU_SCRIPT},
{"plu405/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
- {"plu405/pImage_$(bd_type)", 0x00000000, 0x00100000, AU_NAND},
+ {"plu405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND},
{"plu405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND},
{"plu405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND},
{"plu405/postinst.img", 0, 0, AU_SCRIPT},
*/
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
puts ("Board: ");
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
+ cpu/ppc4xx/4xx_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
../common/xilinx_jtag/micro.o \
../common/xilinx_jtag/ports.o
-OBJS = $(BOARD).o strataflash.o ../common/misc.o $(CPLD)
+OBJS = $(BOARD).o ../common/misc.o ../common/cmd_loadpci.o $(CPLD)
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
/*
* (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2005
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
* project.
mtebc (epcr, 0xa8400000);
/*
- * Setup GPIO pins (CS6+CS7 as GPIO)
+ * Setup GPIO pins
*/
- mtdcr(cntrl0, mfdcr(cntrl0) | 0x00300000);
- /*
- * Configure GPIO pins
+ mtdcr(cntrl0, mfdcr(cntrl0) | ((CFG_FPGA_INIT | \
+ CFG_FPGA_DONE | \
+ CFG_XEREADY | \
+ CFG_NONMONARCH | \
+ CFG_REV1_2) << 5));
+
+ if (!(in32(GPIO0_IR) & CFG_REV1_2)) {
+ /* rev 1.2 boards */
+ mtdcr(cntrl0, mfdcr(cntrl0) | ((CFG_INTA_FAKE | \
+ CFG_SELF_RST) << 5));
+ }
+
+ out32(GPIO0_OR, 0);
+ out32(GPIO0_TCR, CFG_FPGA_PRG | CFG_FPGA_CLK | CFG_FPGA_DATA | CFG_XEREADY); /* setup for output */
+
+ /* - check if rev1_2 is low, then:
+ * - set/reset CFG_INTA_FAKE/CFG_SELF_RST in TCR to assert INTA# or SELFRST#
*/
- out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
- out32(GPIO0_TCR, CFG_FPGA_PRG | CFG_FPGA_CLK | CFG_FPGA_DATA); /* setup for output */
- out32(GPIO0_OR, 0); /* outputs -> low */
return 0;
}
/* ------------------------------------------------------------------------- */
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
int misc_init_r (void)
{
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_XEREADY); /* deassert EREADY# */
return (0);
}
+ushort pmc405_pci_subsys_deviceid(void)
+{
+ ulong val;
+ val = in32(GPIO0_IR);
+ if (!(val & CFG_REV1_2)) { /* low=rev1.2 */
+ if (val & CFG_NONMONARCH) { /* monarch# signal */
+ return CFG_PCI_SUBSYS_DEVICEID_NONMONARCH;
+ }
+ return CFG_PCI_SUBSYS_DEVICEID_MONARCH;
+ }
+ return CFG_PCI_SUBSYS_DEVICEID_NONMONARCH;
+}
/*
* Check Board Identity:
*/
-
int checkboard (void)
{
- unsigned char str[64];
+ ulong val;
+
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
puts ("Board: ");
puts(str);
}
- putc ('\n');
+ val = in32(GPIO0_IR);
+ if (!(val & CFG_REV1_2)) { /* low=rev1.2 */
+ puts(" rev1.2 (");
+ if (val & CFG_NONMONARCH) { /* monarch# signal */
+ puts("non-");
+ }
+ puts("monarch)");
+ } else {
+ puts(" <=rev1.1");
+ }
- /*
- * Disable sleep mode in LXT971
- */
- lxt971_no_sleep();
+ putc ('\n');
return 0;
}
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
-/* ------------------------------------------------------------------------- */
-int testdram (void)
+/* ------------------------------------------------------------------------- */
+void reset_phy(void)
{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
+#ifdef CONFIG_LXT971_NO_SLEEP
- return (0);
+ /*
+ * Disable sleep mode in LXT971
+ */
+ lxt971_no_sleep();
+#endif
}
-/* ------------------------------------------------------------------------- */
int do_cantest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
+ cpu/ppc4xx/4xx_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
puts ("Board: ");
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
/* ------------------------------------------------------------------------- */
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
int misc_init_r (void)
{
DECLARE_GLOBAL_DATA_PTR;
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
int flashcnt;
int delay;
}
*led_reg = 0x40;
- /*
- * Disable sleep mode in LXT971
- */
- lxt971_no_sleep();
-
return 0;
}
/* ------------------------------------------------------------------------- */
-int testdram (void)
+void reset_phy(void)
{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
+#ifdef CONFIG_LXT971_NO_SLEEP
- return (0);
+ /*
+ * Disable sleep mode in LXT971
+ */
+ lxt971_no_sleep();
+#endif
}
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
puts ("Board: ");
* Check Bank 0 Memory Size for re-configuration
*
*/
- size_b0 = get_ram_size ((ulong *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
- size_b1 = get_ram_size ((ulong *) SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+ size_b0 = get_ram_size ( (long *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+ size_b1 = get_ram_size ( (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
printf ("\nbank 0 size %lu\nbank 1 size %lu\n", size_b0, size_b1);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(16);
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
DECLARE_GLOBAL_DATA_PTR;
- unsigned char *s = getenv ("serial#");
- unsigned char *e;
+ char *s = getenv ("serial#");
+ char *e;
puts ("Board: ");
*
* try 8 column mode
*/
- size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE2_PRELIM,
+ size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
udelay (1000);
/*
* try 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE2_PRELIM,
+ size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
* but then only half the real size will be used.]
*/
size_b1 =
- dram_size (memctl->memc_mamr, (ulong *) SDRAM_BASE3_PRELIM,
+ dram_size (memctl->memc_mamr, (long *) SDRAM_BASE3_PRELIM,
SDRAM_MAX_SIZE);
/* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */
} else {
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
static const char ether_port_phy_addr[3]={4,5,6};
#endif
+/* MII PHY access routines are common for all i/f, use gal_ent0 */
+#define GT6426x_MII_DEVNAME "gal_enet0"
+
+int gt6426x_miiphy_read(char *devname, unsigned char phy,
+ unsigned char reg, unsigned short *val);
static inline unsigned short
miiphy_read_ret(unsigned short phy, unsigned short reg)
{
unsigned short val;
- miiphy_read(phy,reg,&val);
+ gt6426x_miiphy_read(GT6426x_MII_DEVNAME,phy,reg,&val);
return val;
}
*/
/* let the upper layer handle the packet */
- NetReceive (eth_data, eth_len);
+ NetReceive ((uchar *)eth_data, eth_len);
rx->buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16;
#endif
memcpy(dev->eth_tx_buffer, (char *) p, s);
- tx->buff_pointer = dev->eth_tx_buffer;
+ tx->buff_pointer = (uchar *)dev->eth_tx_buffer;
tx->bytecount_reserved = ((__u16)s) << 16;
/* 31 - own
MII utilities - write: write to an MII register via SMI
***************************************************************************/
int
-miiphy_write(unsigned char phy, unsigned char reg,
- unsigned short data)
+gt6426x_miiphy_write(char *devname, unsigned char phy,
+ unsigned char reg, unsigned short data)
{
unsigned int temp= (reg<<21) | (phy<<16) | data;
MII utilities - read: read from an MII register via SMI
***************************************************************************/
int
-miiphy_read(unsigned char phy, unsigned char reg,
- unsigned short *val)
+gt6426x_miiphy_read(char *devname, unsigned char phy,
+ unsigned char reg, unsigned short *val)
{
unsigned int temp= (reg<<21) | (phy<<16) | 1<<26;
if ((psr & 0x3) != want) {
printf("MII: GT thinks %x, PHY thinks %x, restarting autoneg..\n",
psr & 0x3, want);
- miiphy_write(ether_port_phy_addr[p->dev],0,
+ miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev],0,
miiphy_read_ret(ether_port_phy_addr[p->dev],0) | (1<<9));
udelay(10000); /* the EVB's GT takes a while to notice phy
went down and up */
led 2: 0xc=link/rxact
led 3: 0x2=rxact (N/C)
strch: 0,2=30 ms, enable */
- miiphy_write(ether_port_phy_addr[p->dev], 20, 0x1c22);
+ miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev], 20, 0x1c22);
/* 2.7ns port rise time */
/*miiphy_write(ether_port_phy_addr[p->dev], 30, 0x0<<10); */
/* Initialize Rx Side */
for (temp = 0; temp < NR; temp++) {
- p->eth_rx_desc[temp].buff_pointer = p->eth_rx_buffer[temp];
+ p->eth_rx_desc[temp].buff_pointer = (uchar *)p->eth_rx_buffer[temp];
p->eth_rx_desc[temp].buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16;
/* GT96100 Owner */
dev->send = (void*)gt6426x_eth_transmit;
dev->recv = (void*)gt6426x_eth_poll;
- dev->priv = (void*)p = calloc( sizeof(*p), 1 );
+ p = calloc( sizeof(*p), 1 );
+ dev->priv = (void*)p;
if (!p)
{
printf( "%s: %s allocation failure, %s\n",
eth_register(dev);
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+ miiphy_register(dev->name,
+ gt6426x_miiphy_read, gt6426x_miiphy_write);
+#endif
}
+
}
#endif /* CFG_CMD_NET && CONFIG_NET_MULTI */
volatile struct eth0_tx_desc_struct * next_desc;
/* Note - the following will not work for 64 bit addressing */
volatile unsigned char * buff_pointer;
-} eth0_tx_desc_single __attribute__ ((packed));
+} __attribute__ ((packed)) eth0_tx_desc_single;
typedef struct eth0_rx_desc_struct {
volatile __u32 buff_size_byte_count;
volatile __u32 command_status;
volatile struct eth0_rx_desc_struct * next_desc;
volatile unsigned char * buff_pointer;
-} eth0_rx_desc_single __attribute__ ((packed));
+} __attribute__ ((packed)) eth0_rx_desc_single;
#define NT 20 /* Number of Transmit buffers */
#define NR 20 /* Number of Receive buffers */
int bytes =
hashLength[hashSizeSelector] * sizeof (addrTblEntry);
- tableBase = (unsigned int) realAddrTableBase[port] =
+ realAddrTableBase[port] =
malloc (bytes + 64);
+ tableBase = (unsigned int)realAddrTableBase;
if (!tableBase) {
printf ("%s: alloc memory failed \n", __FUNCTION__);
int
flash_erase (flash_info_t *info, int s_first, int s_last)
{
- volatile unsigned char *addr = (char *)(info->start[0]);
+ volatile unsigned char *addr = (uchar *)(info->start[0]);
int flag, prot, sect, l_sect;
ulong start, now, last;
if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) {
for (sect = s_first; sect<=s_last; sect++) {
int sector_size=info->size/info->sector_count;
- addr = (char *)(info->start[sect]);
+ addr = (uchar *)(info->start[sect]);
memset((void *)addr, 0, sector_size);
}
return 0;
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
- addr = (char *)(info->start[sect]);
+ addr = (uchar *)(info->start[sect]);
flash_cmd(info->portwidth,addr,0,0x30);
l_sect = sect;
}
static int
write_word (flash_info_t *info, ulong dest, ulong data)
{
- volatile unsigned char *addr = (char *)(info->start[0]);
+ volatile unsigned char *addr = (uchar *)(info->start[0]);
ulong start;
int flag, i;
static uchar
i2c_get_data(uchar* return_data, int len) {
- unsigned int data, status;
+ unsigned int data, status = 0;
int count = 0;
DP(puts("i2c_get_data\n"));
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
static void
zuma_mbox_setenv(void)
{
- unsigned char *data, buf[32];
+ char *data, buf[32];
unsigned char save = 0;
data = getenv("baudrate");
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"dhcp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"bootm"
#undef CONFIG_WATCHDOG /* watchdog disabled */
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
/*** reset all phys into powerdown ************************************/
for (i=0, err=0; i<M88X_PHY_CNT; i++) {
- err += miiphy_read( devAddr+phyTab[i],M88X_PHY_CNTL,&val );
+ err += bb_miiphy_read(NULL, devAddr+phyTab[i],M88X_PHY_CNTL,&val );
/* keep SpeedLSB, Duplex */
val &= 0x2100;
/* set SWReset, AnegEn, PwrDwn, RestartAneg */
val |= 0x9a00;
- err += miiphy_write( devAddr+phyTab[i],M88X_PHY_CNTL,val );
+ err += bb_miiphy_write(NULL, devAddr+phyTab[i],M88X_PHY_CNTL,val );
}
if (err) {
printf( "%s [ERR] reset phys\n",_f );
/*** disable all ports ************************************************/
for (i=0, err=0; i<M88X_PRT_CNT; i++) {
- err += miiphy_read( devAddr+prtTab[i],M88X_PRT_CNTL,&val );
+ err += bb_miiphy_read(NULL, devAddr+prtTab[i],M88X_PRT_CNTL,&val );
val &= 0xfffc;
- err += miiphy_write( devAddr+prtTab[i],M88X_PRT_CNTL,val );
+ err += bb_miiphy_write(NULL, devAddr+prtTab[i],M88X_PRT_CNTL,val );
}
if (err) {
printf( "%s [ERR] disable ports\n",_f );
/* set switch mac addr */
#define ea eth_get_dev()->enetaddr
val = (ea[4] << 8) | ea[5];
- err = miiphy_write( devAddr+15,M88X_GLB_MAC45,val );
+ err = bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC45,val );
val = (ea[2] << 8) | ea[3];
- err += miiphy_write( devAddr+15,M88X_GLB_MAC23,val );
+ err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC23,val );
val = (ea[0] << 8) | ea[1];
#undef ea
val &= 0xfeff; /* clear DiffAddr */
- err += miiphy_write( devAddr+15,M88X_GLB_MAC01,val );
+ err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC01,val );
if (err) {
printf( "%s [ERR] switch mac address register\n",_f );
return( -1 );
}
/* !DiscardExcessive, MaxFrameSize, CtrMode */
- err = miiphy_read( devAddr+15,M88X_GLB_CNTL,&val );
+ err = bb_miiphy_read(NULL, devAddr+15,M88X_GLB_CNTL,&val );
val &= 0xd870;
val |= 0x0500;
- err += miiphy_write( devAddr+15,M88X_GLB_CNTL,val );
+ err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_CNTL,val );
if (err) {
printf( "%s [ERR] switch global control register\n",_f );
return( -1 );
}
/* LernDis off, ATUSize 1024, AgeTime 5min */
- err = miiphy_read( devAddr+15,M88X_ATU_CNTL,&val );
+ err = bb_miiphy_read(NULL, devAddr+15,M88X_ATU_CNTL,&val );
val &= 0x000f;
val |= 0x2130;
- err += miiphy_write( devAddr+15,M88X_ATU_CNTL,val );
+ err += bb_miiphy_write(NULL, devAddr+15,M88X_ATU_CNTL,val );
if (err) {
printf( "%s [ERR] atu control register\n",_f );
return( -1 );
}
while (p->reg != -1) {
err = 0;
- err += miiphy_read( devAddr+prtTab[i],p->reg,&val );
+ err += bb_miiphy_read(NULL, devAddr+prtTab[i],p->reg,&val );
val &= p->msk;
val |= p->val;
- err += miiphy_write( devAddr+prtTab[i],p->reg,val );
+ err += bb_miiphy_write(NULL, devAddr+prtTab[i],p->reg,val );
if (err) {
printf( "%s [ERR] config port %d register %d\n",_f,i,p->reg );
/* XXX what todo */
}
while (p->reg != -1) {
err = 0;
- err += miiphy_read( devAddr+phyTab[i],p->reg,&val );
+ err += bb_miiphy_read(NULL, devAddr+phyTab[i],p->reg,&val );
val &= p->msk;
val |= p->val;
- err += miiphy_write( devAddr+phyTab[i],p->reg,val );
+ err += bb_miiphy_write(NULL, devAddr+phyTab[i],p->reg,val );
if (err) {
printf( "%s [ERR] config phy %d register %d\n",_f,i,p->reg );
/* XXX what todo */
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
iop->pdat |= 0x00080000;
for (i=0; i<100; i++) {
udelay(20000);
- if (miiphy_read( CFG_PHY_ADDR,2,&val ) == 0) {
+ if (bb_miiphy_read("FCC1 ETHERNET", CFG_PHY_ADDR,2,&val ) == 0) {
break;
}
}
*/
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
puts ("Board: ");
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
+ cpu/ppc4xx/4xx_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
{
DECLARE_GLOBAL_DATA_PTR;
- unsigned char *s;
- unsigned char buf[64];
+ char *s;
+ char buf[64];
int i;
i = getenv_r ("board_id", buf, sizeof (buf));
int last_stage_init (void)
{
#if !defined(CONFIG_SC)
- unsigned char buf[256];
+ char buf[256];
int i;
/*
_edata = .;
PROVIDE (edata = .);
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
#endif
switch (value)
{
- case 0x01:
- case AMD_MANUFACT:
+ case 0x1: /* AMD_MANUFACT */
info->flash_id = FLASH_MAN_AMD;
break;
- case FUJ_MANUFACT:
+ case 0x4: /* FUJ_MANUFACT */
info->flash_id = FLASH_MAN_FUJ;
break;
PrintState ();
#endif
/* printf ("\nChecking bank1..."); */
- size8 = dram_size (CFG_MBMR_8COL, (ulong *) SDRAM_BASE1_PRELIM,
+ size8 = dram_size (CFG_MBMR_8COL, (long *) SDRAM_BASE1_PRELIM,
SDRAM_MAX_SIZE);
size_b0 = size8;
/* printf ("\nChecking bank2..."); */
size_b1 =
- dram_size (memctl->memc_mbmr, (ulong *) SDRAM_BASE2_PRELIM,
+ dram_size (memctl->memc_mbmr, (long *) SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
/*
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
#if 0
ulong base = (ulong)addr;
#endif
- uchar value;
+ ulong value;
/* Write auto select command: read Manufacturer ID */
#if 0
switch (value)
{
- case AMD_MANUFACT:case 0x01:
+ case AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
(Rx[8] != ':') | (Rx[11] != ':') | (Rx[14] != ':')) {
printf ("*** ethernet addr invalid, using default ***\n");
} else {
- setenv ("ethaddr", Rx);
+ setenv ("ethaddr", (char *)Rx);
}
return (0);
}
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
int mem_test_data (void)
{
unsigned long long *pmem = (unsigned long long *) CFG_SDRAM_BASE;
- unsigned long long temp64;
+ unsigned long long temp64 = 0;
int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
int i;
unsigned int hi, lo;
unsigned long long wmask, short read, short write)
{
unsigned int i;
- unsigned long long temp;
+ unsigned long long temp = 0;
unsigned int hitemp, lotemp, himask, lomask;
for (i = 0; i < size; i++) {
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
DECLARE_GLOBAL_DATA_PTR;
- unsigned char *s = getenv ("serial#");
- unsigned char *e;
+ char *s = getenv ("serial#");
+ char *e;
puts ("Board: ");
*
* try 8 column mode
*/
- size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE_PRELIM,
+ size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE_PRELIM,
SDRAM_MAX_SIZE);
udelay (1000);
/*
* try 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE_PRELIM,
+ size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
+#include <malloc.h>
#ifndef CFG_RAMBOOT
static void sdram_start (int hi_addr)
return 0;
}
-int misc_init_f (void)
+#ifdef CONFIG_PREBOOT
+
+static uchar kbd_magic_prefix[] = "key_magic";
+static uchar kbd_command_prefix[] = "key_cmd";
+
+#define S1_ROT 0xf0
+#define S2_Q 0x40
+#define S2_M 0x20
+
+struct kbd_data_t {
+ char s1;
+ char s2;
+};
+
+struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
+{
+ kbd_data->s1 = *((volatile uchar*)(CFG_STATUS1_BASE));
+ kbd_data->s2 = *((volatile uchar*)(CFG_STATUS2_BASE));
+
+ return kbd_data;
+}
+
+static int compare_magic (const struct kbd_data_t *kbd_data, uchar *str)
{
+ char s1 = str[0];
+ char s2;
+
+ if (s1 >= '0' && s1 <= '9')
+ s1 -= '0';
+ else if (s1 >= 'a' && s1 <= 'f')
+ s1 = s1 - 'a' + 10;
+ else if (s1 >= 'A' && s1 <= 'F')
+ s1 = s1 - 'A' + 10;
+ else
+ return -1;
+
+ if (((S1_ROT & kbd_data->s1) >> 4) != s1)
+ return -1;
+
+ s2 = (S2_Q | S2_M) & kbd_data->s2;
+
+ switch (str[1]) {
+ case 'q':
+ case 'Q':
+ if (s2 == S2_Q)
+ return -1;
+ break;
+ case 'm':
+ case 'M':
+ if (s2 == S2_M)
+ return -1;
+ break;
+ case '\0':
+ if (s2 == (S2_Q | S2_M))
+ return 0;
+ default:
+ return -1;
+ }
+
+ if (str[2])
+ return -1;
+
+ return 0;
+}
+
+static uchar *key_match (const struct kbd_data_t *kbd_data)
+{
+ uchar magic[sizeof (kbd_magic_prefix) + 1];
+ uchar *suffix;
+ uchar *kbd_magic_keys;
+
+ /*
+ * The following string defines the characters that can be appended
+ * to "key_magic" to form the names of environment variables that
+ * hold "magic" key codes, i. e. such key codes that can cause
+ * pre-boot actions. If the string is empty (""), then only
+ * "key_magic" is checked (old behaviour); the string "125" causes
+ * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
+ */
+ if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
+ kbd_magic_keys = "";
+
+ /* loop over all magic keys;
+ * use '\0' suffix in case of empty string
+ */
+ for (suffix = kbd_magic_keys; *suffix ||
+ suffix == kbd_magic_keys; ++suffix) {
+ sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
+
+ if (compare_magic(kbd_data, getenv(magic)) == 0) {
+ uchar cmd_name[sizeof (kbd_command_prefix) + 1];
+ char *cmd;
+
+ sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
+ cmd = getenv (cmd_name);
+
+ return (cmd);
+ }
+ }
+
+ return (NULL);
+}
+
+#endif /* CONFIG_PREBOOT */
+
+int misc_init_r (void)
+{
+#ifdef CONFIG_PREBOOT
+ struct kbd_data_t kbd_data;
+ /* Decode keys */
+ uchar *str = strdup (key_match (get_keys (&kbd_data)));
+ /* Set or delete definition */
+ setenv ("preboot", str);
+ free (str);
+#endif /* CONFIG_PREBOOT */
+
return 0;
}
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
eeprom_read (dev_addr, offset, (uchar *)&crc, sizeof (ulong));
offset += sizeof (ulong);
- if (crc32 (crc32 (0, (char *)&hdr, sizeof hdr), data, len) != crc)
+ if (crc32 (crc32 (0, (uchar *)&hdr, sizeof hdr), data, len) != crc)
return (0);
ep->ver = hdr.ver;
char *eval;
ulong lval;
- lval = simple_strtol (val, &eval, 10);
+ lval = simple_strtol ((char *)val, &eval, 10);
if ((uchar *)eval == val || *eval != '\0') {
printf ("%s rec (%s) is not a valid uint\n", rp->name, val);
date_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp)
{
hymod_date_t date;
- uchar *p = val;
+ char *p = (char *)val;
char *ep;
ulong lval;
lval = simple_strtol (p, &ep, 10);
- if ((uchar *)ep == p || *ep++ != '-') {
+ if (ep == p || *ep++ != '-') {
bad_date:
printf ("%s rec (%s) is not a valid date\n", rp->name, val);
return (NULL);
date.year = lval;
lval = simple_strtol (p = ep, &ep, 10);
- if ((uchar *)ep == p || *ep++ != '-' || lval == 0 || lval > 12)
+ if (ep == p || *ep++ != '-' || lval == 0 || lval > 12)
goto bad_date;
date.month = lval;
lval = simple_strtol (p = ep, &ep, 10);
- if ((uchar *)ep == p || *ep != '\0' || lval == 0 || lval > 31)
+ if (ep == p || *ep != '\0' || lval == 0 || lval > 31)
goto bad_date;
date.day = lval;
{
uint len;
- if ((len = strlen (val)) > rp->maxlen) {
+ if ((len = strlen ((char *)val)) > rp->maxlen) {
printf ("%s rec (%s) string is too long (%d>%d)\n",
rp->name, val, len, rp->maxlen);
return (NULL);
for (nbytes = 0, p = val; *p != '\0'; p = (uchar *)ep) {
ulong lval;
- lval = simple_strtol (p, &ep, 10);
+ lval = simple_strtol ((char *)p, &ep, 10);
if ((uchar *)ep == p || (*ep != '\0' && *ep != ',') || \
lval >= 256) {
printf ("%s rec (%s) byte array has invalid uint\n",
eerec_map_t *rp;
for (rp = eerec_map; rp < &eerec_map[neerecs]; rp++)
- if (strcmp (name, rp->name) == 0)
+ if (strcmp ((char *)name, rp->name) == 0)
break;
if (rp >= &eerec_map[neerecs])
char ov[CFG_CBSIZE], nv[CFG_CBSIZE], *p, *q, *nn, c, *curver, *newver;
int override = 1, append = 0, remove = 0, nnl, ovl, nvl;
- nn = name;
+ nn = (char *)name;
if (*nn == '-') {
override = 0;
return (0);
}
- p = value;
+ p = (char *)value;
q = nv;
while ((c = *p) == ' ' || c == '\t')
fetchlinux=tftp 100000 /hymod/linux.bin
eraselinux=erase 1:2-4
-copylinux=cp.b 100000 40080000 $(filesize)
-cmplinux=cmp.b 100000 40080000 $(filesize)
+copylinux=cp.b 100000 40080000 ${filesize}
+cmplinux=cmp.b 100000 40080000 ${filesize}
newlinux=run fetchlinux eraselinux copylinux cmplinux
fetchaltlinux=tftp 100000 /hymod/altlinux.bin
erasealtlinux=erase 1:5-7
-copyaltlinux=cp.b 100000 40140000 $(filesize)
-cmpaltlinux=cmp.b 100000 40140000 $(filesize)
+copyaltlinux=cp.b 100000 40140000 ${filesize}
+cmpaltlinux=cmp.b 100000 40140000 ${filesize}
newaltlinux=run fetchaltlinux erasealtlinux copyaltlinux cmpaltlinux
fetchroot=tftp 100000 /hymod/root.bin
eraseroot=erase 1:8-47
-copyroot=cp.b 100000 40200000 $(filesize)
-cmproot=cmp.b 100000 40200000 $(filesize)
+copyroot=cp.b 100000 40200000 ${filesize}
+cmproot=cmp.b 100000 40200000 ${filesize}
newroot=run fetchroot eraseroot copyroot cmproot
fetchard=tftp 100000 /hymod/apprd.bin
eraseard=erase 1:48-63
-copyard=cp.b 100000 40c00000 $(filesize)
-cmpard=cmp.b 100000 40c00000 $(filesize)
+copyard=cp.b 100000 40c00000 ${filesize}
+cmpard=cmp.b 100000 40c00000 ${filesize}
newapprd=run fetchard eraseard copyard cmpard
# pass above map to linux mtd driver
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
int i;
uchar *boottype;
uchar *bootletter;
- uchar *fmt;
+ char *fmt;
uchar botbootletter[] = "B";
uchar topbootletter[] = "T";
uchar botboottype[] = "bottom boot sector";
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
- test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
sdram_start(1);
- test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
/* find RAM size using SDRAM CS1 only */
if (!dramsize)
sdram_start(0);
- test2 = test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+ test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
if (!dramsize) {
sdram_start(1);
- test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+ test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
}
if (test1 > test2) {
sdram_start(0);
/* find RAM size */
sdram_start(0);
- test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
sdram_start(1);
- test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
value = addr[1]; /* device ID */
- switch (value) {
+ switch ((unsigned long)value) {
case AMD_ID_F040B:
info->flash_id += FLASH_AM040;
info->sector_count = 8;
*
* try 8 column mode
*/
- size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE1_PRELIM,
+ size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE1_PRELIM,
SDRAM_MAX_SIZE);
udelay (1000);
/*
* try 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE1_PRELIM,
+ size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE1_PRELIM,
SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
int i;
uchar *boottype;
uchar *bootletter;
- uchar *fmt;
+ char *fmt;
uchar botbootletter[] = "B";
uchar topbootletter[] = "T";
uchar botboottype[] = "bottom boot sector";
{
*INCA_IP_SDRAM_MC_CFGPB0 = (0x14 << 8) |
(rows << 4) | cols;
- size = get_ram_size((ulong *)CFG_SDRAM_BASE,
+ size = get_ram_size((long *)CFG_SDRAM_BASE,
max_sdram_size());
if (size > max_size)
.globl ebu_init
.ent ebu_init
ebu_init:
+__ebu_init:
li t1, EBU_MODUL_BASE
li t2, 0xA0000041
.globl cgu_init
.ent cgu_init
cgu_init:
+__cgu_init:
li t1, CGU_MODUL_BASE
.globl sdram_init
.ent sdram_init
sdram_init:
+__sdram_init:
li t1, MC_MODUL_BASE
/* We rely on the fact that neither ebu_init() nor cgu_init() nor sdram_init()
* modify t0 and a0.
*/
- bal cgu_init
+ bal __cgu_init
nop
- bal ebu_init
+ bal __ebu_init
nop
- bal sdram_init
+ bal __sdram_init
nop
move ra, t0
.sdata : { *(.sdata) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
LIB = lib$(BOARD).a
OBJS := integratorap.o flash.o
-SOBJS := platform.o
+SOBJS := lowlevel_init.o memsetup.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
#include <common.h>
#ifdef CONFIG_PCI
+#include <pci.h>
#endif
void flash__init (void);
#if defined(CONFIG_SHOW_BOOT_PROGRESS)
void show_boot_progress(int progress)
{
- printf("Boot reached stage %d\n", progress);
+ printf("Boot reached stage %d\n", progress);
}
#endif
gd->flags = 0;
+#ifdef CONFIG_CM_REMAP
+extern void cm_remap(void);
+ cm_remap(); /* remaps writeable memory to 0x00000000 */
+#endif
+
icache_enable ();
flash__init ();
/* V3 access routines */
#define _V3Write16(o,v) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned short)(v))
-#define _V3Read16(o) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)))
+#define _V3Read16(o) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)))
#define _V3Write32(o,v) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned int)(v))
-#define _V3Read32(o) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)))
+#define _V3Read32(o) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)))
/* Compute address necessary to access PCI config space for the given */
/* bus and device. */
#define PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) ({ \
unsigned int __address, __devicebit; \
unsigned short __mapaddress; \
- unsigned int __dev = PCI_DEV (__devfn); /* FIXME to check!! (slot?) */ \
+ unsigned int __dev = PCI_DEV (__devfn); /* FIXME to check!! (slot?) */ \
\
if (__bus == 0) { \
/* local bus segment so need a type 0 config cycle */ \
/* A31-A24 are don't care (so clear to 0) */ \
__mapaddress = 0x000B; /* 101=>config cycle, 1=>A1&A0 from PCI_CFG */ \
__address = PCI_CONFIG_BASE; \
- __address |= ((__bus & 0xFF) << 16); /* bits 23..16 = bus number */ \
- __address |= ((__dev & 0x1F) << 11); /* bits 15..11 = device number */ \
+ __address |= ((__bus & 0xFF) << 16); /* bits 23..16 = bus number */ \
+ __address |= ((__dev & 0x1F) << 11); /* bits 15..11 = device number */ \
__address |= ((__devfn & 0x07) << 8); /* bits 10..8 = function number */ \
- __address |= __offset & 0xFF; /* bits 7..0 = register number */ \
+ __address |= __offset & 0xFF; /* bits 7..0 = register number */ \
} \
_V3Write16 (V3_LB_MAP1, __mapaddress); \
__address; \
/*************************************************************
Routine:ether__init
Description: take the Ethernet controller out of reset and wait
- for the EEPROM load to complete.
+ for the EEPROM load to complete.
*************************************************************/
void ether__init (void)
{
******************************/
int dram_init (void)
{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+#ifdef CONFIG_CM_SPD_DETECT
+ {
+extern void dram_query(void);
+ unsigned long cm_reg_sdram;
+ unsigned long sdram_shift;
+
+ dram_query(); /* Assembler accesses to CM registers */
+ /* Queries the SPD values */
+
+ /* Obtain the SDRAM size from the CM SDRAM register */
+
+ cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM);
+ /* Register SDRAM size
+ *
+ * 0xXXXXXXbbb000bb 16 MB
+ * 0xXXXXXXbbb001bb 32 MB
+ * 0xXXXXXXbbb010bb 64 MB
+ * 0xXXXXXXbbb011bb 128 MB
+ * 0xXXXXXXbbb100bb 256 MB
+ *
+ */
+ sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
+ gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift;
+
+ }
+#endif /* CM_SPD_DETECT */
+
return 0;
}
+
+/* The Integrator/AP timer1 is clocked at 24MHz
+ * can be divided by 16 or 256
+ * and is a 16-bit counter
+ */
+/* U-Boot expects a 32 bit timer running at CFG_HZ*/
+static ulong timestamp; /* U-Boot ticks since startup */
+static ulong total_count = 0; /* Total timer count */
+static ulong lastdec; /* Timer reading at last call */
+static ulong div_clock = 256; /* Divisor applied to the timer clock */
+static ulong div_timer = 1; /* Divisor to convert timer reading
+ * change to U-Boot ticks
+ */
+/* CFG_HZ = CFG_HZ_CLOCK/(div_clock * div_timer) */
+
+#define TIMER_LOAD_VAL 0x0000FFFFL
+#define READ_TIMER ((*(volatile ulong *)(CFG_TIMERBASE+4)) & 0x0000FFFFL)
+
+/* all function return values in U-Boot ticks i.e. (1/CFG_HZ) sec
+ * - unless otherwise stated
+ */
+
+/* starts a counter
+ * - the Integrator/AP timer issues an interrupt
+ * each time it reaches zero
+ */
+int interrupt_init (void)
+{
+ /* Load timer with initial value */
+ *(volatile ulong *)(CFG_TIMERBASE + 0) = TIMER_LOAD_VAL;
+ /* Set timer to be
+ * enabled 1
+ * free-running 0
+ * XX 00
+ * divider 256 10
+ * XX 00
+ */
+ *(volatile ulong *)(CFG_TIMERBASE + 8) = 0x00000088;
+ total_count = 0;
+ /* init the timestamp and lastdec value */
+ reset_timer_masked();
+
+ div_timer = CFG_HZ_CLOCK / CFG_HZ;
+ div_timer /= div_clock;
+
+ return (0);
+}
+
+/*
+ * timer without interrupts
+ */
+void reset_timer (void)
+{
+ reset_timer_masked ();
+}
+
+ulong get_timer (ulong base_ticks)
+{
+ return get_timer_masked () - base_ticks;
+}
+
+void set_timer (ulong ticks)
+{
+ timestamp = ticks;
+ total_count = ticks * div_timer;
+ reset_timer_masked();
+}
+
+/* delay x useconds */
+void udelay (unsigned long usec)
+{
+ ulong tmo, tmp;
+
+ /* Convert to U-Boot ticks */
+ tmo = usec * CFG_HZ;
+ tmo /= (1000000L);
+
+ tmp = get_timer_masked(); /* get current timestamp */
+ tmo += tmp; /* wake up timestamp */
+
+ while (get_timer_masked () < tmo) { /* loop till event */
+ /*NOP*/;
+ }
+}
+
+void reset_timer_masked (void)
+{
+ /* reset time */
+ lastdec = READ_TIMER; /* capture current decrementer value */
+ timestamp = 0; /* start "advancing" time stamp from 0 */
+}
+
+/* converts the timer reading to U-Boot ticks */
+/* the timestamp is the number of ticks since reset */
+/* This routine does not detect wraps unless called regularly
+ ASSUMES a call at least every 16 seconds to detect every reload */
+ulong get_timer_masked (void)
+{
+ ulong now = READ_TIMER; /* current count */
+
+ if (now > lastdec) {
+ /* Must have wrapped */
+ total_count += lastdec + TIMER_LOAD_VAL + 1 - now;
+ } else {
+ total_count += lastdec - now;
+ }
+ lastdec = now;
+ timestamp = total_count/div_timer;
+
+ return timestamp;
+}
+
+/* waits specified delay value and resets timestamp */
+void udelay_masked (unsigned long usec)
+{
+ udelay(usec);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * Return the timebase clock frequency
+ * i.e. how often the timer decrements
+ */
+ulong get_tbclk (void)
+{
+ return CFG_HZ_CLOCK/div_clock;
+}
--- /dev/null
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2004, ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+ /* Reset using CM control register */
+.global reset_cpu
+reset_cpu:
+ mov r0, #CM_BASE
+ ldr r1,[r0,#OS_CTRL]
+ orr r1,r1,#CMMASK_RESET
+ str r1,[r0,#OS_CTRL]
+
+reset_failed:
+ b reset_failed
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+ /* If U-Boot has been run after the ARM boot monitor
+ * then all the necessary actions have been done
+ * otherwise we are running from user flash mapped to 0x00000000
+ * --- DO NOT REMAP BEFORE THE CODE HAS BEEN RELOCATED --
+ * Changes to the (possibly soft) reset defaults of the processor
+ * itself should be performed in cpu/arm<>/start.S
+ * This function affects only the core module or board settings
+ */
+
+#ifdef CONFIG_CM_INIT
+ /* CM has an initialization register
+ * - bits in it are wired into test-chip pins to force
+ * reset defaults
+ * - may need to change its contents for U-Boot
+ */
+
+ /* set the desired CM specific value */
+ mov r2,#CMMASK_LOWVEC /* Vectors at 0x00000000 for all */
+
+#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
+ orr r2,r2,#CMMASK_INIT_102
+#else
+
+#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
+ !defined (CONFIG_CM940T)
+
+#ifdef CONFIG_CM_MULTIPLE_SSRAM
+ /* set simple mapping */
+ and r2,r2,#CMMASK_MAP_SIMPLE
+#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */
+
+#ifdef CONFIG_CM_TCRAM
+ /* disable TCRAM */
+ and r2,r2,#CMMASK_TCRAM_DISABLE
+#endif /* #ifdef CONFIG_CM_TCRAM */
+
+#if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \
+ defined (CONFIG_CM1136JF_S)
+
+ and r2,r2,#CMMASK_LE
+
+#endif /* cpu with little endian initialization */
+
+ orr r2,r2,#CMMASK_CMxx6_COMMON
+
+#endif /* CMxx6 code */
+
+#endif /* ARM102xxE value */
+
+ /* read CM_INIT */
+ mov r0, #CM_BASE
+ ldr r1, [r0, #OS_INIT]
+ /* check against desired bit setting */
+ and r3,r1,r2
+ cmp r3,r2
+ beq init_reg_OK
+
+ /* lock for change */
+ mov r3, #CMVAL_LOCK1
+ add r3,r3,#CMVAL_LOCK2
+ str r3, [r0, #OS_LOCK]
+ /* set desired value */
+ orr r1,r1,r2
+ /* write & relock CM_INIT */
+ str r1, [r0, #OS_INIT]
+ mov r1, #CMVAL_UNLOCK
+ str r1, [r0, #OS_LOCK]
+
+ /* soft reset so new values used */
+ b reset_cpu
+
+init_reg_OK:
+
+#endif /* CONFIG_CM_INIT */
+
+ mov pc, lr
+
+#ifdef CONFIG_CM_SPD_DETECT
+ /* Fast memory is available for the DRAM data
+ * - ensure it has been transferred, then summarize the data
+ * into a CM register
+ */
+.globl dram_query
+dram_query:
+ stmfd r13!,{r4-r6,lr}
+ /* set up SDRAM info */
+ /* - based on example code from the CM User Guide */
+ mov r0, #CM_BASE
+
+readspdbit:
+ ldr r1, [r0, #OS_SDRAM] /* read the SDRAM register */
+ and r1, r1, #0x20 /* mask SPD bit (5) */
+ cmp r1, #0x20 /* test if set */
+ bne readspdbit
+
+setupsdram:
+ add r0, r0, #OS_SPD /* address the copy of the SDP data */
+ ldrb r1, [r0, #3] /* number of row address lines */
+ ldrb r2, [r0, #4] /* number of column address lines */
+ ldrb r3, [r0, #5] /* number of banks */
+ ldrb r4, [r0, #31] /* module bank density */
+ mul r5, r4, r3 /* size of SDRAM (MB divided by 4) */
+ mov r5, r5, ASL#2 /* size in MB */
+ mov r0, #CM_BASE /* reload for later code */
+ cmp r5, #0x10 /* is it 16MB? */
+ bne not16
+ mov r6, #0x2 /* store size and CAS latency of 2 */
+ b writesize
+
+not16:
+ cmp r5, #0x20 /* is it 32MB? */
+ bne not32
+ mov r6, #0x6
+ b writesize
+
+not32:
+ cmp r5, #0x40 /* is it 64MB? */
+ bne not64
+ mov r6, #0xa
+ b writesize
+
+not64:
+ cmp r5, #0x80 /* is it 128MB? */
+ bne not128
+ mov r6, #0xe
+ b writesize
+
+not128:
+ /* if it is none of these sizes then it is either 256MB, or
+ * there is no SDRAM fitted so default to 256MB
+ */
+ mov r6, #0x12
+
+writesize:
+ mov r1, r1, ASL#8 /* row addr lines from SDRAM reg */
+ orr r2, r1, r2, ASL#12 /* OR in column address lines */
+ orr r3, r2, r3, ASL#16 /* OR in number of banks */
+ orr r6, r6, r3 /* OR in size and CAS latency */
+ str r6, [r0, #OS_SDRAM] /* store SDRAM parameters */
+
+#endif /* #ifdef CONFIG_CM_SPD_DETECT */
+
+ ldmfd r13!,{r4-r6,pc} /* back to caller */
+
+#ifdef CONFIG_CM_REMAP
+ /* CM remap bit is operational
+ * - use it to map writeable memory at 0x00000000, in place of flash
+ */
+.globl cm_remap
+cm_remap:
+ stmfd r13!,{r4-r10,lr}
+
+ mov r0, #CM_BASE
+ ldr r1, [r0, #OS_CTRL]
+ orr r1, r1, #CMMASK_REMAP /* set remap and led bits */
+ str r1, [r0, #OS_CTRL]
+
+ /* Now 0x00000000 is writeable, replace the vectors */
+ ldr r0, =_start /* r0 <- start of vectors */
+ ldr r2, =_armboot_start /* r2 <- past vectors */
+ sub r1,r1,r1 /* destination 0x00000000 */
+
+copy_vec:
+ ldmia r0!, {r3-r10} /* copy from source address [r0] */
+ stmia r1!, {r3-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ ble copy_vec
+
+ ldmfd r13!,{r4-r10,pc} /* back to caller */
+
+#endif /* #ifdef CONFIG_CM_REMAP */
/*
- * Board specific setup info
- *
- * (C) Copyright 2004, ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
+ * Memory setup for integratorAP
*
* See file CREDITS for list of people who contributed to this
* project.
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
+/*
+ * Memory setup
+ * - the reset defaults are assumed sufficient
+ */
-#include <config.h>
-#include <version.h>
-
-.globl platformsetup
-platformsetup:
-
- /* All done by Integrator's boot monitor! */
- mov pc, lr
+.globl memsetup
+memsetup:
+ mov pc,lr
--- /dev/null
+#!/bin/sh
+# ---------------------------------------------------------
+# Set the platform defines
+# ---------------------------------------------------------
+echo -n "/* Integrator configuration implied " > tmp.fil
+echo " by Makefile target */" >> tmp.fil
+echo -n "#define CONFIG_INTEGRATOR" >> tmp.fil
+echo " /* Integrator board */" >> tmp.fil
+echo -n "#define CONFIG_ARCH_INTEGRATOR" >> tmp.fil
+echo " 1 /* Integrator/AP */" >> tmp.fil
+# ---------------------------------------------------------
+# Set the core module defines according to Core Module
+# ---------------------------------------------------------
+cpu="arm_intcm"
+variant="unknown core module"
+
+if [ "$1" == "" ]
+then
+ echo "$0:: No parameters - using arm_intcm"
+else
+ case "$1" in
+ ap7_config)
+ cpu="arm_intcm"
+ variant="unported core module CM7TDMI"
+ ;;
+
+ ap966)
+ cpu="arm_intcm"
+ variant="unported core module CM966E-S"
+ ;;
+
+ ap922_config)
+ cpu="arm_intcm"
+ variant="unported core module CM922T"
+ ;;
+
+ integratorap_config | \
+ ap_config)
+ cpu="arm_intcm"
+ variant="unspecified core module"
+ ;;
+
+ ap720t_config)
+ cpu="arm720t"
+ echo -n "#define CONFIG_CM720T" >> tmp.fil
+ echo " 1 /* CPU core is ARM720T */ " >> tmp.fil
+ variant="Core module CM720T"
+ ;;
+
+ ap922_XA10_config)
+ cpu="arm_intcm"
+ variant="unported core module CM922T_XA10"
+ echo -n "#define CONFIG_CM922T_XA10" >> tmp.fil
+ echo " 1 /* CPU core is ARM922T_XA10 */" >> tmp.fil
+ ;;
+
+ ap920t_config)
+ cpu="arm920t"
+ variant="Core module CM920T"
+ echo -n "#define CONFIG_CM920T" >> tmp.fil
+ echo " 1 /* CPU core is ARM920T */" >> tmp.fil
+ ;;
+
+ ap926ejs_config)
+ cpu="arm926ejs"
+ variant="Core module CM926EJ-S"
+ echo -n "#define CONFIG_CM926EJ_S" >> tmp.fil
+ echo " 1 /* CPU core is ARM926EJ-S */ " >> tmp.fil
+ ;;
+
+ ap946es_config)
+ cpu="arm946es"
+ variant="Core module CM946E-S"
+ echo -n "#define CONFIG_CM946E_S" >> tmp.fil
+ echo " 1 /* CPU core is ARM946E-S */ " >> tmp.fil
+ ;;
+
+ *)
+ echo "$0:: Unknown core module"
+ variant="unknown core module"
+ cpu="arm_intcm"
+ ;;
+
+ esac
+fi
+
+if [ "$cpu" == "arm_intcm" ]
+then
+ echo "/* Core module undefined/not ported */" >> tmp.fil
+ echo "#define CONFIG_ARM_INTCM 1" >> tmp.fil
+ echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> tmp.fil
+ echo -n " /* CM may not have " >> tmp.fil
+ echo "multiple SSRAM mapping */" >> tmp.fil
+ echo -n "#undef CONFIG_CM_SPD_DETECT " >> tmp.fil
+ echo -n " /* CM may not support SPD " >> tmp.fil
+ echo "query */" >> tmp.fil
+ echo -n "#undef CONFIG_CM_REMAP " >> tmp.fil
+ echo -n " /* CM may not support " >> tmp.fil
+ echo "remapping */" >> tmp.fil
+ echo -n "#undef CONFIG_CM_INIT " >> tmp.fil
+ echo -n " /* CM may not have " >> tmp.fil
+ echo "initialization reg */" >> tmp.fil
+ echo -n "#undef CONFIG_CM_TCRAM " >> tmp.fil
+ echo " /* CM may not have TCRAM */" >> tmp.fil
+fi
+mv tmp.fil ./include/config.h
+# ---------------------------------------------------------
+# Ensure correct core object loaded first in U-Boot image
+# ---------------------------------------------------------
+sed -r 's/CPU_FILE/cpu\/'$cpu'\/start.o/; s/#.*//' board/integratorap/u-boot.lds.template > board/integratorap/u-boot.lds
+# ---------------------------------------------------------
+# Complete the configuration
+# ---------------------------------------------------------
+./mkconfig -a integratorap arm $cpu integratorap;
+echo "Variant:: $variant with core $cpu"
+
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+# Template used during configuration to emsure the core module processor code,
+# from CPU_FILE, is placed at the start of the image */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+ . = ALIGN(4);
+ .text :
+ {
+ CPU_FILE (.text)
+ *(.text)
+ }
+ .rodata : { *(.rodata) }
+ . = ALIGN(4);
+ .data : { *(.data) }
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
LIB = lib$(BOARD).a
OBJS := integratorcp.o flash.o
-SOBJS := platform.o
+SOBJS := lowlevel_init.o memsetup.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
#if defined(CONFIG_SHOW_BOOT_PROGRESS)
void show_boot_progress(int progress)
{
- printf("Boot reached stage %d\n", progress);
+ printf("Boot reached stage %d\n", progress);
}
#endif
#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
-static inline void delay (unsigned long loops)
-{
- __asm__ volatile ("1:\n"
- "subs %0, %1, #1\n"
- "bne 1b":"=r" (loops):"0" (loops));
-}
-
/*
* Miscellaneous platform dependent initialisations
*/
gd->flags = 0;
+#ifdef CONFIG_CM_REMAP
+extern void cm_remap(void);
+ cm_remap(); /* remaps writeable memory to 0x00000000 */
+#endif
+
icache_enable ();
flash__init ();
/*************************************************************
Routine:ether__init
Description: take the Ethernet controller out of reset and wait
- for the EEPROM load to complete.
+ for the EEPROM load to complete.
*************************************************************/
void ether__init (void)
{
******************************/
int dram_init (void)
{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+#ifdef CONFIG_CM_SPD_DETECT
+ {
+extern void dram_query(void);
+ unsigned long cm_reg_sdram;
+ unsigned long sdram_shift;
+
+ dram_query(); /* Assembler accesses to CM registers */
+ /* Queries the SPD values */
+
+ /* Obtain the SDRAM size from the CM SDRAM register */
+
+ cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM);
+ /* Register SDRAM size
+ *
+ * 0xXXXXXXbbb000bb 16 MB
+ * 0xXXXXXXbbb001bb 32 MB
+ * 0xXXXXXXbbb010bb 64 MB
+ * 0xXXXXXXbbb011bb 128 MB
+ * 0xXXXXXXbbb100bb 256 MB
+ *
+ */
+ sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
+ gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift;
+
+ }
+#endif /* CM_SPD_DETECT */
+
return 0;
}
+
+/* The Integrator/CP timer1 is clocked at 1MHz
+ * can be divided by 16 or 256
+ * and can be set up as a 32-bit timer
+ */
+/* U-Boot expects a 32 bit timer, running at CFG_HZ */
+/* Keep total timer count to avoid losing decrements < div_timer */
+static unsigned long long total_count = 0;
+static unsigned long long lastdec; /* Timer reading at last call */
+static unsigned long long div_clock = 1; /* Divisor applied to timer clock */
+static unsigned long long div_timer = 1; /* Divisor to convert timer reading
+ * change to U-Boot ticks
+ */
+/* CFG_HZ = CFG_HZ_CLOCK/(div_clock * div_timer) */
+static ulong timestamp; /* U-Boot ticks since startup */
+
+#define TIMER_LOAD_VAL ((ulong)0xFFFFFFFF)
+#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+4))
+
+/* all function return values in U-Boot ticks i.e. (1/CFG_HZ) sec
+ * - unless otherwise stated
+ */
+
+/* starts up a counter
+ * - the Integrator/CP timer can be set up to issue an interrupt */
+int interrupt_init (void)
+{
+ /* Load timer with initial value */
+ *(volatile ulong *)(CFG_TIMERBASE + 0) = TIMER_LOAD_VAL;
+ /* Set timer to be
+ * enabled 1
+ * periodic 1
+ * no interrupts 0
+ * X 0
+ * divider 1 00 == less rounding error
+ * 32 bit 1
+ * wrapping 0
+ */
+ *(volatile ulong *)(CFG_TIMERBASE + 8) = 0x000000C2;
+ /* init the timestamp */
+ total_count = 0ULL;
+ reset_timer_masked();
+
+ div_timer = (unsigned long long)(CFG_HZ_CLOCK / CFG_HZ);
+ div_timer /= div_clock;
+
+ return (0);
+}
+
+/*
+ * timer without interrupts
+ */
+void reset_timer (void)
+{
+ reset_timer_masked ();
+}
+
+ulong get_timer (ulong base_ticks)
+{
+ return get_timer_masked () - base_ticks;
+}
+
+void set_timer (ulong ticks)
+{
+ timestamp = ticks;
+ total_count = (unsigned long long)ticks * div_timer;
+}
+
+/* delay usec useconds */
+void udelay (unsigned long usec)
+{
+ ulong tmo, tmp;
+
+ /* Convert to U-Boot ticks */
+ tmo = usec * CFG_HZ;
+ tmo /= (1000000L);
+
+ tmp = get_timer_masked(); /* get current timestamp */
+ tmo += tmp; /* form target timestamp */
+
+ while (get_timer_masked () < tmo) {/* loop till event */
+ /*NOP*/;
+ }
+}
+
+void reset_timer_masked (void)
+{
+ /* capure current decrementer value */
+ lastdec = (unsigned long long)READ_TIMER;
+ /* start "advancing" time stamp from 0 */
+ timestamp = 0L;
+}
+
+/* converts the timer reading to U-Boot ticks */
+/* the timestamp is the number of ticks since reset */
+ulong get_timer_masked (void)
+{
+ /* get current count */
+ unsigned long long now = (unsigned long long)READ_TIMER;
+
+ if(now > lastdec) {
+ /* Must have wrapped */
+ total_count += lastdec + TIMER_LOAD_VAL + 1 - now;
+ } else {
+ total_count += lastdec - now;
+ }
+ lastdec = now;
+ timestamp = (ulong)(total_count/div_timer);
+
+ return timestamp;
+}
+
+/* waits specified delay value and resets timestamp */
+void udelay_masked (unsigned long usec)
+{
+ udelay(usec);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return (unsigned long long)get_timer(0);
+}
+
+/*
+ * Return the timebase clock frequency
+ * i.e. how often the timer decrements
+ */
+ulong get_tbclk (void)
+{
+ return (ulong)(((unsigned long long)CFG_HZ_CLOCK)/div_clock);
+}
--- /dev/null
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003, ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+/* Reset using CM control register */
+.global reset_cpu
+reset_cpu:
+ mov r0, #CM_BASE
+ ldr r1,[r0,#OS_CTRL]
+ orr r1,r1,#CMMASK_RESET
+ str r1,[r0,#OS_CTRL]
+
+reset_failed:
+ b reset_failed
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+ /* If U-Boot has been run after the ARM boot monitor
+ * then all the necessary actions have been done
+ * otherwise we are running from user flash mapped to 0x00000000
+ * --- DO NOT REMAP BEFORE THE CODE HAS BEEN RELOCATED --
+ * Changes to the (possibly soft) reset defaults of the processor
+ * itself should be performed in cpu/arm<>/start.S
+ * This function affects only the core module or board settings
+ */
+
+#ifdef CONFIG_CM_INIT
+ /* CM has an initialization register
+ * - bits in it are wired into test-chip pins to force
+ * reset defaults
+ * - may need to change its contents for U-Boot
+ */
+
+ /* set the desired CM specific value */
+ mov r2,#CMMASK_LOWVEC /* Vectors at 0x00000000 for all */
+
+#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
+ orr r2,r2,#CMMASK_INIT_102
+#else
+
+#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
+ !defined (CONFIG_CM940T)
+ /* CMxx6 code */
+
+#ifdef CONFIG_CM_MULTIPLE_SSRAM
+ /* set simple mapping */
+ and r2,r2,#CMMASK_MAP_SIMPLE
+#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */
+
+#ifdef CONFIG_CM_TCRAM
+ /* disable TCRAM */
+ and r2,r2,#CMMASK_TCRAM_DISABLE
+#endif /* #ifdef CONFIG_CM_TCRAM */
+
+#if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \
+ defined (CONFIG_CM1136JF_S)
+
+ and r2,r2,#CMMASK_LE
+
+#endif /* cpu with little endian initialization */
+
+ orr r2,r2,#CMMASK_CMxx6_COMMON
+
+#endif /* CMxx6 code */
+
+#endif /* ARM102xxE value */
+
+ /* read CM_INIT */
+ mov r0, #CM_BASE
+ ldr r1, [r0, #OS_INIT]
+ /* check against desired bit setting */
+ and r3,r1,r2
+ cmp r3,r2
+ beq init_reg_OK
+
+ /* lock for change */
+ mov r3, #CMVAL_LOCK1
+ and r3, r3, #CMVAL_LOCK2
+ str r3, [r0, #OS_LOCK]
+ /* set desired value */
+ orr r1,r1,r2
+ /* write & relock CM_INIT */
+ str r1, [r0, #OS_INIT]
+ mov r1, #CMVAL_UNLOCK
+ str r1, [r0, #OS_LOCK]
+
+ /* soft reset so new values used */
+ b reset_cpu
+
+init_reg_OK:
+
+#endif /* CONFIG_CM_INIT */
+
+ mov pc, lr
+
+#ifdef CONFIG_CM_SPD_DETECT
+ /* Fast memory is available for the DRAM data
+ * - ensure it has been transferred, then summarize the data
+ * into a CM register
+ */
+.globl dram_query
+dram_query:
+ stmfd r13!,{r4-r6,lr}
+ /* set up SDRAM info */
+ /* - based on example code from the CM User Guide */
+ mov r0, #CM_BASE
+
+readspdbit:
+ ldr r1, [r0, #OS_SDRAM] /* read the SDRAM register */
+ and r1, r1, #0x20 /* mask SPD bit (5) */
+ cmp r1, #0x20 /* test if set */
+ bne readspdbit
+
+setupsdram:
+ add r0, r0, #OS_SPD /* address the copy of the SDP data */
+ ldrb r1, [r0, #3] /* number of row address lines */
+ ldrb r2, [r0, #4] /* number of column address lines */
+ ldrb r3, [r0, #5] /* number of banks */
+ ldrb r4, [r0, #31] /* module bank density */
+ mul r5, r4, r3 /* size of SDRAM (MB divided by 4) */
+ mov r5, r5, ASL#2 /* size in MB */
+ mov r0, #CM_BASE /* reload for later code */
+ cmp r5, #0x10 /* is it 16MB? */
+ bne not16
+ mov r6, #0x2 /* store size and CAS latency of 2 */
+ b writesize
+
+not16:
+ cmp r5, #0x20 /* is it 32MB? */
+ bne not32
+ mov r6, #0x6
+ b writesize
+
+not32:
+ cmp r5, #0x40 /* is it 64MB? */
+ bne not64
+ mov r6, #0xa
+ b writesize
+
+not64:
+ cmp r5, #0x80 /* is it 128MB? */
+ bne not128
+ mov r6, #0xe
+ b writesize
+
+not128:
+ /* if it is none of these sizes then it is either 256MB, or
+ * there is no SDRAM fitted so default to 256MB
+ */
+ mov r6, #0x12
+
+writesize:
+ mov r1, r1, ASL#8 /* row addr lines from SDRAM reg */
+ orr r2, r1, r2, ASL#12 /* OR in column address lines */
+ orr r3, r2, r3, ASL#16 /* OR in number of banks */
+ orr r6, r6, r3 /* OR in size and CAS latency */
+ str r6, [r0, #OS_SDRAM] /* store SDRAM parameters */
+
+#endif /* #ifdef CONFIG_CM_SPD_DETECT */
+
+ ldmfd r13!,{r4-r6,pc} /* back to caller */
+
+#ifdef CONFIG_CM_REMAP
+ /* CM remap bit is operational
+ * - use it to map writeable memory at 0x00000000, in place of flash
+ */
+.globl cm_remap
+cm_remap:
+ stmfd r13!,{r4-r10,lr}
+
+ mov r0, #CM_BASE
+ ldr r1, [r0, #OS_CTRL]
+ orr r1, r1, #CMMASK_REMAP /* set remap and led bits */
+ str r1, [r0, #OS_CTRL]
+
+ /* Now 0x00000000 is writeable, replace the vectors */
+ ldr r0, =_start /* r0 <- start of vectors */
+ ldr r2, =_armboot_start /* r2 <- past vectors */
+ sub r1,r1,r1 /* destination 0x00000000 */
+
+copy_vec:
+ ldmia r0!, {r3-r10} /* copy from source address [r0] */
+ stmia r1!, {r3-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ ble copy_vec
+
+ ldmfd r13!,{r4-r10,pc} /* back to caller */
+
+#endif /* #ifdef CONFIG_CM_REMAP */
/*
- * Board specific setup info
- *
- * (C) Copyright 2003, ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
+ * Memory setup for integratorAP
*
* See file CREDITS for list of people who contributed to this
* project.
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
+/*
+ * Memory setup
+ * - the reset defaults are assumed sufficient
+ */
-#include <config.h>
-#include <version.h>
-
-.globl platformsetup
-platformsetup:
-
- /* All done by IntegratorCP's boot monitor! */
- mov pc, lr
+.globl memsetup
+memsetup:
+ mov pc,lr
--- /dev/null
+#!/bin/sh
+# ---------------------------------------------------------
+# Set the platform defines
+# ---------------------------------------------------------
+echo -n "/* Integrator configuration implied " > tmp.fil
+echo " by Makefile target */" >> tmp.fil
+echo -n "#define CONFIG_INTEGRATOR" >> tmp.fil
+echo " /* Integrator board */" >> tmp.fil
+echo -n "#define CONFIG_ARCH_CINTEGRATOR" >> tmp.fil
+echo " 1 /* Integrator/CP */" >> tmp.fil
+
+cpu="arm_intcm"
+variant="unknown core module"
+
+if [ "$1" == "" ]
+then
+ echo "$0:: No parameters - using arm_intcm"
+else
+ case "$1" in
+ ap966)
+ cpu="arm_intcm"
+ variant="unported core module CM966E-S"
+ ;;
+
+ ap922_config)
+ cpu="arm_intcm"
+ variant="unported core module CM922T"
+ ;;
+
+ integratorcp_config | \
+ cp_config)
+ cpu="arm_intcm"
+ variant="unspecified core module"
+ ;;
+
+ cp922_XA10_config)
+ cpu="arm_intcm"
+ variant="unported core module CM922T_XA10"
+ echo -n "#define CONFIG_CM922T_XA10" >> tmp.fil
+ echo " 1 /* CPU core is ARM922T_XA10 */" >> tmp.fil
+ ;;
+
+ cp920t_config)
+ cpu="arm920t"
+ variant="Core module CM920T"
+ echo -n "#define CONFIG_CM920T" >> tmp.fil
+ echo " 1 /* CPU core is ARM920T */" >> tmp.fil
+ ;;
+
+ cp926ejs_config)
+ cpu="arm926ejs"
+ variant="Core module CM926EJ-S"
+ echo -n "#define CONFIG_CM926EJ_S" >> tmp.fil
+ echo " 1 /* CPU core is ARM926EJ-S */ " >> tmp.fil
+ ;;
+
+
+ cp946es_config)
+ cpu="arm946es"
+ variant="Core module CM946E-S"
+ echo -n "#define CONFIG_CM946E_S" >> tmp.fil
+ echo " 1 /* CPU core is ARM946E-S */ " >> tmp.fil
+ ;;
+
+ cp1136_config)
+ cpu="arm1136"
+ variant="Core module CM1136EJF-S"
+ echo -n "#define CONFIG_CM1136EJF_S" >> tmp.fil
+ echo " 1 /* CPU core is ARM1136JF-S */ " >> tmp.fil
+ ;;
+
+ *)
+ echo "$0:: Unknown core module"
+ variant="unknown core module"
+ cpu="arm_intcm"
+ ;;
+
+ esac
+
+fi
+
+if [ "$cpu" == "arm_intcm" ]
+then
+ echo "/* Core module undefined/not ported */" >> tmp.fil
+ echo "#define CONFIG_ARM_INTCM 1" >> tmp.fil
+ echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> tmp.fil
+ echo -n " /* CM may not have " >> tmp.fil
+ echo "multiple SSRAM mapping */" >> tmp.fil
+ echo -n "#undef CONFIG_CM_SPD_DETECT " >> tmp.fil
+ echo -n " /* CM may not support SPD " >> tmp.fil
+ echo "query */" >> tmp.fil
+ echo -n "#undef CONFIG_CM_REMAP " >> tmp.fil
+ echo -n " /* CM may not support " >> tmp.fil
+ echo "remapping */" >> tmp.fil
+ echo -n "#undef CONFIG_CM_INIT " >> tmp.fil
+ echo -n " /* CM may not have " >> tmp.fil
+ echo "initialization reg */" >> tmp.fil
+ echo -n "#undef CONFIG_CM_TCRAM " >> tmp.fil
+ echo " /* CM may not have TCRAM */" >> tmp.fil
+fi
+mv tmp.fil ./include/config.h
+# ---------------------------------------------------------
+# Ensure correct core object loaded first in U-Boot image
+# ---------------------------------------------------------
+sed -r 's/CPU_FILE/cpu\/'$cpu'\/start.o/; s/#.*//' board/integratorcp/u-boot.lds.template > board/integratorcp/u-boot.lds
+# ---------------------------------------------------------
+# Complete the configuration
+# ---------------------------------------------------------
+./mkconfig -a integratorcp arm $cpu integratorcp;
+echo "Variant:: $variant with core $cpu"
+
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+# Template used during configuration to emsure the core module processor code,
+# from CPU_FILE, is placed at the start of the image */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+ . = ALIGN(4);
+ .text :
+ {
+ CPU_FILE (.text)
+ *(.text)
+ }
+ .rodata : { *(.rodata) }
+ . = ALIGN(4);
+ .data : { *(.data) }
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
puts ("Board: ");
- i = getenv_r ("serial#", buf, sizeof (buf));
+ i = getenv_r ("serial#", (char *)buf, sizeof (buf));
s = (i > 0) ? buf : NULL;
- if (!s || strncmp (s, "IP860", 5)) {
+ if (!s || strncmp ((char *)s, "IP860", 5)) {
puts ("### No HW ID - assuming IP860");
} else {
for (e = s; *e; ++e) {
* Check SDRAM Memory Size
*/
if (ip860_get_dram_size() == 16)
- size = dram_size (refresh_val | 0x00804114, (ulong *)SDRAM_BASE, SDRAM_MAX_SIZE);
+ size = dram_size (refresh_val | 0x00804114, SDRAM_BASE, SDRAM_MAX_SIZE);
else
- size = dram_size (refresh_val | 0x00906114, (ulong *)SDRAM_BASE, SDRAM_MAX_SIZE);
+ size = dram_size (refresh_val | 0x00906114, SDRAM_BASE, SDRAM_MAX_SIZE);
udelay (1000);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
{
int sn = -1;
- if (!seeprom_read (0xa0, (char *) &sn, sizeof (sn))) {
+ if (!seeprom_read (0xa0, (uchar *) &sn, sizeof (sn))) {
sn = cpu_to_le32 (sn);
}
return sn;
{
char mac[6];
- if (!seeprom_read (0xb0, mac, sizeof (mac))) {
+ if (!seeprom_read (0xb0, (uchar *)mac, sizeof (mac))) {
sprintf (str, "%02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
} else {
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
int sn = -1;
- if (!seeprom_read (0xa0, (char *) &sn, sizeof (sn))) {
+ if (!seeprom_read (0xa0, (uchar *) &sn, sizeof (sn))) {
sn = cpu_to_le32 (sn);
}
return sn;
{
char mac[6];
- if (!seeprom_read (0xb0, mac, sizeof (mac))) {
+ if (!seeprom_read (0xb0, (uchar *)mac, sizeof (mac))) {
sprintf (str, "%02X:%02X:%02X:%02X:%02X:%02X",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
} else {
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
* Check Bank 0 Memory Size for re-configuration
*/
size_b0 =
- dram_size (CFG_MBMR_8COL, (ulong *) SDRAM_BASE3_PRELIM,
+ dram_size (CFG_MBMR_8COL, (long *) SDRAM_BASE3_PRELIM,
SDRAM_MAX_SIZE);
memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
/**********************************************************/
extern struct pci_controller hose;
+extern void pci_ixp_init(struct pci_controller * hose);
void pci_init_board(void)
{
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
--- /dev/null
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Adapted for KwikByte KB920x boards - APR2005
+#
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := kb9202.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+TEXT_BASE = 0x21f00000
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Adapted for KwikByte KB920x board from at91rm9200dk.c: 22APR2005
+ */
+
+#include <common.h>
+#include <asm/arch/AT91RM9200.h>
+#include <at91rm9200_net.h>
+#include <lxt971a.h>
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+void lowlevel_init(void) {
+ /* Required by assembly functions - do nothing */
+}
+
+int board_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ /* Enable Ctrlc */
+ console_init_f ();
+
+ /* memory and cpu-speed are setup before relocation */
+ /* so we do _nothing_ here */
+
+ gd->bd->bi_arch_number = MACH_TYPE_KB9200;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int dram_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_ETHER
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+
+unsigned int lxt972_IsPhyConnected (AT91PS_EMAC p_mac);
+UCHAR lxt972_GetLinkSpeed (AT91PS_EMAC p_mac);
+UCHAR lxt972_InitPhy (AT91PS_EMAC p_mac);
+UCHAR lxt972_AutoNegotiate (AT91PS_EMAC p_mac, int *status);
+
+/*
+ * Name:
+ * at91rm9200_GetPhyInterface
+ * Description:
+ * Initialise the interface functions to the PHY
+ * Arguments:
+ * None
+ * Return value:
+ * None
+ */
+void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
+{
+ p_phyops->Init = lxt972_InitPhy;
+ p_phyops->IsPhyConnected = lxt972_IsPhyConnected;
+ p_phyops->GetLinkSpeed = lxt972_GetLinkSpeed;
+ p_phyops->AutoNegotiate = lxt972_AutoNegotiate;
+}
+
+#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
+#endif /* CONFIG_DRIVER_ETHER */
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
+
. = ALIGN(4);
- .text :
+ .text :
{
- cpu/arm926ejs/start.o (.text)
+ cpu/arm920t/start.o (.text)
*(.text)
}
+
+ . = ALIGN(4);
.rodata : { *(.rodata) }
+
. = ALIGN(4);
.data : { *(.data) }
+
. = ALIGN(4);
.got : { *(.got) }
void load_sernum_ethaddr (void)
{
unsigned char *hwi;
- unsigned char *var;
+ char *var;
unsigned char hwi_stack[CFG_HWINFO_SIZE];
- unsigned char *p;
+ char *p;
hwi = (unsigned char *) (CFG_FLASH_BASE + CFG_HWINFO_OFFSET);
if (*((unsigned long *) hwi) != (unsigned long) CFG_HWINFO_MAGIC) {
/*
** ethaddr
*/
- var = strstr (hwi_stack, ETHADDR_TOKEN);
+ var = strstr ((char *)hwi_stack, ETHADDR_TOKEN);
if (var) {
var += sizeof (ETHADDR_TOKEN) - 1;
p = strchr (var, '\r');
- if (p < hwi + CFG_HWINFO_SIZE) {
+ if ((unsigned char *)p < hwi + CFG_HWINFO_SIZE) {
*p = '\0';
setenv ("ethaddr", var);
*p = '\r';
/*
** lcd
*/
- var = strstr (hwi_stack, LCD_TOKEN);
+ var = strstr ((char *)hwi_stack, LCD_TOKEN);
if (var) {
var += sizeof (LCD_TOKEN) - 1;
p = strchr (var, '\r');
- if (p < hwi + CFG_HWINFO_SIZE) {
+ if ((unsigned char *)p < hwi + CFG_HWINFO_SIZE) {
*p = '\0';
setenv ("lcd", var);
*p = '\r';
int r = 8, g = 8, b = 4;
int r1, g1, b1;
int n;
- uchar tmp[64]; /* long enough for environment variables */
+ char tmp[64]; /* long enough for environment variables */
int tft = 0;
immr->im_cpm.cp_pbpar &= ~(PB_LCD_PWM);
}
/* copy bitmap */
- fb = (char *) (fb_info.VmemAddr);
+ fb = (uchar *) (fb_info.VmemAddr);
memcpy (fb, (uchar *) CONFIG_KUP4K_LOGO, 320 * 240);
}
#endif /* CONFIG_KUP4K_LOGO */
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
* Check Bank 0 Memory Size for re-configuration
*/
size_b0 = dram_size (CFG_MAMR_8COL,
- (ulong *) SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+ (long *) SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTAE;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
chert:
(1) => setenv magic_keys 01234#X
-(2) => setenv key_cmd# setenv addfb setenv bootargs \\$(bootargs) console=tty0 console=ttyS1,\\$(baudrate)
-(3) => setenv nfsargs setenv bootargs root=/dev/nfs rw nfsroot=\$(serverip):\$(rootpath)
-(4) => setenv addip setenv bootargs \$(bootargs) ip=\$(ipaddr):\$(serverip):\$(gatewayip):\$(netmask):\$(hostname)::off panic=1
-(5) => setenv addfb setenv bootargs \$(bootargs) console=ttyS1,\$(baudrate)
+(2) => setenv key_cmd# setenv addfb setenv bootargs \\${bootargs} console=tty0 console=ttyS1,\\${baudrate}
+(3) => setenv nfsargs setenv bootargs root=/dev/nfs rw nfsroot=\${serverip}:\${rootpath}
+(4) => setenv addip setenv bootargs \${bootargs} ip=\${ipaddr}:\${serverip}:\${gatewayip}:\${netmask}:\${hostname}::off panic=1
+(5) => setenv addfb setenv bootargs \${bootargs} console=ttyS1,\${baudrate}
(6) => setenv bootcmd bootp\;run nfsargs\;run addip\;run addfb\;bootm
Hierbei wird die Linux Commandline (in der Variablen "bootargs") im
*
* try 8 column mode
*/
- size8 = dram_size (CFG_MAMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+ size8 = dram_size (CFG_MAMR_8COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
udelay (1000);
/*
* try 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+ size9 = dram_size (CFG_MAMR_9COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
size_b0 = size9;
DECLARE_GLOBAL_DATA_PTR;
uchar kbd_data[KEYBD_DATALEN];
- uchar keybd_env[2 * KEYBD_DATALEN + 1];
+ char keybd_env[2 * KEYBD_DATALEN + 1];
uchar kbd_init_status = gd->kbd_status >> 8;
uchar kbd_status = gd->kbd_status;
uchar val;
- uchar *str;
+ char *str;
int i;
if (kbd_init_status) {
}
setenv ("keybd", keybd_env);
- str = strdup (key_match (kbd_data)); /* decode keys */
+ str = strdup ((char *)key_match (kbd_data)); /* decode keys */
#ifdef KEYBD_SET_DEBUGMODE
if (kbd_data[0] == KEYBD_SET_DEBUGMODE) { /* set debug mode */
if ((console_assign (stdout, "lcd") < 0) ||
/* Don't include modifier byte */
memcpy (compare, kbd_data+1, KEYBD_DATALEN-1);
- for (; str != NULL; str = (*nxt) ? nxt+1 : nxt) {
+ for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) {
uchar c;
int k;
- c = (uchar) simple_strtoul (str, (char **) (&nxt), 16);
+ c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16);
if (str == (uchar *)nxt) { /* invalid character */
break;
***********************************************************************/
static uchar *key_match (uchar *kbd_data)
{
- uchar magic[sizeof (kbd_magic_prefix) + 1];
+ char magic[sizeof (kbd_magic_prefix) + 1];
uchar *suffix;
- uchar *kbd_magic_keys;
+ char *kbd_magic_keys;
/*
* The following string defines the characters that can pe appended
/* loop over all magic keys;
* use '\0' suffix in case of empty string
*/
- for (suffix=kbd_magic_keys; *suffix || suffix==kbd_magic_keys; ++suffix) {
+ for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) {
sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
#if 0
printf ("### Check magic \"%s\"\n", magic);
#endif
- if (compare_magic(kbd_data, getenv(magic)) == 0) {
- uchar cmd_name[sizeof (kbd_command_prefix) + 1];
+ if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) {
+ char cmd_name[sizeof (kbd_command_prefix) + 1];
char *cmd;
sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
cmd_name, cmd ? cmd : "<<NULL>>");
#endif
*kbd_data = *suffix;
- return (cmd);
+ return ((uchar *)cmd);
}
}
#if 0
int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
uchar kbd_data[KEYBD_DATALEN];
- uchar keybd_env[2 * KEYBD_DATALEN + 1];
+ char keybd_env[2 * KEYBD_DATALEN + 1];
uchar val;
int i;
i2c_write (kbd_addr, 0, 0, &val, 1);
i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
- return (compare_magic(kbd_data, CONFIG_MODEM_KEY_MAGIC) == 0);
+ return (compare_magic(kbd_data, (uchar *)CONFIG_MODEM_KEY_MAGIC) == 0);
}
#endif /* CONFIG_MODEM_SUPPORT */
i2c_write (kbd_addr, 0, 0, &val, 1);
i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
- return (compare_magic(kbd_data, CONFIG_POST_KEY_MAGIC) == 0);
+ return (compare_magic(kbd_data, (uchar *)CONFIG_POST_KEY_MAGIC) == 0);
}
#endif
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
return rc;
}
-volatile static int write_word (flash_info_t *info, ulong dest, unsigned long long data) {
+static int write_word (flash_info_t *info, ulong dest, unsigned long long data) {
volatile unsigned long long *addr=(unsigned long long *)dest;
unsigned long long result;
int checkboard (void)
{
- unsigned char *s = getenv ("serial#");
- unsigned char *e;
+ char *s = getenv ("serial#");
+ char *e;
if (!s || strncmp (s, "ML2", 9)) {
printf ("### No HW ID - assuming ML2");
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
+ cpu/ppc4xx/4xx_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
tftp 100000 u-boot.bin
protect off FFF00000 FFF7FFFF
erase FFF00000 FFF7FFFF
-cp.b 100000 FFF00000 \$(filesize)\
+cp.b 100000 FFF00000 \${filesize}\
Here is an example:
tftp 100000 u-boot.bin
protect off FFF80000 FFFFFFFF
erase FFF80000 FFFFFFFF
-cp.b 100000 FFF80000 \$(filesize)\
+cp.b 100000 FFF80000 \${filesize}\
C. FLASH KERNEL REGION (960KB)
tftp 100000 vmlinux.img
protect off FFE10000 FFEFFFFF
erase FFE10000 FFEFFFFF
-cp.b 100000 FFE10000 \$(filesize)\
+cp.b 100000 FFE10000 \${filesize}\
reset
Here is an example:
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(16);
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
--- /dev/null
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := mp2usb.o flash.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+TEXT_BASE = 0x27F00000
+## For testing: load at 0x20100000 and "go" at 0x201000A4
+#TEXT_BASE = 0x20100000
* (C) Copyright 2001
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
*
- * (C) Copyright 2001-2004
+ * (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
-
- * (C) Copyright 2004
- * Texas Instruments <www.ti.com>
- * Rishi Bhattacharya
+ * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
+ * ebenard@eukrea.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
#include <common.h>
#include <linux/byteorder/swab.h>
-#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+#define CFG_MAX_FLASH_BANKS 1
+#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */
-/* Board support for 1 or 2 flash devices */
-#undef FLASH_PORT_WIDTH32
-#define FLASH_PORT_WIDTH16
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
-#ifdef FLASH_PORT_WIDTH16
#define FLASH_PORT_WIDTH ushort
#define FLASH_PORT_WIDTHV vu_short
#define SWAP(x) __swab16(x)
-#else
-#define FLASH_PORT_WIDTH ulong
-#define FLASH_PORT_WIDTHV vu_long
-#define SWAP(x) __swab32(x)
-#endif
-#define FPW FLASH_PORT_WIDTH
-#define FPWV FLASH_PORT_WIDTHV
+#define FPW FLASH_PORT_WIDTH
+#define FPWV FLASH_PORT_WIDTHV
#define mb() __asm__ __volatile__ ("" : : : "memory")
-
-/* Flash Organization Structure */
-typedef struct OrgDef {
- unsigned int sector_number;
- unsigned int sector_size;
-} OrgDef;
-
-
-/* Flash Organizations */
-OrgDef OrgIntel_28F256L18T[] = {
- {4, 32 * 1024}, /* 4 * 32kBytes sectors */
- {255, 128 * 1024}, /* 255 * 128kBytes sectors */
-};
-
+/* Intel-compatible flash commands */
+#define INTEL_PROGRAM 0x00100010
+#define INTEL_ERASE 0x00200020
+#define INTEL_PROG 0x00400040
+#define INTEL_CLEAR 0x00500050
+#define INTEL_LOCKBIT 0x00600060
+#define INTEL_PROTECT 0x00010001
+#define INTEL_STATUS 0x00700070
+#define INTEL_READID 0x00900090
+#define INTEL_SUSPEND 0x00B000B0
+#define INTEL_CONFIRM 0x00D000D0
+#define INTEL_RESET 0xFFFFFFFF
+
+/* Intel-compatible flash status bits */
+#define INTEL_FINISHED 0x00800080
+#define INTEL_OK 0x00800080
/*-----------------------------------------------------------------------
* Functions
*/
-unsigned long flash_init (void);
-static ulong flash_get_size (FPW * addr, flash_info_t * info);
-static int write_data (flash_info_t * info, ulong dest, FPW data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
void inline spin_wheel (void);
-void flash_print_info (flash_info_t * info);
-void flash_unprotect_sectors (FPWV * addr);
-int flash_erase (flash_info_t * info, int s_first, int s_last);
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
/*-----------------------------------------------------------------------
*/
{
int i;
ulong size = 0;
+
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
switch (i) {
case 0:
/* Protect monitor and environment sectors
*/
- flash_protect (FLAG_PROTECT_SET,
+ flash_protect ( FLAG_PROTECT_SET,
CFG_FLASH_BASE,
- CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+ CFG_FLASH_BASE + monitor_flash_len - 1,
+ &flash_info[0] );
- flash_protect (FLAG_PROTECT_SET,
+ flash_protect ( FLAG_PROTECT_SET,
CFG_ENV_ADDR,
- CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );
return size;
}
/*-----------------------------------------------------------------------
*/
-static void flash_get_offsets (ulong base, flash_info_t * info)
+static void flash_get_offsets (ulong base, flash_info_t *info)
{
int i;
- OrgDef *pOrgDef;
- pOrgDef = OrgIntel_28F256L18T;
if (info->flash_id == FLASH_UNKNOWN) {
return;
}
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
for (i = 0; i < info->sector_count; i++) {
- if (i > 255) {
- info->start[i] = base + (i * 0x8000);
- info->protect[i] = 0;
- } else {
- info->start[i] = base +
- (i * PHYS_FLASH_SECT_SIZE);
- info->protect[i] = 0;
- }
+ info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+ info->protect[i] = 0;
}
}
}
/*-----------------------------------------------------------------------
*/
-void flash_print_info (flash_info_t * info)
+void flash_print_info (flash_info_t *info)
{
int i;
}
switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F256L18T:
- printf ("FLASH 28F256L18T\n");
+ case FLASH_28F640J3A:
+ printf ("28F640J3A\n");
break;
case FLASH_28F128J3A:
- printf ("FLASH 28F128J3A\n");
+ printf ("28F128J3A\n");
break;
default:
printf ("Unknown Chip Type\n");
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
- info->start[i], info->protect[i] ? " (RO)" : " ");
+ info->start[i],
+ info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
return;
/*
* The following code cannot be run from FLASH!
*/
-static ulong flash_get_size (FPW * addr, flash_info_t * info)
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
{
volatile FPW value;
case (FPW) INTEL_MANUFACT:
info->flash_id = FLASH_MAN_INTEL;
break;
- case (FPW) MT2_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
- addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
- return (0); /* no or unknown flash */
+ addr[0] = (FPW) INTEL_RESET; /* restore read mode */
+ return (0); /* no or unknown flash */
}
mb ();
- value = addr[1]; /* device ID */
+ value = addr[1]; /* device ID */
+
switch (value) {
- case (FPW) (INTEL_ID_28F256L18T):
- info->flash_id += FLASH_28F256L18T;
- info->sector_count = 259;
- info->size = 0x02000000;
- break; /* => 32 MB */
-
- case (FPW) (INTEL_ID_28F256K3):
- info->flash_id +=FLASH_28F256K3;
- info->sector_count = 259;
- info->size = 0x02000000;
- debug ("Intel StrataFlash 28F256K3C device initialized\n");
- break; /* => 32 MB */
-
- case (FPW) (INTEL_ID_28F128J3A):
- info->flash_id +=FLASH_28F128J3A;
- info->sector_count = 259;
- info->size = 0x02000000;
- debug ("Micron StrataFlash MT28F128J3 device initialized\n");
- break; /* => 32 MB */
+ case (FPW) INTEL_ID_28F640J3A:
+ info->flash_id += FLASH_28F640J3A;
+ info->sector_count = 64;
+ info->size = 0x00800000;
+ break; /* => 8 MB */
+
+ case (FPW) INTEL_ID_28F128J3A:
+ info->flash_id += FLASH_28F128J3A;
+ info->sector_count = 128;
+ info->size = 0x01000000;
+ break; /* => 16 MB */
default:
info->flash_id = FLASH_UNKNOWN;
if (info->sector_count > CFG_MAX_FLASH_SECT) {
printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CFG_MAX_FLASH_SECT);
+ info->sector_count, CFG_MAX_FLASH_SECT);
info->sector_count = CFG_MAX_FLASH_SECT;
}
- addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
+ addr[0] = (FPW) INTEL_RESET; /* restore read mode */
return (info->size);
}
-/* unprotects a sector for write and erase
- * on some intel parts, this unprotects the entire chip, but it
- * wont hurt to call this additional times per sector...
- */
-void flash_unprotect_sectors (FPWV * addr)
-{
-#define PD_FINTEL_WSMS_READY_MASK 0x0080
-
-FPW status;
-
- *addr = (FPW) 0x00500050; /* clear status register */
-
- /* this sends the clear lock bit command */
- *addr = (FPW) 0x00600060;
- *addr = (FPW) 0x00D000D0;
-
- while (((status =*addr) & (FPW) 0x00800080) != (FPW) 0x00800080);
-
- *addr = (FPW) 0x00FF00FF;
-
-}
-
-
/*-----------------------------------------------------------------------
*/
-int flash_erase (flash_info_t * info, int s_first, int s_last)
+int flash_erase (flash_info_t *info, int s_first, int s_last)
{
- int flag, prot, sect;
+ int prot, sect;
ulong type, start, last;
int rcode = 0;
+ int cflag, iflag;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
type = (info->flash_id & FLASH_VENDMASK);
if ((type != FLASH_MAN_INTEL)) {
printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
+ info->flash_id);
return 1;
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
+ prot);
} else {
printf ("\n");
}
-
start = get_timer (0);
last = start;
+ /*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+ cflag = icache_status ();
+ icache_disable ();
/* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
+ iflag = disable_interrupts ();
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
+ if (info->protect[sect] == 0) { /* not protected */
FPWV *addr = (FPWV *) (info->start[sect]);
FPW status;
printf ("Erasing sector %2d ... ", sect);
- flash_unprotect_sectors (addr);
-
/* arm simple, non interrupt dependent timer */
reset_timer_masked ();
- *addr = (FPW) 0x00500050;/* clear status register */
- *addr = (FPW) 0x00200020;/* erase setup */
- *addr = (FPW) 0x00D000D0;/* erase confirm */
+ *addr = (FPW) INTEL_CLEAR; /* clear status register */
+ *addr = (FPW) INTEL_ERASE; /* erase setup */
+ *addr = (FPW) INTEL_CONFIRM; /* erase confirm */
- while (((status =
- *addr) & (FPW) 0x00800080) !=
- (FPW) 0x00800080) {
- if (get_timer_masked () >
- CFG_FLASH_ERASE_TOUT) {
+ while (((status = *addr) & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
+ if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
- /* suspend erase */
- *addr = (FPW) 0x00B000B0;
- /* reset to read mode */
- *addr = (FPW) 0x00FF00FF;
+ *addr = (FPW) INTEL_SUSPEND; /* suspend erase */
+ *addr = (FPW) INTEL_RESET; /* reset to read mode */
rcode = 1;
break;
}
}
- /* clear status register cmd. */
- *addr = (FPW) 0x00500050;
- *addr = (FPW) 0x00FF00FF;/* resest to read mode */
+ *addr = (FPWV)INTEL_CLEAR; /* clear status register cmd. */
+ *addr = (FPWV)INTEL_RESET; /* resest to read mode */
+
printf (" done\n");
}
}
+
+ if (iflag)
+ enable_interrupts ();
+
+ if (cflag)
+ icache_enable ();
+
return rcode;
}
* 4 - Flash not identified
*/
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp;
FPW data;
if (info->flash_id == FLASH_UNKNOWN) {
return 4;
}
-/* get lower word aligned address */
-#ifdef FLASH_PORT_WIDTH16
+
+ /* get lower word aligned address */
wp = (addr & ~1);
port_width = 2;
-#else
- wp = (addr & ~3);
- port_width = 4;
-#endif
/*
* handle unaligned start bytes
* 1 - write timeout
* 2 - Flash not erased
*/
-static int write_data (flash_info_t * info, ulong dest, FPW data)
+static int write_data (flash_info_t *info, ulong dest, FPW data)
{
FPWV *addr = (FPWV *) dest;
ulong status;
- int flag;
+ int cflag, iflag;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
- printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+ printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
return (2);
}
+ /*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+ cflag = icache_status ();
+ icache_disable ();
/* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
- *addr = (FPW) 0x00400040; /* write setup */
+ iflag = disable_interrupts ();
+
+ *addr = (FPW) INTEL_PROG; /* write setup */
*addr = data;
/* arm simple, non interrupt dependent timer */
reset_timer_masked ();
/* wait while polling the status register */
- while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+ while (((status = *addr) & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
- *addr = (FPW) 0x00FF00FF; /* restore read mode */
+ *addr = (FPW) INTEL_RESET; /* restore read mode */
return (1);
}
}
- *addr = (FPW) 0x00FF00FF; /* restore read mode */
+
+ *addr = (FPW) INTEL_RESET; /* restore read mode */
+
+ if (iflag)
+ enable_interrupts ();
+
+ if (cflag)
+ icache_enable ();
+
return (0);
}
printf ("\010%c", w[p]);
(++p == 3) ? (p = 0) : 0;
}
+
+/*-----------------------------------------------------------------------
+ * Set/Clear sector's lock bit, returns:
+ * 0 - OK
+ * 1 - Error (timeout, voltage problems, etc.)
+ */
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+ int i;
+ int rc = 0;
+ FPWV *addr = (FPWV *)(info->start[sector]);
+ int flag = disable_interrupts();
+
+ *addr = (FPW) INTEL_CLEAR; /* Clear status register */
+ if (prot) { /* Set sector lock bit */
+ *addr = (FPW) INTEL_LOCKBIT; /* Sector lock bit */
+ *addr = (FPW) INTEL_PROTECT; /* set */
+ }
+ else { /* Clear sector lock bit */
+ *addr = (FPW) INTEL_LOCKBIT; /* All sectors lock bits */
+ *addr = (FPW) INTEL_CONFIRM; /* clear */
+ }
+
+ reset_timer_masked ();
+
+ while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
+ if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT) {
+ printf("Flash lock bit operation timed out\n");
+ rc = 1;
+ break;
+ }
+ }
+
+ if (*addr != (FPW) INTEL_OK) {
+ printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
+ (uint)addr, (uint)*addr);
+ rc = 1;
+ }
+
+ if (!rc)
+ info->protect[sector] = prot;
+
+ /*
+ * Clear lock bit command clears all sectors lock bits, so
+ * we have to restore lock bits of protected sectors.
+ */
+ if (!prot)
+ {
+ for (i = 0; i < info->sector_count; i++)
+ {
+ if (info->protect[i])
+ {
+ reset_timer_masked ();
+ addr = (FPWV *) (info->start[i]);
+ *addr = (FPW) INTEL_LOCKBIT; /* Sector lock bit */
+ *addr = (FPW) INTEL_PROTECT; /* set */
+ while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED)
+ {
+ if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT)
+ {
+ printf("Flash lock bit operation timed out\n");
+ rc = 1;
+ break;
+ }
+ }
+ }
+ }
+ }
+
+ if (flag)
+ enable_interrupts();
+
+ *addr = (FPW) INTEL_RESET; /* Reset to read array mode */
+
+ return rc;
+}
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
+ * ebenard@eukrea.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/AT91RM9200.h>
+#include <at91rm9200_net.h>
+#include <dm9161.h>
+#include <asm/mach-types.h>
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ /* Enable Ctrlc */
+ console_init_f ();
+
+ /* memory and cpu-speed are setup before relocation */
+ /* so we do _nothing_ here */
+
+ /* arch number of MP2USB-Board. */
+ gd->bd->bi_arch_number = MACH_TYPE_MP2USB;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int dram_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_ETHER
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+
+/*
+ * Name:
+ * at91rm9200_GetPhyInterface
+ * Description:
+ * Initialise the interface functions to the PHY
+ * Arguments:
+ * None
+ * Return value:
+ * None
+ */
+void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
+{
+ p_phyops->Init = dm9161_InitPhy;
+ p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
+ p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
+ p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
+}
+
+#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
+#endif /* CONFIG_DRIVER_ETHER */
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm920t/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
* Yuli Barcohen <yuli@arabellasw.com>
* Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
*
+ * Copyright (c) 2005 MontaVista Software, Inc.
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ * Added support for PCI.
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
#include <i2c.h>
#include <spd.h>
#include <miiphy.h>
+#ifdef CONFIG_PCI
+#include <pci.h>
+#endif
/*
* I/O Port configuration table
* Do not bypass Rx/Tx (de)scrambler (fix configuration error)
* Enable autonegotiation.
*/
- miiphy_write(CFG_PHY_ADDR, 16, 0x610);
- miiphy_write(CFG_PHY_ADDR, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+ bb_miiphy_write(NULL, CFG_PHY_ADDR, 16, 0x610);
+ bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR,
+ PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
#else
/*
* Ethernet PHY is configured (by means of configuration pins)
* to advertise all capabilities, including 100Mb/s, and
* restart autonegotiation.
*/
- miiphy_write(CFG_PHY_ADDR, PHY_ANAR, 0x01E1); /* Advertise all capabilities */
- miiphy_write(CFG_PHY_ADDR, PHY_DCR, 0x0000); /* Do not bypass Rx/Tx (de)scrambler */
- miiphy_write(CFG_PHY_ADDR, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+
+ /* Advertise all capabilities */
+ bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_ANAR, 0x01E1);
+
+ /* Do not bypass Rx/Tx (de)scrambler */
+ bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_DCR, 0x0000);
+
+ bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR,
+ PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
#endif /* CONFIG_MII */
}
+#ifdef CONFIG_PCI
+typedef struct pci_ic_s {
+ unsigned long pci_int_stat;
+ unsigned long pci_int_mask;
+}pci_ic_t;
+#endif
+
int board_early_init_f (void)
{
vu_long *bcsr = (vu_long *)CFG_BCSR;
+#ifdef CONFIG_PCI
+ volatile pci_ic_t* pci_ic = (pci_ic_t *) CFG_PCI_INT;
+
+ /* mask alll the PCI interrupts */
+ pci_ic->pci_int_mask |= 0xfff00000;
+#endif
#if (CONFIG_CONS_INDEX == 1) || (CONFIG_KGDB_INDEX == 1)
bcsr[1] &= ~RS232EN_1;
#endif
#endif
return 0;
}
+
+#ifdef CONFIG_PCI
+struct pci_controller hose;
+
+extern void pci_mpc8250_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+ pci_mpc8250_init(&hose);
+}
+#endif
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
udelay(1000);
#endif
#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
- miiphy_reset(0x0); /* reset PHY */
- miiphy_write(0, PHY_MIPSCR, 0xf028); /* change PHY address to 0x02 */
- miiphy_write(0x02, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+ /* reset PHY */
+ miiphy_reset("FCC1 ETHERNET", 0x0);
+
+ /* change PHY address to 0x02 */
+ bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
+
+ bb_miiphy_write(NULL, 0x02, PHY_BMCR,
+ PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
#endif /* CONFIG_MII */
}
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
#endif
printf("flash erased, programming from 0x%lx 0x%lx Bytes\n",
(ulong)src, size);
- if ((rc = flash_write (src, start, size)) != 0) {
+ if ((rc = flash_write ((char *)src, start, size)) != 0) {
puts("ERROR ");
flash_perror(rc);
return (1);
len = sizeof(image_header_t);
checksum = ntohl(hdr->ih_hcrc);
hdr->ih_hcrc = 0;
- if (crc32 (0, (char *)data, len) != checksum) {
+ if (crc32 (0, (uchar *)data, len) != checksum) {
puts("Bad Header Checksum\n");
return 1;
}
data = ld_addr + sizeof(image_header_t);
len = ntohl(hdr->ih_size);
puts("Verifying Checksum ... ");
- if (crc32 (0, (char *)data, len) != ntohl(hdr->ih_dcrc)) {
+ if (crc32 (0, (uchar *)data, len) != ntohl(hdr->ih_dcrc)) {
puts("Bad Data CRC\n");
return 1;
}
} while(len > off);
name=&name_buf[0];
value=&value_buf[0];
- if(strncmp(name,"baudrate",8)!=0) {
- setenv(name,value);
+ if(strncmp((char *)name,"baudrate",8)!=0) {
+ setenv((char *)name,(char *)value);
}
}
void check_env(void)
{
- unsigned char *s;
+ char *s;
int i=0;
char buf[32];
backup_t back;
char buf[64];
char tmp[16];
char cpustr[16];
- unsigned char *s, *e, bc;
+ char *s, *e, bc;
switch (line_number)
{
case 2:
void isa_sio_loadtable(void)
{
- unsigned char *s = getenv("floppy");
+ char *s = getenv("floppy");
/* setup Floppy device 0*/
isa_write_table((SIO_LOGDEV_TABLE *)&sio_fdc,0);
/* setup parallel port device 3 */
| KBD_MODE_DISABLE_MOUSE
| KBD_MODE_KCC);
- /* ibm powerpc portables need this to use scan-code set 1 -- Cort */
+ /* AMCC powerpc portables need this to use scan-code set 1 -- Cort */
kbd_write_command_w(KBD_CCMD_READ_MODE);
if (!(kbd_wait_for_input() & KBD_MODE_KCC)) {
/*
{ } /* end of device table */
};
/* PPC405 Dummy only used to prevent autosetup on this host bridge */
-static struct pci_pip405_config_entry ibm405_dummy[] = {
+static struct pci_pip405_config_entry ppc405_dummy[] = {
{ } /* end of device table */
};
PCI_DEVICE_ID_IBM_405GP,
PCI_ANY_ID,
PCI_ANY_ID, PCI_ANY_ID, 0,
- pci_pip405_write_regs, {(unsigned long) ibm405_dummy}},
+ pci_pip405_write_regs, {(unsigned long) ppc405_dummy}},
{PCI_VENDOR_ID_INTEL, /* PIIX4 ISA Bridge Function 0 */
PCI_DEVICE_ID_INTEL_82371AB_0,
int checkboard (void)
{
- unsigned char s[50];
+ char s[50];
unsigned char bc, var;
int i;
backup_t *b = (backup_t *) s;
puts ("Board: ");
get_pcbrev_var(&bc,&var);
- i = getenv_r ("serial#", s, 32);
- if ((i == 0) || strncmp (s, BOARD_NAME,sizeof(BOARD_NAME))) {
+ i = getenv_r ("serial#", (char *)s, 32);
+ if ((i == 0) || strncmp ((char *)s, BOARD_NAME,sizeof(BOARD_NAME))) {
get_backup_values (b);
if (strncmp (b->signature, "MPL\0", 4) != 0) {
puts ("### No HW ID - assuming " BOARD_NAME);
{
unsigned long stop;
struct rtc_time newtm;
- unsigned char *s;
+ char *s;
mem_test_reloc();
/* write correct LED configuration */
- if (miiphy_write (0x1, 0x14, 0x2402) != 0) {
+ if (miiphy_write("ppc_4xx_eth0", 0x1, 0x14, 0x2402) != 0) {
printf ("Error writing to the PHY\n");
}
/* since LED/CFG2 is not connected on the -2,
* write to correct capability information */
- if (miiphy_write (0x1, 0x4, 0x01E1) != 0) {
+ if (miiphy_write("ppc_4xx_eth0", 0x1, 0x4, 0x01E1) != 0) {
printf ("Error writing to the PHY\n");
}
print_mip405_rev ();
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
+ cpu/ppc4xx/4xx_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
unsigned char dataout[1];
unsigned char datain[128];
- unsigned long sdram_size;
+ unsigned long sdram_size = 0;
SDRAM_SETUP *t = (SDRAM_SETUP *) sdram_setup_table;
unsigned long memclk;
unsigned long tmemclk = 0;
int checkboard (void)
{
- unsigned char s[50];
+ char s[50];
unsigned char bc;
int i;
backup_t *b = (backup_t *) s;
puts ("Board: ");
- i = getenv_r ("serial#", s, 32);
- if ((i == 0) || strncmp (s, "PIP405", 6)) {
+ i = getenv_r ("serial#", (char *)s, 32);
+ if ((i == 0) || strncmp ((char *)s, "PIP405", 6)) {
get_backup_values (b);
if (strncmp (b->signature, "MPL\0", 4) != 0) {
puts ("### No HW ID - assuming PIP405");
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*
* try 8 column mode
*/
- size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE2_PRELIM,
+ size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
udelay (1000);
/*
* try 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE2_PRELIM,
+ size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
#include <watchdog.h>
#endif
+int fec8xx_miiphy_read(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value);
+int fec8xx_miiphy_write(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value);
+
/****************************************************************/
/* some sane bit macros */
mii_init();
for (phyno = 0; phyno < 32; ++phyno) {
- miiphy_read(phyno, PHY_PHYIDR1, &v);
+ fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v);
if (v == 0xFFFF)
continue;
- miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
+ fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD);
udelay(10000);
- miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
+ fec8xx_miiphy_write(NULL, phyno, PHY_BMCR,
+ PHY_BMCR_RESET | PHY_BMCR_AUTON);
udelay(10000);
}
}
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
# XXX TEXT_BASE = 0x20012000
TEXT_BASE = 0x13FC0000
+
+# Compile the new NAND code (needed iff #ifdef CONFIG_NEW_NAND_CODE)
+BOARDLIBS = drivers/nand/libnand.a
+
#include <watchdog.h>
#endif
+int fec8xx_miiphy_read(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value);
+int fec8xx_miiphy_write(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value);
+
/****************************************************************/
/* some sane bit macros */
mii_init();
for (phyno = 0; phyno < 32; ++phyno) {
- miiphy_read(phyno, PHY_PHYIDR1, &v);
+ fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v);
if (v == 0xFFFF)
continue;
- miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
+ fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD);
udelay(10000);
- miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
+ fec8xx_miiphy_write(NULL, phyno, PHY_BMCR,
+ PHY_BMCR_RESET | PHY_BMCR_AUTON);
udelay(10000);
}
}
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
#include <watchdog.h>
#endif
+int fec8xx_miiphy_read(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value);
+int fec8xx_miiphy_write(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value);
+
/****************************************************************/
/* some sane bit macros */
mii_init();
for (phyno = 0; phyno < 32; ++phyno) {
- miiphy_read(phyno, PHY_PHYIDR1, &v);
+ fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v);
if (v == 0xFFFF)
continue;
- miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
+ fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD);
udelay(10000);
- miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
+ fec8xx_miiphy_write(NULL, phyno, PHY_BMCR,
+ PHY_BMCR_RESET | PHY_BMCR_AUTON);
udelay(10000);
}
}
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
LIB = lib$(BOARD).a
OBJS := ns9750dev.o flash.o led.o
-SOBJS := platform.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
.word 0x00022000 @ for CAS2 latency
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-.globl platformsetup
-platformsetup:
+.globl lowlevel_init
+lowlevel_init:
/* U-Boot may be linked to RAM at 0x780000. But this code will run in
flash from 0x0. But in order to enable RAM we have to disable the
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
*
* try 8 column mode
*/
- size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE1_PRELIM,
+ size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE1_PRELIM,
SDRAM_MAX_SIZE);
udelay (1000);
/*
* try 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE1_PRELIM,
+ size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE1_PRELIM,
SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
* [9 column SDRAM may also be used in 8 column mode,
* but then only half the real size will be used.]
*/
- size_b1 = dram_size (memctl->memc_mamr, (ulong *) SDRAM_BASE2_PRELIM,
+ size_b1 = dram_size (memctl->memc_mamr, (long *) SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
/* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
+
#
-# (C) Copyright 2001
+# (C) Copyright 2005
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
LIB = lib$(BOARD).a
-OBJS := $(BOARD).o
-SOBJS := init.o
-#SOBJS :=
+OBJS := $(BOARD).o flash.o
-$(LIB): $(OBJS) $(SOBJS)
+$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
clean:
- rm -f $(OBJS) $(SOBJS)
+ rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
--- /dev/null
+#
+# (C) Copyright 2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# boot low for 16 MiB boards
+TEXT_BASE = 0xFF000000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * flash_real_protect() routine based on boards/alaska/flash.c
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* Intel-compatible flash commands */
+#define INTEL_ERASE 0x20
+#define INTEL_PROGRAM 0x40
+#define INTEL_CLEAR 0x50
+#define INTEL_LOCKBIT 0x60
+#define INTEL_PROTECT 0x01
+#define INTEL_STATUS 0x70
+#define INTEL_READID 0x90
+#define INTEL_READID 0x90
+#define INTEL_SUSPEND 0xB0
+#define INTEL_CONFIRM 0xD0
+#define INTEL_RESET 0xFF
+
+/* Intel-compatible flash status bits */
+#define INTEL_FINISHED 0x80
+#define INTEL_OK 0x80
+
+typedef unsigned char FLASH_PORT_WIDTH;
+typedef volatile unsigned char FLASH_PORT_WIDTHV;
+#define FPW FLASH_PORT_WIDTH
+#define FPWV FLASH_PORT_WIDTHV
+#define FLASH_ID_MASK 0xFF
+
+#define ORMASK(size) ((-size) & OR_AM_MSK)
+
+#define FLASH_CYCLE1 0x0555
+#define FLASH_CYCLE2 0x02aa
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPWV *addr, flash_info_t *info);
+static void flash_reset(flash_info_t *info);
+static flash_info_t *flash_get_info(ulong base);
+static int write_data (flash_info_t *info, FPWV *dest, FPW data); /* O2D */
+static void flash_sync_real_protect (flash_info_t * info);
+static unsigned char intel_sector_protected (flash_info_t *info, ushort sector);
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+ unsigned long size = 0;
+ int i;
+ extern void flash_preinit(void);
+ extern void flash_afterinit(ulong);
+
+ flash_preinit();
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ memset(&flash_info[i], 0, sizeof(flash_info_t));
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Query flash chip */
+ flash_info[0].size =
+ flash_get_size((FPW *)CFG_FLASH_BASE, &flash_info[0]);
+ size += flash_info[0].size;
+
+ /* get the h/w and s/w protection status in sync */
+ flash_sync_real_protect(&flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+monitor_flash_len-1,
+ flash_get_info(CFG_MONITOR_BASE));
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+ /* ENV protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+ flash_get_info(CFG_ENV_ADDR));
+#endif
+
+
+ flash_afterinit(size);
+ return (size ? size : 1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t *info)
+{
+ FPWV *base = (FPWV *)(info->start[0]);
+
+ /* Put FLASH back in read mode */
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+ *base = (FPW) INTEL_RESET; /* Intel Read Mode */
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static flash_info_t *flash_get_info(ulong base)
+{
+ int i;
+ flash_info_t * info;
+
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
+ info = & flash_info[i];
+ if (info->size &&
+ info->start[0] <= base &&
+ base <= info->start[0] + info->size - 1)
+ break;
+ }
+
+ return (i == CFG_MAX_FLASH_BANKS ? 0 : info);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+ uchar *boottype;
+ uchar *bootletter;
+ char *fmt;
+ uchar botbootletter[] = "B";
+ uchar topbootletter[] = "T";
+ uchar botboottype[] = "bottom boot sector";
+ uchar topboottype[] = "top boot sector";
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_INTEL:
+ printf ("INTEL ");
+ break;
+ default:
+ printf ("Unknown Vendor ");
+ break;
+ }
+
+ /* check for top or bottom boot, if it applies */
+ if (info->flash_id & FLASH_BTYPE) {
+ boottype = botboottype;
+ bootletter = botbootletter;
+ } else {
+ boottype = topboottype;
+ bootletter = topbootletter;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F128J3A:
+ fmt = "28F128J3 (128 Mbit, uniform sectors)\n";
+ break;
+ default:
+ fmt = "Unknown Chip Type\n";
+ break;
+ }
+
+ printf (fmt, bootletter, boottype);
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20,
+ info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+
+ printf (" %08lX%s", info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+ }
+ printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+ulong flash_get_size (FPWV *addr, flash_info_t *info)
+{
+ int i;
+
+ /* Write auto select command: read Manufacturer ID */
+ /* Write auto select command sequence and test FLASH answer */
+ addr[FLASH_CYCLE1] = (FPW) INTEL_READID; /* selects Intel or AMD */
+
+ /* The manufacturer codes are only 1 byte, so just use 1 byte.
+ * This works for any bus width and any FLASH device width.
+ */
+ udelay(100);
+ switch (addr[0] & 0xff) {
+ case (uchar)INTEL_MANUFACT:
+ info->flash_id = FLASH_MAN_INTEL;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ break;
+ }
+
+ /* Strataflash is configurable to 8/16bit Bus,
+ * but the Query-Structure is Word-orientated */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ switch ((FPW)addr[2]) {
+ case (FPW)INTEL_ID_28F128J3:
+ info->flash_id += FLASH_28F128J3A;
+ info->sector_count = 128;
+ info->size = 0x01000000;
+ for( i = 0; i < info->sector_count; i++ )
+ info->start[i] = (ulong)addr + (i * 0x20000);
+ break; /* => Intel Strataflash 16MB */
+ default:
+ printf("Flash_id != %xd\n", (FPW)addr[2]);
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* => no or unknown flash */
+ }
+ }
+
+ /* Put FLASH back in read mode */
+ flash_reset(info);
+
+ return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ FPWV *addr;
+ int flag, prot, sect;
+ ulong start, now, last;
+ int rcode = 0;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F128J3A:
+ break;
+ case FLASH_UNKNOWN:
+ default:
+ printf ("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect)
+ if (info->protect[sect])
+ prot++;
+
+ if (prot)
+ printf ("- Warning: %d protected sectors will not be erased!",
+ prot);
+
+ printf ("\n");
+ last = get_timer(0);
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last && rcode == 0; sect++) {
+
+ if (info->protect[sect] != 0) /* protected, skip it */
+ continue;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr = (FPWV *)(info->start[sect]);
+ *addr = (FPW) INTEL_CLEAR; /* clear status register */
+ *addr = (FPW) INTEL_ERASE; /* erase setup */
+ *addr = (FPW) INTEL_CONFIRM; /* erase confirm */
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ start = get_timer(0);
+
+ /* wait at least 80us for Intel - let's wait 1 ms */
+ udelay (1000);
+
+ while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ *addr = (FPW) INTEL_SUSPEND;/* suspend erase */
+ flash_reset(info); /* reset to read mode */
+ rcode = 1; /* failed */
+ break;
+ }
+
+ /* show that we're waiting */
+ if ((get_timer(last)) > CFG_HZ) { /* every second */
+ putc ('.');
+ last = get_timer(0);
+ }
+ }
+
+ flash_reset(info); /* reset to read mode */
+ }
+
+ printf (" done\n");
+ return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
+ int bytes; /* number of bytes to program in current word */
+ int left; /* number of bytes left to program */
+ int i, res;
+
+ for (left = cnt, res = 0;
+ left > 0 && res == 0;
+ addr += sizeof(data), left -= sizeof(data) - bytes) {
+
+ bytes = addr & (sizeof(data) - 1);
+ addr &= ~(sizeof(data) - 1);
+
+ /* combine source and destination data so can program
+ * an entire word of 16 or 32 bits */
+ for (i = 0; i < sizeof(data); i++) {
+ data <<= 8;
+ if (i < bytes || i - bytes >= left )
+ data += *((uchar *)addr + i);
+ else
+ data += *src++;
+ }
+
+ /* write one word to the flash */
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_INTEL:
+ res = write_data(info, (FPWV *)addr, data);
+ break;
+ default:
+ /* unknown flash type, error! */
+ printf ("missing or unknown FLASH type\n");
+ res = 1; /* not really a timeout, but gives error */
+ break;
+ }
+ }
+
+ return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, FPWV *dest, FPW data)
+{
+ FPWV *addr = dest;
+ ulong status;
+ ulong start;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*addr & data) != data) {
+ printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts ();
+
+ *addr = (FPW) INTEL_PROGRAM; /* write setup */
+ *addr = data;
+
+ /* arm simple, non interrupt dependent timer */
+ start = get_timer(0);
+
+ /* wait while polling the status register */
+ while (((status = *addr) & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ *addr = (FPW) INTEL_RESET; /* restore read mode */
+ return (1);
+ }
+ }
+
+ *addr = (FPW) INTEL_RESET; /* restore read mode */
+ if (flag)
+ enable_interrupts();
+
+ return (0);
+}
+
+
+/*-----------------------------------------------------------------------
+ * Set/Clear sector's lock bit, returns:
+ * 0 - OK
+ * 1 - Error (timeout, voltage problems, etc.)
+ */
+int flash_real_protect (flash_info_t * info, long sector, int prot)
+{
+ ulong start;
+ int i;
+ int rc = 0;
+ FPWV *addr = (FPWV *) (info->start[sector]);
+ int flag = disable_interrupts ();
+
+ *addr = INTEL_CLEAR; /* Clear status register */
+ if (prot) { /* Set sector lock bit */
+ *addr = INTEL_LOCKBIT; /* Sector lock bit */
+ *addr = INTEL_PROTECT; /* set */
+ } else { /* Clear sector lock bit */
+ *addr = INTEL_LOCKBIT; /* All sectors lock bits */
+ *addr = INTEL_CONFIRM; /* clear */
+ }
+
+ start = get_timer (0);
+
+ while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
+ if (get_timer (start) > CFG_FLASH_UNLOCK_TOUT) {
+ printf ("Flash lock bit operation timed out\n");
+ rc = 1;
+ break;
+ }
+ }
+
+ if (*addr != INTEL_OK) {
+ printf ("Flash lock bit operation failed at %08X, CSR=%08X\n",
+ (uint) addr, (uint) * addr);
+ rc = 1;
+ }
+
+ if (!rc)
+ info->protect[sector] = prot;
+
+ /*
+ * Clear lock bit command clears all sectors lock bits, so
+ * we have to restore lock bits of protected sectors.
+ */
+ if (!prot) {
+ for (i = 0; i < info->sector_count; i++) {
+ if (info->protect[i]) {
+ start = get_timer (0);
+ addr = (FPWV *) (info->start[i]);
+ *addr = INTEL_LOCKBIT; /* Sector lock bit */
+ *addr = INTEL_PROTECT; /* set */
+ while ((*addr & INTEL_FINISHED) !=
+ INTEL_FINISHED) {
+ if (get_timer (start) >
+ CFG_FLASH_UNLOCK_TOUT) {
+ printf ("Flash lock bit operation timed out\n");
+ rc = 1;
+ break;
+ }
+ }
+ }
+ }
+ }
+
+ if (flag)
+ enable_interrupts ();
+
+ *addr = INTEL_RESET; /* Reset to read array mode */
+
+ return rc;
+}
+
+
+/*
+ * This function gets the u-boot flash sector protection status
+ * (flash_info_t.protect[]) in sync with the sector protection
+ * status stored in hardware.
+ */
+static void flash_sync_real_protect (flash_info_t * info)
+{
+ int i;
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F128J3A:
+ for (i = 0; i < info->sector_count; ++i) {
+ info->protect[i] = intel_sector_protected(info, i);
+ }
+ break;
+ default:
+ /* no h/w protect support */
+ break;
+ }
+}
+
+
+/*
+ * checks if "sector" in bank "info" is protected. Should work on intel
+ * strata flash chips 28FxxxJ3x in 8-bit mode.
+ * Returns 1 if sector is protected (or timed-out while trying to read
+ * protection status), 0 if it is not.
+ */
+static unsigned char intel_sector_protected (flash_info_t *info, ushort sector)
+{
+ FPWV *addr;
+ FPWV *lock_conf_addr;
+ ulong start;
+ unsigned char ret;
+
+ /*
+ * first, wait for the WSM to be finished. The rationale for
+ * waiting for the WSM to become idle for at most
+ * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy
+ * because of: (1) erase, (2) program or (3) lock bit
+ * configuration. So we just wait for the longest timeout of
+ * the (1)-(3), i.e. the erase timeout.
+ */
+
+ /* wait at least 35ns (W12) before issuing Read Status Register */
+ udelay(1);
+ addr = (FPWV *) info->start[sector];
+ *addr = (FPW) INTEL_STATUS;
+
+ start = get_timer (0);
+ while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
+ if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
+ *addr = (FPW) INTEL_RESET; /* restore read mode */
+ printf("WSM busy too long, can't get prot status\n");
+ return 1;
+ }
+ }
+
+ /* issue the Read Identifier Codes command */
+ *addr = (FPW) INTEL_READID;
+
+ /* wait at least 35ns (W12) before reading */
+ udelay(1);
+
+ /* Intel example code uses offset of 4 for 8-bit flash */
+ lock_conf_addr = (FPWV *) info->start[sector] + 4;
+ ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0;
+
+ /* put flash back in read mode */
+ *addr = (FPW) INTEL_RESET;
+
+ return ret;
+}
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#define SDRAM_MODE 0x00CD0000
+#define SDRAM_CONTROL 0x504F0000
+#define SDRAM_CONFIG1 0xD2322800
+#define SDRAM_CONFIG2 0x8AD70000
+
+static void sdram_start (int hi_addr)
+{
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+ /* unlock mode register */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* precharge all banks */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* precharge all banks */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* auto refresh */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* set mode register */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+ __asm__ volatile ("sync");
+
+ /* normal operation */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+ __asm__ volatile ("sync");
+}
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ * is something else than 0x00000000.
+ */
+long int initdram (int board_type)
+{
+ ulong dramsize = 0;
+ ulong dramsize2 = 0;
+ ulong test1, test2;
+
+ /* setup SDRAM chip selects */
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+ __asm__ volatile ("sync");
+
+ /* setup config registers */
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+ __asm__ volatile ("sync");
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start(0);
+ test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+ sdram_start(1);
+ test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else {
+ dramsize = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20)) {
+ dramsize = 0;
+ }
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0)
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+ else
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+
+ /* let SDRAM CS1 start right after CS0 */
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+ /* find RAM size using SDRAM CS1 only */
+ if (!dramsize)
+ sdram_start(0);
+
+ test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+
+ if (!dramsize) {
+ sdram_start(1);
+ test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+ }
+
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize2 = test1;
+ } else {
+ dramsize2 = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize2 < (1 << 20))
+ dramsize2 = 0;
+
+ /* set SDRAM CS1 size according to the amount of RAM found */
+ if (dramsize2 > 0) {
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+ | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+ } else {
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+ }
+
+ return dramsize + dramsize2;
+}
+
+int checkboard (void)
+{
+ puts ("Board: O2DNT\n");
+ return 0;
+}
+
+void flash_preinit(void)
+{
+ /*
+ * Now, when we are in RAM, enable flash write
+ * access for detection process.
+ * Note that CS_BOOT cannot be cleared when
+ * executing in flash.
+ */
+ *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+}
+
+void flash_afterinit(ulong size)
+{
+ if (size == 0x800000) { /* adjust mapping */
+ *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
+ START_REG(CFG_BOOTCS_START | size);
+
+ *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
+ STOP_REG(CFG_BOOTCS_START | size, size);
+ }
+}
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+ pci_mpc5xxx_init(&hose);
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc5xxx/start.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ . = ALIGN(16);
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
LIB = lib$(BOARD).a
OBJS := omap1510innovator.o
-SOBJS := platform.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
_TEXT_BASE:
.word TEXT_BASE /* sdram load addr from config.mk */
-.globl platformsetup
-platformsetup:
+.globl lowlevel_init
+lowlevel_init:
/*
* Configure 1510 pins functions to match our board.
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
LIB = lib$(BOARD).a
OBJS := omap1610innovator.o flash.o
-SOBJS := platform.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
_TEXT_BASE:
.word TEXT_BASE /* sdram load addr from config.mk */
-.globl platformsetup
-platformsetup:
+.globl lowlevel_init
+lowlevel_init:
/*------------------------------------------------------*
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
LIB = lib$(BOARD).a
-OBJS := omap2420h4.o flash.o mem.o sys_info.o
-SOBJS := platform.o
+OBJS := omap2420h4.o mem.o sys_info.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
# Used with full SRAM boot.
# This is either with a GP system or a signed boot image.
# easiest, and safest way to go if you can.
-#TEXT_BASE = 0x40280000
+#TEXT_BASE = 0x40270000
+
+
+# Handy to get symbols to debug ROM version.
+#TEXT_BASE = 0x0
+#TEXT_BASE = 0x08000000
+#TEXT_BASE = 0x04000000
pll_div_val:
.word DPLL_VAL /* DPLL setting (300MHz default) */
-.globl platformsetup
-platformsetup:
+.globl lowlevel_init
+lowlevel_init:
ldr sp, SRAM_STACK
str ip, [sp] /* stash old link register */
mov ip, lr /* save link reg across call */
*********************************************************************************/
void prcm_init(void)
{
- u32 rev,div;
+ u32 div;
void (*f_lock_pll) (u32, u32, u32, u32);
extern void *_end_vect, *_start;
__raw_writel(DSP_DIV, CM_CLKSEL_DSP); /* set dsp and iva dividers */
__raw_writel(GFX_DIV, CM_CLKSEL_GFX); /* set gfx dividers */
- rev = get_cpu_rev();
- if (rev == CPU_2420_ES1 || rev == CPU_2422_ES1)
- div = BUS_DIV_ES1;
- else
- div = BUS_DIV;
+ div = BUS_DIV;
__raw_writel(div, CM_CLKSEL1_CORE);/* set L3/L4/USB/Display/Vlnc/SSi dividers */
sdelay(1000);
sdelay(1000);
}
+/**************************************************************************
+ * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
+ * command line mem=xyz use all memory with out discontigious support
+ * compiled in. Could do it at the ATAG, but there really is two banks...
+ * Called as part of 2nd phase DDR init.
+ **************************************************************************/
+void make_cs1_contiguous(void)
+{
+ u32 size, a_add_low, a_add_high;
+
+ size = get_sdr_cs_size(SDRC_CS0_OSET);
+ size /= SZ_32M; /* find size to offset CS1 */
+ a_add_high = (size & 3) << 8; /* set up low field */
+ a_add_low = (size & 0x3C) >> 2; /* set up high field */
+ __raw_writel((a_add_high|a_add_low),SDRC_CS_CFG);
+
+}
/********************************************************
* mem_ok() - test used to see if timings are correct
return(1);
}
+
/********************************************************
* sdrc_init() - init the sdrc chip selects CS0 and CS1
* - early init routines, called from flash or
**************************************************************************/
void do_sdrc_init(u32 offset, u32 early)
{
- u32 cpu, bug=0, rev, common=0, cs0=0, pmask=0, pass_type;
+ u32 cpu, dllen=0, rev, common=0, cs0=0, pmask=0, pass_type, mtype;
sdrc_data_t *sdata; /* do not change type */
u32 a, b, r;
static const sdrc_data_t sdrc_2422 =
{
H4_2422_SDRC_SHARING, H4_2422_SDRC_MDCFG_0_DDR, 0 , H4_2422_SDRC_ACTIM_CTRLA_0,
- H4_2422_SDRC_ACTIM_CTRLB_0, H4_2422_SDRC_RFR_CTRL_ES1, H4_2422_SDRC_MR_0_DDR,
- 0, H4_2422_SDRC_DLLA_CTRL, H4_2422_SDRC_DLLB_CTRL
+ H4_2422_SDRC_ACTIM_CTRLB_0, H4_2422_SDRC_RFR_CTRL, H4_2422_SDRC_MR_0_DDR,
+ 0, H4_2422_SDRC_DLLAB_CTRL
};
static const sdrc_data_t sdrc_2420 =
{
H4_2420_SDRC_SHARING, H4_2420_SDRC_MDCFG_0_DDR, H4_2420_SDRC_MDCFG_0_SDR,
H4_2420_SDRC_ACTIM_CTRLA_0, H4_2420_SDRC_ACTIM_CTRLB_0,
- H4_2420_SDRC_RFR_CTRL_ES1, H4_2420_SDRC_MR_0_DDR, H4_2420_SDRC_MR_0_SDR,
- H4_2420_SDRC_DLLA_CTRL, H4_2420_SDRC_DLLB_CTRL
+ H4_2420_SDRC_RFR_CTRL, H4_2420_SDRC_MR_0_DDR, H4_2420_SDRC_MR_0_SDR,
+ H4_2420_SDRC_DLLAB_CTRL
};
if (offset == SDRC_CS0_OSET)
cs0 = common = 1; /* int regs shared between both chip select */
cpu = get_cpu_type();
+ rev = get_cpu_rev();
/* warning generated, though code generation is correct. this may bite later,
* but is ok for now. there is only so much C code you can do on stack only
if(running_from_internal_boot())
sdata = (sdrc_data_t *)((u32)sdata + 0x4000);
}
- if (!early && (get_mem_type() == DDR_COMBO)) {/* combo part has a shared CKE signal, can't use feature */
- pmask = BIT2;
- pass_type = COMBO_DDR; /* CS1 config */
+
+ if (!early && (((mtype = get_mem_type()) == DDR_COMBO)||(mtype == DDR_STACKED))) {
+ if(mtype == DDR_COMBO){
+ pmask = BIT2;/* combo part has a shared CKE signal, can't use feature */
+ pass_type = COMBO_DDR; /* CS1 config */
+ __raw_writel((__raw_readl(SDRC_POWER)) & ~pmask, SDRC_POWER);
+ }
+ if(rev != CPU_2420_2422_ES1) /* for es2 and above smooth things out */
+ make_cs1_contiguous();
}
next_mem_type:
wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);/* wait till reset done set */
__raw_writel(0, SDRC_SYSCONFIG); /* clear soft reset */
__raw_writel(sdata->sdrc_sharing, SDRC_SHARING);
- __raw_writel((__raw_readl(SDRC_POWER)) & ~pmask, SDRC_POWER);
#ifdef POWER_SAVE
__raw_writel(__raw_readl(SMS_SYSCONFIG)|SMART_IDLE, SMS_SYSCONFIG);
__raw_writel(sdata->sdrc_sharing|SMART_IDLE, SDRC_SHARING);
- __raw_writel((__raw_readl(SDRC_POWER)|BIT6) & ~pmask, SDRC_POWER);
+ __raw_writel((__raw_readl(SDRC_POWER)|BIT6), SDRC_POWER);
#endif
}
__raw_writel(sdata->sdrc_mdcfg_0_sdr, SDRC_MCFG_0+offset);
}
- if(pass_type == IP_SDR){ /* SDRAM can run full speed only rated for 105MHz*/
- a = H4_242X_SDRC_ACTIM_CTRLA_0_100MHz;
- b = H4_242X_SDRC_ACTIM_CTRLB_0_100MHz;
- r = H4_2420_SDRC_RFR_CTRL;
- } else {
- a = sdata->sdrc_actim_ctrla_0;
- b = sdata->sdrc_actim_ctrlb_0;
- r = sdata->sdrc_rfr_ctrl;
- }
+ a = sdata->sdrc_actim_ctrla_0;
+ b = sdata->sdrc_actim_ctrlb_0;
+ r = sdata->sdrc_dllab_ctrl;
+
+ /* work around ES1 DDR issues */
+ if((pass_type != IP_SDR) && (rev == CPU_2420_2422_ES1)){
+ a = H4_242x_SDRC_ACTIM_CTRLA_0_ES1;
+ b = H4_242x_SDRC_ACTIM_CTRLB_0_ES1;
+ r = H4_242x_SDRC_RFR_CTRL_ES1;
+ }
if (cs0) {
__raw_writel(a, SDRC_ACTIM_CTRLA_0);
__raw_writel(a, SDRC_ACTIM_CTRLA_1);
__raw_writel(b, SDRC_ACTIM_CTRLB_1);
}
-
__raw_writel(r, SDRC_RFR_CTRL+offset);
/* init sequence for mDDR/mSDR using manual commands (DDR is a bit different) */
__raw_writel(sdata->sdrc_mr_0_ddr, SDRC_MR_0+offset);
/* NOTE: ES1 242x _BUG_ DLL + External Bandwidth fix*/
- rev = get_cpu_rev();
- if (rev == CPU_2420_ES1 || rev == CPU_2422_ES1){
- bug = BIT0;
+ if (rev == CPU_2420_2422_ES1){
+ dllen = (BIT0|BIT3); /* es1 clear both bit0 and bit3 */
__raw_writel((__raw_readl(SMS_CLASS_ARB0)|BURSTCOMPLETE_GROUP7)
,SMS_CLASS_ARB0);/* enable bust complete for lcd */
}
- /* enable & load up DLL with good value for 75MHz, and set phase to 90% */
+ else
+ dllen = BIT0|BIT1; /* es2, clear bit0, and 1 (set phase to 72) */
+
+ /* enable & load up DLL with good value for 75MHz, and set phase to 90
+ * ES1 recommends 90 phase, ES2 recommends 72 phase.
+ */
if (common && (pass_type != IP_SDR)) {
- __raw_writel(sdata->sdrc_dlla_ctrl, SDRC_DLLA_CTRL);
- __raw_writel(sdata->sdrc_dlla_ctrl & ~(BIT2|bug), SDRC_DLLA_CTRL);
- __raw_writel(sdata->sdrc_dllb_ctrl, SDRC_DLLB_CTRL);
- __raw_writel(sdata->sdrc_dllb_ctrl & ~(BIT2|bug) , SDRC_DLLB_CTRL);
+ __raw_writel(sdata->sdrc_dllab_ctrl, SDRC_DLLA_CTRL);
+ __raw_writel(sdata->sdrc_dllab_ctrl & ~(BIT2|dllen), SDRC_DLLA_CTRL);
+ __raw_writel(sdata->sdrc_dllab_ctrl, SDRC_DLLB_CTRL);
+ __raw_writel(sdata->sdrc_dllab_ctrl & ~(BIT2|dllen) , SDRC_DLLB_CTRL);
}
sdelay(90000);
*****************************************************/
void gpmc_init(void)
{
- u32 mux=0, mtype, mwidth;
+ u32 mux=0, mtype, mwidth, rev, tval;
+
+ rev = get_cpu_rev();
+ if (rev == CPU_2420_2422_ES1)
+ tval = 1;
+ else
+ tval = 0; /* disable bit switched meaning */
/* global settings */
__raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
__raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
- __raw_writel(0x1, GPMC_TIMEOUT_CONTROL);/* timeout disable */
+ __raw_writel(tval, GPMC_TIMEOUT_CONTROL);/* timeout disable */
#ifdef CFG_NAND_BOOT
__raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */
#else
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
#endif
-static void wait_for_command_complete(unsigned int wd_base);
+ void wait_for_command_complete(unsigned int wd_base);
/*******************************************************
* Routine: delay
}
/**********************************************************
+ * Routine: try_unlock_sram()
+ * Description: If chip is GP type, unlock the SRAM for
+ * general use.
+ ***********************************************************/
+void try_unlock_sram(void)
+{
+ /* if GP device unlock device SRAM for general use */
+ if (get_device_type() == GP_DEVICE) {
+ __raw_writel(0xFF, A_REQINFOPERM0);
+ __raw_writel(0xCFDE, A_READPERM0);
+ __raw_writel(0xCFDE, A_WRITEPERM0);
+ }
+}
+
+/**********************************************************
* Routine: s_init
* Description: Does early system init of muxing and clocks.
* - Called path is with sram stack.
watchdog_init();
set_muxconf_regs();
delay(100);
+ try_unlock_sram();
if(!in_sdram)
prcm_init();
*****************************************/
void watchdog_init(void)
{
- int mode;
- #define GP (BIT8|BIT9)
-
/* There are 4 watch dogs. 1 secure, and 3 general purpose.
- * I would expect that the ROM takes care of the secure one,
- * but we will try also. Of the 3 GP ones, 1 can reset us
- * directly, the other 2 only generate MPU interrupts.
- */
- mode = (__raw_readl(CONTROL_STATUS) & (BIT8|BIT9));
- if (mode == GP) {
- __raw_writel(WD_UNLOCK1 ,WD1_BASE+WSPR);
- wait_for_command_complete(WD1_BASE);
- __raw_writel(WD_UNLOCK2 ,WD1_BASE+WSPR);
- }
+ * The ROM takes care of the secure one. Of the 3 GP ones,
+ * 1 can reset us directly, the other 2 only generate MPU interrupts.
+ */
__raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR);
wait_for_command_complete(WD2_BASE);
__raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR);
* Routine: wait_for_command_complete
* Description: Wait for posting to finish on watchdog
******************************************************/
-static void wait_for_command_complete(unsigned int wd_base)
+void wait_for_command_complete(unsigned int wd_base)
{
int pending = 1;
do {
{
DECLARE_GLOBAL_DATA_PTR;
unsigned int size0=0,size1=0;
- u32 mtype, btype;
+ u32 mtype, btype, rev, cpu;
u8 chg_on = 0x5; /* enable charge of back up battery */
u8 vmode_on = 0x8C;
#define NOT_EARLY 0
btype = get_board_type();
mtype = get_mem_type();
+ rev = get_cpu_rev();
+ cpu = get_cpu_type();
display_board_info(btype);
if (btype == BOARD_H4_MENELAUS){
if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); /* init other chip select */
- size0 = size1 = SZ_32M;
- } else if (mtype == SDR_DISCRETE)
- size0 = SZ_128M;
- else
- size0 = SZ_64M;
+ }
+ size0 = get_sdr_cs_size(SDRC_CS0_OSET);
+ size1 = get_sdr_cs_size(SDRC_CS1_OSET);
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = size0;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ if(rev == CPU_2420_2422_ES1) /* ES1's 128MB remap granularity isn't worth doing */
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ else /* ES2 and above can remap at 32MB granularity */
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0;
gd->bd->bi_dram[1].size = size1;
return 0;
#include <i2c.h>
/**************************************************************************
+ * get_prod_id() - get id info from chips
+ ***************************************************************************/
+static u32 get_prod_id(void)
+{
+ u32 p;
+ p = __raw_readl(PRODUCTION_ID); /* get production ID */
+ return((p & CPU_242X_PID_MASK) >> 16);
+}
+
+/**************************************************************************
* get_cpu_type() - low level get cpu type
* - no C globals yet.
* - just looking to say if this is a 2422 or 2420 or ...
{
u32 v;
+ switch(get_prod_id()){
+ case 1:;/* 2420 */
+ case 2: return(CPU_2420); break; /* 2420 pop */
+ case 4: return(CPU_2422); break;
+ case 8: return(CPU_2423); break;
+ default: break; /* early 2420/2422's unmarked */
+ }
+
v = __raw_readl(TAP_IDCODE_REG);
v &= CPU_24XX_ID_MASK;
if (v == CPU_2420_CHIPID) { /* currently 2420 and 2422 have same id */
v = v >> 28;
return(v+1); /* currently 2422 and 2420 match up */
}
+/****************************************************
+ * is_mem_sdr() - return 1 if mem type in use is SDR
+ ****************************************************/
+u32 is_mem_sdr(void)
+{
+ volatile u32 *burst = (volatile u32 *)(SDRC_MR_0+SDRC_CS0_OSET);
+ if(*burst == H4_2420_SDRC_MR_0_SDR)
+ return(1);
+ return(0);
+}
/***********************************************************
* get_mem_type() - identify type of mDDR part used.
*************************************************************/
u32 get_mem_type(void)
{
- volatile u32 *burst = (volatile u32 *)(SDRC_MR_0+SDRC_CS0_OSET);
+ u32 cpu, sdr = is_mem_sdr();
- if (get_cpu_type() == CPU_2422)
+ cpu = get_cpu_type();
+ if (cpu == CPU_2422 || cpu == CPU_2423)
return(DDR_STACKED);
+ if(get_prod_id() == 0x2)
+ return(XDR_POP);
+
if (get_board_type() == BOARD_H4_MENELAUS)
- if(*burst == H4_2420_SDRC_MR_0_SDR)
+ if(sdr)
return(SDR_DISCRETE);
else
return(DDR_COMBO);
else
- if(*burst == H4_2420_SDRC_MR_0_SDR) /* SDP + SDR kit */
+ if(sdr) /* SDP + SDR kit */
return(SDR_DISCRETE);
else
return(DDR_DISCRETE); /* origional SDP */
}
/***********************************************************************
+ * get_cs0_size() - get size of chip select 0/1
+ ************************************************************************/
+u32 get_sdr_cs_size(u32 offset)
+{
+ u32 size;
+ size = __raw_readl(SDRC_MCFG_0+offset) >> 8; /* get ram size field */
+ size &= 0x2FF; /* remove unwanted bits */
+ size *= SZ_2M; /* find size in MB */
+ return(size);
+}
+
+/***********************************************************************
* get_board_type() - get board type based on current production stats.
* --- NOTE: 2 I2C EEPROMs will someday be populated with proper info.
* when they are available we can get info from there. This should
/******************************************************************
* get_sysboot_value() - get init word settings (dip switch on h4)
******************************************************************/
-u32 get_sysboot_value(void)
+inline u32 get_sysboot_value(void)
{
return(0x00000FFF & __raw_readl(CONTROL_STATUS));
}
*********************************************************************/
void display_board_info(u32 btype)
{
- char cpu_2420[] = "2420";
+ char cpu_2420[] = "2420"; /* cpu type */
char cpu_2422[] = "2422";
- char db_men[] = "Menelaus";
- char db_ip[]= "IP";
- char *cpu_s, *db_s;
- u32 cpu = get_cpu_type();
+ char cpu_2423[] = "2423";
+ char db_men[] = "Menelaus"; /* board type */
+ char db_ip[] = "IP";
+ char mem_sdr[] = "mSDR"; /* memory type */
+ char mem_ddr[] = "mDDR";
+ char t_tst[] = "TST"; /* security level */
+ char t_emu[] = "EMU";
+ char t_hs[] = "HS";
+ char t_gp[] = "GP";
+ char unk[] = "?";
- if(cpu == CPU_2420)
- cpu_s = cpu_2420;
+ char *cpu_s, *db_s, *mem_s, *sec_s;
+ u32 cpu, rev, sec;
+
+ rev = get_cpu_rev();
+ cpu = get_cpu_type();
+ sec = get_device_type();
+
+ if(is_mem_sdr())
+ mem_s = mem_sdr;
else
+ mem_s = mem_ddr;
+
+ if(cpu == CPU_2423)
+ cpu_s = cpu_2423;
+ else if (cpu == CPU_2422)
cpu_s = cpu_2422;
+ else
+ cpu_s = cpu_2420;
+
if(btype == BOARD_H4_MENELAUS)
db_s = db_men;
else
db_s = db_ip;
- printf("TI H4 SDP Base Board with OMAP%s %s Daughter Board\n",cpu_s, db_s);
+
+ switch(sec){
+ case TST_DEVICE: sec_s = t_tst; break;
+ case EMU_DEVICE: sec_s = t_emu; break;
+ case HS_DEVICE: sec_s = t_hs; break;
+ case GP_DEVICE: sec_s = t_gp; break;
+ default: sec_s = unk;
+ }
+
+ printf("OMAP%s-%s revision %d\n", cpu_s, sec_s, rev-1);
+ printf("TI H4 SDP Base Board + %s Daughter Board + %s \n", db_s, mem_s);
}
/*************************************************************************
/********************************************************
* get_base(); get upper addr of current execution
*******************************************************/
-static u32 get_base(void)
+u32 get_base(void)
{
u32 val;
__asm__ __volatile__("mov %0, pc \n" : "=r" (val) : : "memory");
/********************************************************
* get_base2(); get 2upper addr of current execution
*******************************************************/
-static u32 get_base2(void)
+u32 get_base2(void)
{
u32 val;
__asm__ __volatile__("mov %0, pc \n" : "=r" (val) : : "memory");
else
return(0);
}
+
+/*************************************************************
+ * get_device_type(): tell if GP/HS/EMU/TST
+ *************************************************************/
+u32 get_device_type(void)
+{
+ int mode;
+ mode = __raw_readl(CONTROL_STATUS) & (BIT10|BIT9|BIT8);
+ return(mode >>= 8);
+}
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
LIB = lib$(BOARD).a
-OBJS := omap5912osk.o flash.o
-SOBJS := platform.o
+OBJS := omap5912osk.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
_TEXT_BASE:
.word TEXT_BASE /* sdram load addr from config.mk */
-.globl platformsetup
-platformsetup:
+.globl lowlevel_init
+lowlevel_init:
/*------------------------------------------------------*
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
LIB = lib$(BOARD).a
OBJS := omap730p2.o flash.o
-SOBJS := platform.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
_TEXT_BASE:
.word TEXT_BASE /* sdram load addr from config.mk */
-.globl platformsetup
-platformsetup:
+.globl lowlevel_init
+lowlevel_init:
/* Save callers address in r11 - r11 must never be modified */
mov r11, lr
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
--- /dev/null
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o
+SOBJS = memsetup.o
+
+$(LIB): .depend $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+By Thomas.Lange@corelatus.se 2004-Oct-05
+----------------------------------------
+DbAu1xx0 are development boards from AMD containing
+an Alchemy AU1xx0 series cpu with mips32 core.
+Existing cpu:s are Au1000, Au1100, Au1500 and Au1550
+
+Limitations & comments
+----------------------
+Support was originally big endian only.
+I have not tested, but several u-boot users report working
+configurations in little endian mode.
+
+I named the board dbau1x00, to allow
+support for all three development boards
+( dbau1000, dbau1100 and dbau1500 ).
+Now there is a new board called dbau1550 also, which
+should be supported RSN.
+
+I only have a dbau1000, so my testing is limited
+to this board.
+
+The board has two different flash banks, that can
+be selected via dip switch. This makes it possible
+to test new bootloaders without thrashing the YAMON
+boot loader delivered with board.
+
+NOTE! When you switch between the two boot flashes, the
+base addresses will be swapped.
+Have this in mind when you compile u-boot. TEXT_BASE has
+to match the address where u-boot is located when you
+actually launch.
+
+Ethernet only supported for mac0.
+
+PCMCIA only supported for slot 0, only 3.3V.
+
+PCMCIA IDE tested with Sandisk Compact Flash and
+IBM microdrive.
+
+###################################
+######## NOTE!!!!!! #########
+###################################
+If you partition a disk on another system (e.g. laptop),
+all bytes will be swapped on 16bit level when using
+PCMCIA and running cpu in big endian mode!!!!
+
+This is probably due to an error in Au1000 chip.
+
+Solution:
+
+a) Boot via network and partition disk directly from
+dbau1x00. The endian will then be correct.
+
+b) Partition disk on "laptop" and fill it with all files
+you need. Then write a simple program that endian swaps
+whole disk,
+
+Example:
+Original "laptop" byte order:
+B0 B1 B2 B3 B4 B5 B6 B7 B8 B9...
+
+Dbau1000 byte order will then be:
+B1 B0 B3 B2 B5 B4 B7 B6 B9 B8...
--- /dev/null
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# AMD development board AMD Alchemy Pb1x00, MIPS32 core
+#
+
+# ROM version
+#TEXT_BASE = 0xbfc00000
+
+# SDRAM version
+TEXT_BASE = 0x83800000
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+ printf ("Skipping flash_init\n");
+ return (0);
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ printf ("write_buff not implemented\n");
+ return (-1);
+}
--- /dev/null
+/* Memory sub-system initialization code */
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+#include <asm/au1x00.h>
+#include <asm/mipsregs.h>
+
+#define AU1500_SYS_ADDR 0xB1900000
+#define sys_endian 0x0038
+#define CP0_Config0 $16
+#define MEM_1MS ((396000000/1000000) * 1000)
+
+ .text
+ .set noreorder
+ .set mips32
+
+ .globl memsetup
+memsetup:
+ /*
+ * Step 1) Establish CPU endian mode.
+ * NOTE: A fair amount of code is necessary on the Pb1000 to
+ * obtain the value of Switch S8.1 which is used to determine
+ * endian at run-time.
+ */
+
+ /* RCE1 */
+ li t0, MEM_STCFG1
+ li t1, 0x00000083
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME1
+ li t1, 0x33030A10
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR1
+ li t1, 0x11803E40
+ sw t1, 0(t0)
+
+ /* Set DSTRB bits so switch will read correctly */
+ li t1, 0xBE00000C
+ lw t2, 0(t1)
+ or t2, t2, 0x00000300
+ sw t2, 0(t1)
+
+ /* Check switch setting */
+ li t1, 0xBE000014
+ lw t2, 0(t1)
+ and t2, t2, 0x00000100
+ bne t2, zero, big_endian
+ nop
+
+little_endian:
+
+ /* Change Au1 core to little endian */
+ li t0, AU1500_SYS_ADDR
+ li t1, 1
+ sw t1, sys_endian(t0)
+ mfc0 t2, CP0_CONFIG
+ mtc0 t2, CP0_CONFIG
+ nop
+ nop
+
+ /* Big Endian is default so nothing to do but fall through */
+
+big_endian:
+
+ /*
+ * Step 2) Establish Status Register
+ * (set BEV, clear ERL, clear EXL, clear IE)
+ */
+ li t1, 0x00400000
+ mtc0 t1, CP0_STATUS
+
+ /*
+ * Step 3) Establish CP0 Config0
+ * (set OD, set K0=3)
+ */
+ li t1, 0x00080003
+ mtc0 t1, CP0_CONFIG
+
+ /*
+ * Step 4) Disable Watchpoint facilities
+ */
+ li t1, 0x00000000
+ mtc0 t1, CP0_WATCHLO
+ mtc0 t1, CP0_IWATCHLO
+ /*
+ * Step 5) Disable the performance counters
+ */
+ mtc0 zero, CP0_PERFORMANCE
+ nop
+
+ /*
+ * Step 6) Establish EJTAG Debug register
+ */
+ mtc0 zero, CP0_DEBUG
+ nop
+
+ /*
+ * Step 7) Establish Cause
+ * (set IV bit)
+ */
+ li t1, 0x00800000
+ mtc0 t1, CP0_CAUSE
+
+ /* Establish Wired (and Random) */
+ mtc0 zero, CP0_WIRED
+ nop
+
+ /* First setup pll:s to make serial work ok */
+ /* We have a 12 MHz crystal */
+ li t0, SYS_CPUPLL
+ li t1, 0x21 /* 396 MHz */
+ sw t1, 0(t0)
+ sync
+ nop
+ nop
+
+ /* wait 1mS for clocks to settle */
+ li t1, MEM_1MS
+1: add t1, -1
+ bne t1, zero, 1b
+ nop
+ /* Setup AUX PLL */
+ li t0, SYS_AUXPLL
+ li t1, 8 /* 96 MHz */
+ sw t1, 0(t0) /* aux pll */
+ sync
+
+ /* Static memory controller */
+
+ /* RCE0 8MB AMD29D323 Flash */
+ li t0, MEM_STCFG0
+ li t1, 0x00001403
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME0
+ li t1, 0xFFFFFFDD
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR0
+ li t1, 0x11F83FE0
+ sw t1, 0(t0)
+
+ /* RCE1 CPLD Board Logic */
+ li t0, MEM_STCFG1
+ li t1, 0x00000083
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME1
+ li t1, 0x33030A10
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR1
+ li t1, 0x11803E40
+ sw t1, 0(t0)
+
+ /* RCE2 CPLD Board Logic */
+ li t0, MEM_STCFG2
+ li t1, 0x00000004
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME2
+ li t1, 0x08061908
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR2
+ li t1, 0x12A03FC0
+ sw t1, 0(t0)
+
+ /* RCE3 PCMCIA 250ns */
+ li t0, MEM_STCFG3
+ li t1, 0x00000002
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME3
+ li t1, 0x280E3E07
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR3
+ li t1, 0x10000000
+ sw t1, 0(t0)
+
+ sync
+
+ /* Set peripherals to a known state */
+ li t0, IC0_CFG0CLR
+ li t1, 0xFFFFFFFF
+ sw t1, 0(t0)
+
+ li t0, IC0_CFG0CLR
+ sw t1, 0(t0)
+
+ li t0, IC0_CFG1CLR
+ sw t1, 0(t0)
+
+ li t0, IC0_CFG2CLR
+ sw t1, 0(t0)
+
+ li t0, IC0_SRCSET
+ sw t1, 0(t0)
+
+ li t0, IC0_ASSIGNSET
+ sw t1, 0(t0)
+
+ li t0, IC0_WAKECLR
+ sw t1, 0(t0)
+
+ li t0, IC0_RISINGCLR
+ sw t1, 0(t0)
+
+ li t0, IC0_FALLINGCLR
+ sw t1, 0(t0)
+
+ li t0, IC0_TESTBIT
+ li t1, 0x00000000
+ sw t1, 0(t0)
+ sync
+
+ li t0, IC1_CFG0CLR
+ li t1, 0xFFFFFFFF
+ sw t1, 0(t0)
+
+ li t0, IC1_CFG0CLR
+ sw t1, 0(t0)
+
+ li t0, IC1_CFG1CLR
+ sw t1, 0(t0)
+
+ li t0, IC1_CFG2CLR
+ sw t1, 0(t0)
+
+ li t0, IC1_SRCSET
+ sw t1, 0(t0)
+
+ li t0, IC1_ASSIGNSET
+ sw t1, 0(t0)
+
+ li t0, IC1_WAKECLR
+ sw t1, 0(t0)
+
+ li t0, IC1_RISINGCLR
+ sw t1, 0(t0)
+
+ li t0, IC1_FALLINGCLR
+ sw t1, 0(t0)
+
+ li t0, IC1_TESTBIT
+ li t1, 0x00000000
+ sw t1, 0(t0)
+ sync
+
+ li t0, SYS_FREQCTRL0
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, SYS_FREQCTRL1
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, SYS_CLKSRC
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, SYS_PININPUTEN
+ li t1, 0x00000000
+ sw t1, 0(t0)
+ sync
+
+ li t0, 0xB1100100
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, 0xB1400100
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+
+ li t0, SYS_WAKEMSK
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, SYS_WAKESRC
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ /* wait 1mS before setup */
+ li t1, MEM_1MS
+1: add t1, -1
+ bne t1, zero, 1b
+ nop
+
+ /*
+ * Skip memory setup if we are running from memory
+ */
+ li t0, 0x90000000
+ sub t0, ra, t0
+ bltz t0, skip_memsetup
+ nop
+
+ /*
+ * SDCS0 - Not used, for SMROM
+ * SDCS1 - 32MB Micron 48LCBM16A2
+ * SDCS2 - 32MB Micron 48LCBM16A2
+ */
+ li t0, MEM_SDMODE0
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, MEM_SDMODE1
+ li t1, 0x00552229
+ sw t1, 0(t0)
+
+ li t0, MEM_SDMODE2
+ li t1, 0x00552229
+ sw t1, 0(t0)
+
+ li t0, MEM_SDADDR0
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, MEM_SDADDR1
+ li t1, 0x001003F8
+ sw t1, 0(t0)
+
+ li t0, MEM_SDADDR2
+ li t1, 0x001023F8
+ sw t1, 0(t0)
+
+ sync
+
+ li t0, MEM_SDREFCFG
+ li t1, 0x74000c30 /* Disable */
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDPRECMD
+ sw zero, 0(t0)
+ sync
+
+ li t0, MEM_SDAUTOREF
+ sw zero, 0(t0)
+ sync
+ sw zero, 0(t0)
+ sync
+
+ li t0, MEM_SDREFCFG
+ li t1, 0x76000c30 /* Enable */
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDWRMD0
+ li t1, 0x00000023
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDWRMD1
+ li t1, 0x00000023
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDWRMD2
+ li t1, 0x00000023
+ sw t1, 0(t0)
+ sync
+
+ /* wait 1mS after setup */
+ li t1, MEM_1MS
+1: add t1, -1
+ bne t1, zero, 1b
+ nop
+
+skip_memsetup:
+
+ li t0, SYS_PINFUNC
+ li t1, 0/*0x00008080*/
+ sw t1, 0(t0)
+
+ /*
+ li t0, SYS_TRIOUTCLR
+ li t1, 0x00001FFF
+ sw t1, 0(t0)
+
+ li t0, SYS_OUTPUTCLR
+ li t1, 0x00008000
+ sw t1, 0(t0)
+ */
+ sync
+
+ j ra
+ nop
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Thomas.Lange@corelatus.se
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/au1x00.h>
+#include <asm/mipsregs.h>
+
+long int initdram(int board_type)
+{
+ /* Sdram is setup by assembler code */
+ /* If memory could be changed, we should return the true value here */
+ return 64*1024*1024;
+}
+
+#define BCSR_PCMCIA_PC0DRVEN 0x0010
+#define BCSR_PCMCIA_PC0RST 0x0080
+
+/* In cpu/mips/cpu.c */
+void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
+
+int checkboard (void)
+{
+ u16 status;
+ /* volatile u32 *pcmcia_bcsr = (u32*)(DB1000_BCSR_ADDR+0x10); */
+ volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
+ u32 proc_id;
+
+ *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
+
+ proc_id = read_32bit_cp0_register(CP0_PRID);
+
+ switch (proc_id >> 24) {
+ case 0:
+ puts ("Board: Pb1000\n");
+ printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n",
+ (proc_id >> 8) & 0xFF, proc_id & 0xFF);
+ break;
+ case 1:
+ puts ("Board: Pb1500\n");
+ printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n",
+ (proc_id >> 8) & 0xFF, proc_id & 0xFF);
+ break;
+ case 2:
+ puts ("Board: Pb1100\n");
+ printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n",
+ (proc_id >> 8) & 0xFF, proc_id & 0xFF);
+ break;
+ default:
+ printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
+ }
+#if defined(CONFIG_IDE_PCMCIA) && 0
+ /* Enable 3.3 V on slot 0 ( VCC )
+ No 5V */
+ status = 4;
+ *pcmcia_bcsr = status;
+
+ status |= BCSR_PCMCIA_PC0DRVEN;
+ *pcmcia_bcsr = status;
+ au_sync();
+
+ udelay(300*1000);
+
+ status |= BCSR_PCMCIA_PC0RST;
+ *pcmcia_bcsr = status;
+ au_sync();
+
+ udelay(100*1000);
+
+ /* PCMCIA is on a 36 bit physical address.
+ We need to map it into a 32 bit addresses */
+
+#if 0
+ /* We dont need theese unless we run whole pcmcia package */
+ write_one_tlb(20, /* index */
+ 0x01ffe000, /* Pagemask, 16 MB pages */
+ CFG_PCMCIA_IO_BASE, /* Hi */
+ 0x3C000017, /* Lo0 */
+ 0x3C200017); /* Lo1 */
+
+ write_one_tlb(21, /* index */
+ 0x01ffe000, /* Pagemask, 16 MB pages */
+ CFG_PCMCIA_ATTR_BASE, /* Hi */
+ 0x3D000017, /* Lo0 */
+ 0x3D200017); /* Lo1 */
+#endif /* 0 */
+ write_one_tlb(22, /* index */
+ 0x01ffe000, /* Pagemask, 16 MB pages */
+ CFG_PCMCIA_MEM_ADDR, /* Hi */
+ 0x3E000017, /* Lo0 */
+ 0x3E200017); /* Lo1 */
+#endif /* CONFIG_IDE_PCMCIA */
+
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
+*/
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .sdata : { *(.sdata) }
+
+ _gp = ALIGN(16);
+
+ __got_start = .;
+ .got : { *(.got) }
+ __got_end = .;
+
+ .sdata : { *(.sdata) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ uboot_end_data = .;
+ num_got_entries = (__got_end - __got_start) >> 2;
+
+ . = ALIGN(4);
+ .sbss : { *(.sbss) }
+ .bss : { *(.bss) }
+ uboot_end = .;
+}
DEBUGF("Device ID @ 0x%08lx: 0x%08x\n", addr+1, value);
- switch (value) {
+ switch ((ulong)value) {
case AMD_ID_F040B:
DEBUGF("Am29F040B\n");
info->flash_id += FLASH_AM040;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
}
switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F256J3A:
+ printf ("28F256J3A\n");
+ break;
+
case FLASH_28F128J3A:
printf ("28F128J3A\n");
break;
switch (value) {
+ case (FPW) INTEL_ID_28F256J3A:
+ info->flash_id += FLASH_28F256J3A;
+ /* In U-Boot we support only 32 MB (no bank-switching) */
+ info->sector_count = 256 / 2;
+ info->size = 0x04000000 / 2;
+ info->start[0] = CFG_FLASH_BASE + 0x02000000;
+ break; /* => 32 MB */
+
case (FPW) INTEL_ID_28F128J3A:
info->flash_id += FLASH_28F128J3A;
info->sector_count = 128;
info->size = 0x02000000;
- info->start[0] = CFG_FLASH_BASE;
+ info->start[0] = CFG_FLASH_BASE + 0x02000000;
break; /* => 32 MB */
case (FPW) INTEL_ID_28F640J3A:
info->flash_id += FLASH_28F640J3A;
info->sector_count = 64;
info->size = 0x01000000;
- info->start[0] = CFG_FLASH_BASE + 0x01000000;
+ info->start[0] = CFG_FLASH_BASE + 0x03000000;
break; /* => 16 MB */
case (FPW) INTEL_ID_28F320J3A:
info->flash_id += FLASH_28F320J3A;
info->sector_count = 32;
info->size = 0x800000;
- info->start[0] = CFG_FLASH_BASE + 0x01800000;
+ info->start[0] = CFG_FLASH_BASE + 0x03800000;
break; /* => 8 MB */
default:
switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F256J3A:
case FLASH_28F128J3A:
case FLASH_28F640J3A:
case FLASH_28F320J3A:
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
- test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
sdram_start(1);
- test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
/* find RAM size using SDRAM CS1 only */
if (!dramsize)
sdram_start(0);
- test2 = test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+ test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
if (!dramsize) {
sdram_start(1);
- test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+ test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
}
if (test1 > test2) {
sdram_start(0);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
if (size < I2155X_VPD_SN_SIZE)
size = I2155X_VPD_SN_SIZE;
for (i = 0; i < (size - 1); i++) {
- i2155x_read_vpd (I2155X_VPD_SN_START + i, 1, &c);
+ i2155x_read_vpd (I2155X_VPD_SN_START + i, 1, (uchar *)&c);
if (c == '\0')
break;
string[i] = c;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
int res;
if ((ds != 0) && (ds != 0xff)) {
- res = getenv_r ("ethaddr", tmp, sizeof (tmp));
+ res = getenv_r ("ethaddr", (char *)tmp, sizeof (tmp));
if (res > 0) {
ss = ((ds >> 4) & 0x0f);
ss += ss < 0x0a ? '0' : ('a' - 10);
tmp[16] = ss;
tmp[17] = '\0';
- setenv ("ethaddr", tmp);
+ setenv ("ethaddr", (char *)tmp);
/* set the led to show the address */
*((unsigned char *) (CFG_LED_BASE + 1)) = ds;
}
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
--- /dev/null
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o
+SOBJS = init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ADCIOP boards
+#
+
+#TEXT_BASE = 0xFFFE0000
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0x07FD0000
+else
+TEXT_BASE = 0xFFFC0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID 0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K 0x00000000
+#define SZ_4K 0x00000010
+#define SZ_16K 0x00000020
+#define SZ_64K 0x00000030
+#define SZ_256K 0x00000040
+#define SZ_1M 0x00000050
+#define SZ_16M 0x00000070
+#define SZ_256M 0x00000090
+
+/* Storage attributes */
+#define SA_W 0x00000800 /* Write-through */
+#define SA_I 0x00000400 /* Caching inhibited */
+#define SA_M 0x00000200 /* Memory coherence */
+#define SA_G 0x00000100 /* Guarded */
+#define SA_E 0x00000080 /* Endian */
+
+/* Access control */
+#define AC_X 0x00000024 /* Execute */
+#define AC_W 0x00000012 /* Write */
+#define AC_R 0x00000009 /* Read */
+
+/* Some handy macros */
+
+#define EPN(e) ((e) & 0xfffffc00)
+#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a) ( (a)&0x00000fbf )
+
+#define tlbtab_start\
+ mflr r1 ;\
+ bl 0f ;
+
+#define tlbtab_end\
+ .long 0, 0, 0 ; \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+ .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+ tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+ tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
+ tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
+ tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+ tlbtab_end
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+
+#include "p3p440.h"
+
+void set_led(int color)
+{
+ switch (color) {
+ case LED_OFF:
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LED_GREEN & ~CFG_LED_RED);
+ break;
+
+ case LED_GREEN:
+ out32(GPIO0_OR, (in32(GPIO0_OR) | CFG_LED_GREEN) & ~CFG_LED_RED);
+ break;
+
+ case LED_RED:
+ out32(GPIO0_OR, (in32(GPIO0_OR) | CFG_LED_RED) & ~CFG_LED_GREEN);
+ break;
+
+ case LED_ORANGE:
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LED_GREEN | CFG_LED_RED);
+ break;
+ }
+}
+
+static int is_monarch(void)
+{
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_GPIO_RDY);
+ udelay(1000);
+
+ if (in32(GPIO0_IR) & CFG_MONARCH_IO)
+ return 0;
+ else
+ return 1;
+}
+
+static void wait_for_pci_ready(void)
+{
+ /*
+ * Configure EREADY_IO as input
+ */
+ out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_EREADY_IO);
+ udelay(1000);
+
+ for (;;) {
+ if (in32(GPIO0_IR) & CFG_EREADY_IO)
+ return;
+ }
+
+}
+
+int board_early_init_f(void)
+{
+ uint reg;
+
+ /*--------------------------------------------------------------------
+ * Setup the external bus controller/chip selects
+ *-------------------------------------------------------------------*/
+ mtdcr(ebccfga, xbcfg);
+ reg = mfdcr(ebccfgd);
+ mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
+
+ /*--------------------------------------------------------------------
+ * Setup pin multiplexing (GPIO/IRQ...)
+ *-------------------------------------------------------------------*/
+ mtdcr(cpc0_gpio, 0x03F01F80);
+
+ out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
+ out32(GPIO0_TCR, CFG_GPIO_RDY | CFG_EREADY_IO | CFG_LED_RED | CFG_LED_GREEN);
+ out32(GPIO0_OR, CFG_GPIO_RDY);
+
+ /*--------------------------------------------------------------------
+ * Setup the interrupt controller polarities, triggers, etc.
+ *-------------------------------------------------------------------*/
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+ mtdcr(uic0er, 0x00000000); /* disable all */
+ mtdcr(uic0cr, 0x00000001); /* UIC1 crit is critical */
+ mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
+ mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
+ mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+ mtdcr(uic1er, 0x00000000); /* disable all */
+ mtdcr(uic1cr, 0x00000000); /* all non-critical */
+ mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
+ mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
+ mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+
+ printf("Board: P3P440");
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+
+ if (is_monarch()) {
+ puts(", Monarch");
+ } else {
+ puts(", None-Monarch");
+ }
+
+ putc('\n');
+
+ return (0);
+}
+
+int misc_init_r (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ /*
+ * Adjust flash start and offset to detected values
+ */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+ /*
+ * Check if only one FLASH bank is available
+ */
+ if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
+ mtebc(pb1cr, 0); /* disable cs */
+ mtebc(pb1ap, 0);
+ mtebc(pb2cr, 0); /* disable cs */
+ mtebc(pb2ap, 0);
+ mtebc(pb3cr, 0); /* disable cs */
+ mtebc(pb3ap, 0);
+ }
+
+ return 0;
+}
+
+/*************************************************************************
+ * pci_pre_init
+ *
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
+ *
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller *hose)
+{
+ unsigned long strap;
+
+ /*--------------------------------------------------------------------------+
+ * The P3P440 board is always configured as the host & requires the
+ * PCI arbiter to be disabled because it's an PMC module.
+ *--------------------------------------------------------------------------*/
+ strap = mfdcr(cpc0_strp1);
+ if (strap & 0x00100000) {
+ printf("PCI: CPC0_STRP1[PAE] set.\n");
+ return 0;
+ }
+
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ * pci_target_init
+ *
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ /*--------------------------------------------------------------------------+
+ * Disable everything
+ *--------------------------------------------------------------------------*/
+ out32r(PCIX0_PIM0SA, 0); /* disable */
+ out32r(PCIX0_PIM1SA, 0); /* disable */
+ out32r(PCIX0_PIM2SA, 0); /* disable */
+ out32r(PCIX0_EROMBA, 0); /* disable expansion rom */
+
+ /*--------------------------------------------------------------------------+
+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
+ * options to not support sizes such as 128/256 MB.
+ *--------------------------------------------------------------------------*/
+ out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE);
+ out32r(PCIX0_PIM0LAH, 0);
+ out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
+
+ out32r(PCIX0_BAR0, 0);
+
+ /*--------------------------------------------------------------------------+
+ * Program the board's subsystem id/vendor id
+ *--------------------------------------------------------------------------*/
+ out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
+ out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
+
+ out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+/*************************************************************************
+ * is_pci_host
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+ if (is_monarch()) {
+ wait_for_pci_ready();
+ return 1; /* return 1 for host controller */
+ } else {
+ return 0; /* return 0 for adapter controller */
+ }
+}
+#endif /* defined(CONFIG_PCI) */
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __P3P440_H__
+#define __P3P440_H__
+
+#define CFG_GPIO_RDY (0x80000000 >> 11)
+#define CFG_MONARCH_IO (0x80000000 >> 18)
+#define CFG_EREADY_IO (0x80000000 >> 20)
+#define CFG_LED_GREEN (0x80000000 >> 21)
+#define CFG_LED_RED (0x80000000 >> 22)
+
+#define LED_OFF 1
+#define LED_GREEN 2
+#define LED_RED 3
+#define LED_ORANGE 4
+
+long int fixed_sdram(void);
+
+#endif /* __P3P440_H__ */
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ board/prodrive/p3p440/init.o (.text)
+ cpu/ppc4xx/kgdb.o (.text)
+ cpu/ppc4xx/traps.o (.text)
+ cpu/ppc4xx/interrupts.o (.text)
+ cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/cpu_init.o (.text)
+ cpu/ppc4xx/speed.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+
+/* . = env_offset;*/
+/* common/environment.o(.text)*/
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
* the initialization code relocates the command table as
* well -- admittedly, this is just pure laziness ;-)
*/
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd :
{
* the initialization code relocates the command table as
* well -- admittedly, this is just pure laziness ;-)
*/
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd :
{
.sdata : { *(.sdata) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
--- /dev/null
+
+#
+# (C) Copyright 2000-2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := pxa_idp.o
+SOBJS := memsetup.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+Tested:
+
+- MMC
+- Ethernet
+- BL console (on serial port connector J5)
+- flash support
+
+Todo:
+
+- display support
+- PCMCIA support
--- /dev/null
+#TEXT_BASE = 0xa1700000
+TEXT_BASE = 0xa3000000
+#TEXT_BASE = 0
--- /dev/null
+Notes on the Vibren PXA255 IDP.
+
+Chip select usage:
+
+CS0 - flash
+CS1 - alt flash (Mdoc or main flash)
+CS2 - high speed expansion bus
+CS3 - Media Q, low speed exp bus
+CS4 - low speed exp bus
+CS5 - low speed exp bus
+ - IDE: offset 0x03000000 (abs: 0x17000000)
+ - Eth: offset 0x03400000 (abs: 0x17400000)
+ - core voltage latch: offset 0x03800000 (abs: 0x17800000)
+ - CPLD: offset 0x03C00000 (abs: 0x17C00000)
+
+PCMCIA Power control
+
+MAX1602EE w/ code pulled high (Cirrus code)
+vx = 5v
+vy = 3v
+
+ Bit pattern
+ PWR 3,2,1,0
+vcc vpp A1VCC A0VCC A1VPP A0VPP
+=====================================================
+0 0 0 0 0 0 0x0
+3 (vy) 0 1 0 1 1 0xB
+3 (vy) 3 (vy) 1 0 0 1 0x9
+3 (vy) 12(12in) 1 0 1 0 0xA
+5 (vx) 0 0 1 1 1 0x7
+5 (vx) 5 (vx) 0 1 0 1 0x5
+5 (vx 12(12in) 0 1 1 0 0x6
+
+Display power sequencing:
+
+- VDD applied
+- within 1sec, activate scanning signals
+- wait at least 50mS - scanning signals must be active before activating DISP
+
+Signal mapping:
+Schematic LV8V31 signal name
+=========================================
+LCD_ENAVLCD DISP
+LCD_PWR Applies VDD to board
+
+Both of the above signals are controlled by the CPLD
--- /dev/null
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/memsetup.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE: .long CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+ .macro CPWAIT reg
+ mrc p15,0,\reg,c2,c0,0
+ mov \reg,\reg
+ sub pc,pc,#4
+ .endm
+
+/*
+ * Memory setup
+ */
+.globl memsetup
+memsetup:
+
+ mov r10, lr
+
+#ifdef DEBUG_BLINK_ENABLE
+ /* 3rd blink */
+ bl blink
+#endif
+
+ /* Set up GPIO pins first ----------------------------------------- */
+ ldr r0, =GPSR0
+ ldr r1, =CFG_GPSR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR1
+ ldr r1, =CFG_GPSR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR2
+ ldr r1, =CFG_GPSR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR0
+ ldr r1, =CFG_GPCR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR1
+ ldr r1, =CFG_GPCR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR2
+ ldr r1, =CFG_GPCR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR0
+ ldr r1, =CFG_GPDR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR1
+ ldr r1, =CFG_GPDR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR2
+ ldr r1, =CFG_GPDR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR0_L
+ ldr r1, =CFG_GAFR0_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR0_U
+ ldr r1, =CFG_GAFR0_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR1_L
+ ldr r1, =CFG_GAFR1_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR1_U
+ ldr r1, =CFG_GAFR1_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR2_L
+ ldr r1, =CFG_GAFR2_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR2_U
+ ldr r1, =CFG_GAFR2_U_VAL
+ str r1, [r0]
+
+ ldr r0, =PSSR /* enable GPIO pins */
+ ldr r1, =CFG_PSSR_VAL
+ str r1, [r0]
+
+#ifdef DEBUG_BLINK_ENABLE
+ /* 4th debug blink */
+ bl blink
+#endif
+
+ /* ---------------------------------------------------------------- */
+ /* Enable memory interface */
+ /* */
+ /* The sequence below is based on the recommended init steps */
+ /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+ /* Chapter 10. */
+ /* ---------------------------------------------------------------- */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 1: Wait for at least 200 microsedonds to allow internal */
+ /* clocks to settle. Only necessary after hard reset... */
+ /* FIXME: can be optimized later */
+ /* ---------------------------------------------------------------- */
+
+ ldr r3, =OSCR /* reset the OS Timer Count to zero */
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
+ /* so 0x300 should be plenty */
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+mem_init:
+
+ ldr r1, =MEMC_BASE /* get memory controller base addr. */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2a: Initialize Asynchronous static memory controller */
+ /* ---------------------------------------------------------------- */
+
+ /* MSC registers: timing, bus width, mem type */
+
+ /* MSC0: nCS(0,1) */
+ ldr r2, =CFG_MSC0_VAL
+ str r2, [r1, #MSC0_OFFSET]
+ ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
+ /* that data latches */
+ /* MSC1: nCS(2,3) */
+ ldr r2, =CFG_MSC1_VAL
+ str r2, [r1, #MSC1_OFFSET]
+ ldr r2, [r1, #MSC1_OFFSET]
+
+ /* MSC2: nCS(4,5) */
+ ldr r2, =CFG_MSC2_VAL
+ str r2, [r1, #MSC2_OFFSET]
+ ldr r2, [r1, #MSC2_OFFSET]
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2b: Initialize Card Interface */
+ /* ---------------------------------------------------------------- */
+
+ /* MECR: Memory Expansion Card Register */
+ ldr r2, =CFG_MECR_VAL
+ str r2, [r1, #MECR_OFFSET]
+ ldr r2, [r1, #MECR_OFFSET]
+
+ /* MCMEM0: Card Interface slot 0 timing */
+ ldr r2, =CFG_MCMEM0_VAL
+ str r2, [r1, #MCMEM0_OFFSET]
+ ldr r2, [r1, #MCMEM0_OFFSET]
+
+ /* MCMEM1: Card Interface slot 1 timing */
+ ldr r2, =CFG_MCMEM1_VAL
+ str r2, [r1, #MCMEM1_OFFSET]
+ ldr r2, [r1, #MCMEM1_OFFSET]
+
+ /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
+ ldr r2, =CFG_MCATT0_VAL
+ str r2, [r1, #MCATT0_OFFSET]
+ ldr r2, [r1, #MCATT0_OFFSET]
+
+ /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
+ ldr r2, =CFG_MCATT1_VAL
+ str r2, [r1, #MCATT1_OFFSET]
+ ldr r2, [r1, #MCATT1_OFFSET]
+
+ /* MCIO0: Card Interface I/O Space Timing, slot 0 */
+ ldr r2, =CFG_MCIO0_VAL
+ str r2, [r1, #MCIO0_OFFSET]
+ ldr r2, [r1, #MCIO0_OFFSET]
+
+ /* MCIO1: Card Interface I/O Space Timing, slot 1 */
+ ldr r2, =CFG_MCIO1_VAL
+ str r2, [r1, #MCIO1_OFFSET]
+ ldr r2, [r1, #MCIO1_OFFSET]
+
+#ifdef DEBUG_BLINK_ENABLE
+ /* 5th blink */
+ bl blink
+#endif
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2c: Write FLYCNFG FIXME: what's that??? */
+ /* ---------------------------------------------------------------- */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
+ /* ---------------------------------------------------------------- */
+
+ /* Before accessing MDREFR we need a valid DRI field, so we set */
+ /* this to power on defaults + DRI field. */
+
+ ldr r3, =CFG_MDREFR_VAL
+ ldr r2, =0xFFF
+ and r3, r3, r2
+ ldr r4, =0x03ca4000
+ orr r4, r4, r3
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ /* Note: preserve the mdrefr value in r4 */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
+ /* ---------------------------------------------------------------- */
+
+ /* Initialize SXCNFG register. Assert the enable bits */
+
+ /* Write SXMRS to cause an MRS command to all enabled banks of */
+ /* synchronous static memory. Note that SXLCR need not be written */
+ /* at this time. */
+
+ /* FIXME: we use async mode for now */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 4: Initialize SDRAM */
+ /* ---------------------------------------------------------------- */
+
+ /* set MDREFR according to user define with exception of a few bits */
+
+ ldr r4, =CFG_MDREFR_VAL
+ orr r4, r4, #(MDREFR_SLFRSH)
+ bic r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ /* Step 4b: de-assert MDREFR:SLFRSH. */
+
+ bic r4, r4, #(MDREFR_SLFRSH)
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired */
+
+ ldr r4, =CFG_MDREFR_VAL
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+
+ /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
+ /* configure but not enable each SDRAM partition pair. */
+
+ ldr r4, =CFG_MDCNFG_VAL
+ bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
+
+ str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
+ ldr r4, [r1, #MDCNFG_OFFSET]
+
+ /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
+ /* 100..200 µsec. */
+
+ ldr r3, =OSCR /* reset the OS Timer Count to zero */
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
+ /* so 0x300 should be plenty */
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+ /* Step 4f: Trigger a number (usually 8) refresh cycles by */
+ /* attempting non-burst read or write accesses to disabled */
+ /* SDRAM, as commonly specified in the power up sequence */
+ /* documented in SDRAM data sheets. The address(es) used */
+ /* for this purpose must not be cacheable. */
+
+ ldr r3, =CFG_DRAM_BASE
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+
+ /* Step 4g: Write MDCNFG with enable bits asserted */
+ /* (MDCNFG:DEx set to 1). */
+
+ ldr r3, [r1, #MDCNFG_OFFSET]
+ orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
+ str r3, [r1, #MDCNFG_OFFSET]
+
+ /* Step 4h: Write MDMRS. */
+
+ ldr r2, =CFG_MDMRS_VAL
+ str r2, [r1, #MDMRS_OFFSET]
+
+ /* We are finished with Intel's memory controller initialisation */
+#if 0
+ /* FIXME turn on serial ports */
+ /* look into moving this to board_init() */
+ ldr r2, =(PXA_CS5_PHYS + 0x03C0002c)
+ mov r3, #0x13
+ str r3, [r2]
+#endif
+
+#ifdef DEBUG_BLINK_ENABLE
+ /* 6th blink */
+ bl blink
+#endif
+
+ /* ---------------------------------------------------------------- */
+ /* Disable (mask) all interrupts at interrupt controller */
+ /* ---------------------------------------------------------------- */
+
+initirqs:
+
+ mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
+ ldr r2, =ICLR
+ str r1, [r2]
+
+ ldr r2, =ICMR /* mask all interrupts at the controller */
+ str r1, [r2]
+
+ /* ---------------------------------------------------------------- */
+ /* Clock initialisation */
+ /* ---------------------------------------------------------------- */
+
+initclks:
+
+ /* Disable the peripheral clocks, and set the core clock frequency */
+ /* (hard-coding at 398.12MHz for now). */
+
+ /* Turn Off ALL on-chip peripheral clocks for re-configuration */
+ /* Note: See label 'ENABLECLKS' for the re-enabling */
+#if 0
+ ldr r1, =CKEN
+ mov r2, #0
+ str r2, [r1]
+
+ /* default value in case no valid rotary switch setting is found */
+ ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
+
+ /* ... and write the core clock config register */
+ ldr r1, =CCCR
+ str r2, [r1]
+
+#endif
+
+#ifdef RTC
+ /* enable the 32Khz oscillator for RTC and PowerManager */
+
+ ldr r1, =OSCC
+ mov r2, #OSCC_OON
+ str r2, [r1]
+
+ /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
+ /* has settled. */
+60:
+ ldr r2, [r1]
+ ands r2, r2, #1
+ beq 60b
+#endif
+
+ /* ---------------------------------------------------------------- */
+ /* */
+ /* ---------------------------------------------------------------- */
+
+ /* Save SDRAM size */
+ ldr r1, =DRAM_SIZE
+ str r8, [r1]
+
+ /* Interrupt init: Mask all interrupts */
+ ldr r0, =ICMR /* enable no sources */
+ mov r1, #0
+ str r1, [r0]
+
+ /* FIXME */
+
+#define NODEBUG
+#ifdef NODEBUG
+ /*Disable software and data breakpoints */
+ mov r0,#0
+ mcr p15,0,r0,c14,c8,0 /* ibcr0 */
+ mcr p15,0,r0,c14,c9,0 /* ibcr1 */
+ mcr p15,0,r0,c14,c4,0 /* dbcon */
+
+ /*Enable all debug functionality */
+ mov r0,#0x80000000
+ mcr p14,0,r0,c10,c0,0 /* dcsr */
+#endif
+
+ /* ---------------------------------------------------------------- */
+ /* End memsetup */
+ /* ---------------------------------------------------------------- */
+
+#ifdef DEBUG_BLINK_ENABLE
+ /* 7th blink */
+ bl blink
+#endif
+
+endmemsetup:
+
+ mov pc, r10
+
+
+#ifdef DEBUG_BLINK_ENABLE
+
+/* debug LED code */
+
+/* delay about 200ms */
+delay:
+
+ /* reset OSCR to 0 */
+ ldr r8, =OSCR
+ mov r9, #0
+ str r9, [r8]
+
+ /* make sure new value has stuck */
+1:
+ ldr r8, =OSCR
+ ldr r9, [r8]
+ mov r8, #0x10000
+ cmp r9, r8
+ bgt 1b
+
+ /* now, wait for delay to expire */
+1:
+ ldr r8, =OSCR
+ ldr r9, [r8]
+ mov r8, #0xd4000
+ cmp r8, r9
+ bgt 1b
+
+ mov pc, lr
+
+/* blink code -- trashes r7, r8, r9 */
+
+.globl blink
+blink:
+
+ mov r7, lr
+
+ /* set GPIO10 as outout */
+ ldr r8, =GPDR0
+ ldr r9, [r8]
+ orr r9, r9, #(1<<10)
+ str r9, [r8]
+
+ /* turn LED off */
+ mov r9, #(1<<10)
+ ldr r8, =GPCR0
+ str r9, [r8]
+ bl delay
+
+ /* turn LED on */
+ mov r9, #(1<<10)
+ ldr r8, =GPSR0
+ str r9, [r8]
+ bl delay
+
+ /* turn LED off */
+ mov r9, #(1<<10)
+ ldr r8, =GPCR0
+ str r9, [r8]
+
+ mov pc, r7
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2004
+ * BEC Systems <http://bec-systems.com>
+ * Cliff Brake <cliff.brake@gmail.com>
+ * Support for Accelent/Vibren PXA255 IDP
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ /* memory and cpu-speed are setup before relocation */
+ /* so we do _nothing_ here */
+
+ /* arch number of Lubbock-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_PXA_IDP;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ /* turn on serial ports */
+ *(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C0002c) = 0x13;
+
+ /* set PWM for LCD */
+ /* a value that works is 60Hz, 77% duty cycle */
+ CKEN |= CKEN0_PWM0;
+ PWM_CTRL0 = 0x3f;
+ PWM_PERVAL0 = 0x3ff;
+ PWM_PWDUTY0 = 792;
+
+ /* clear reset to AC97 codec */
+ CKEN |= CKEN2_AC97;
+ GCR = GCR_COLD_RST;
+
+ /* enable LCD backlight */
+ /* *(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C00030) = 0x7; */
+
+ /* test display */
+ /* lcd_puts("This is a test\nTest #2\n"); */
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ setenv("stdout", "serial");
+ setenv("stderr", "serial");
+ return 0;
+}
+
+
+int dram_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+ gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+ gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+ gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+ gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+
+ return 0;
+}
+
+
+#ifdef DEBUG_BLINKC_ENABLE
+
+void delay_c(void)
+{
+ /* reset OSCR to 0 */
+ OSCR = 0;
+ while(OSCR > 0x10000)
+ ;
+
+ while(OSCR < 0xd4000)
+ ;
+}
+
+void blink_c(void)
+{
+ int led_bit = (1<<10);
+
+ GPDR0 = led_bit;
+ GPCR0 = led_bit;
+ delay_c();
+ GPSR0 = led_bit;
+ delay_c();
+ GPCR0 = led_bit;
+}
+
+int do_idpcmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ printf("IDPCMD started\n");
+ return 0;
+}
+
+U_BOOT_CMD(idpcmd, CFG_MAXARGS, 0, do_idpcmd,
+ "idpcmd - custom IDP command\n",
+ "no args at this time\n"
+);
+
+#endif
--- /dev/null
+gafr0_l: 0x80001005
+gafr0_u: 0xa5128012
+gafr1_l: 0x699a9558
+gafr1_u: 0xaaa5aa6a
+gafr2_l: 0xaaaaaaaa
+gafr2_u: 0x2
+gpcr0: 0x1800400
+gpcr1: 0x0
+gpcr2: 0x0
+gpdr0: 0xc1818440
+gpdr1: 0xfcffab82
+gpdr2: 0x1ffff
+gpsr0: 0x8000
+gpsr1: 0x3f0002
+gpsr2: 0x1c000
+
+
+#define CFG_GAFR0_L_VAL 0x80001005
+#define CFG_GAFR0_U_VAL 0xa5128012
+#define CFG_GAFR1_L_VAL 0x699a9558
+#define CFG_GAFR1_U_VAL 0xaaa5aa6a
+#define CFG_GAFR2_L_VAL 0xaaaaaaaa
+#define CFG_GAFR2_U_VAL 0x2
+#define CFG_GPCR0_VAL 0x1800400
+#define CFG_GPCR1_VAL 0x0
+#define CFG_GPCR2_VAL 0x0
+#define CFG_GPDR0_VAL 0xc1818440
+#define CFG_GPDR1_VAL 0xfcffab82
+#define CFG_GPDR2_VAL 0x1ffff
+#define CFG_GPSR0_VAL 0x8000
+#define CFG_GPSR1_VAL 0x3f0002
+#define CFG_GPSR2_VAL 0x1c000
+
+
+GPIO: 0, dir=0, set=0, clr=0, alt=none, desc=USER_RESET#
+GPIO: 1, dir=0, set=0, clr=0, alt=gpio reset, desc=USER_RESET#
+GPIO: 2, dir=0, set=0, clr=0, alt=gpio, desc=BAT_DATA
+GPIO: 3, dir=0, set=0, clr=0, alt=gpio, desc=MQ_IRQ#
+GPIO: 4, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_ETH
+GPIO: 5, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_TOUCH#
+GPIO: 6, dir=1, set=0, clr=0, alt=MMC clk, desc=MMC_CLK
+GPIO: 7, dir=0, set=0, clr=0, alt=gpio, desc=PCC_S0_CD#
+GPIO: 8, dir=0, set=0, clr=0, alt=gpio, desc=PCC_S1_CD#
+GPIO: 9, dir=0, set=0, clr=0, alt=gpio, desc=MMC_CD#
+GPIO: 10, dir=1, set=0, clr=1, alt=gpio, desc=GPIO_10/RTC_CLK/debug LED
+GPIO: 11, dir=0, set=0, clr=0, alt=gpio, desc=3M6_CLK
+GPIO: 12, dir=0, set=0, clr=0, alt=gpio, desc=GPIO_12/32K_CLK
+GPIO: 13, dir=0, set=0, clr=0, alt=gpio, desc=MBGNT
+GPIO: 14, dir=0, set=0, clr=0, alt=gpio, desc=MBREQ
+GPIO: 15, dir=1, set=1, clr=0, alt=nCS_1, desc=CS1#
+GPIO: 16, dir=1, set=0, clr=0, alt=PWM0, desc=PWM0
+GPIO: 17, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_AXB
+GPIO: 18, dir=0, set=0, clr=0, alt=RDY, desc=RDY
+GPIO: 19, dir=0, set=0, clr=0, alt=gpio, desc=XB_DREQ1, PCC_SO_IRQ_O#
+GPIO: 20, dir=0, set=0, clr=0, alt=gpio, desc=XB_DREQ0
+GPIO: 21, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_IDE, PFI
+GPIO: 22, dir=0, set=0, clr=0, alt=gpio, desc=Consumer IR, PCC_S1_IRQ_O#
+GPIO: 23, dir=1, set=0, clr=1, alt=SSP SCLK, desc=SSP_SCLK
+GPIO: 24, dir=1, set=0, clr=1, alt=SSP SFRM, desc=SSP_SFRM
+GPIO: 25, dir=0, set=0, clr=0, alt=gpio, desc=SSP_TXD
+GPIO: 26, dir=0, set=0, clr=0, alt=SSP RXD, desc=SSP_RXD
+GPIO: 27, dir=0, set=0, clr=0, alt=gpio, desc=SSP_EXTCLK
+GPIO: 28, dir=0, set=0, clr=0, alt=AC97 bitclk in, I2S bitclock out, desc=AC_BITCLK
+GPIO: 29, dir=0, set=0, clr=0, alt=AC97 SDATA_IN0, desc=AUD_SDIN0
+GPIO: 30, dir=1, set=0, clr=0, alt=AC97 SDATA_OUT, desc=AC_SDOUT
+GPIO: 31, dir=1, set=0, clr=0, alt=AC97 SYNC, desc=AC_SYNC
+GPIO: 32, dir=0, set=0, clr=0, alt=gpio, desc=AUD_SDIN1
+GPIO: 33, dir=1, set=1, clr=0, alt=nCS_5, desc=CS5#
+GPIO: 34, dir=0, set=0, clr=0, alt=FF RXD, desc=FF_RXD
+GPIO: 35, dir=0, set=0, clr=0, alt=FF CTS, desc=FF_CTS
+GPIO: 36, dir=0, set=0, clr=0, alt=FF DCD, desc=FF_DCD
+GPIO: 37, dir=0, set=0, clr=0, alt=FF DSR, desc=FF_DSR
+GPIO: 38, dir=0, set=0, clr=0, alt=FF RI, desc=FF_RI
+GPIO: 39, dir=1, set=0, clr=0, alt=FF TXD, desc=FF_TXD
+GPIO: 40, dir=1, set=0, clr=0, alt=FF DTR, desc=FF_DTR
+GPIO: 41, dir=1, set=0, clr=0, alt=FF RTS, desc=FF_RTS
+GPIO: 42, dir=0, set=0, clr=0, alt=BT RXD, desc=BT_RXD
+GPIO: 43, dir=1, set=0, clr=0, alt=BT TXD, desc=BT_TXD
+GPIO: 44, dir=0, set=0, clr=0, alt=BT CTS, desc=BT_CTS
+GPIO: 45, dir=1, set=0, clr=0, alt=BT RTS, desc=BT_RTS
+GPIO: 46, dir=0, set=0, clr=0, alt=STD RXD, desc=IR_RXD
+GPIO: 47, dir=1, set=0, clr=0, alt=STD TXD, desc=IR_TXD
+GPIO: 48, dir=1, set=1, clr=0, alt=nPOE, desc=PCC_OE#
+GPIO: 49, dir=1, set=1, clr=0, alt=nPWE, desc=PCC_WE#
+GPIO: 50, dir=1, set=1, clr=0, alt=nPIOR, desc=PCC_IOR#
+GPIO: 51, dir=1, set=1, clr=0, alt=nPIOW, desc=PCC_IOW#
+GPIO: 52, dir=1, set=1, clr=0, alt=nPCE[1], desc=PCC_CE1#
+GPIO: 53, dir=1, set=1, clr=0, alt=nPCE[2], desc=PCC_CE2#
+GPIO: 54, dir=1, set=0, clr=0, alt=nPSKSEL, desc=PCC_SCKSEL
+GPIO: 55, dir=1, set=0, clr=0, alt=nPREG, desc=PCC_REG#
+GPIO: 56, dir=0, set=0, clr=0, alt=nPWAIT, desc=PCC_WAIT#
+GPIO: 57, dir=0, set=0, clr=0, alt=nIOIS16, desc=PCC_IOIS16#
+GPIO: 58, dir=1, set=0, clr=0, alt=LDD[0], desc=LDD0
+GPIO: 59, dir=1, set=0, clr=0, alt=LDD[1], desc=LDD1
+GPIO: 60, dir=1, set=0, clr=0, alt=LDD[2], desc=LDD2
+GPIO: 61, dir=1, set=0, clr=0, alt=LDD[3], desc=LDD3
+GPIO: 62, dir=1, set=0, clr=0, alt=LDD[4], desc=LDD4
+GPIO: 63, dir=1, set=0, clr=0, alt=LDD[5], desc=LDD5
+GPIO: 64, dir=1, set=0, clr=0, alt=LDD[6], desc=LDD6
+GPIO: 65, dir=1, set=0, clr=0, alt=LDD[7], desc=LDD7
+GPIO: 66, dir=1, set=0, clr=0, alt=LDD[8], desc=LDD8
+GPIO: 67, dir=1, set=0, clr=0, alt=LDD[9], desc=LDD9
+GPIO: 68, dir=1, set=0, clr=0, alt=LDD[10], desc=LDD10
+GPIO: 69, dir=1, set=0, clr=0, alt=LDD[11], desc=LDD11
+GPIO: 70, dir=1, set=0, clr=0, alt=LDD[12], desc=LDD12
+GPIO: 71, dir=1, set=0, clr=0, alt=LDD[13], desc=LDD13
+GPIO: 72, dir=1, set=0, clr=0, alt=LDD[14], desc=LDD14
+GPIO: 73, dir=1, set=0, clr=0, alt=LDD[15], desc=LDD15
+GPIO: 74, dir=1, set=0, clr=0, alt=LCD_FCLK, desc=FCLK
+GPIO: 75, dir=1, set=0, clr=0, alt=LCD_LCLK, desc=LCLK
+GPIO: 76, dir=1, set=0, clr=0, alt=LCD_PCLK, desc=PCLK
+GPIO: 77, dir=1, set=0, clr=0, alt=LCD_ACBIAS, desc=ACBIAS
+GPIO: 78, dir=1, set=1, clr=0, alt=nCS_2, desc=CS2#
+GPIO: 79, dir=1, set=1, clr=0, alt=nCS_3, desc=CS3#
+GPIO: 80, dir=1, set=1, clr=0, alt=nCS_4, desc=CS4#
+GPIO: 81, dir=0, set=0, clr=0, alt=gpio, desc=
+GPIO: 82, dir=0, set=0, clr=0, alt=gpio, desc=
+GPIO: 83, dir=0, set=0, clr=0, alt=gpio, desc=
+GPIO: 84, dir=0, set=0, clr=0, alt=gpio, desc=
--- /dev/null
+#!/usr/bin/python
+
+# (C) Copyright 2004
+# BEC Systems <http://bec-systems.com>
+# Cliff Brake <cliff.brake@gmail.com>
+
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+# calculations for PXA255 registers
+
+class gpio:
+ dir = '0'
+ set = '0'
+ clr = '0'
+ alt = '0'
+ desc = ''
+
+ def __init__(self, dir=0, set=0, clr=0, alt=0, desc=''):
+ self.dir = dir
+ self.set = set
+ self.clr = clr
+ self.alt = alt
+ self.desc = desc
+
+
+# the following is a dictionary of all GPIOs in the system
+# the key is the GPIO number
+
+
+pxa255_alt_func = {
+ 0: ['gpio', 'none', 'none', 'none'],
+ 1: ['gpio', 'gpio reset', 'none', 'none'],
+ 2: ['gpio', 'none', 'none', 'none'],
+ 3: ['gpio', 'none', 'none', 'none'],
+ 4: ['gpio', 'none', 'none', 'none'],
+ 5: ['gpio', 'none', 'none', 'none'],
+ 6: ['gpio', 'MMC clk', 'none', 'none'],
+ 7: ['gpio', '48MHz clock', 'none', 'none'],
+ 8: ['gpio', 'MMC CS0', 'none', 'none'],
+ 9: ['gpio', 'MMC CS1', 'none', 'none'],
+ 10: ['gpio', 'RTC Clock', 'none', 'none'],
+ 11: ['gpio', '3.6MHz', 'none', 'none'],
+ 12: ['gpio', '32KHz', 'none', 'none'],
+ 13: ['gpio', 'none', 'MBGNT', 'none'],
+ 14: ['gpio', 'MBREQ', 'none', 'none'],
+ 15: ['gpio', 'none', 'nCS_1', 'none'],
+ 16: ['gpio', 'none', 'PWM0', 'none'],
+ 17: ['gpio', 'none', 'PWM1', 'none'],
+ 18: ['gpio', 'RDY', 'none', 'none'],
+ 19: ['gpio', 'DREQ[1]', 'none', 'none'],
+ 20: ['gpio', 'DREQ[0]', 'none', 'none'],
+ 21: ['gpio', 'none', 'none', 'none'],
+ 22: ['gpio', 'none', 'none', 'none'],
+ 23: ['gpio', 'none', 'SSP SCLK', 'none'],
+ 24: ['gpio', 'none', 'SSP SFRM', 'none'],
+ 25: ['gpio', 'none', 'SSP TXD', 'none'],
+ 26: ['gpio', 'SSP RXD', 'none', 'none'],
+ 27: ['gpio', 'SSP EXTCLK', 'none', 'none'],
+ 28: ['gpio', 'AC97 bitclk in, I2S bitclock out', 'I2S bitclock in', 'none'],
+ 29: ['gpio', 'AC97 SDATA_IN0', 'I2S SDATA_IN', 'none'],
+ 30: ['gpio', 'I2S SDATA_OUT', 'AC97 SDATA_OUT', 'none'],
+ 31: ['gpio', 'I2S SYNC', 'AC97 SYNC', 'none'],
+ 32: ['gpio', 'AC97 SDATA_IN1', 'I2S SYSCLK', 'none'],
+ 33: ['gpio', 'none', 'nCS_5', 'none'],
+ 34: ['gpio', 'FF RXD', 'MMC CS0', 'none'],
+ 35: ['gpio', 'FF CTS', 'none', 'none'],
+ 36: ['gpio', 'FF DCD', 'none', 'none'],
+ 37: ['gpio', 'FF DSR', 'none', 'none'],
+ 38: ['gpio', 'FF RI', 'none', 'none'],
+ 39: ['gpio', 'MMC CS1', 'FF TXD', 'none'],
+ 40: ['gpio', 'none', 'FF DTR', 'none'],
+ 41: ['gpio', 'none', 'FF RTS', 'none'],
+ 42: ['gpio', 'BT RXD', 'none', 'HW RXD'],
+ 43: ['gpio', 'none', 'BT TXD', 'HW TXD'],
+ 44: ['gpio', 'BT CTS', 'none', 'HW CTS'],
+ 45: ['gpio', 'none', 'BT RTS', 'HW RTS'],
+ 46: ['gpio', 'ICP_RXD', 'STD RXD', 'none'],
+ 47: ['gpio', 'STD TXD', 'ICP_TXD', 'none'],
+ 48: ['gpio', 'HW TXD', 'nPOE', 'none'],
+ 49: ['gpio', 'HW RXD', 'nPWE', 'none'],
+ 50: ['gpio', 'HW CTS', 'nPIOR', 'none'],
+ 51: ['gpio', 'nPIOW', 'HW RTS', 'none'],
+ 52: ['gpio', 'none', 'nPCE[1]', 'none'],
+ 53: ['gpio', 'MMC CLK', 'nPCE[2]', 'none'],
+ 54: ['gpio', 'MMC CLK', 'nPSKSEL', 'none'],
+ 55: ['gpio', 'none', 'nPREG', 'none'],
+ 56: ['gpio', 'nPWAIT', 'none', 'none'],
+ 57: ['gpio', 'nIOIS16', 'none', 'none'],
+ 58: ['gpio', 'none', 'LDD[0]', 'none'],
+ 59: ['gpio', 'none', 'LDD[1]', 'none'],
+ 60: ['gpio', 'none', 'LDD[2]', 'none'],
+ 61: ['gpio', 'none', 'LDD[3]', 'none'],
+ 62: ['gpio', 'none', 'LDD[4]', 'none'],
+ 63: ['gpio', 'none', 'LDD[5]', 'none'],
+ 64: ['gpio', 'none', 'LDD[6]', 'none'],
+ 65: ['gpio', 'none', 'LDD[7]', 'none'],
+ 66: ['gpio', 'MBREQ', 'LDD[8]', 'none'],
+ 67: ['gpio', 'MMC CS0', 'LDD[9]', 'none'],
+ 68: ['gpio', 'MMC CS1', 'LDD[10]', 'none'],
+ 69: ['gpio', 'MMC CLK', 'LDD[11]', 'none'],
+ 70: ['gpio', 'RTC CLK', 'LDD[12]', 'none'],
+ 71: ['gpio', '3.6 MHz', 'LDD[13]', 'none'],
+ 72: ['gpio', '32 KHz', 'LDD[14]', 'none'],
+ 73: ['gpio', 'MBGNT', 'LDD[15]', 'none'],
+ 74: ['gpio', 'none', 'LCD_FCLK', 'none'],
+ 75: ['gpio', 'none', 'LCD_LCLK', 'none'],
+ 76: ['gpio', 'none', 'LCD_PCLK', 'none'],
+ 77: ['gpio', 'none', 'LCD_ACBIAS', 'none'],
+ 78: ['gpio', 'none', 'nCS_2', 'none'],
+ 79: ['gpio', 'none', 'nCS_3', 'none'],
+ 80: ['gpio', 'none', 'nCS_4', 'none'],
+ 81: ['gpio', 'NSSPSCLK', 'none', 'none'],
+ 82: ['gpio', 'NSSPSFRM', 'none', 'none'],
+ 83: ['gpio', 'NSSPTXD', 'NSSPRXD', 'none'],
+ 84: ['gpio', 'NSSPTXD', 'NSSPRXD', 'none'],
+}
+
+
+#def __init__(self, dir=0, set=0, clr=0, alt=0, desc=''):
+
+gpio_list = []
+
+for i in range(0,85):
+ gpio_list.append(gpio())
+
+#chip select GPIOs
+gpio_list[18] = gpio(0, 0, 0, 1, 'RDY')
+gpio_list[33] = gpio(1, 1, 0, 2, 'CS5#')
+gpio_list[80] = gpio(1, 1, 0, 2, 'CS4#')
+gpio_list[79] = gpio(1, 1, 0, 2, 'CS3#')
+gpio_list[78] = gpio(1, 1, 0, 2, 'CS2#')
+gpio_list[15] = gpio(1, 1, 0, 2, 'CS1#')
+gpio_list[22] = gpio(0, 0, 0, 0, 'Consumer IR, PCC_S1_IRQ_O#')
+gpio_list[21] = gpio(0, 0, 0, 0, 'IRQ_IDE, PFI')
+gpio_list[19] = gpio(0, 0, 0, 0, 'XB_DREQ1, PCC_SO_IRQ_O#')
+gpio_list[20] = gpio(0, 0, 0, 0, 'XB_DREQ0')
+gpio_list[20] = gpio(0, 0, 0, 0, 'XB_DREQ0')
+gpio_list[17] = gpio(0, 0, 0, 0, 'IRQ_AXB')
+gpio_list[16] = gpio(1, 0, 0, 2, 'PWM0')
+
+# PCMCIA stuff
+gpio_list[57] = gpio(0, 0, 0, 1, 'PCC_IOIS16#')
+gpio_list[56] = gpio(0, 0, 0, 1, 'PCC_WAIT#')
+gpio_list[55] = gpio(1, 0, 0, 2, 'PCC_REG#')
+gpio_list[54] = gpio(1, 0, 0, 2, 'PCC_SCKSEL')
+gpio_list[53] = gpio(1, 1, 0, 2, 'PCC_CE2#')
+gpio_list[52] = gpio(1, 1, 0, 2, 'PCC_CE1#')
+gpio_list[51] = gpio(1, 1, 0, 1, 'PCC_IOW#')
+gpio_list[50] = gpio(1, 1, 0, 2, 'PCC_IOR#')
+gpio_list[49] = gpio(1, 1, 0, 2, 'PCC_WE#')
+gpio_list[48] = gpio(1, 1, 0, 2, 'PCC_OE#')
+
+# SSP port
+gpio_list[26] = gpio(0, 0, 0, 1, 'SSP_RXD')
+gpio_list[25] = gpio(0, 0, 0, 0, 'SSP_TXD')
+gpio_list[24] = gpio(1, 0, 1, 2, 'SSP_SFRM')
+gpio_list[23] = gpio(1, 0, 1, 2, 'SSP_SCLK')
+gpio_list[27] = gpio(0, 0, 0, 0, 'SSP_EXTCLK')
+
+# audio codec
+gpio_list[32] = gpio(0, 0, 0, 0, 'AUD_SDIN1')
+gpio_list[31] = gpio(1, 0, 0, 2, 'AC_SYNC')
+gpio_list[30] = gpio(1, 0, 0, 2, 'AC_SDOUT')
+gpio_list[29] = gpio(0, 0, 0, 1, 'AUD_SDIN0')
+gpio_list[28] = gpio(0, 0, 0, 1, 'AC_BITCLK')
+
+# serial ports
+gpio_list[39] = gpio(1, 0, 0, 2, 'FF_TXD')
+gpio_list[34] = gpio(0, 0, 0, 1, 'FF_RXD')
+gpio_list[41] = gpio(1, 0, 0, 2, 'FF_RTS')
+gpio_list[35] = gpio(0, 0, 0, 1, 'FF_CTS')
+gpio_list[40] = gpio(1, 0, 0, 2, 'FF_DTR')
+gpio_list[37] = gpio(0, 0, 0, 1, 'FF_DSR')
+gpio_list[38] = gpio(0, 0, 0, 1, 'FF_RI')
+gpio_list[36] = gpio(0, 0, 0, 1, 'FF_DCD')
+
+gpio_list[43] = gpio(1, 0, 0, 2, 'BT_TXD')
+gpio_list[42] = gpio(0, 0, 0, 1, 'BT_RXD')
+gpio_list[45] = gpio(1, 0, 0, 2, 'BT_RTS')
+gpio_list[44] = gpio(0, 0, 0, 1, 'BT_CTS')
+
+gpio_list[47] = gpio(1, 0, 0, 1, 'IR_TXD')
+gpio_list[46] = gpio(0, 0, 0, 2, 'IR_RXD')
+
+# misc GPIO signals
+gpio_list[14] = gpio(0, 0, 0, 0, 'MBREQ')
+gpio_list[13] = gpio(0, 0, 0, 0, 'MBGNT')
+gpio_list[12] = gpio(0, 0, 0, 0, 'GPIO_12/32K_CLK')
+gpio_list[11] = gpio(0, 0, 0, 0, '3M6_CLK')
+gpio_list[10] = gpio(1, 0, 1, 0, 'GPIO_10/RTC_CLK/debug LED')
+gpio_list[9] = gpio(0, 0, 0, 0, 'MMC_CD#')
+gpio_list[8] = gpio(0, 0, 0, 0, 'PCC_S1_CD#')
+gpio_list[7] = gpio(0, 0, 0, 0, 'PCC_S0_CD#')
+gpio_list[6] = gpio(1, 0, 0, 1, 'MMC_CLK')
+gpio_list[5] = gpio(0, 0, 0, 0, 'IRQ_TOUCH#')
+gpio_list[4] = gpio(0, 0, 0, 0, 'IRQ_ETH')
+gpio_list[3] = gpio(0, 0, 0, 0, 'MQ_IRQ#')
+gpio_list[2] = gpio(0, 0, 0, 0, 'BAT_DATA')
+gpio_list[1] = gpio(0, 0, 0, 1, 'USER_RESET#')
+gpio_list[0] = gpio(0, 0, 0, 1, 'USER_RESET#')
+
+# LCD GPIOs
+gpio_list[58] = gpio(1, 0, 0, 2, 'LDD0')
+gpio_list[59] = gpio(1, 0, 0, 2, 'LDD1')
+gpio_list[60] = gpio(1, 0, 0, 2, 'LDD2')
+gpio_list[61] = gpio(1, 0, 0, 2, 'LDD3')
+gpio_list[62] = gpio(1, 0, 0, 2, 'LDD4')
+gpio_list[63] = gpio(1, 0, 0, 2, 'LDD5')
+gpio_list[64] = gpio(1, 0, 0, 2, 'LDD6')
+gpio_list[65] = gpio(1, 0, 0, 2, 'LDD7')
+gpio_list[66] = gpio(1, 0, 0, 2, 'LDD8')
+gpio_list[67] = gpio(1, 0, 0, 2, 'LDD9')
+gpio_list[68] = gpio(1, 0, 0, 2, 'LDD10')
+gpio_list[69] = gpio(1, 0, 0, 2, 'LDD11')
+gpio_list[70] = gpio(1, 0, 0, 2, 'LDD12')
+gpio_list[71] = gpio(1, 0, 0, 2, 'LDD13')
+gpio_list[72] = gpio(1, 0, 0, 2, 'LDD14')
+gpio_list[73] = gpio(1, 0, 0, 2, 'LDD15')
+gpio_list[74] = gpio(1, 0, 0, 2, 'FCLK')
+gpio_list[75] = gpio(1, 0, 0, 2, 'LCLK')
+gpio_list[76] = gpio(1, 0, 0, 2, 'PCLK')
+gpio_list[77] = gpio(1, 0, 0, 2, 'ACBIAS')
+
+# calculate registers
+pxa_regs = {
+ 'gpdr0':0, 'gpdr1':0, 'gpdr2':0,
+ 'gpsr0':0, 'gpsr1':0, 'gpsr2':0,
+ 'gpcr0':0, 'gpcr1':0, 'gpcr2':0,
+ 'gafr0_l':0, 'gafr0_u':0,
+ 'gafr1_l':0, 'gafr1_u':0,
+ 'gafr2_l':0, 'gafr2_u':0,
+}
+
+# U-boot define names
+uboot_reg_names = {
+ 'gpdr0':'CFG_GPDR0_VAL', 'gpdr1':'CFG_GPDR1_VAL', 'gpdr2':'CFG_GPDR2_VAL',
+ 'gpsr0':'CFG_GPSR0_VAL', 'gpsr1':'CFG_GPSR1_VAL', 'gpsr2':'CFG_GPSR2_VAL',
+ 'gpcr0':'CFG_GPCR0_VAL', 'gpcr1':'CFG_GPCR1_VAL', 'gpcr2':'CFG_GPCR2_VAL',
+ 'gafr0_l':'CFG_GAFR0_L_VAL', 'gafr0_u':'CFG_GAFR0_U_VAL',
+ 'gafr1_l':'CFG_GAFR1_L_VAL', 'gafr1_u':'CFG_GAFR1_U_VAL',
+ 'gafr2_l':'CFG_GAFR2_L_VAL', 'gafr2_u':'CFG_GAFR2_U_VAL',
+}
+
+# bit mappings
+
+bit_mappings = [
+
+{ 'gpio':(0,32), 'shift':1, 'regs':{'dir':'gpdr0', 'set':'gpsr0', 'clr':'gpcr0'} },
+{ 'gpio':(32,64), 'shift':1, 'regs':{'dir':'gpdr1', 'set':'gpsr1', 'clr':'gpcr1'} },
+{ 'gpio':(64,85), 'shift':1, 'regs':{'dir':'gpdr2', 'set':'gpsr2', 'clr':'gpcr2'} },
+{ 'gpio':(0,16), 'shift':2, 'regs':{'alt':'gafr0_l'} },
+{ 'gpio':(16,32), 'shift':2, 'regs':{'alt':'gafr0_u'} },
+{ 'gpio':(32,48), 'shift':2, 'regs':{'alt':'gafr1_l'} },
+{ 'gpio':(48,64), 'shift':2, 'regs':{'alt':'gafr1_u'} },
+{ 'gpio':(64,80), 'shift':2, 'regs':{'alt':'gafr2_l'} },
+{ 'gpio':(80,85), 'shift':2, 'regs':{'alt':'gafr2_u'} },
+
+]
+
+def stuff_bits(bit_mapping, gpio_list):
+ gpios = range( bit_mapping['gpio'][0], bit_mapping['gpio'][1])
+
+ for gpio in gpios:
+ for reg in bit_mapping['regs'].keys():
+ value = eval( 'gpio_list[gpio].%s' % (reg) )
+ if ( value ):
+ # we have a high bit
+ bit_shift = (gpio - bit_mapping['gpio'][0]) * bit_mapping['shift']
+ bit = value << (bit_shift)
+ pxa_regs[bit_mapping['regs'][reg]] |= bit
+
+for i in bit_mappings:
+ stuff_bits(i, gpio_list)
+
+# now print out all regs
+registers = pxa_regs.keys()
+registers.sort()
+for reg in registers:
+ print '%s: 0x%x' % (reg, pxa_regs[reg])
+
+# print define to past right into U-Boot source code
+
+print
+print
+
+for reg in registers:
+ print '#define %s 0x%x' % (uboot_reg_names[reg], pxa_regs[reg])
+
+# print all GPIOS
+print
+print
+
+for i in range(len(gpio_list)):
+ gpio_i = gpio_list[i]
+ alt_func_desc = pxa255_alt_func[i][gpio_i.alt]
+ print 'GPIO: %i, dir=%i, set=%i, clr=%i, alt=%s, desc=%s' % (i, gpio_i.dir, gpio_i.set, gpio_i.clr, alt_func_desc, gpio_i.desc)
+
+
--- /dev/null
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/pxa/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
int checkboard (void)
{
- unsigned char *s = getenv ("serial#");
+ char *s = getenv ("serial#");
puts ("Board QUANTUM, Serial No: ");
/* Check Bank 0 Memory Size,
* 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE_PRELIM,
+ size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
SDRAM_MAX_SIZE);
/*
* Final mapping:
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile long int *addr;
+ volatile ulong *addr;
ulong cnt, val, size;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
*
* try 8 column mode
*/
- size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE2_PRELIM,
+ size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
udelay (1000);
/*
* try 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE2_PRELIM,
+ size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
int misc_init_r (void)
{
- uchar kbd_data[KEYBD_DATALEN];
- uchar keybd_env[2 * KEYBD_DATALEN + 1];
- uchar *str;
+ char kbd_data[KEYBD_DATALEN];
+ char keybd_env[2 * KEYBD_DATALEN + 1];
+ char *str;
int i;
i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
- i2c_read (CFG_I2C_KEY_ADDR, 0, 0, kbd_data, KEYBD_DATALEN);
+ i2c_read (CFG_I2C_KEY_ADDR, 0, 0, (uchar *)kbd_data, KEYBD_DATALEN);
for (i = 0; i < KEYBD_DATALEN; ++i) {
sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
}
setenv ("keybd", keybd_env);
- str = strdup (key_match (keybd_env)); /* decode keys */
+ str = strdup ((char *)key_match ((uchar *)keybd_env)); /* decode keys */
#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */
setenv ("preboot", str); /* set or delete definition */
* "key_magic" is checked (old behaviour); the string "125" causes
* checks for "key_magic1", "key_magic2" and "key_magic5", etc.
*/
- if ((kbd_magic_keys = getenv ("magic_keys")) != NULL) {
+ if ((kbd_magic_keys = (uchar *)getenv ("magic_keys")) != NULL) {
/* loop over all magic keys;
* use '\0' suffix in case of empty string
*/
for (suffix = kbd_magic_keys;
*suffix || suffix == kbd_magic_keys;
++suffix) {
- sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
+ sprintf ((char *)magic, "%s%c", kbd_magic_prefix, *suffix);
#if 0
printf ("### Check magic \"%s\"\n", magic);
#endif
- if ((str = getenv (magic)) != 0) {
+ if ((str = (uchar *)getenv ((char *)magic)) != 0) {
#if 0
printf ("### Compare \"%s\" \"%s\"\n",
kbd_str, str);
#endif
- if (strcmp (kbd_str, str) == 0) {
- sprintf (cmd_name, "%s%c",
+ if (strcmp ((char *)kbd_str, (char *)str) == 0) {
+ sprintf ((char *)cmd_name, "%s%c",
kbd_command_prefix,
*suffix);
- if ((cmd = getenv (cmd_name)) != 0) {
+ if ((cmd = getenv ((char *)cmd_name)) != 0) {
#if 0
printf ("### Set PREBOOT to $(%s): \"%s\"\n",
cmd_name, cmd);
#endif
- return (cmd);
+ return ((uchar *)cmd);
}
}
}
puts ("Keys:");
for (i = 0; i < KEYBD_DATALEN; ++i) {
- sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
+ sprintf ((char *)(keybd_env + i + i), "%02X", kbd_data[i]);
printf (" %02x", kbd_data[i]);
}
putc ('\n');
- setenv ("keybd", keybd_env);
+ setenv ("keybd", (char *)keybd_env);
return 0;
}
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
#endif
switch (value)
{
- case 0x01:
- case AMD_MANUFACT:
+ case 0x01: /*AMD_MANUFACT*/
info->flash_id = FLASH_MAN_AMD;
break;
- case FUJ_MANUFACT:
+ case 0x04: /*FUJ_MANUFACT*/
info->flash_id = FLASH_MAN_FUJ;
break;
int checkboard (void)
{
- unsigned char *s = getenv ("serial#");
+ char *s = getenv ("serial#");
if (!s || strncmp (s, "TQM8", 4)) {
printf ("### No HW ID - assuming RBC823\n");
*
* try 8 column mode
*/
- size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE4_PRELIM,
+ size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE4_PRELIM,
SDRAM_MAX_SIZE);
udelay (1000);
/*
* try 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE4_PRELIM,
+ size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE4_PRELIM,
SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
* 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE_PRELIM,
+ size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
SDRAM_MAX_SIZE);
/*
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*/
uchar i2c_reg_read1(uchar i2c_addr, uchar reg)
{
- char buf;
+ uchar buf;
- i2c_read1(i2c_addr, reg, 1, &buf, 1);
+ i2c_read1(i2c_addr, reg, 1, &buf, (uchar)1);
return(buf);
}
sys_info_t sysinfo;
unsigned char brd_rev, brd_id;
unsigned short sernum;
- unsigned char scan_rev, scan_id, ofem_rev, ofem_id;
+ unsigned char scan_rev, scan_id, ofem_rev=0, ofem_id=0;
unsigned char ofem_brd_rev, ofem_brd_id;
KAREF_FPGA_REGS_ST *karef_ps;
OFEM_FPGA_REGS_ST *ofem_ps;
printf("OFEM Board Rev:\t0x%02X\tID: 0x%02X\n", ofem_brd_id, ofem_brd_rev);
}
- printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
- printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
- printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
- printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
- printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
-
/* Fix the ack in the bme 32 */
udelay(5000);
out32(CFG_BME32_BASE + 0x0000000C, 0x00000001);
char envstr[255];
KAREF_FPGA_REGS_ST *karef_ps;
OFEM_FPGA_REGS_ST *ofem_ps;
- unsigned char ofem_id;
if(NULL != getenv("secondserial")) {
puts("secondserial is set, switching to second serial port\n");
volatile unsigned long brdout_enable_ul; /* Read/Write */
volatile unsigned long brdin_data_ul; /* Read Only */
volatile unsigned long misc_ul; /* Read/Write */
-} KAREF_FPGA_REGS_ST __attribute__((packed)), * KAREF_FPGA_REGS_PST;
+} __attribute__((packed)) KAREF_FPGA_REGS_ST , * KAREF_FPGA_REGS_PST;
/* OFEM FPGA */
typedef struct ofem_fpga_regs_s
volatile unsigned long scrmask_ul; /* Read/Write */
volatile unsigned long control_ul; /* Read/Write */
volatile unsigned long mac_flow_ctrl_ul; /* Read/Write */
-} OFEM_FPGA_REGS_ST __attribute__((packed)), * OFEM_FPGA_REGS_PST;
+} __attribute__((packed)) OFEM_FPGA_REGS_ST , * OFEM_FPGA_REGS_PST;
#endif /* __KAREF_H__ */
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/440gx_enet.o (.text)
+ cpu/ppc4xx/4xx_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/440gx_enet.o (.text)
+ cpu/ppc4xx/4xx_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
printf ("OptoFPGA ID:\t0x%02X\tRev: 0x%02X\n", opto_id, opto_rev);
printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, board_id_as[brd_id]);
- printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
- printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
- printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
- printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
- printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
-
-
/* Fix the ack in the bme 32 */
udelay(5000);
out32(CFG_BME32_BASE + 0x0000000C, 0x00000001);
volatile unsigned long scrmask_ul; /* Read/Write */
volatile unsigned long control_ul; /* Read/Write */
volatile unsigned long boardinfo_ul; /* Read Only */
-} OPTO_FPGA_REGS_ST __attribute__ ((packed)), *OPTO_FPGA_REGS_PST;
+} __attribute__ ((packed)) OPTO_FPGA_REGS_ST , *OPTO_FPGA_REGS_PST;
#endif /* __METROBOX_H__ */
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/440gx_enet.o (.text)
+ cpu/ppc4xx/4xx_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/440gx_enet.o (.text)
+ cpu/ppc4xx/4xx_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
puts ("Board: ");
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
+ cpu/ppc4xx/4xx_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
udelay(1000);
#endif
#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
- miiphy_reset(0x0); /* reset PHY */
- miiphy_write(0, PHY_MIPSCR, 0xf028); /* change PHY address to 0x02 */
- miiphy_write(0x02, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+ /* reset PHY */
+ miiphy_reset("FCC1 ETHERNET", 0x0);
+
+ /* change PHY address to 0x02 */
+ bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
+
+ bb_miiphy_write(NULL, 0x02, PHY_BMCR,
+ PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
#endif /* CONFIG_MII */
}
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
_i386boot_bios_size = SIZEOF(.bios);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
_i386boot_bss_size = SIZEOF(.bss);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
unsigned char *s;
unsigned char buf[64];
- s = (getenv_r ("serial#", buf, sizeof(buf)) > 0) ? buf : NULL;
+ s = (getenv_r ("serial#", (char *)&buf, sizeof(buf)) > 0) ? buf : NULL;
puts ("Board: Siemens CCM");
*
* try 8 column mode
*/
- size8 = dram_size (CFG_MAMR_8COL, (ulong *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+ size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
udelay (1000);
/*
* try 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+ size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
size = size9;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
* Check Bank 0 Memory Size for re-configuration
*
*/
- size = dram_size (CFG_MAMR, (ulong *) SDRAM_BASE_PRELIM,
+ size = dram_size (CFG_MAMR, (long *) SDRAM_BASE_PRELIM,
SDRAM_MAX_SIZE);
udelay (1000);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*/
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof (str));
puts ("Board: ");
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
geben werden:
=> printenv addmtd
- addmtd=setenv bootargs $(bootargs)
+ addmtd=setenv bootargs ${bootargs}
mtdparts=0:256k(U-Boot)ro,768k(Kernel),-(Rest)\;1:-(myJFFS2)
Die Portierung auf SMC ist natuerlich noch nicht getestet.
}
}
- if (checkall && fpga_get_version(fpga, hdr.ih_name) < 0)
+ if (checkall && fpga_get_version(fpga, (char *)(hdr.ih_name)) < 0)
return 1;
/* align length */
}
hdr = (image_header_t *)addr;
- if ((new_id = fpga_get_version(fpga, hdr->ih_name)) == -1)
+ if ((new_id = fpga_get_version(fpga, (char *)(hdr->ih_name))) == -1)
return 1;
do_load = 1;
* Check Bank 0 Memory Size for re-configuration
*/
#if PCU_E_WITH_SWAPPED_CS /* XXX */
- size_b0 = dram_size (CFG_MAMR, (ulong *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE);
+ size_b0 = dram_size (CFG_MAMR, (long *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE);
#else /* XXX */
- size_b0 = dram_size (CFG_MAMR, (ulong *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+ size_b0 = dram_size (CFG_MAMR, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
#endif /* XXX */
memctl->memc_mamr = CFG_MAMR | MAMR_PTAE;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
int i;
uchar *boottype;
uchar *bootletter;
- uchar *fmt;
+ char *fmt;
uchar botbootletter[] = "B";
uchar topbootletter[] = "T";
uchar botboottype[] = "bottom boot sector";
static long ram_size(ulong *base, long maxsize)
{
volatile long *test_addr;
- volatile long *base_addr = base;
+ volatile ulong *base_addr = base;
ulong ofs; /* byte offset from base_addr */
ulong save; /* to make test non-destructive */
ulong save2; /* to make test non-destructive */
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(16);
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
int checkboard (void)
{
- unsigned char *s, *e;
- unsigned char buf[64];
+ char *s, *e;
+ char buf[64];
int i;
i = getenv_r("serial#", buf, sizeof(buf));
* Check for 32M SDRAM Memory Size
*/
size = dram_size(CFG_32M_MAMR|MAMR_PTAE,
- (ulong *)SDRAM_BASE, SDRAM_32M_MAX_SIZE);
+ (long *)SDRAM_BASE, SDRAM_32M_MAX_SIZE);
udelay (1000);
/*
*/
if (size != SDRAM_32M_MAX_SIZE) {
size = dram_size(CFG_16M_MAMR|MAMR_PTAE,
- (ulong *)SDRAM_BASE, SDRAM_16M_MAX_SIZE);
+ (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE);
udelay (1000);
}
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
int checkboard (void)
{
- unsigned char *s, *e;
- unsigned char buf[64];
+ char *s, *e;
+ char buf[64];
int i;
i = getenv_r("serial#", buf, sizeof(buf));
*/
if (size != SDRAM_64M_MAX_SIZE) {
#endif
- size = dram_size (CFG_16M_MBMR, (ulong *)SDRAM_BASE, SDRAM_16M_MAX_SIZE);
+ size = dram_size (CFG_16M_MBMR, (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE);
udelay (1000);
#if 0
}
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
* Check Bank 0 Memory Size for re-configuration
*/
size_b0 =
- dram_size (CFG_MBMR_8COL, (ulong *) SDRAM_BASE3_PRELIM,
+ dram_size (CFG_MBMR_8COL, SDRAM_BASE3_PRELIM,
SDRAM_MAX_SIZE);
memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
. = ALIGN(4);
__data_end = .;
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd :
{
udelay(1000);
#endif
#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
- miiphy_reset(0x0); /* reset PHY */
- miiphy_write(0, PHY_MIPSCR, 0xf028); /* change PHY address to 0x02 */
- miiphy_write(0x02, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+ /* reset PHY */
+ miiphy_reset("FCC1 ETHERNET", 0x0);
+
+ /* change PHY address to 0x02 */
+ bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
+
+ bb_miiphy_write(NULL, 0x02, PHY_BMCR,
+ PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
#endif /* CONFIG_MII */
#endif
}
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
LIB = lib$(BOARD).a
-OBJS = $(BOARD).o
+OBJS = $(BOARD).o oftree.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
+%.dtb: %.dts
+ dtc -f -V 0x10 -I dts -O dtb $< >$@
+
+%.c: %.dtb
+ xxd -i $< \
+ | sed -e "s/^unsigned char/const unsigned char/g" \
+ | sed -e "s/^unsigned int/const unsigned int/g" > $@
+
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
--- /dev/null
+/ {
+ model = "STXXTC V1";
+ compatible = "STXXTC";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ linux,phandle = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ PowerPC,MPC870@0 {
+ linux,phandle = <3>;
+ name = "PowerPC,MPC870";
+ device_type = "cpu";
+ reg = <0>;
+ clock-frequency = <0>; /* place-holder for runtime fillup */
+ timebase-frequency = <0>; /* dido */
+ linux,boot-cpu;
+ i-cache-size = <2000>;
+ d-cache-size = <2000>;
+ 32-bit;
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <00000000 00000000 00000000 20000000>;
+ };
+
+ /* copy of the bd_t information (place-holders) */
+ bd_t {
+ memstart = <0>;
+ memsize = <0>;
+ flashstart = <0>;
+ flashsize = <0>;
+ flashoffset = <0>;
+ sramstart = <0>;
+ sramsize = <0>;
+
+ immr_base = <0>;
+
+ bootflags = <0>;
+ ip_addr = <0>;
+ enetaddr = [ 00 00 00 00 00 00 ];
+ ethspeed = <0>;
+ intfreq = <0>;
+ busfreq = <0>;
+
+ baudrate = <0>;
+ };
+
+};
mii_init();
for (phyno = 0; phyno < 32; ++phyno) {
- miiphy_read(phyno, PHY_PHYIDR1, &v);
+ miiphy_read("FEC ETHERNET", phyno, PHY_PHYIDR1, &v);
if (v == 0xFFFF)
continue;
- miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
+ miiphy_write("FEC ETHERNET", phyno, PHY_BMCR, PHY_BMCR_POWD);
udelay(10000);
- miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
+ miiphy_write("FEC ETHERNET", phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
udelay(10000);
}
}
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
int checkboard (void)
{
- unsigned char *s = getenv("serial#");
+ char *s = getenv("serial#");
int board_type;
if (!s || strncmp(s, "SVM8", 4)) {
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
LIB = lib$(BOARD).a
OBJS := sx1.o
-SOBJS := platform.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
_TEXT_BASE:
.word TEXT_BASE /* sdram load addr from config.mk */
-.globl platformsetup
-platformsetup:
+.globl lowlevel_init
+lowlevel_init:
/*
* Configure 1510 pins functions to match our board.
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
.sdata : { *(.sdata) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
/* find RAM size using SDRAM CS0 only */
mpc5xxx_sdram_start(sdram_conf, 0);
- test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
mpc5xxx_sdram_start(sdram_conf, 1);
- test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
mpc5xxx_sdram_start(sdram_conf, 0);
dramsize = test1;
/* find RAM size using SDRAM CS1 only */
mpc5xxx_sdram_start(sdram_conf, 0);
- test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+ test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
mpc5xxx_sdram_start(sdram_conf, 1);
- test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+ test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
if (test1 > test2) {
mpc5xxx_sdram_start(sdram_conf, 0);
dramsize2 = test1;
/* find RAM size */
mpc5xxx_sdram_start(sdram_conf, 0);
- test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
mpc5xxx_sdram_start(sdram_conf, 1);
- test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
mpc5xxx_sdram_start(sdram_conf, 0);
dramsize = test1;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
LIB = lib$(BOARD).a
#OBJS := $(BOARD).o flash.o
-OBJS := $(BOARD).o
+OBJS := $(BOARD).o cmd_stk52xx.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * SKT52XX specific functions
+ */
+/*#define DEBUG*/
+
+#include <common.h>
+#include <command.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+
+#define DEFAULT_VOL 45
+#define DEFAULT_FREQ 500
+#define DEFAULT_DURATION 200
+#define LEFT 1
+#define RIGHT 2
+#define LEFT_RIGHT 3
+#define BL_OFF 0
+#define BL_ON 1
+
+#define SM501_GPIO_CTRL_LOW 0x00000008UL
+#define SM501_GPIO_CTRL_HIGH 0x0000000CUL
+#define SM501_POWER_MODE0_GATE 0x00000040UL
+#define SM501_POWER_MODE1_GATE 0x00000048UL
+#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL
+#define SM501_GPIO_DATA_LOW 0x00010000UL
+#define SM501_GPIO_DATA_HIGH 0x00010004UL
+#define SM501_GPIO_DATA_DIR_LOW 0x00010008UL
+#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL
+#define SM501_PANEL_DISPLAY_CONTROL 0x00080000UL
+
+static int i2s_squarewave(unsigned long duration, unsigned int freq,
+ unsigned int channel);
+static int i2s_sawtooth(unsigned long duration, unsigned int freq,
+ unsigned int channel);
+static void spi_init(void);
+static int spi_transmit(unsigned char data);
+static void pcm1772_write_reg(unsigned char addr, unsigned char data);
+static void set_attenuation(unsigned char attenuation);
+
+#ifdef CONFIG_STK52XX
+static void spi_init(void)
+{
+ struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI;
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+
+ /* PSC3 as SPI and GPIOs */
+ gpio->port_config &= 0xFFFFF0FF;
+ gpio->port_config |= 0x00000800;
+ /*
+ * Its important to use the correct order when initializing the
+ * registers
+ */
+ spi->ddr = 0x0F; /* set all SPI pins as output */
+ spi->pdr = 0x08; /* set SS high */
+ spi->cr1 = 0x50; /* SPI is master, SS is general purpose output */
+ spi->cr2 = 0x00; /* normal operation */
+ spi->brr = 0xFF; /* baud rate: IPB clock / 2048 */
+}
+
+static int spi_transmit(unsigned char data)
+{
+ int dummy;
+ struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI;
+
+ spi->dr = data;
+ /* wait for SPI transmission completed */
+ while(!(spi->sr & 0x80))
+ {
+ if (spi->sr & 0x40) /* if write collision occured */
+ {
+ /* do dummy read to clear status register */
+ dummy = spi->dr;
+ printf ("SPI write collision\n");
+ return -1;
+ }
+ }
+ return (spi->dr);
+}
+
+static void pcm1772_write_reg(unsigned char addr, unsigned char data)
+{
+ struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI;
+
+ spi->pdr = 0x00; /* Set SS low */
+ spi_transmit(addr);
+ spi_transmit(data);
+ /* wait some time to meet MS# hold time of PCM1772 */
+ udelay (1);
+ spi->pdr = 0x08; /* set SS high */
+}
+
+static void set_attenuation(unsigned char attenuation)
+{
+ pcm1772_write_reg(0x01, attenuation); /* left channel */
+ debug ("PCM1772 attenuation left set to %d.\n", attenuation);
+ pcm1772_write_reg(0x02, attenuation); /* right channel */
+ debug ("PCM1772 attenuation right set to %d.\n", attenuation);
+}
+
+void amplifier_init(void)
+{
+ static int init_done = 0;
+ int i;
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+
+ /* Do this only once, because of the long time delay */
+ if (!init_done) {
+ /* configure PCM1772 audio format as I2S */
+ pcm1772_write_reg(0x03, 0x01);
+ /* enable audio amplifier */
+ gpio->sint_gpioe |= 0x02; /* PSC3_5 as GPIO */
+ gpio->sint_ode &= ~0x02; /* PSC3_5 is not open Drain */
+ gpio->sint_dvo &= ~0x02; /* PSC3_5 is LOW */
+ gpio->sint_ddr |= 0x02; /* PSC3_5 as output */
+ /*
+ * wait some time to allow amplifier to recover from shutdown
+ * mode.
+ */
+ for(i = 0; i < 350; i++)
+ udelay(1000);
+ /*
+ * The used amplifier (LM4867) has a so called "pop and click"
+ * elmination filter. The input signal of the amplifier must
+ * exceed a certain level once after power up to activate the
+ * generation of the output signal. This is achieved by
+ * sending a low frequent (nearly inaudible) sawtooth with a
+ * sufficient signal level.
+ */
+ set_attenuation(50);
+ i2s_sawtooth (200, 5, LEFT_RIGHT);
+ init_done = 1;
+ }
+}
+
+static void i2s_init(void)
+{
+ unsigned long i;
+ struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;;
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+
+ gpio->port_config |= 0x00000070; /* PSC2 ports as Codec with MCLK */
+ psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
+ psc->sicr = 0x22E00000; /* 16 bit data; I2S */
+
+ *(vu_long *)(CFG_MBAR + 0x22C) = 0x805d; /* PSC2 CDM MCLK config; MCLK
+ * 5.617 MHz */
+ *(vu_long *)(CFG_MBAR + 0x214) |= 0x00000040; /* CDM clock enable
+ * register */
+ psc->ccr = 0x1F03; /* 16 bit data width; 5.617MHz MCLK */
+ psc->ctur = 0x0F; /* 16 bit frame width */
+
+ for(i=0;i<128;i++)
+ {
+ psc->psc_buffer_32 = 0; /* clear tx fifo */
+ }
+}
+
+static int i2s_play_wave(unsigned long addr, unsigned long len)
+{
+ unsigned long i;
+ unsigned char *wave_file = (uchar *)addr + 44; /* quick'n dirty: skip
+ * wav header*/
+ unsigned char swapped[4];
+ struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;
+
+ /*
+ * play wave file in memory; bytes/words are be swapped
+ */
+ psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE);
+
+ for(i = 0;i < (len / 4); i++) {
+ swapped[3]=*wave_file++;
+ swapped[2]=*wave_file++;
+ swapped[1]=*wave_file++;
+ swapped[0]=*wave_file++;
+ psc->psc_buffer_32 = *((unsigned long*)swapped);
+ while (psc->tfnum > 400) {
+ if(ctrlc())
+ return 0;
+ }
+ }
+ while (psc->tfnum > 0); /* wait for fifo empty */
+ udelay (100);
+ psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
+ return 0;
+}
+
+static int i2s_sawtooth(unsigned long duration, unsigned int freq,
+ unsigned int channel)
+{
+ long i,j;
+ unsigned long data;
+ struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;
+
+ psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE);
+
+ /*
+ * Generate sawtooth. Start with middle level up to highest level. Then
+ * go to lowest level and back to middle level.
+ */
+ for(j = 0; j < ((duration * freq) / 1000); j++) {
+ for(i = 0; i <= 0x7FFF; i += (0x7FFF/(44100/(freq*4)))) {
+ data = (i & 0xFFFF);
+ /* data format: right data left data) */
+ if (channel == LEFT_RIGHT)
+ data |= (data<<16);
+ if (channel == RIGHT)
+ data = (data<<16);
+ psc->psc_buffer_32 = data;
+ while (psc->tfnum > 400);
+ }
+ for(i = 0x7FFF; i >= -0x7FFF; i -= (0xFFFF/(44100/(freq*2)))) {
+ data = (i & 0xFFFF);
+ /* data format: right data left data) */
+ if (channel == LEFT_RIGHT)
+ data |= (data<<16);
+ if (channel == RIGHT)
+ data = (data<<16);
+ psc->psc_buffer_32 = data;
+ while (psc->tfnum > 400);
+ }
+ for(i = -0x7FFF; i <= 0; i += (0x7FFF/(44100/(freq*4)))) {
+ data = (i & 0xFFFF);
+ /* data format: right data left data) */
+ if (channel == LEFT_RIGHT)
+ data |= (data<<16);
+ if (channel == RIGHT)
+ data = (data<<16);
+ psc->psc_buffer_32 = data;
+ while (psc->tfnum > 400);
+ }
+ }
+ while (psc->tfnum > 0); /* wait for fifo empty */
+ udelay (100);
+ psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
+
+ return 0;
+}
+
+static int i2s_squarewave(unsigned long duration, unsigned int freq,
+ unsigned int channel)
+{
+ long i,j;
+ unsigned long data;
+ struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;
+
+ psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE);
+
+ /*
+ * Generate sqarewave. Start with high level, duty cycle 1:1.
+ */
+ for(j = 0; j < ((duration * freq) / 1000); j++) {
+ for(i = 0; i < (44100/(freq*2)); i ++) {
+ data = 0x7FFF;
+ /* data format: right data left data) */
+ if (channel == LEFT_RIGHT)
+ data |= (data<<16);
+ if (channel == RIGHT)
+ data = (data<<16);
+ psc->psc_buffer_32 = data;
+ while (psc->tfnum > 400);
+ }
+ for(i = 0; i < (44100/(freq*2)); i ++) {
+ data = 0x8000;
+ /* data format: right data left data) */
+ if (channel == LEFT_RIGHT)
+ data |= (data<<16);
+ if (channel == RIGHT)
+ data = (data<<16);
+ psc->psc_buffer_32 = data;
+ while (psc->tfnum > 400);
+ }
+ }
+ while (psc->tfnum > 0); /* wait for fifo empty */
+ udelay (100);
+ psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
+
+ return 0;
+}
+
+static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned long reg, val, duration;
+ char *tmp;
+ unsigned int freq, channel;
+ unsigned char volume;
+ int rcode = 1;
+
+#ifdef CONFIG_STK52XX_REV100
+ printf ("Revision 100 of STK52XX not supported!\n");
+ return 1;
+#endif
+ spi_init();
+ i2s_init();
+ amplifier_init();
+
+ if ((tmp = getenv ("volume")) != NULL) {
+ volume = simple_strtoul (tmp, NULL, 10);
+ } else {
+ volume = DEFAULT_VOL;
+ }
+ set_attenuation(volume);
+
+ switch (argc) {
+ case 0:
+ case 1:
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ case 2:
+ if (strncmp(argv[1],"saw",3) == 0) {
+ printf ("Play sawtooth\n");
+ rcode = i2s_sawtooth (DEFAULT_DURATION, DEFAULT_FREQ,
+ LEFT_RIGHT);
+ return rcode;
+ } else if (strncmp(argv[1],"squ",3) == 0) {
+ printf ("Play squarewave\n");
+ rcode = i2s_squarewave (DEFAULT_DURATION, DEFAULT_FREQ,
+ LEFT_RIGHT);
+ return rcode;
+ }
+
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ case 3:
+ if (strncmp(argv[1],"saw",3) == 0) {
+ duration = simple_strtoul(argv[2], NULL, 10);
+ printf ("Play sawtooth\n");
+ rcode = i2s_sawtooth (duration, DEFAULT_FREQ,
+ LEFT_RIGHT);
+ return rcode;
+ } else if (strncmp(argv[1],"squ",3) == 0) {
+ duration = simple_strtoul(argv[2], NULL, 10);
+ printf ("Play squarewave\n");
+ rcode = i2s_squarewave (duration, DEFAULT_FREQ,
+ LEFT_RIGHT);
+ return rcode;
+ }
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ case 4:
+ if (strncmp(argv[1],"saw",3) == 0) {
+ duration = simple_strtoul(argv[2], NULL, 10);
+ freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
+ printf ("Play sawtooth\n");
+ rcode = i2s_sawtooth (duration, freq,
+ LEFT_RIGHT);
+ return rcode;
+ } else if (strncmp(argv[1],"squ",3) == 0) {
+ duration = simple_strtoul(argv[2], NULL, 10);
+ freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
+ printf ("Play squarewave\n");
+ rcode = i2s_squarewave (duration, freq,
+ LEFT_RIGHT);
+ return rcode;
+ } else if (strcmp(argv[1],"pcm1772") == 0) {
+ reg = simple_strtoul(argv[2], NULL, 10);
+ val = simple_strtoul(argv[3], NULL, 10);
+ printf("Set PCM1772 %lu. %lu\n", reg, val);
+ pcm1772_write_reg((uchar)reg, (uchar)val);
+ return 0;
+ }
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ case 5:
+ if (strncmp(argv[1],"saw",3) == 0) {
+ duration = simple_strtoul(argv[2], NULL, 10);
+ freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
+ if (strncmp(argv[4],"l",1) == 0)
+ channel = LEFT;
+ else if (strncmp(argv[4],"r",1) == 0)
+ channel = RIGHT;
+ else
+ channel = LEFT_RIGHT;
+ printf ("Play squarewave\n");
+ rcode = i2s_sawtooth (duration, freq,
+ channel);
+ return rcode;
+ } else if (strncmp(argv[1],"squ",3) == 0) {
+ duration = simple_strtoul(argv[2], NULL, 10);
+ freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
+ if (strncmp(argv[4],"l",1) == 0)
+ channel = LEFT;
+ else if (strncmp(argv[4],"r",1) == 0)
+ channel = RIGHT;
+ else
+ channel = LEFT_RIGHT;
+ printf ("Play squarewave\n");
+ rcode = i2s_squarewave (duration, freq,
+ channel);
+ return rcode;
+ }
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+ printf ("Usage:\nsound cmd [arg1] [arg2] ...\n");
+ return 1;
+}
+
+static int cmd_wav(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned long length, addr;
+ unsigned char volume;
+ int rcode = 1;
+ char *tmp;
+
+#ifdef CONFIG_STK52XX_REV100
+ printf ("Revision 100 of STK52XX not supported!\n");
+ return 1;
+#endif
+ spi_init();
+ i2s_init();
+ amplifier_init();
+
+ switch (argc) {
+
+ case 3:
+ length = simple_strtoul(argv[2], NULL, 16);
+ addr = simple_strtoul(argv[1], NULL, 16);
+ break;
+
+ case 2:
+ if ((tmp = getenv ("filesize")) != NULL) {
+ length = simple_strtoul (tmp, NULL, 16);
+ } else {
+ puts ("No filesize provided\n");
+ return 1;
+ }
+ addr = simple_strtoul(argv[1], NULL, 16);
+
+ case 1:
+ if ((tmp = getenv ("filesize")) != NULL) {
+ length = simple_strtoul (tmp, NULL, 16);
+ } else {
+ puts ("No filesize provided\n");
+ return 1;
+ }
+ if ((tmp = getenv ("loadaddr")) != NULL) {
+ addr = simple_strtoul (tmp, NULL, 16);
+ } else {
+ puts ("No loadaddr provided\n");
+ return 1;
+ }
+ break;
+
+ default:
+ printf("Usage:\nwav <addr> <length[s]\n");
+ return 1;
+ break;
+ }
+
+ if ((tmp = getenv ("volume")) != NULL) {
+ volume = simple_strtoul (tmp, NULL, 10);
+ } else {
+ volume = DEFAULT_VOL;
+ }
+ set_attenuation(volume);
+
+ printf("Play wave file at %#p with length %#x\n", addr, length);
+ rcode = i2s_play_wave(addr, length);
+
+ return rcode;
+}
+
+static int cmd_beep(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned char volume;
+ unsigned int channel;
+ int rcode;
+ char *tmp;
+
+#ifdef CONFIG_STK52XX_REV100
+ printf ("Revision 100 of STK52XX not supported!\n");
+ return 1;
+#endif
+ spi_init();
+ i2s_init();
+ amplifier_init();
+
+ switch (argc) {
+ case 0:
+ case 1:
+ channel = LEFT_RIGHT;
+ break;
+ case 2:
+ if (strncmp(argv[1],"l",1) == 0)
+ channel = LEFT;
+ else if (strncmp(argv[1],"r",1) == 0)
+ channel = RIGHT;
+ else
+ channel = LEFT_RIGHT;
+ break;
+ default:
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
+ if ((tmp = getenv ("volume")) != NULL) {
+ volume = simple_strtoul (tmp, NULL, 10);
+ } else {
+ volume = DEFAULT_VOL;
+ }
+ set_attenuation(volume);
+
+ printf("Beep on ");
+ if (channel == LEFT)
+ printf ("left ");
+ else if (channel == RIGHT)
+ printf ("right ");
+ else
+ printf ("left and right ");
+ printf ("channel\n");
+
+ rcode = i2s_squarewave (DEFAULT_DURATION, DEFAULT_FREQ, channel);
+
+ return rcode;
+}
+
+void led_init(void)
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+ struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+
+ /* configure PSC3 for SPI and GPIO */
+ gpio->port_config &= ~(0x00000F00);
+ gpio->port_config |= 0x00000800;
+
+ gpio->simple_gpioe &= ~(0x00000F00);
+ gpio->simple_gpioe |= 0x00000F00;
+
+ gpio->simple_ddr &= ~(0x00000F00);
+ gpio->simple_ddr |= 0x00000F00;
+
+ /* configure timer 4-7 for simple GPIO output */
+ gpt->gpt4.emsr |= 0x00000024;
+ gpt->gpt5.emsr |= 0x00000024;
+ gpt->gpt6.emsr |= 0x00000024;
+ gpt->gpt7.emsr |= 0x00000024;
+
+
+ /* enable SM501 GPIO control (in both power modes) */
+ *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
+ POWER_MODE_GATE_GPIO_PWM_I2C;
+ *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
+ POWER_MODE_GATE_GPIO_PWM_I2C;
+
+ /* configure SM501 gpio pins 24-27 as output */
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_CTRL_LOW) &= ~(0xF << 24);
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_LOW) |= (0xF << 24);
+
+ /* configure SM501 gpio pins 48-51 as output */
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |= (0xF << 16);
+}
+
+/*
+ * return 1 if led number unknown
+ * return 0 else
+ */
+int do_led(char *argv[])
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+ struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+
+ switch (simple_strtoul(argv[2], NULL, 10)) {
+
+ case 0:
+ if (strcmp (argv[3], "on") == 0) {
+ gpio->simple_dvo |= (1 << 8);
+ } else {
+ gpio->simple_dvo &= ~(1 << 8);
+ }
+ break;
+
+ case 1:
+ if (strcmp (argv[3], "on") == 0) {
+ gpio->simple_dvo |= (1 << 9);
+ } else {
+ gpio->simple_dvo &= ~(1 << 9);
+ }
+ break;
+
+ case 2:
+ if (strcmp (argv[3], "on") == 0) {
+ gpio->simple_dvo |= (1 << 10);
+ } else {
+ gpio->simple_dvo &= ~(1 << 10);
+ }
+ break;
+
+ case 3:
+ if (strcmp (argv[3], "on") == 0) {
+ gpio->simple_dvo |= (1 << 11);
+ } else {
+ gpio->simple_dvo &= ~(1 << 11);
+ }
+ break;
+
+ case 4:
+ if (strcmp (argv[3], "on") == 0) {
+ gpt->gpt4.emsr |= (1 << 4);
+ } else {
+ gpt->gpt4.emsr &= ~(1 << 4);
+ }
+ break;
+
+ case 5:
+ if (strcmp (argv[3], "on") == 0) {
+ gpt->gpt5.emsr |= (1 << 4);
+ } else {
+ gpt->gpt5.emsr &= ~(1 << 4);
+ }
+ break;
+
+ case 6:
+ if (strcmp (argv[3], "on") == 0) {
+ gpt->gpt6.emsr |= (1 << 4);
+ } else {
+ gpt->gpt6.emsr &= ~(1 << 4);
+ }
+ break;
+
+ case 7:
+ if (strcmp (argv[3], "on") == 0) {
+ gpt->gpt7.emsr |= (1 << 4);
+ } else {
+ gpt->gpt7.emsr &= ~(1 << 4);
+ }
+ break;
+
+ case 24:
+ if (strcmp (argv[3], "on") == 0) {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
+ (0x1 << 24);
+ } else {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
+ ~(0x1 << 24);
+ }
+ break;
+
+ case 25:
+ if (strcmp (argv[3], "on") == 0) {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
+ (0x1 << 25);
+ } else {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
+ ~(0x1 << 25);
+ }
+ break;
+
+ case 26:
+ if (strcmp (argv[3], "on") == 0) {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
+ (0x1 << 26);
+ } else {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
+ ~(0x1 << 26);
+ }
+ break;
+
+ case 27:
+ if (strcmp (argv[3], "on") == 0) {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
+ (0x1 << 27);
+ } else {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
+ ~(0x1 << 27);
+ }
+ break;
+
+ case 48:
+ if (strcmp (argv[3], "on") == 0) {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
+ (0x1 << 16);
+ } else {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
+ ~(0x1 << 16);
+ }
+ break;
+
+ case 49:
+ if (strcmp (argv[3], "on") == 0) {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
+ (0x1 << 17);
+ } else {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
+ ~(0x1 << 17);
+ }
+ break;
+
+ case 50:
+ if (strcmp (argv[3], "on") == 0) {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
+ (0x1 << 18);
+ } else {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
+ ~(0x1 << 18);
+ }
+ break;
+
+ case 51:
+ if (strcmp (argv[3], "on") == 0) {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
+ (0x1 << 19);
+ } else {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
+ ~(0x1 << 19);
+ }
+ break;
+
+ default:
+ printf ("%s: invalid led number %s\n", __FUNCTION__, argv[2]);
+ return 1;
+ }
+
+ return 0;
+}
+
+/*
+ * return 1 on CAN initialization failure
+ * return 0 if no failure
+ */
+int can_init(void)
+{
+ static int init_done = 0;
+ int i;
+ struct mpc5xxx_mscan *can1 =
+ (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0900);
+ struct mpc5xxx_mscan *can2 =
+ (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0980);
+
+ /* GPIO configuration of the CAN pins is done in TQM5200.h */
+
+ if (!init_done) {
+ /* init CAN 1 */
+ can1->canctl1 |= 0x80; /* CAN enable */
+ udelay(100);
+
+ i = 0;
+ can1->canctl0 |= 0x02; /* sleep mode */
+ /* wait until sleep mode reached */
+ while (!(can1->canctl1 & 0x02)) {
+ udelay(10);
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN1 initialize error, "
+ "can not enter sleep mode!\n",
+ __FUNCTION__);
+ return 1;
+ }
+ }
+ i = 0;
+ can1->canctl0 = 0x01; /* enter init mode */
+ /* wait until init mode reached */
+ while (!(can1->canctl1 & 0x01)) {
+ udelay(10);
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN1 initialize error, "
+ "can not enter init mode!\n",
+ __FUNCTION__);
+ return 1;
+ }
+ }
+ can1->canctl1 = 0x80;
+ can1->canctl1 |= 0x40;
+ can1->canbtr0 = 0x0F;
+ can1->canbtr1 = 0x7F;
+ can1->canidac &= ~(0x30);
+ can1->canidar1 = 0x00;
+ can1->canidar3 = 0x00;
+ can1->canidar5 = 0x00;
+ can1->canidar7 = 0x00;
+ can1->canidmr0 = 0xFF;
+ can1->canidmr1 = 0xFF;
+ can1->canidmr2 = 0xFF;
+ can1->canidmr3 = 0xFF;
+ can1->canidmr4 = 0xFF;
+ can1->canidmr5 = 0xFF;
+ can1->canidmr6 = 0xFF;
+ can1->canidmr7 = 0xFF;
+
+ i = 0;
+ can1->canctl0 &= ~(0x01); /* leave init mode */
+ can1->canctl0 &= ~(0x02);
+ /* wait until init and sleep mode left */
+ while ((can1->canctl1 & 0x01) || (can1->canctl1 & 0x02)) {
+ udelay(10);
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN1 initialize error, "
+ "can not leave init/sleep mode!\n",
+ __FUNCTION__);
+ return 1;
+ }
+ }
+
+ /* init CAN 2 */
+ can2->canctl1 |= 0x80; /* CAN enable */
+ udelay(100);
+
+ i = 0;
+ can2->canctl0 |= 0x02; /* sleep mode */
+ /* wait until sleep mode reached */
+ while (!(can2->canctl1 & 0x02)) {
+ udelay(10);
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN2 initialize error, "
+ "can not enter sleep mode!\n",
+ __FUNCTION__);
+ return 1;
+ }
+ }
+ i = 0;
+ can2->canctl0 = 0x01; /* enter init mode */
+ /* wait until init mode reached */
+ while (!(can2->canctl1 & 0x01)) {
+ udelay(10);
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN2 initialize error, "
+ "can not enter init mode!\n",
+ __FUNCTION__);
+ return 1;
+ }
+ }
+ can2->canctl1 = 0x80;
+ can2->canctl1 |= 0x40;
+ can2->canbtr0 = 0x0F;
+ can2->canbtr1 = 0x7F;
+ can2->canidac &= ~(0x30);
+ can2->canidar1 = 0x00;
+ can2->canidar3 = 0x00;
+ can2->canidar5 = 0x00;
+ can2->canidar7 = 0x00;
+ can2->canidmr0 = 0xFF;
+ can2->canidmr1 = 0xFF;
+ can2->canidmr2 = 0xFF;
+ can2->canidmr3 = 0xFF;
+ can2->canidmr4 = 0xFF;
+ can2->canidmr5 = 0xFF;
+ can2->canidmr6 = 0xFF;
+ can2->canidmr7 = 0xFF;
+ can2->canctl0 &= ~(0x01); /* leave init mode */
+ can2->canctl0 &= ~(0x02);
+
+ i = 0;
+ /* wait until init mode left */
+ while ((can2->canctl1 & 0x01) || (can2->canctl1 & 0x02)) {
+ udelay(10);
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN2 initialize error, "
+ "can not leave init/sleep mode!\n",
+ __FUNCTION__);
+ return 1;
+ }
+ }
+ init_done = 1;
+ }
+ return 0;
+}
+
+/*
+ * return 1 on CAN failure
+ * return 0 if no failure
+ */
+int do_can(char *argv[])
+{
+ int i;
+ struct mpc5xxx_mscan *can1 =
+ (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0900);
+ struct mpc5xxx_mscan *can2 =
+ (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0980);
+
+ /* send a message on CAN1 */
+ can1->cantbsel = 0x01;
+ can1->cantxfg.idr[0] = 0x55;
+ can1->cantxfg.idr[1] = 0x00;
+ can1->cantxfg.idr[1] &= ~0x8;
+ can1->cantxfg.idr[1] &= ~0x10;
+ can1->cantxfg.dsr[0] = 0xCC;
+ can1->cantxfg.dlr = 1;
+ can1->cantxfg.tbpr = 0;
+ can1->cantflg = 0x01;
+
+ i = 0;
+ while ((can1->cantflg & 0x01) == 0) {
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN1 send timeout, "
+ "can not send message!\n",
+ __FUNCTION__);
+ return 1;
+ }
+ udelay(1000);
+ }
+ udelay(1000);
+
+ i = 0;
+ while (!(can2->canrflg & 0x01)) {
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN2 receive timeout, "
+ "no message received!\n",
+ __FUNCTION__);
+ return 1;
+ }
+ udelay(1000);
+ }
+
+ if (can2->canrxfg.dsr[0] != 0xCC) {
+ printf ("%s: CAN2 receive error, "
+ "data mismatch!\n",
+ __FUNCTION__);
+ return 1;
+ }
+
+ /* send a message on CAN2 */
+ can2->cantbsel = 0x01;
+ can2->cantxfg.idr[0] = 0x55;
+ can2->cantxfg.idr[1] = 0x00;
+ can2->cantxfg.idr[1] &= ~0x8;
+ can2->cantxfg.idr[1] &= ~0x10;
+ can2->cantxfg.dsr[0] = 0xCC;
+ can2->cantxfg.dlr = 1;
+ can2->cantxfg.tbpr = 0;
+ can2->cantflg = 0x01;
+
+ i = 0;
+ while ((can2->cantflg & 0x01) == 0) {
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN2 send error, "
+ "can not send message!\n",
+ __FUNCTION__);
+ return 1;
+ }
+ udelay(1000);
+ }
+ udelay(1000);
+
+ i = 0;
+ while (!(can1->canrflg & 0x01)) {
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN1 receive timeout, "
+ "no message received!\n",
+ __FUNCTION__);
+ return 1;
+ }
+ udelay(1000);
+ }
+
+ if (can1->canrxfg.dsr[0] != 0xCC) {
+ printf ("%s: CAN1 receive error 0x%02x\n",
+ __FUNCTION__, (can1->canrxfg.dsr[0]));
+ return 1;
+ }
+
+ return 0;
+}
+
+/*
+ * return 1 if rs232 port unknown
+ * return 2 on txd/rxd failure (only rs232 2)
+ * return 3 on rts/cts failure
+ * return 0 if no failure
+ */
+int do_rs232(char *argv[])
+{
+ int error_status = 0;
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+ struct mpc5xxx_psc *psc1 = (struct mpc5xxx_psc *)MPC5XXX_PSC1;
+
+ switch (simple_strtoul(argv[2], NULL, 10)) {
+
+ case 1:
+ /* check RTS <-> CTS loop */
+ /* set rts to 0 */
+ psc1->op1 |= 0x01;
+
+ /* wait some time before requesting status */
+ udelay(10);
+
+ /* check status at cts */
+ if ((psc1->ip & 0x01) != 0) {
+ error_status = 3;
+ printf ("%s: failure at rs232_1, cts status is %d "
+ "(should be 0)\n",
+ __FUNCTION__, (psc1->ip & 0x01));
+ }
+
+ /* set rts to 1 */
+ psc1->op0 |= 0x01;
+
+ /* wait some time before requesting status */
+ udelay(10);
+
+ /* check status at cts */
+ if ((psc1->ip & 0x01) != 1) {
+ error_status = 3;
+ printf ("%s: failure at rs232_1, cts status is %d "
+ "(should be 1)\n",
+ __FUNCTION__, (psc1->ip & 0x01));
+ }
+
+ break;
+
+ case 2:
+ /* set PSC3_0, PSC3_2 as output and PSC3_1, PSC3_3 as input */
+ gpio->simple_ddr &= ~(0x00000F00);
+ gpio->simple_ddr |= 0x00000500;
+
+ /* check TXD <-> RXD loop */
+ /* set TXD to 1 */
+ gpio->simple_dvo |= (1 << 8);
+
+ /* wait some time before requesting status */
+ udelay(10);
+
+ if ((gpio->simple_ival & 0x00000200) != 0x00000200) {
+ error_status = 2;
+ printf ("%s: failure at rs232_2, rxd status is %d "
+ "(should be 1)\n",
+ __FUNCTION__,
+ (gpio->simple_ival & 0x00000200) >> 9);
+ }
+
+ /* set TXD to 0 */
+ gpio->simple_dvo &= ~(1 << 8);
+
+ /* wait some time before requesting status */
+ udelay(10);
+
+ if ((gpio->simple_ival & 0x00000200) != 0x00000000) {
+ error_status = 2;
+ printf ("%s: failure at rs232_2, rxd status is %d "
+ "(should be 0)\n",
+ __FUNCTION__,
+ (gpio->simple_ival & 0x00000200) >> 9);
+ }
+
+ /* check RTS <-> CTS loop */
+ /* set RTS to 1 */
+ gpio->simple_dvo |= (1 << 10);
+
+ /* wait some time before requesting status */
+ udelay(10);
+
+ if ((gpio->simple_ival & 0x00000800) != 0x00000800) {
+ error_status = 3;
+ printf ("%s: failure at rs232_2, cts status is %d "
+ "(should be 1)\n",
+ __FUNCTION__,
+ (gpio->simple_ival & 0x00000800) >> 11);
+ }
+
+ /* set RTS to 0 */
+ gpio->simple_dvo &= ~(1 << 10);
+
+ /* wait some time before requesting status */
+ udelay(10);
+
+ if ((gpio->simple_ival & 0x00000800) != 0x00000000) {
+ error_status = 3;
+ printf ("%s: failure at rs232_2, cts status is %d "
+ "(should be 0)\n",
+ __FUNCTION__,
+ (gpio->simple_ival & 0x00000800) >> 11);
+ }
+
+ /* set PSC3_0, PSC3_1, PSC3_2 and PSC3_3 as output */
+ gpio->simple_ddr &= ~(0x00000F00);
+ gpio->simple_ddr |= 0x00000F00;
+ break;
+
+ default:
+ printf ("%s: invalid rs232 number %s\n", __FUNCTION__, argv[2]);
+ error_status = 1;
+ break;
+ }
+
+ return error_status;
+}
+
+static void sm501_backlight (unsigned int state)
+{
+ if (state == BL_ON) {
+ *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) |=
+ (1 << 26) | (1 << 27);
+ } else if (state == BL_OFF)
+ *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &=
+ ~((1 << 26) | (1 << 27));
+}
+
+int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int rcode;
+
+#ifdef CONFIG_STK52XX_REV100
+ printf ("Revision 100 of STK52XX not supported!\n");
+ return 1;
+#endif
+ led_init();
+ can_init();
+
+ switch (argc) {
+
+ case 0:
+ case 1:
+ break;
+
+ case 2:
+ if (strncmp (argv[1], "can", 3) == 0) {
+ rcode = do_can (argv);
+ if (rcode == 0)
+ printf ("OK\n");
+ else
+ printf ("Error\n");
+ return rcode;
+ }
+ break;
+
+ case 3:
+ if (strncmp (argv[1], "rs232", 3) == 0) {
+ rcode = do_rs232 (argv);
+ if (rcode == 0)
+ printf ("OK\n");
+ else
+ printf ("Error\n");
+ return rcode;
+ } else if (strncmp (argv[1], "backlight", 4) == 0) {
+ if (strncmp (argv[2], "on", 2) == 0) {
+ sm501_backlight (BL_ON);
+ return 0;
+ }
+ else if (strncmp (argv[2], "off", 3) == 0) {
+ sm501_backlight (BL_OFF);
+ return 0;
+ }
+ }
+ break;
+
+ case 4:
+ if (strcmp (argv[1], "led") == 0) {
+ return (do_led (argv));
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ printf ("Usage:\nfkt cmd [arg1] [arg2] ...\n");
+ return 1;
+}
+
+
+U_BOOT_CMD(
+ sound , 5, 1, cmd_sound,
+ "sound - Sound sub-system\n",
+ "saw [duration] [freq] [channel]\n"
+ " - generate sawtooth for 'duration' ms with frequency 'freq'\n"
+ " on left \"l\" or right \"r\" channel\n"
+ "sound square [duration] [freq] [channel]\n"
+ " - generate squarewave for 'duration' ms with frequency 'freq'\n"
+ " on left \"l\" or right \"r\" channel\n"
+ "pcm1772 reg val\n"
+);
+
+U_BOOT_CMD(
+ wav , 3, 1, cmd_wav,
+ "wav - play wav file\n",
+ "[addr] [bytes]\n"
+ " - play wav file at address 'addr' with length 'bytes'\n"
+);
+
+U_BOOT_CMD(
+ beep , 2, 1, cmd_beep,
+ "beep - play short beep\n",
+ "[channel]\n"
+ " - play short beep on \"l\"eft or \"r\"ight channel\n"
+);
+
+U_BOOT_CMD(
+ fkt , 4, 1, cmd_fkt,
+ "fkt - Function test routines\n",
+ "led number on/off\n"
+ " - 'number's like printed on SKT52XX board\n"
+ "fkt can\n"
+ " - loopback plug for X83 required\n"
+ "fkt rs232 number\n"
+ " - loopback plug(s) for X2 required\n"
+ "fkt backlight on/off\n"
+ " - switch backlight on or off\n"
+);
+#endif /* CONFIG_STK52XX */
+#endif /* CFG_CMD_BSP */
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
- test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
+ test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
sdram_start(1);
- test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
+ test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
/* find RAM size using SDRAM CS1 only */
sdram_start(0);
- test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
+ test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
sdram_start(1);
- test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
+ test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
if (test1 > test2) {
sdram_start(0);
dramsize2 = test1;
* Check for SRAM and SRAM size
*/
- /* save origianl SRAM content */
+ /* save original SRAM content */
save = *(volatile u16 *)CFG_CS2_START;
restore = 1;
*(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
restore = 0;
__asm__ volatile ("sync");
- }
- else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) {
+ } else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) {
/* make sure that we access a mirrored address */
*(volatile u16 *)CFG_CS2_START = 0x1111;
__asm__ volatile ("sync");
}
else
puts ("!! possible error in SRAM detection\n");
- }
- else {
+ } else {
puts ("SRAM: 1 MB\n");
}
/* restore origianl SRAM content */
*(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
restore = 0;
__asm__ volatile ("sync");
- }
- else {
+ } else {
puts ("VGA: SMI501 (Voyager) with 8 MB\n");
}
/* restore origianl FB content */
#endif
/*
- * Returns SM501 register base address. First thing called in the driver.
+ * Returns SM501 register base address. First thing called in the
+ * driver. Checks if SM501 is physically present.
*/
unsigned int board_video_init (void)
{
- return SM501_MMIO_BASE;
+ u16 save, tmp;
+ int restore, ret;
+
+ /*
+ * Check for Grafic Controller
+ */
+
+ /* save origianl FB content */
+ save = *(volatile u16 *)CFG_CS1_START;
+ restore = 1;
+
+ /* write test pattern to FB memory */
+ *(volatile u16 *)CFG_CS1_START = 0xA5A5;
+ __asm__ volatile ("sync");
+ /*
+ * Put a different pattern on the data lines: otherwise they may float
+ * long enough to read back what we wrote.
+ */
+ tmp = *(volatile u16 *)CFG_FLASH_BASE;
+ if (tmp == 0xA5A5)
+ puts ("!! possible error in grafic controller detection\n");
+
+ if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
+ /* no grafic controller found */
+ restore = 0;
+ ret = 0;
+ } else {
+ ret = SM501_MMIO_BASE;
+ }
+
+ if (restore) {
+ *(volatile u16 *)CFG_CS1_START = save;
+ __asm__ volatile ("sync");
+ }
+ return ret;
}
/*
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*/
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof (str));
puts ("Board: ");
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
--- /dev/null
+#
+# Copyright 2004 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o pci.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+#
+# Copyright 2004 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x80000000
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <asm/mmu.h>
+#include <common.h>
+#include <pci.h>
+
+#ifdef CONFIG_PCI
+
+/* System RAM mapped to PCI space */
+#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_tqm834x_config_table[] = {
+ {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+ PCI_IDSEL_NUMBER, PCI_ANY_ID,
+ pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+ }
+ },
+ {}
+};
+#endif
+
+static struct pci_controller pci1_hose = {
+#ifndef CONFIG_PCI_PNP
+ config_table:pci_tqm834x_config_table,
+#endif
+};
+
+
+/**************************************************************************
+ * pci_init_board()
+ *
+ * NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since
+ * per TQM834x design physical connections to external devices (PCI sockets)
+ * are routed only to the PCI1 we do not account for the second one - this code
+ * supports PCI1 module only. Should support for the PCI2 be required in the
+ * future it needs a separate pci_controller structure (above) and handling -
+ * please refer to other boards' implementation for dual PCI host controllers,
+ * for example board/Marvell/db64360/pci.c, pci_init_board()
+ *
+ */
+void
+pci_init_board(void)
+{
+ volatile immap_t * immr;
+ volatile clk8349_t * clk;
+ volatile law8349_t * pci_law;
+ volatile pot8349_t * pci_pot;
+ volatile pcictrl8349_t * pci_ctrl;
+ volatile pciconf8349_t * pci_conf;
+ u16 reg16;
+ u32 reg32;
+ struct pci_controller * hose;
+
+ immr = (immap_t *)CFG_IMMRBAR;
+ clk = (clk8349_t *)&immr->clk;
+ pci_law = immr->sysconf.pcilaw;
+ pci_pot = immr->ios.pot;
+ pci_ctrl = immr->pci_ctrl;
+ pci_conf = immr->pci_conf;
+
+ hose = &pci1_hose;
+
+ /*
+ * Configure PCI controller and PCI_CLK_OUTPUT
+ */
+
+ /*
+ * WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one
+ * line actually used for clocking all external PCI devices in TQM83xx.
+ * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for
+ * unknown reasons - particularly PCI_CLK_OUTPUT6 and PCI_CLK_OUTPUT7
+ * are known to hang the board; this issue is under investigation
+ * (13 oct 05)
+ */
+ reg32 = OCCR_PCICOE1;
+#if 0
+ /* enabling all PCI_CLK_OUTPUT lines HANGS the board... */
+ reg32 = 0xff000000;
+#endif
+ if (clk->spmr & SPMR_CKID) {
+ /* PCI Clock is half CONFIG_83XX_CLKIN so need to set up OCCR
+ * fields accordingly */
+ reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR);
+
+ reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \
+ | OCCR_PCICD3 | OCCR_PCICD4 | OCCR_PCICD5 \
+ | OCCR_PCICD6 | OCCR_PCICD7);
+ }
+
+ clk->occr = reg32;
+ udelay(2000);
+
+ /*
+ * Release PCI RST Output signal
+ */
+ pci_ctrl[0].gcr = 0;
+ udelay(2000);
+ pci_ctrl[0].gcr = 1;
+ udelay(2000);
+
+ /*
+ * Configure PCI Local Access Windows
+ */
+ pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
+
+ pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
+
+ /*
+ * Configure PCI Outbound Translation Windows
+ */
+
+ /* PCI1 mem space */
+ pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK);
+
+ /* PCI1 IO space */
+ pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
+
+ /*
+ * Configure PCI Inbound Translation Windows
+ */
+
+ /* we need RAM mapped to PCI space for the devices to
+ * access main memory */
+ pci_ctrl[0].pitar1 = 0x0;
+ pci_ctrl[0].pibar1 = 0x0;
+ pci_ctrl[0].piebar1 = 0x0;
+ pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_256M;
+
+ hose->first_busno = 0;
+ hose->last_busno = 0xff;
+
+ /* PCI memory space */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI1_MEM_BASE,
+ CFG_PCI1_MEM_PHYS,
+ CFG_PCI1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* PCI IO space */
+ pci_set_region(hose->regions + 1,
+ CFG_PCI1_IO_BASE,
+ CFG_PCI1_IO_PHYS,
+ CFG_PCI1_IO_SIZE,
+ PCI_REGION_IO);
+
+ /* System memory space */
+ pci_set_region(hose->regions + 2,
+ CONFIG_PCI_SYS_MEM_BUS,
+ CONFIG_PCI_SYS_MEM_PHYS,
+ CONFIG_PCI_SYS_MEM_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ hose->region_count = 3;
+
+ pci_setup_indirect(hose,
+ (CFG_IMMRBAR+0x8300),
+ (CFG_IMMRBAR+0x8304));
+
+ pci_register_hose(hose);
+
+ /*
+ * Write to Command register
+ */
+ reg16 = 0xff;
+ pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND,
+ ®16);
+ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND,
+ reg16);
+
+ /*
+ * Clear non-reserved bits in status register.
+ */
+ pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS,
+ 0xffff);
+ pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER,
+ 0x80);
+
+#ifdef CONFIG_PCI_SCAN_SHOW
+ printf("PCI: Bus Dev VenId DevId Class Int\n");
+#endif
+ /*
+ * Hose scan.
+ */
+ hose->last_busno = pci_hose_scan(hose);
+}
+#endif /* CONFIG_PCI */
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#include <i2c.h>
+#include <spd.h>
+#include <miiphy.h>
+#include <asm-ppc/mmu.h>
+#include <pci.h>
+
+#define IOSYNC asm("eieio")
+#define ISYNC asm("isync")
+#define SYNC asm("sync")
+#define FPW FLASH_PORT_WIDTH
+#define FPWV FLASH_PORT_WIDTHV
+
+#define DDR_MAX_SIZE_PER_CS 0x20000000
+
+#if defined(DDR_CASLAT_20)
+#define TIMING_CASLAT TIMING_CFG1_CASLAT_20
+#define MODE_CASLAT DDR_MODE_CASLAT_20
+#else
+#define TIMING_CASLAT TIMING_CFG1_CASLAT_25
+#define MODE_CASLAT DDR_MODE_CASLAT_25
+#endif
+
+#define INITIAL_CS_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_12 | \
+ CSCONFIG_COL_BIT_9)
+
+/* Global variable used to store detected number of banks */
+int tqm834x_num_flash_banks;
+
+/* External definitions */
+ulong flash_get_size (ulong base, int banknum);
+extern flash_info_t flash_info[];
+extern long spd_sdram (void);
+
+/* Local functions */
+static int detect_num_flash_banks(void);
+static long int get_ddr_bank_size(short cs, volatile long *base);
+static void set_cs_bounds(short cs, long base, long size);
+static void set_cs_config(short cs, long config);
+static void set_ddr_config(void);
+
+/* Local variable */
+static volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
+
+/**************************************************************************
+ * Board initialzation after relocation to RAM. Used to detect the number
+ * of Flash banks on TQM834x.
+ */
+int board_early_init_r (void) {
+ /* sanity check, IMMARBAR should be mirrored at offset zero of IMMR */
+ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+ return 0;
+
+ /* detect the number of Flash banks */
+ return detect_num_flash_banks();
+}
+
+/**************************************************************************
+ * DRAM initalization and size detection
+ */
+long int initdram (int board_type)
+{
+ long bank_size;
+ long size;
+ int cs;
+
+ /* during size detection, set up the max DDRLAW size */
+ im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE;
+ im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G);
+
+ /* set CS bounds to maximum size */
+ for(cs = 0; cs < 4; ++cs) {
+ set_cs_bounds(cs,
+ CFG_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS),
+ DDR_MAX_SIZE_PER_CS);
+
+ set_cs_config(cs, INITIAL_CS_CONFIG);
+ }
+
+ /* configure ddr controller */
+ set_ddr_config();
+
+ udelay(200);
+
+ /* enable DDR controller */
+ im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN |
+ SDRAM_CFG_SREN |
+ SDRAM_CFG_SDRAM_TYPE_DDR);
+ SYNC;
+
+ /* size detection */
+ debug("\n");
+ size = 0;
+ for(cs = 0; cs < 4; ++cs) {
+ debug("\nDetecting Bank%d\n", cs);
+
+ bank_size = get_ddr_bank_size(cs,
+ (volatile long*)(CFG_DDR_BASE + size));
+ size += bank_size;
+
+ debug("DDR Bank%d size: %d MiB\n\n", cs, bank_size >> 20);
+
+ /* exit if less than one bank */
+ if(size < DDR_MAX_SIZE_PER_CS) break;
+ }
+
+ return size;
+}
+
+/**************************************************************************
+ * checkboard()
+ */
+int checkboard (void)
+{
+ puts("Board: TQM834x\n");
+
+#ifdef CONFIG_PCI
+ DECLARE_GLOBAL_DATA_PTR;
+ volatile immap_t * immr;
+ u32 w, f;
+
+ immr = (immap_t *)CFG_IMMRBAR;
+ if (!(immr->reset.rcwh & RCWH_PCIHOST)) {
+ printf("PCI: NOT in host mode..?!\n");
+ return 0;
+ }
+
+ /* get bus width */
+ w = 32;
+ if (immr->reset.rcwh & RCWH_PCI64)
+ w = 64;
+
+ /* get clock */
+ f = gd->pci_clk;
+
+ printf("PCI1: %d bit, %d MHz\n", w, f / 1000000);
+#else
+ printf("PCI: disabled\n");
+#endif
+ return 0;
+}
+
+
+/**************************************************************************
+ *
+ * Local functions
+ *
+ *************************************************************************/
+
+/**************************************************************************
+ * Detect the number of flash banks (1 or 2). Store it in
+ * a global variable tqm834x_num_flash_banks.
+ * Bank detection code based on the Monitor code.
+ */
+static int detect_num_flash_banks(void)
+{
+ typedef unsigned long FLASH_PORT_WIDTH;
+ typedef volatile unsigned long FLASH_PORT_WIDTHV;
+ FPWV *bank1_base;
+ FPWV *bank2_base;
+ FPW bank1_read;
+ FPW bank2_read;
+ ulong bank1_size;
+ ulong bank2_size;
+ ulong total_size;
+
+ tqm834x_num_flash_banks = 2; /* assume two banks */
+
+ /* Get bank 1 and 2 information */
+ bank1_size = flash_get_size(CFG_FLASH_BASE, 0);
+ debug("Bank1 size: %lu\n", bank1_size);
+ bank2_size = flash_get_size(CFG_FLASH_BASE + bank1_size, 1);
+ debug("Bank2 size: %lu\n", bank2_size);
+ total_size = bank1_size + bank2_size;
+
+ if (bank2_size > 0) {
+ /* Seems like we've got bank 2, but maybe it's mirrored 1 */
+
+ /* Set the base addresses */
+ bank1_base = (FPWV *) (CFG_FLASH_BASE);
+ bank2_base = (FPWV *) (CFG_FLASH_BASE + bank1_size);
+
+ /* Put bank 2 into CFI command mode and read */
+ bank2_base[0x55] = 0x00980098;
+ IOSYNC;
+ ISYNC;
+ bank2_read = bank2_base[0x10];
+
+ /* Read from bank 1 (it's in read mode) */
+ bank1_read = bank1_base[0x10];
+
+ /* Reset Flash */
+ bank1_base[0] = 0x00F000F0;
+ bank2_base[0] = 0x00F000F0;
+
+ if (bank2_read == bank1_read) {
+ /*
+ * Looks like just one bank, but not sure yet. Let's
+ * read from bank 2 in autosoelect mode.
+ */
+ bank2_base[0x0555] = 0x00AA00AA;
+ bank2_base[0x02AA] = 0x00550055;
+ bank2_base[0x0555] = 0x00900090;
+ IOSYNC;
+ ISYNC;
+ bank2_read = bank2_base[0x10];
+
+ /* Read from bank 1 (it's in read mode) */
+ bank1_read = bank1_base[0x10];
+
+ /* Reset Flash */
+ bank1_base[0] = 0x00F000F0;
+ bank2_base[0] = 0x00F000F0;
+
+ if (bank2_read == bank1_read) {
+ /*
+ * In both CFI command and autoselect modes,
+ * we got the some data reading from Flash.
+ * There is only one mirrored bank.
+ */
+ tqm834x_num_flash_banks = 1;
+ total_size = bank1_size;
+ }
+ }
+ }
+
+ debug("Number of flash banks detected: %d\n", tqm834x_num_flash_banks);
+
+ /* set OR0 and BR0 */
+ im->lbus.bank[0].or = CFG_OR_TIMING_FLASH |
+ (-(total_size) & OR_GPCM_AM);
+ im->lbus.bank[0].br = (CFG_FLASH_BASE & BR_BA) |
+ (BR_MS_GPCM | BR_PS_32 | BR_V);
+
+ return (0);
+}
+
+/*************************************************************************
+ * Detect the size of a ddr bank. Sets CS bounds and CS config accordingly.
+ */
+static long int get_ddr_bank_size(short cs, volatile long *base)
+{
+ /* This array lists all valid DDR SDRAM configurations, with
+ * Bank sizes in bytes. (Refer to Table 9-27 in the MPC8349E RM).
+ * The last entry has to to have size equal 0 and is igonred during
+ * autodection. Bank sizes must be in increasing order of size
+ */
+ struct {
+ long row;
+ long col;
+ long size;
+ } conf[] = {
+ {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_8, 32 << 20},
+ {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_9, 64 << 20},
+ {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_10, 128 << 20},
+ {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_9, 128 << 20},
+ {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_10, 256 << 20},
+ {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_11, 512 << 20},
+ {CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_10, 512 << 20},
+ {CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_11, 1024 << 20},
+ {0, 0, 0}
+ };
+
+ int i;
+ int detected;
+ long size;
+
+ detected = -1;
+ for(i = 0; conf[i].size != 0; ++i) {
+
+ /* set sdram bank configuration */
+ set_cs_config(cs, CSCONFIG_EN | conf[i].col | conf[i].row);
+
+ debug("Getting RAM size...\n");
+ size = get_ram_size(base, DDR_MAX_SIZE_PER_CS);
+
+ if((size == conf[i].size) && (i == detected + 1))
+ detected = i;
+
+ debug("Trying %ld x %ld (%ld MiB) at addr %p, detected: %ld MiB\n",
+ conf[i].row,
+ conf[i].col,
+ conf[i].size >> 20,
+ base,
+ size >> 20);
+ }
+
+ if(detected == -1){
+ /* disable empty cs */
+ debug("\nNo valid configurations for CS%d, disabling...\n", cs);
+ set_cs_config(cs, 0);
+ return 0;
+ }
+
+ debug("\nDetected configuration %ld x %ld (%ld MiB) at addr %p\n",
+ conf[detected].row, conf[detected].col, conf[detected].size >> 20, base);
+
+ /* configure cs ro detected params */
+ set_cs_config(cs, CSCONFIG_EN | conf[detected].row |
+ conf[detected].col);
+
+ set_cs_bounds(cs, (long)base, conf[detected].size);
+
+ return(conf[detected].size);
+}
+
+/**************************************************************************
+ * Sets DDR bank CS bounds.
+ */
+static void set_cs_bounds(short cs, long base, long size)
+{
+ debug("Setting bounds %08x, %08x for cs %d\n", base, size, cs);
+ if(size == 0){
+ im->ddr.csbnds[cs].csbnds = 0x00000000;
+ } else {
+ im->ddr.csbnds[cs].csbnds =
+ ((base >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((base + size - 1) >> CSBNDS_EA_SHIFT) &
+ CSBNDS_EA);
+ }
+ SYNC;
+}
+
+/**************************************************************************
+ * Sets DDR banks CS configuration.
+ * config == 0x00000000 disables the CS.
+ */
+static void set_cs_config(short cs, long config)
+{
+ debug("Setting config %08x for cs %d\n", config, cs);
+ im->ddr.cs_config[cs] = config;
+ SYNC;
+}
+
+/**************************************************************************
+ * Sets DDR clocks, timings and configuration.
+ */
+static void set_ddr_config(void) {
+ /* clock control */
+ im->ddr.sdram_clk_cntl = DDR_SDRAM_CLK_CNTL_SS_EN |
+ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05;
+ SYNC;
+
+ /* timing configuration */
+ im->ddr.timing_cfg_1 =
+ (4 << TIMING_CFG1_PRETOACT_SHIFT) |
+ (7 << TIMING_CFG1_ACTTOPRE_SHIFT) |
+ (4 << TIMING_CFG1_ACTTORW_SHIFT) |
+ (5 << TIMING_CFG1_REFREC_SHIFT) |
+ (3 << TIMING_CFG1_WRREC_SHIFT) |
+ (3 << TIMING_CFG1_ACTTOACT_SHIFT) |
+ (1 << TIMING_CFG1_WRTORD_SHIFT) |
+ (TIMING_CFG1_CASLAT & TIMING_CASLAT);
+
+ im->ddr.timing_cfg_2 =
+ TIMING_CFG2_CPO_DEF |
+ (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT);
+ SYNC;
+
+ /* don't enable DDR controller yet */
+ im->ddr.sdram_cfg =
+ SDRAM_CFG_SREN |
+ SDRAM_CFG_SDRAM_TYPE_DDR;
+ SYNC;
+
+ /* Set SDRAM mode */
+ im->ddr.sdram_mode =
+ ((DDR_MODE_EXT_MODEREG | DDR_MODE_WEAK) <<
+ SDRAM_MODE_ESD_SHIFT) |
+ ((DDR_MODE_MODEREG | DDR_MODE_BLEN_4) <<
+ SDRAM_MODE_SD_SHIFT) |
+ ((DDR_MODE_CASLAT << SDRAM_MODE_SD_SHIFT) &
+ MODE_CASLAT);
+ SYNC;
+
+ /* Set fast SDRAM refresh rate */
+ im->ddr.sdram_interval =
+ (DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) |
+ (DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT);
+ SYNC;
+}
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc83xx/start.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ . = ALIGN(16);
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+ENTRY(_start)
+++ /dev/null
-/*
- * Copyright 2004 Freescale Semiconductor.
- * Copyright (C) 2002,2003, Motorola Inc.
- * Xianghua Xiao <X.Xiao@motorola.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <config.h>
-#include <mpc85xx.h>
-
-
-/*
- * TLB0 and TLB1 Entries
- *
- * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
- * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
- * these TLB entries are established.
- *
- * The TLB entries for DDR are dynamically setup in spd_sdram()
- * and use TLB1 Entries 8 through 15 as needed according to the
- * size of DDR memory.
- *
- * MAS0: tlbsel, esel, nv
- * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
- * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
- */
-
-#define entry_start \
- mflr r1 ; \
- bl 0f ;
-
-#define entry_end \
-0: mflr r0 ; \
- mtlr r1 ; \
- blr ;
-
-
- .section .bootpg, "ax"
- .globl tlb1_entry
-tlb1_entry:
- entry_start
-
- /*
- * Number of TLB0 and TLB1 entries in the following table
- */
- .long 13
-
- /*
- * TLB0 16K Cacheable, non-guarded
- * 0xd001_0000 16K Temporary Global data for initialization
- *
- * Use four 4K TLB0 entries. These entries must be cacheable
- * as they provide the bootstrap memory before the memory
- * controler and real memory have been configured.
- *
- * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
- * and must not collide with other TLB0 entries.
- */
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
-
- /*
- * TLB 0, 1: 32M Non-cacheable, guarded
- * 0xfe000000 32M FLASH
- * Out of reset this entry is only 4K.
- */
- .long TLB1_MAS0(1, 1, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
- .long TLB1_MAS0(1, 0, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE+0x1000000), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE+0x1000000), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 2: 256M Non-cacheable, guarded
- * 0x80000000 256M PCI1 MEM First half
- */
- .long TLB1_MAS0(1, 2, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 3: 256M Non-cacheable, guarded
- * 0x90000000 256M PCI1 MEM Second half
- */
- .long TLB1_MAS0(1, 3, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
- 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 4: 256M Non-cacheable, guarded
- * 0xc0000000 256M Rapid IO MEM First half
- */
- .long TLB1_MAS0(1, 4, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 5: 256M Non-cacheable, guarded
- * 0xd0000000 256M Rapid IO MEM Second half
- */
- .long TLB1_MAS0(1, 5, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
- 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 6: 64M Non-cacheable, guarded
- * 0xe000_0000 1M CCSRBAR
- * 0xe200_0000 16M PCI1 IO
- */
- .long TLB1_MAS0(1, 6, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
-
-#if !defined(CONFIG_SPD_EEPROM)
- /*
- * TLB 7: 256M DDR
- * 0x00000000 256M DDR System memory
- * Without SPD EEPROM configured DDR, this must be setup manually.
- * Make sure the TLB count at the top of this table is correct.
- * Likely it needs to be increased by two for these entries.
- */
- .long TLB1_MAS0(1, 7, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
- .long TLB1_MAS0(1, 8, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,0,1,0,1,0,1)
-#endif
-
- entry_end
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G
- * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
- * 0xc000_0000 0xdfff_ffff RapidIO 512M
- * 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
- * 0xf800_0000 0xf80f_ffff BCSR 1M
- * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
- *
- * Notes:
- * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-#if !defined(CONFIG_SPD_EEPROM)
-#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M))
-#else
-#define LAWBAR0 0
-#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
-#endif
-
-#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-#define LAWBAR2 ((CFG_LBC_FLASH_BASE>>12) & 0xfffff)
-#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
-
-#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
-#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
-
-/*
- * Rapid IO at 0xc000_0000 for 512 M
- */
-#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
-#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-
- .section .bootpg, "ax"
- .globl law_entry
-law_entry:
- entry_start
- .long 0x05
- .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
- .long LAWBAR4,LAWAR4
- entry_end
+++ /dev/null
-/*
- * Copyright 2005 DENX Software Engineering
- * Copyright 2004 Freescale Semiconductor.
- * (C) Copyright 2002,2003, Motorola Inc.
- * Xianghua Xiao, (X.Xiao@motorola.com)
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <spd.h>
-
-#if defined(CONFIG_DDR_ECC)
-extern void ddr_enable_ecc (unsigned int dram_size);
-#endif
-
-extern long int spd_sdram (void);
-
-void local_bus_init (void);
-long int fixed_sdram (void);
-
-
-int board_early_init_f (void)
-{
- return 0;
-}
-
-int checkboard (void)
-{
- puts ("Board: TQM8540\n");
-
-#ifdef CONFIG_PCI
- printf ("PCI1: 32 bit, %d MHz (compiled)\n",
- CONFIG_SYS_CLK_FREQ / 1000000);
-#else
- printf ("PCI1: disabled\n");
-#endif
- /*
- * Initialize local bus.
- */
- local_bus_init ();
-
- return 0;
-}
-
-
-long int initdram (int board_type)
-{
- long dram_size = 0;
- extern long spd_sdram (void);
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
-
-#if defined(CONFIG_DDR_DLL)
- {
- volatile ccsr_gur_t *gur = &immap->im_gur;
- uint temp_ddrdll = 0;
-
- /*
- * Work around to stabilize DDR DLL
- */
- temp_ddrdll = gur->ddrdllcr;
- gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
- asm ("sync;isync;msync");
- }
-#endif
-
-#if defined(CONFIG_SPD_EEPROM)
- dram_size = spd_sdram ();
-#else
- dram_size = fixed_sdram ();
-#endif
-
-#if defined(CONFIG_DDR_ECC)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc (dram_size);
-#endif
-
- return dram_size;
-}
-
-
-/*
- * Initialize Local Bus
- */
-
-void local_bus_init (void)
-{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
-
- uint clkdiv;
- uint lbc_hz;
- sys_info_t sysinfo;
-
- /*
- * Errata LBC11.
- * Fix Local Bus clock glitch when DLL is enabled.
- *
- * If localbus freq is < 66Mhz, DLL bypass mode must be used.
- * If localbus freq is > 133Mhz, DLL can be safely enabled.
- * Between 66 and 133, the DLL is enabled with an override workaround.
- */
-
- get_sys_info (&sysinfo);
- clkdiv = lbc->lcrr & 0x0f;
- lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
-
- if (lbc_hz < 66) {
- lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
- lbc->ltedr = 0xa4c80000; /* DK: !!! */
-
- } else if (lbc_hz >= 133) {
- lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
-
- } else {
- /*
- * On REV1 boards, need to change CLKDIV before enable DLL.
- * Default CLKDIV is 8, change it to 4 temporarily.
- */
- uint pvr = get_pvr ();
- uint temp_lbcdll = 0;
-
- if (pvr == PVR_85xx_REV1) {
- /* FIXME: Justify the high bit here. */
- lbc->lcrr = 0x10000004;
- }
-
- lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
- udelay (200);
-
- /*
- * Sample LBC DLL ctrl reg, upshift it to set the
- * override bits.
- */
- temp_lbcdll = gur->lbcdllcr;
- gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
- asm ("sync;isync;msync");
- }
-}
-
-
-#if defined(CFG_DRAM_TEST)
-int testdram (void)
-{
- uint *pstart = (uint *) CFG_MEMTEST_START;
- uint *pend = (uint *) CFG_MEMTEST_END;
- uint *p;
-
- printf ("SDRAM test phase 1:\n");
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf ("SDRAM test phase 2:\n");
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf ("SDRAM test passed.\n");
- return 0;
-}
-#endif
-
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- * fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-long int fixed_sdram (void)
-{
-#ifndef CFG_RAMBOOT
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
- volatile ccsr_ddr_t *ddr = &immap->im_ddr;
-
- ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
- ddr->cs0_config = CFG_DDR_CS0_CONFIG;
- ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
- ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
- ddr->sdram_mode = CFG_DDR_MODE;
- ddr->sdram_interval = CFG_DDR_INTERVAL;
- ddr->err_disable = 0x0000000D;
-#if defined (CONFIG_DDR_ECC)
- ddr->err_disable = 0x0000000D;
- ddr->err_sbe = 0x00ff0000;
-#endif
- asm ("sync;isync;msync");
- udelay (500);
-#if defined (CONFIG_DDR_ECC)
- /* Enable ECC checking */
- ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
-#else
- ddr->sdram_cfg = CFG_DDR_CONTROL;
-#endif
- asm ("sync; isync; msync");
- udelay (500);
-#endif
- return get_ram_size (0, CFG_SDRAM_SIZE * 1024 * 1024);
-}
-#endif /* !defined(CONFIG_SPD_EEPROM) */
-
-
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI Devices, report devices found.
- */
-
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc85xxads_config_table[] = {
- {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_IDSEL_NUMBER, PCI_ANY_ID,
- pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY |
- PCI_COMMAND_MASTER}},
- {}
-};
-#endif
-
-
-static struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc85xxads_config_table,
-#endif
-};
-
-#endif /* CONFIG_PCI */
-
-
-void pci_init_board (void)
-{
-#ifdef CONFIG_PCI
- extern void pci_mpc85xx_init (struct pci_controller *hose);
-
- pci_mpc85xx_init (&hose);
-#endif /* CONFIG_PCI */
-}
LIB = lib$(BOARD).a
-OBJS := $(BOARD).o
+OBJS := $(BOARD).o sdram.o
SOBJS := init.o
#SOBJS :=
#
#
-# tqm8560 board
+# tqm85xx board
# default CCARBAR is at 0xff700000
# assume U-Boot is less than 256k
#
/*
- * TLB 0, 1: 32M Non-cacheable, guarded
- * 0xfe000000 32M FLASH
+ * TLB 0, 1: 128M Non-cacheable, guarded
+ * 0xf8000000 128M FLASH
* Out of reset this entry is only 4K.
*/
.long TLB1_MAS0(1, 1, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1, 0, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE+0x1000000), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE+0x1000000), 0,0,0,0,0,1,0,1,0,1)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE+0x4000000), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE+0x4000000), 0,0,0,0,0,1,0,1,0,1)
/*
* TLB 2: 256M Non-cacheable, guarded
.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
-#if !defined(CONFIG_SPD_EEPROM)
/*
- * TLB 7: 256M DDR
- * 0x00000000 256M DDR System memory
+ * TLB 7+8: 512M DDR, cache disabled (needed for memory test)
+ * 0x00000000 512M DDR System memory
* Without SPD EEPROM configured DDR, this must be setup manually.
* Make sure the TLB count at the top of this table is correct.
* Likely it needs to be increased by two for these entries.
*/
.long TLB1_MAS0(1, 7, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1, 8, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,0,1,0,1,0,1)
-#endif
entry_end
* If flash is 8M at default position (last 8M), no LAW needed.
*/
-#if !defined(CONFIG_SPD_EEPROM)
#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M))
-#else
-#define LAWBAR0 0
-#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
-#endif
+#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M))
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
#define LAWBAR2 ((CFG_LBC_FLASH_BASE>>12) & 0xfffff)
-#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <spd.h>
+
+struct sdram_conf_s {
+ unsigned long size;
+ unsigned long reg;
+};
+
+typedef struct sdram_conf_s sdram_conf_t;
+
+sdram_conf_t ddr_cs_conf[] = {
+ {(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */
+ {(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */
+ {(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */
+ {(64 << 20), 0x80000001}, /* 64MB, 12x9(4) */
+};
+
+#define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))
+
+int cas_latency(void);
+
+/*
+ * Autodetect onboard DDR SDRAM on 85xx platforms
+ *
+ * NOTE: Some of the hardcoded values are hardware dependant,
+ * so this should be extended for other future boards
+ * using this routine!
+ */
+long int sdram_setup(int casl)
+{
+ int i;
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile ccsr_ddr_t *ddr = &immap->im_ddr;
+ unsigned long cfg_ddr_timing1;
+ unsigned long cfg_ddr_mode;
+
+ /*
+ * Disable memory controller.
+ */
+ ddr->cs0_config = 0;
+ ddr->sdram_cfg = 0;
+
+ switch (casl) {
+ case 20:
+ cfg_ddr_timing1 = 0x47405331 | (3 << 16);
+ cfg_ddr_mode = 0x40020002 | (2 << 4);
+ break;
+
+ case 25:
+ cfg_ddr_timing1 = 0x47405331 | (4 << 16);
+ cfg_ddr_mode = 0x40020002 | (6 << 4);
+ break;
+
+ case 30:
+ default:
+ cfg_ddr_timing1 = 0x47405331 | (5 << 16);
+ cfg_ddr_mode = 0x40020002 | (3 << 4);
+ break;
+ }
+
+ ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
+ ddr->cs0_config = ddr_cs_conf[0].reg;
+ ddr->timing_cfg_1 = cfg_ddr_timing1;
+ ddr->timing_cfg_2 = 0x00000800; /* P9-45,may need tuning */
+ ddr->sdram_mode = cfg_ddr_mode;
+ ddr->sdram_interval = 0x05160100; /* autocharge,no open page */
+ ddr->err_disable = 0x0000000D;
+
+ asm ("sync;isync;msync");
+ udelay(1000);
+
+ ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */
+ asm ("sync; isync; msync");
+ udelay(1000);
+
+ for (i=0; i<N_DDR_CS_CONF; i++) {
+ ddr->cs0_config = ddr_cs_conf[i].reg;
+
+ if (get_ram_size(0, ddr_cs_conf[i].size) == ddr_cs_conf[i].size) {
+ /*
+ * OK, size detected -> all done
+ */
+ return ddr_cs_conf[i].size;
+ }
+ }
+
+ return 0; /* nothing found ! */
+}
+
+void board_add_ram_info(int use_default)
+{
+ int casl;
+
+ if (use_default)
+ casl = CONFIG_DDR_DEFAULT_CL;
+ else
+ casl = cas_latency();
+
+ puts(" (CL=");
+ switch (casl) {
+ case 20:
+ puts("2)");
+ break;
+
+ case 25:
+ puts("2.5)");
+ break;
+
+ case 30:
+ puts("3)");
+ break;
+ }
+}
+
+long int initdram (int board_type)
+{
+ long dram_size = 0;
+ int casl;
+
+#if defined(CONFIG_DDR_DLL)
+ /*
+ * This DLL-Override only used on TQM8540 and TQM8560
+ */
+ {
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile ccsr_gur_t *gur= &immap->im_gur;
+ int i,x;
+
+ x = 10;
+
+ /*
+ * Work around to stabilize DDR DLL
+ */
+ gur->ddrdllcr = 0x81000000;
+ asm("sync;isync;msync");
+ udelay (200);
+ while (gur->ddrdllcr != 0x81000100) {
+ gur->devdisr = gur->devdisr | 0x00010000;
+ asm("sync;isync;msync");
+ for (i=0; i<x; i++)
+ ;
+ gur->devdisr = gur->devdisr & 0xfff7ffff;
+ asm("sync;isync;msync");
+ x++;
+ }
+ }
+#endif
+
+ casl = cas_latency();
+ dram_size = sdram_setup(casl);
+ if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) {
+ /*
+ * Try again with default CAS latency
+ */
+ puts("Problem with CAS lantency");
+ board_add_ram_info(1);
+ puts(", using default CL!\n");
+ casl = CONFIG_DDR_DEFAULT_CL;
+ dram_size = sdram_setup(casl);
+ puts(" ");
+ }
+
+ return dram_size;
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ printf ("SDRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf ("SDRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf ("SDRAM test passed.\n");
+ return 0;
+}
+#endif
/*
- * Copyright 2005 DENX Software Engineering
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
* Copyright 2004 Freescale Semiconductor.
* (C) Copyright 2002,2003, Motorola Inc.
* Xianghua Xiao, (X.Xiao@motorola.com)
#include <asm/immap_85xx.h>
#include <ioports.h>
#include <spd.h>
+#include <flash.h>
-#if defined(CONFIG_DDR_ECC)
-extern void ddr_enable_ecc (unsigned int dram_size);
-#endif
-
-extern long int spd_sdram (void);
+extern flash_info_t flash_info[]; /* FLASH chips info */
void local_bus_init (void);
long int fixed_sdram (void);
+ulong flash_get_size (ulong base, int banknum);
+#ifdef CONFIG_CPM2
/*
* I/O Port configuration table
*
/* Port A configuration */
{ /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
- /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
- /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
- /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
- /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
- /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
+ /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
+ /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
+ /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
+ /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
+ /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
+ /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
- /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
- /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
- /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
- /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
- /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
- /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
- /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
- /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
+ /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
+ /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
+ /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
+ /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
+ /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
+ /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
+ /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
+ /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
/* Port B configuration */
{ /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
/* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
/* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
/* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
- /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
- /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
- /* PC19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
+ /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
+ /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
+ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
/* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
+ /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
/* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
/* PC13 */ { 0, 1, 0, 0, 0, 0 }, /* PC13 */
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
}
};
+#endif /* CONFIG_CPM2 */
+
+#define CASL_STRING1 "casl=xx"
+#define CASL_STRING2 "casl="
+static const int casl_table[] = { 20, 25, 30 };
+#define N_CASL (sizeof(casl_table) / sizeof(casl_table[0]))
-int board_early_init_f (void)
+int cas_latency(void)
{
- return 0;
+ char *s = getenv("serial#");
+ int casl;
+ int val;
+ int i;
+
+ casl = CONFIG_DDR_DEFAULT_CL;
+
+ if (s != NULL) {
+ if (strncmp(s + strlen(s) - strlen(CASL_STRING1), CASL_STRING2,
+ strlen(CASL_STRING2)) == 0) {
+ val = simple_strtoul(s + strlen(s) - 2, NULL, 10);
+
+ for (i=0; i<N_CASL; ++i) {
+ if (val == casl_table[i]) {
+ return val;
+ }
+ }
+ }
+ }
+
+ return casl;
}
int checkboard (void)
{
- puts ("Board: TQM8560\n");
+ char *s = getenv("serial#");
+
+ printf("Board: %s", CONFIG_BOARDNAME);
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ putc('\n');
#ifdef CONFIG_PCI
printf ("PCI1: 32 bit, %d MHz (compiled)\n",
#else
printf ("PCI1: disabled\n");
#endif
+
/*
* Initialize local bus.
*/
return 0;
}
-
-long int initdram (int board_type)
+int misc_init_r (void)
{
- long dram_size = 0;
- extern long spd_sdram (void);
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ DECLARE_GLOBAL_DATA_PTR;
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_lbc_t *memctl = &immap->im_lbc;
-#if defined(CONFIG_DDR_DLL)
- {
- volatile ccsr_gur_t *gur = &immap->im_gur;
- uint temp_ddrdll = 0;
+ /*
+ * Adjust flash start and offset to detected values
+ */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+ /*
+ * Check if boot FLASH isn't max size
+ */
+ if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) {
+ memctl->or0 = gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff);
+ memctl->br0 = gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff);
/*
- * Work around to stabilize DDR DLL
+ * Re-check to get correct base address
*/
- temp_ddrdll = gur->ddrdllcr;
- gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
- asm ("sync;isync;msync");
+ flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
}
-#endif
-#if defined(CONFIG_SPD_EEPROM)
- dram_size = spd_sdram ();
-#else
- dram_size = fixed_sdram ();
-#endif
-
-#if defined(CONFIG_DDR_ECC)
/*
- * Initialize and enable DDR ECC.
+ * Check if only one FLASH bank is available
*/
- ddr_enable_ecc (dram_size);
-#endif
+ if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
+ memctl->or1 = 0;
+ memctl->br1 = 0;
- return dram_size;
-}
+ /*
+ * Re-do flash protection upon new addresses
+ */
+ flash_protect (FLAG_PROTECT_CLEAR,
+ gd->bd->bi_flashstart, 0xffffffff,
+ &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+
+ /* Monitor protection ON by default */
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE, 0xffffffff,
+ &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+
+ /* Environment protection ON by default */
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+
+ /* Redundant environment protection ON by default */
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
+ &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+ }
+ return 0;
+}
/*
* Initialize Local Bus
*/
-
void local_bus_init (void)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
}
}
-
-#if defined(CFG_DRAM_TEST)
-int testdram (void)
-{
- uint *pstart = (uint *) CFG_MEMTEST_START;
- uint *pend = (uint *) CFG_MEMTEST_END;
- uint *p;
-
- printf ("SDRAM test phase 1:\n");
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf ("SDRAM test phase 2:\n");
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf ("SDRAM test passed.\n");
- return 0;
-}
-#endif
-
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- * fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-long int fixed_sdram (void)
-{
-#ifndef CFG_RAMBOOT
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
- volatile ccsr_ddr_t *ddr = &immap->im_ddr;
-
- ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
- ddr->cs0_config = CFG_DDR_CS0_CONFIG;
- ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
- ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
- ddr->sdram_mode = CFG_DDR_MODE;
- ddr->sdram_interval = CFG_DDR_INTERVAL;
- ddr->err_disable = 0x0000000D;
-#if defined (CONFIG_DDR_ECC)
- ddr->err_disable = 0x0000000D;
- ddr->err_sbe = 0x00ff0000;
-#endif
- asm ("sync;isync;msync");
- udelay (500);
-#if defined (CONFIG_DDR_ECC)
- /* Enable ECC checking */
- ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
-#else
- ddr->sdram_cfg = CFG_DDR_CONTROL;
-#endif
- asm ("sync; isync; msync");
- udelay (500);
-#endif
- return get_ram_size (0, CFG_SDRAM_SIZE * 1024 * 1024);
-}
-#endif /* !defined(CONFIG_SPD_EEPROM) */
-
-
#if defined(CONFIG_PCI)
/*
* Initialize PCI Devices, report devices found.
.bootpg 0xFFFFF000 :
{
cpu/mpc85xx/start.o (.bootpg)
- board/tqm8540/init.o (.bootpg)
+ board/tqm85xx/init.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
.text :
{
cpu/mpc85xx/start.o (.text)
- board/tqm8540/init.o (.text)
+ board/tqm85xx/init.o (.text)
cpu/mpc85xx/traps.o (.text)
cpu/mpc85xx/interrupts.o (.text)
cpu/mpc85xx/cpu_init.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
/* set serial# and ethaddr if not yet defined */
if (getenv("serial#") == NULL) {
- setenv ("serial#", serial);
+ setenv ((char *)"serial#", (char *)serial);
}
if (getenv("ethaddr") == NULL) {
- setenv ("ethaddr", ethaddr);
+ setenv ((char *)"ethaddr", (char *)ethaddr);
}
}
{
DECLARE_GLOBAL_DATA_PTR;
- unsigned char *s = getenv ("serial#");
+ char *s = getenv ("serial#");
puts ("Board: ");
*
* try 8 column mode
*/
- size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE2_PRELIM,
+ size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
/*
* try 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE2_PRELIM,
+ size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
* [9 column SDRAM may also be used in 8 column mode,
* but then only half the real size will be used.]
*/
- size_b1 = dram_size (memctl->memc_mamr, (ulong *) SDRAM_BASE3_PRELIM,
+ size_b1 = dram_size (memctl->memc_mamr, (long int *)SDRAM_BASE3_PRELIM,
SDRAM_MAX_SIZE);
debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20);
} else {
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
#endif
extern int flash_sect_erase(ulong, ulong);
extern int flash_sect_protect (int, ulong, ulong);
-extern int flash_write (uchar *, ulong, ulong);
+extern int flash_write (char *, ulong, ulong);
/* change char* to void* to shutup the compiler */
extern int i2c_write_multiple (uchar, uint, int, void *, int);
extern int i2c_read_multiple (uchar, uint, int, void *, int);
/* recycle checksum */
checksum = ntohl(hdr->ih_size);
/* for kernel and app the image header must also fit into flash */
- if (idx != IDX_DISK)
+ if ((idx != IDX_DISK) && (idx != IDX_FIRMWARE))
checksum += sizeof(*hdr);
/* check the size does not exceed space in flash. HUSH scripts */
/* all have ausize[] set to 0 */
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
#include <i2c.h>
#include <miiphy.h>
+int fec8xx_miiphy_write(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value);
/*********************************************************************/
/* UPMA Pre Initilization Table by WV (Miron MT48LC16M16A2-7E B) */
*/
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
puts ("Board: ");
*/
mii_init();
- miiphy_write(0, PHY_BMCR, 0x2100); /* disable auto-negotiation, 100mbit, full-duplex */
- miiphy_write(0, PHY_FCSCR, 0x4122); /* set LED's to Link, Transmit, Receive */
+ /* disable auto-negotiation, 100mbit, full-duplex */
+ fec8xx_miiphy_write(NULL, 0, PHY_BMCR, 0x2100);
+
+ /* set LED's to Link, Transmit, Receive */
+ fec8xx_miiphy_write(NULL, 0, PHY_FCSCR, 0x4122);
return 0;
}
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
LIB = lib$(BOARD).a
OBJS := versatile.o flash.o
-SOBJS := platform.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
#include <config.h>
#include <version.h>
-.globl platformsetup
-platformsetup:
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
/* All done by Versatile's boot monitor! */
mov pc, lr
--- /dev/null
+#!/bin/sh
+# ---------------------------------------------------------
+# Set the core module defines according to Core Module
+# ---------------------------------------------------------
+# ---------------------------------------------------------
+# Set up the Versatile type define
+# ---------------------------------------------------------
+variant=PB926EJ-S
+if [ "$1" == "" ]
+then
+ echo "$0:: No parameters - using versatilepb_config"
+ echo "#define CONFIG_ARCH_VERSATILE_PB" > ./include/config.h
+ variant=PB926EJ-S
+else
+ case "$1" in
+ versatilepb_config | \
+ versatile_config)
+ echo "#define CONFIG_ARCH_VERSATILE_PB" > ./include/config.h
+ ;;
+
+ versatileab_config)
+ echo "#define CONFIG_ARCH_VERSATILE_AB" > ./include/config.h
+ variant=AB926EJ-S
+ ;;
+
+
+ *)
+ echo "$0:: Unrecognised config - using versatilepb_config"
+ echo "#define CONFIG_ARCH_VERSATILE_PB" > ./include/config.h
+ variant=PB926EJ-S
+ ;;
+
+ esac
+
+fi
+# ---------------------------------------------------------
+# Complete the configuration
+# ---------------------------------------------------------
+./mkconfig -a versatile arm arm926ejs versatile
+echo "Variant:: $variant"
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
.byte 0x0c @ COMP_MODE_CTRL_0
.byte 0xff
-.globl platformsetup
-platformsetup:
+.globl lowlevel_init
+lowlevel_init:
/* Improve performance a bit... */
mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register
mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
int flag;
ulong status;
int rcode = 0;
- volatile long *addr = (unsigned long *)sector;
+ volatile long *addr = (long *)sector;
switch(info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F320J3A:
int flag;
ulong status;
int rcode = 0;
- volatile long *addr = (unsigned long *)sector;
+ volatile long *addr = (long *)sector;
switch(info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F320J3A:
dest = (unsigned short *)daddr;
/* Get DCR output register */
- grego = in32(IBM405GP_GPIO0_OR);
+ grego = in32(PPC405GP_GPIO0_OR);
/* Reset FPGA */
grego &= ~GPIO_XCV_PROG; /* PROG line low */
- out32(IBM405GP_GPIO0_OR, grego);
+ out32(PPC405GP_GPIO0_OR, grego);
/* Setup timeout timer */
start = get_timer(0);
/* Wait for FPGA init line */
- while(in32(IBM405GP_GPIO0_IR) & GPIO_XCV_INIT) { /* Wait INIT line low */
+ while(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT) { /* Wait INIT line low */
/* Check for timeout - 100us max, so use 3ms */
if (get_timer(start) > 3) {
printf(" failed to start init.\n");
/* Unreset FPGA */
grego |= GPIO_XCV_PROG; /* PROG line high */
- out32(IBM405GP_GPIO0_OR, grego);
+ out32(PPC405GP_GPIO0_OR, grego);
/* Wait for FPGA end of init period . */
- while(!(in32(IBM405GP_GPIO0_IR) & GPIO_XCV_INIT)) { /* Wait for INIT hi */
+ while(!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT)) { /* Wait for INIT hi */
/* Check for timeout */
if (get_timer(start) > 3) {
/* Reset FPGA */
grego &= ~GPIO_XCV_PROG; /* PROG line low */
- out32(IBM405GP_GPIO0_OR, grego);
+ out32(PPC405GP_GPIO0_OR, grego);
goto done;
}
mtdcr(CPC0_CR0, greg); /* ... just do it */
/* turn on open drain for CNFG */
- greg = in32(IBM405GP_GPIO0_ODR); /* get open drain register */
+ greg = in32(PPC405GP_GPIO0_ODR); /* get open drain register */
greg |= cnfg; /* CNFG open drain */
- out32(IBM405GP_GPIO0_ODR, greg); /* .. just do it */
+ out32(PPC405GP_GPIO0_ODR, greg); /* .. just do it */
/* Turn output enable on for CNFG */
- greg = in32(IBM405GP_GPIO0_TCR); /* get tristate register */
+ greg = in32(PPC405GP_GPIO0_TCR); /* get tristate register */
greg |= cnfg; /* CNFG tristate inactive */
- out32(IBM405GP_GPIO0_TCR, greg); /* ... just do it */
+ out32(PPC405GP_GPIO0_TCR, greg); /* ... just do it */
/* Setup FPGA for programming */
grego &= ~cnfg; /* CONFIG line low */
- out32(IBM405GP_GPIO0_OR, grego);
+ out32(PPC405GP_GPIO0_OR, grego);
/*
* Program the FPGA
/* Done programming */
grego |= cnfg; /* CONFIG line high */
- out32(IBM405GP_GPIO0_OR, grego);
+ out32(PPC405GP_GPIO0_OR, grego);
/* Turn output enable OFF for CNFG */
- greg = in32(IBM405GP_GPIO0_TCR); /* get tristate register */
+ greg = in32(PPC405GP_GPIO0_TCR); /* get tristate register */
greg &= ~cnfg; /* CNFG tristate inactive */
- out32(IBM405GP_GPIO0_TCR, greg); /* ... just do it */
+ out32(PPC405GP_GPIO0_TCR, greg); /* ... just do it */
/* Toggle IRQ/GPIO */
greg = mfdcr(CPC0_CR0); /* get chip ctrl register */
start = get_timer(0);
/* Wait for FPGA end of programming period . */
- while(!(in32(IBM405GP_GPIO0_IR) & GPIO_XCV_DONE)) { /* Test DONE low */
+ while(!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_DONE)) { /* Test DONE low */
/* Check for timeout */
if (get_timer(start) > 3) {
/* Reset FPGA */
grego &= ~GPIO_XCV_PROG; /* PROG line low */
- out32(IBM405GP_GPIO0_OR, grego);
+ out32(PPC405GP_GPIO0_OR, grego);
goto done;
}
xcv_len = len - 14 - fn_len; /* fpga image length */
/* Check for uninitialized FLASH */
- if ((strncmp(buf, "w7o", 3)!=0) || (len > 0x0007ffffL) || (len == 0))
+ if ((strncmp((char *)buf, "w7o", 3)!=0) || (len > 0x0007ffffL) || (len == 0))
goto bad_image;
/*
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
unsigned short stored_crc16, calc_crc16 = 0xffff;
/* Check Eyecatcher */
- if (strncmp(vpd->header.eyecatcher, VPD_EYECATCHER, VPD_EYE_SIZE) != 0) {
+ if (strncmp((char *)(vpd->header.eyecatcher), VPD_EYECATCHER, VPD_EYE_SIZE) != 0) {
unsigned offset = 0;
if (dev_addr == CFG_DEF_EEPROM_ADDR)
offset += SDRAM_SPD_DATA_SIZE;
case VPD_PID_PID:
if (strlen_ok(packet, MAX_PROD_ID)) {
strncpy(vpdInfo->productId,
- packet->data, packet->size);
+ (char *)(packet->data), packet->size);
}
break;
case VPD_PID_REV:
/*
* Setup GPIO pins - reset devices.
*/
- out32 (IBM405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */
- out32 (IBM405GP_GPIO0_OR, 0x3E000000); /* set output pins to default */
- out32 (IBM405GP_GPIO0_TCR, 0x7f800000); /* setup for output */
+ out32 (PPC405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */
+ out32 (PPC405GP_GPIO0_OR, 0x3E000000); /* set output pins to default */
+ out32 (PPC405GP_GPIO0_TCR, 0x7f800000); /* setup for output */
/*
* IRQ 0-15 405GP internally generated; active high; level sensitive
/*
* Setup GPIO pins
*/
- out32 (IBM405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */
- out32 (IBM405GP_GPIO0_OR, 0x03800000); /* set out pins to default */
- out32 (IBM405GP_GPIO0_TCR, 0x66C00000); /* setup for output */
+ out32 (PPC405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */
+ out32 (PPC405GP_GPIO0_OR, 0x03800000); /* set out pins to default */
+ out32 (PPC405GP_GPIO0_TCR, 0x66C00000); /* setup for output */
/*
* IRQ 0-15 405GP internally generated; active high; level sensitive
(strncmp (vpd->productId, "CMM", 3) == 0))) {
char buf[30];
char *eth;
- unsigned char *serial = getenv ("serial#");
- unsigned char *ethaddr = getenv ("ethaddr");
+ char *serial = getenv ("serial#");
+ char *ethaddr = getenv ("ethaddr");
/* Set 'serial#' envvar if serial# isn't set */
if (!serial) {
}
/* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */
- eth = vpd->ethAddrs[0];
+ eth = (char *)(vpd->ethAddrs[0]);
if (ethaddr
&& (strcmp (ethaddr, MK_STR (CONFIG_ETHADDR)) == 0)) {
/* Now setup ethaddr */
#if defined(CONFIG_W7OLMG)
unsigned long greg; /* GPIO Register */
- greg = in32 (IBM405GP_GPIO0_OR);
+ greg = in32 (PPC405GP_GPIO0_OR);
/*
* XXX - Unreset devices - this should be moved into VxWorks driver code
*/
greg |= 0x41800000L; /* SAM, PHY, Galileo */
- out32 (IBM405GP_GPIO0_OR, greg); /* set output pins to default */
+ out32 (PPC405GP_GPIO0_OR, greg); /* set output pins to default */
#endif /* CONFIG_W7OLMG */
/*
#define _W7O_H_
#include <config.h>
-/* IBM 405GP PowerPC GPIO registers */
-#define IBM405GP_GPIO0_OR 0xef600700L /* GPIO Output */
-#define IBM405GP_GPIO0_TCR 0xef600704L /* GPIO Three-State Control */
-#define IBM405GP_GPIO0_ODR 0xef600718L /* GPIO Open Drain */
-#define IBM405GP_GPIO0_IR 0xef60071cL /* GPIO Input */
+/* AMCC 405GP PowerPC GPIO registers */
+#define PPC405GP_GPIO0_OR 0xef600700L /* GPIO Output */
+#define PPC405GP_GPIO0_TCR 0xef600704L /* GPIO Three-State Control */
+#define PPC405GP_GPIO0_ODR 0xef600718L /* GPIO Open Drain */
+#define PPC405GP_GPIO0_IR 0xef60071cL /* GPIO Input */
-/* IBM 405GP DCRs */
+/* AMCC 405GP DCRs */
#define CPC0_CR0 0xb1 /* Chip control register 0 */
/* LMG FPGA <=> CPU GPIO signals */
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
/* initialize the version of the component
*/
- XVersion_FromString(&InstancePtr->Version, "1.00a");
+ XVersion_FromString(&InstancePtr->Version, (s8 *)"1.00a");
/* reset the DMA channel such that it's in a known state and ready
* and indicate the initialization occured with no errors, note that
int
checkboard(void)
{
- uchar tmp[64]; /* long enough for environment variables */
- uchar *s, *e;
+ char tmp[64]; /* long enough for environment variables */
+ char *s, *e;
int i = getenv_r("L", tmp, sizeof (tmp));
if (i < 0) {
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
+ cpu/ppc4xx/4xx_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
RecvFrameLength = PKTSIZE;
Result = XEmac_PollRecv(&Emac, (u8 *) etherrxbuff, &RecvFrameLength);
if (Result == XST_SUCCESS) {
- NetReceive(etherrxbuff, RecvFrameLength);
+ NetReceive((uchar *)etherrxbuff, RecvFrameLength);
return (1);
} else {
return (0);
static void
ip_ml300(uchar * s, uchar * res)
{
- uchar temp[2];
+ char temp[2];
u8 i;
res[0] = 0x00;
for (i = 0; i < 4; i++) {
sprintf(temp, "%02x", atoi(s));
- s = strchr(s, '.') + 1;
- strcat(res, temp);
+ s = (uchar *)strchr((char *)s, '.') + 1;
+ strcat((char *)res, temp);
}
}
change_null(uchar * s)
{
if (s != NULL) {
- change_null(strchr(s + 1, 255));
- *(strchr(s, 255)) = '\0';
+ change_null((uchar *)strchr((char *)s + 1, 255));
+ *(strchr((char *)s, 255)) = '\0';
}
}
void
convert_env(void)
{
- uchar *s; /* pointer to env value */
- uchar temp[20]; /* temp storage for addresses */
+ char *s; /* pointer to env value */
+ char temp[20]; /* temp storage for addresses */
/* E -> ethaddr */
s = getenv("E");
/* I -> ipaddr */
s = getenv("I");
if (s != NULL) {
- sprintf(temp, "%d.%d.%d.%d", axtoi(s), axtoi(s + 2),
- axtoi(s + 4), axtoi(s + 6));
+ sprintf(temp, "%d.%d.%d.%d", axtoi((u8 *)s), axtoi((u8 *)(s + 2)),
+ axtoi((u8 *)(s + 4)), axtoi((u8 *)(s + 6)));
setenv("ipaddr", temp);
setenv("I", NULL);
}
/* S -> serverip */
s = getenv("S");
if (s != NULL) {
- sprintf(temp, "%d.%d.%d.%d", axtoi(s), axtoi(s + 2),
- axtoi(s + 4), axtoi(s + 6));
+ sprintf(temp, "%d.%d.%d.%d", axtoi((u8 *)s), axtoi((u8 *)(s + 2)),
+ axtoi((u8 *)(s + 4)), axtoi((u8 *)(s + 6)));
setenv("serverip", temp);
setenv("S", NULL);
}
static void
save_env(void)
{
- uchar eprom[ENV_SIZE]; /* buffer to be written back to EEPROM */
- uchar *s, temp[20];
- uchar ff[] = { 0xff, 0x00 }; /* dummy null value */
+ char eprom[ENV_SIZE]; /* buffer to be written back to EEPROM */
+ char *s, temp[20];
+ char ff[] = { 0xff, 0x00 }; /* dummy null value */
u32 len; /* length of env to be written to EEPROM */
eprom[0] = 0x00;
s = getenv("ipaddr");
if (s != NULL) {
strcat(eprom, "I=");
- ip_ml300(s, temp);
+ ip_ml300((uchar *)s, (uchar *)temp);
strcat(eprom, temp);
strcat(eprom, ff);
}
s = getenv("serverip");
if (s != NULL) {
strcat(eprom, "S=");
- ip_ml300(s, temp);
+ ip_ml300((uchar *)s, (uchar *)temp);
strcat(eprom, temp);
strcat(eprom, ff);
}
}
len = strlen(eprom); /* find env length without crc */
- change_null(eprom); /* change 0xff to 0x00 */
+ change_null((uchar *)eprom); /* change 0xff to 0x00 */
/* update EEPROM env values if there is enough space */
- if (update_crc(len, eprom) == 0)
- send(CFG_ENV_OFFSET, eprom, len + 6);
+ if (update_crc(len, (uchar *)eprom) == 0)
+ send(CFG_ENV_OFFSET, (uchar *)eprom, len + 6);
}
/************************************************************************
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
int checkboard (void)
{
- sys_info_t sysinfo;
- get_sys_info (&sysinfo);
-
printf ("Board: XES XPedite1000 440GX\n");
- printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
- printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
- printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
- printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
- printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
return (0);
}
}
switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AMLV128U: printf ("AM29LV128ML (128Mbit, uniform sector size)\n");
- break;
- case FLASH_AMLV320U: printf ("AM29LV320ML (32Mbit, uniform sector size)\n");
- break;
case FLASH_AMLV640U: printf ("AM29LV640ML (64Mbit, uniform sector size)\n");
break;
- case FLASH_AMLV320B: printf ("AM29LV320MB (32Mbit, bottom boot sect)\n");
+ case FLASH_S29GL064M: printf ("S29GL064M (64Mbit, top boot sector size)\n");
break;
default: printf ("Unknown Chip Type\n");
break;
debug ("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n",
addr[14], addr[15]);
switch(addr[14]) {
- case AMD_ID_LV128U_2:
- if (addr[15] != AMD_ID_LV128U_3) {
- debug ("Chip: AMLV128U -> unknown\n");
- info->flash_id = FLASH_UNKNOWN;
- } else {
- debug ("Chip: AMLV128U\n");
- info->flash_id += FLASH_AMLV128U;
- info->sector_count = 256;
- info->size = 0x02000000;
- }
- break; /* => 32 MB */
case AMD_ID_LV640U_2:
if (addr[15] != AMD_ID_LV640U_3) {
debug ("Chip: AMLV640U -> unknown\n");
info->size = 0x01000000;
}
break; /* => 16 MB */
- case AMD_ID_LV320B_2:
- if (addr[15] != AMD_ID_LV320B_3) {
- debug ("Chip: AMLV320B -> unknown\n");
+ case AMD_ID_GL064MT_2:
+ if (addr[15] != AMD_ID_GL064MT_3) {
+ debug ("Chip: S29GL064M-R3 -> unknown\n");
info->flash_id = FLASH_UNKNOWN;
} else {
- debug ("Chip: AMLV320B\n");
- info->flash_id += FLASH_AMLV320B;
- info->sector_count = 71;
- info->size = 0x00800000;
+ debug ("Chip: S29GL064M-R3\n");
+ info->flash_id += FLASH_S29GL064M;
+ info->sector_count = 128;
+ info->size = 0x01000000;
}
- break; /* => 8 MB */
+ break; /* => 16 MB */
default:
debug ("Chip: *** unknown ***\n");
info->flash_id = FLASH_UNKNOWN;
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
cmd_ace.o cmd_autoscript.o \
cmd_bdinfo.o cmd_bedbug.o cmd_bmp.o cmd_boot.o cmd_bootm.o \
cmd_cache.o cmd_console.o \
- cmd_date.o cmd_dcr.o cmd_diag.o cmd_doc.o cmd_dtt.o \
+ cmd_date.o cmd_dcr.o cmd_diag.o cmd_display.o cmd_doc.o cmd_dtt.o \
cmd_eeprom.o cmd_elf.o cmd_ext2.o \
cmd_fat.o cmd_fdc.o cmd_fdos.o cmd_flash.o cmd_fpga.o \
cmd_i2c.o cmd_ide.o cmd_immap.o cmd_itest.o cmd_jffs2.o \
cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \
cmd_nand.o cmd_nand_new.o cmd_net.o cmd_nvedit.o \
cmd_pci.o cmd_pcmcia.o cmd_portio.o \
- cmd_reginfo.o cmd_reiser.o cmd_scsi.o cmd_spi.o cmd_universe.o cmd_usb.o cmd_vfd.o \
+ cmd_reginfo.o cmd_reiser.o cmd_scsi.o cmd_spi.o cmd_universe.o \
+ cmd_usb.o cmd_vfd.o \
command.o console.o devices.o dlmalloc.o docecc.o \
environment.o env_common.o \
- env_nand.o env_dataflash.o env_flash.o env_eeprom.o env_nvram.o env_nowhere.o exports.o \
- flash.o fpga.o \
+ env_nand.o env_dataflash.o env_flash.o env_eeprom.o \
+ env_nvram.o env_nowhere.o \
+ exports.o \
+ flash.o fpga.o ft_build.o \
hush.o kgdb.o lcd.o lists.o lynxkdi.o \
memsize.o miiphybb.o miiphyutil.o \
- s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o \
+ s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o spartan3.o \
usb.o usb_kbd.o usb_storage.o \
virtex2.o xilinx.o
not yet initialized. In that case, fill it in. */
if (systemace_dev.blksz == 0) {
systemace_dev.if_type = IF_TYPE_UNKNOWN;
+ systemace_dev.dev = 0;
systemace_dev.part_type = PART_TYPE_UNKNOWN;
systemace_dev.type = DEV_TYPE_HARDDISK;
systemace_dev.blksz = 512;
hdr->ih_hcrc = 0;
len = sizeof (image_header_t);
data = (ulong)hdr;
- if (crc32(0, (char *)data, len) != crc) {
+ if (crc32(0, (uchar *)data, len) != crc) {
puts ("Bad header crc\n");
return 1;
}
len = ntohl(hdr->ih_size);
if (verify) {
- if (crc32(0, (char *)data, len) != ntohl(hdr->ih_dcrc)) {
+ if (crc32(0, (uchar *)data, len) != ntohl(hdr->ih_dcrc)) {
puts ("Bad data crc\n");
return 1;
}
#include <bmp_layout.h>
#include <command.h>
#include <asm/byteorder.h>
+#include <malloc.h>
#if (CONFIG_COMMANDS & CFG_CMD_BMP)
static int bmp_info (ulong addr);
static int bmp_display (ulong addr, int x, int y);
+int gunzip(void *, int, unsigned char *, unsigned long *);
+
/*
* Subroutine: do_bmp
*
static int bmp_info(ulong addr)
{
bmp_image_t *bmp=(bmp_image_t *)addr;
+#ifdef CONFIG_VIDEO_BMP_GZIP
+ unsigned char *dst = NULL;
+ ulong len;
+#endif /* CONFIG_VIDEO_BMP_GZIP */
+
if (!((bmp->header.signature[0]=='B') &&
(bmp->header.signature[1]=='M'))) {
+
+#ifdef CONFIG_VIDEO_BMP_GZIP
+ /*
+ * Decompress bmp image
+ */
+ len = CFG_VIDEO_LOGO_MAX_SIZE;
+ dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE);
+ if (dst == NULL) {
+ printf("Error: malloc in gunzip failed!\n");
+ return(1);
+ }
+ if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)addr, &len) != 0) {
+ printf("There is no valid bmp file at the given address\n");
+ return(1);
+ }
+ if (len == CFG_VIDEO_LOGO_MAX_SIZE) {
+ printf("Image could be truncated (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n");
+ }
+
+ /*
+ * Set addr to decompressed image
+ */
+ bmp = (bmp_image_t *)dst;
+
+ /*
+ * Check for bmp mark 'BM'
+ */
+ if (!((bmp->header.signature[0] == 'B') &&
+ (bmp->header.signature[1] == 'M'))) {
+ printf("There is no valid bmp file at the given address\n");
+ free(dst);
+ return(1);
+ }
+
+ printf("Gzipped BMP image detected!\n");
+#else /* CONFIG_VIDEO_BMP_GZIP */
printf("There is no valid bmp file at the given address\n");
return(1);
+#endif /* CONFIG_VIDEO_BMP_GZIP */
}
printf("Image size : %d x %d\n", le32_to_cpu(bmp->header.width),
le32_to_cpu(bmp->header.height));
printf("Bits per pixel: %d\n", le16_to_cpu(bmp->header.bit_count));
printf("Compression : %d\n", le32_to_cpu(bmp->header.compression));
+
+#ifdef CONFIG_VIDEO_BMP_GZIP
+ if (dst) {
+ free(dst);
+ }
+#endif /* CONFIG_VIDEO_BMP_GZIP */
+
return(0);
}
#include <environment.h>
#include <asm/byteorder.h>
+#ifdef CONFIG_OF_FLAT_TREE
+#include <ft_build.h>
+#endif
+
/*cmd_boot.c*/
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
#if (CONFIG_COMMANDS & CFG_CMD_IMLS)
#include <flash.h>
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+extern flash_info_t flash_info[]; /* info for FLASH chips */
static int do_imls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
#endif
checksum = ntohl(hdr->ih_hcrc);
hdr->ih_hcrc = 0;
- if (crc32 (0, (char *)data, len) != checksum) {
+ if (crc32 (0, (uchar *)data, len) != checksum) {
puts ("Bad Header Checksum\n");
SHOW_BOOT_PROGRESS (-2);
return 1;
}
SHOW_BOOT_PROGRESS (3);
+#ifdef CONFIG_HAS_DATAFLASH
+ if (addr_dataflash(addr)){
+ len = ntohl(hdr->ih_size) + sizeof(image_header_t);
+ read_dataflash(addr, len, (char *)CFG_LOAD_ADDR);
+ addr = CFG_LOAD_ADDR;
+ }
+#endif
+
+
/* for multi-file images we need the data part, too */
print_image_hdr ((image_header_t *)addr);
data = addr + sizeof(image_header_t);
len = ntohl(hdr->ih_size);
-#ifdef CONFIG_HAS_DATAFLASH
- if (addr_dataflash(addr)){
- read_dataflash(data, len, (char *)CFG_LOAD_ADDR);
- data = CFG_LOAD_ADDR;
- }
-#endif
-
if (verify) {
puts (" Verifying Checksum ... ");
- if (crc32 (0, (char *)data, len) != ntohl(hdr->ih_dcrc)) {
+ if (crc32 (0, (uchar *)data, len) != ntohl(hdr->ih_dcrc)) {
printf ("Bad Data CRC\n");
SHOW_BOOT_PROGRESS (-3);
return 1;
}
#endif /* CONFIG_SILENT_CONSOLE */
+#ifdef CONFIG_OF_FLAT_TREE
+extern const unsigned char oftree_dtb[];
+extern const unsigned int oftree_dtb_len;
+#endif
+
#ifdef CONFIG_PPC
static void
do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
bd_t *kbd;
void (*kernel)(bd_t *, ulong, ulong, ulong, ulong);
image_header_t *hdr = &header;
+#ifdef CONFIG_OF_FLAT_TREE
+ char *of_flat_tree;
+#endif
if ((s = getenv ("initrd_high")) != NULL) {
/* a value of "no" or a similar string will act like 0,
checksum = hdr->ih_hcrc;
hdr->ih_hcrc = 0;
- if (crc32 (0, (char *)data, len) != checksum) {
+ if (crc32 (0, (uchar *)data, len) != checksum) {
puts ("Bad Header Checksum\n");
SHOW_BOOT_PROGRESS (-11);
do_reset (cmdtp, flag, argc, argv);
if (chunk > CHUNKSZ)
chunk = CHUNKSZ;
- csum = crc32 (csum, (char *)cdata, chunk);
+ csum = crc32 (csum, (uchar *)cdata, chunk);
cdata += chunk;
WATCHDOG_RESET();
}
#else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */
- csum = crc32 (0, (char *)data, len);
+ csum = crc32 (0, (uchar *)data, len);
#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */
if (csum != hdr->ih_dcrc) {
initrd_end = 0;
}
+#ifdef CONFIG_OF_FLAT_TREE
+ if (initrd_start == 0)
+ of_flat_tree = (char *)(((ulong)kbd - OF_FLAT_TREE_MAX_SIZE -
+ sizeof(bd_t)) & ~0xF);
+ else
+ of_flat_tree = (char *)((initrd_start - OF_FLAT_TREE_MAX_SIZE -
+ sizeof(bd_t)) & ~0xF);
+#endif
debug ("## Transferring control to Linux (at address %08lx) ...\n",
(ulong)kernel);
SHOW_BOOT_PROGRESS (15);
+#ifndef CONFIG_OF_FLAT_TREE
+
#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500)
unlock_ram_in_cache();
#endif
+
/*
* Linux Kernel Parameters:
* r3: ptr to board info data
* r7: End of command line string
*/
(*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end);
+
+#else
+ ft_setup(of_flat_tree, OF_FLAT_TREE_MAX_SIZE, kbd);
+ /* ft_dump_blob(of_flat_tree); */
+
+#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500)
+ unlock_ram_in_cache();
+#endif
+ /*
+ * Linux Kernel Parameters:
+ * r3: ptr to OF flat tree, followed by the board info data
+ * r4: initrd_start or 0 if no initrd
+ * r5: initrd_end - unused if r4 is 0
+ * r6: Start of command line string
+ * r7: End of command line string
+ */
+ (*kernel) ((bd_t *)of_flat_tree, initrd_start, initrd_end, cmd_start, cmd_end);
+
+#endif
}
#endif /* CONFIG_PPC */
checksum = ntohl(hdr->ih_hcrc);
hdr->ih_hcrc = 0;
- if (crc32 (0, (char *)data, len) != checksum) {
+ if (crc32 (0, (uchar *)data, len) != checksum) {
puts (" Bad Header Checksum\n");
return 1;
}
len = ntohl(hdr->ih_size);
puts (" Verifying Checksum ... ");
- if (crc32 (0, (char *)data, len) != ntohl(hdr->ih_dcrc)) {
+ if (crc32 (0, (uchar *)data, len) != ntohl(hdr->ih_dcrc)) {
puts (" Bad Data CRC\n");
return 1;
}
for (i=0, info=&flash_info[0]; i<CFG_MAX_FLASH_BANKS; ++i, ++info) {
if (info->flash_id == FLASH_UNKNOWN)
goto next_bank;
- for (j=0; j<CFG_MAX_FLASH_SECT; ++j) {
+ for (j=0; j<info->sector_count; ++j) {
if (!(hdr=(image_header_t *)info->start[j]) ||
(ntohl(hdr->ih_magic) != IH_MAGIC))
checksum = ntohl(header.ih_hcrc);
header.ih_hcrc = 0;
- if (crc32 (0, (char *)&header, sizeof(image_header_t))
+ if (crc32 (0, (uchar *)&header, sizeof(image_header_t))
!= checksum)
goto next_sector;
len = ntohl(hdr->ih_size);
puts (" Verifying Checksum ... ");
- if (crc32 (0, (char *)data, len) != ntohl(hdr->ih_dcrc)) {
+ if (crc32 (0, (uchar *)data, len) != ntohl(hdr->ih_dcrc)) {
puts (" Bad Data CRC\n");
}
puts ("OK\n");
*/
/*
- * IBM 4XX DCR Functions
+ * AMCC 4XX DCR Functions
*/
#include <common.h>
#if defined(CONFIG_4xx) && (CONFIG_COMMANDS & CFG_CMD_SETGETDCR)
-/* ======================================================================
- * Interpreter command to retrieve an IBM PPC 4xx Device Control Register
- * ======================================================================
+/* =======================================================================
+ * Interpreter command to retrieve an AMCC PPC 4xx Device Control Register
+ * =======================================================================
*/
int do_getdcr ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
{
- unsigned short dcrn; /* Device Control Register Num */
- unsigned long value; /* DCR's value */
+ unsigned short dcrn; /* Device Control Register Num */
+ unsigned long value; /* DCR's value */
- unsigned long get_dcr(unsigned short);
+ unsigned long get_dcr (unsigned short);
- /* Validate arguments */
- if (argc < 2) {
- printf("Usage:\n%s\n", cmdtp->usage);
- return 1;
- }
+ /* Validate arguments */
+ if (argc < 2) {
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
- /* Get a DCR */
- dcrn = (unsigned short)simple_strtoul(argv[ 1 ], NULL, 16);
- value = get_dcr(dcrn);
+ /* Get a DCR */
+ dcrn = (unsigned short) simple_strtoul (argv[1], NULL, 16);
+ value = get_dcr (dcrn);
- printf("%04x: %08lx\n", dcrn, value);
+ printf ("%04x: %08lx\n", dcrn, value);
- return 0;
-} /* do_getdcr */
+ return 0;
+}
/* ======================================================================
- * Interpreter command to set an IBM PPC 4xx Device Control Register
+ * Interpreter command to set an AMCC PPC 4xx Device Control Register
* ======================================================================
*/
-int do_setdcr ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_setdcr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
- unsigned long get_dcr(unsigned short );
- unsigned long set_dcr(unsigned short , unsigned long );
- unsigned short dcrn; /* Device Control Register Num */
- unsigned long value;
- /* DCR's value */
- int nbytes;
- extern char console_buffer[];
-
- /* Validate arguments */
- if (argc < 2) {
- printf("Usage:\n%s\n", cmdtp->usage);
- return 1;
- }
-
- /* Set a DCR */
- dcrn = (unsigned short)simple_strtoul(argv[1], NULL, 16);
- do {
- value = get_dcr(dcrn);
- printf("%04x: %08lx", dcrn, value);
- nbytes = readline(" ? ");
- if (nbytes == 0) {
- /*
- * <CR> pressed as only input, don't modify current
- * location and exit command.
- */
- nbytes = 1;
- return 0;
- } else {
- unsigned long i;
- char *endp;
- i = simple_strtoul(console_buffer, &endp, 16);
- nbytes = endp - console_buffer;
- if (nbytes)
- set_dcr(dcrn, i);
+ unsigned long get_dcr (unsigned short);
+ unsigned long set_dcr (unsigned short, unsigned long);
+ unsigned short dcrn; /* Device Control Register Num */
+ unsigned long value;
+
+ /* DCR's value */
+ int nbytes;
+ extern char console_buffer[];
+
+ /* Validate arguments */
+ if (argc < 2) {
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
}
- } while (nbytes);
- return 0;
-} /* do_setdcr */
+ /* Set a DCR */
+ dcrn = (unsigned short) simple_strtoul (argv[1], NULL, 16);
+ do {
+ value = get_dcr (dcrn);
+ printf ("%04x: %08lx", dcrn, value);
+ nbytes = readline (" ? ");
+ if (nbytes == 0) {
+ /*
+ * <CR> pressed as only input, don't modify current
+ * location and exit command.
+ */
+ nbytes = 1;
+ return 0;
+ } else {
+ unsigned long i;
+ char *endp;
+
+ i = simple_strtoul (console_buffer, &endp, 16);
+ nbytes = endp - console_buffer;
+ if (nbytes)
+ set_dcr (dcrn, i);
+ }
+ } while (nbytes);
+
+ return 0;
+}
/***************************************************/
U_BOOT_CMD(
getdcr, 2, 1, do_getdcr,
- "getdcr - Get an IBM PPC 4xx DCR's value\n",
+ "getdcr - Get an AMCC PPC 4xx DCR's value\n",
"dcrn - return a DCR's value.\n"
);
U_BOOT_CMD(
setdcr, 2, 1, do_setdcr,
- "setdcr - Set an IBM PPC 4xx DCR's value\n",
+ "setdcr - Set an AMCC PPC 4xx DCR's value\n",
"dcrn - set a DCR's value.\n"
);
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_DISPLAY)
+
+#undef DEBUG_DISP
+
+#define DISP_SIZE 8
+#define CWORD_CLEAR 0x80
+#define CLEAR_DELAY (110 * 2)
+
+int do_display (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int i;
+ int pos;
+
+ /* Clear display */
+ *((volatile char*)(CFG_DISP_CWORD)) = CWORD_CLEAR;
+ udelay(1000 * CLEAR_DELAY);
+
+ if (argc < 2)
+ return (0);
+
+ for (pos = 0, i = 1; i < argc && pos < DISP_SIZE; i++) {
+ char *p = argv[i], c;
+
+ if (i > 1) {
+ *((volatile uchar *) (CFG_DISP_CHR_RAM + pos++)) = ' ';
+#ifdef DEBUG_DISP
+ putc(' ');
+#endif
+ }
+
+ while ((c = *p++) != '\0' && pos < DISP_SIZE) {
+ *((volatile uchar *) (CFG_DISP_CHR_RAM + pos++)) = c;
+#ifdef DEBUG_DISP
+ putc(c);
+#endif
+ }
+ }
+
+#ifdef DEBUG_DISP
+ putc('\n');
+#endif
+
+ return (0);
+}
+
+/***************************************************/
+
+U_BOOT_CMD(
+ display, CFG_MAXARGS, 1, do_display,
+ "display- display string on dot matrix display\n",
+ "[<string>]\n"
+ " - with <string> argument: display <string> on dot matrix display\n"
+ " - without arguments: clear dot matrix display\n"
+);
+
+#endif /* CFG_CMD_DISPLAY */
cmd ? "read" : "write", curr_device, off, size);
ret = doc_rw(doc_dev_desc + curr_device, cmd, off, size,
- &total, (u_char*)addr);
+ (size_t *)&total, (u_char*)addr);
printf ("%d bytes %s: %s\n", total, cmd ? "read" : "write",
ret ? "ERROR" : "OK");
if (cmd)
ret = doc_read_ecc(this, from, len,
- &n, (u_char*)buf,
- noecc ? NULL : eccbuf);
+ (size_t *)&n, (u_char*)buf,
+ noecc ? (uchar *)NULL : (uchar *)eccbuf);
else
ret = doc_write_ecc(this, from, len,
- &n, (u_char*)buf,
- noecc ? NULL : eccbuf);
+ (size_t *)&n, (u_char*)buf,
+ noecc ? (uchar *)NULL : (uchar *)eccbuf);
if (ret)
break;
/* Check for ANAND header first. Then can whinge if it's found but later
checks fail */
if ((ret = doc_read_ecc(nftl->mtd, block * nftl->EraseSize, SECTORSIZE,
- &retlen, buf, NULL))) {
+ (size_t *)&retlen, buf, NULL))) {
static int warncount = 5;
if (warncount) {
/* To be safer with BIOS, also use erase mark as discriminant */
if ((ret = doc_read_oob(nftl->mtd, block * nftl->EraseSize + SECTORSIZE + 8,
- 8, &retlen, (char *)&h1) < 0)) {
+ 8, (size_t *)&retlen, (uchar *)&h1) < 0)) {
#ifdef NFTL_DEBUG
printf("ANAND header found at 0x%x, but OOB data read failed\n",
block * nftl->EraseSize);
/* read one sector for every SECTORSIZE of blocks */
if ((ret = doc_read_ecc(nftl->mtd, block * nftl->EraseSize +
i + SECTORSIZE, SECTORSIZE,
- &retlen, buf, (char *)&oob)) < 0) {
+ (size_t *)&retlen, buf, (uchar *)&oob)) < 0) {
puts ("Read of bad sector table failed\n");
return -1;
}
*
*/
+/*
+ * Support for read and write access to EEPROM like memory devices. This
+ * includes regular EEPROM as well as FRAM (ferroelectic nonvolaile RAM).
+ * FRAM devices read and write data at bus speed. In particular, there is no
+ * write delay. Also, there is no limit imposed on the numer of bytes that can
+ * be transferred with a single read or write.
+ *
+ * Use the following configuration options to ensure no unneeded performance
+ * degradation (typical for EEPROM) is incured for FRAM memory:
+ *
+ * #define CFG_I2C_FRAM
+ * #undef CFG_EEPROM_PAGE_WRITE_DELAY_MS
+ *
+ */
+
#include <common.h>
#include <config.h>
#include <command.h>
uchar *buffer, unsigned cnt);
extern int eeprom_write (unsigned dev_addr, unsigned offset,
uchar *buffer, unsigned cnt);
+#if defined(CFG_EEPROM_WREN)
+extern int eeprom_write_enable (unsigned dev_addr, int state);
+#endif
#endif
* because the next page may be in a different device.
*/
while (offset < end) {
- unsigned alen, len, maxlen;
+ unsigned alen, len;
+#if !defined(CFG_I2C_FRAM)
+ unsigned maxlen;
+#endif
+
#if CFG_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
uchar addr[2];
addr[0] |= dev_addr; /* insert device address */
+ len = end - offset;
+
+ /*
+ * For a FRAM device there is no limit on the number of the
+ * bytes that can be ccessed with the single read or write
+ * operation.
+ */
+#if !defined(CFG_I2C_FRAM)
maxlen = 0x100 - blk_off;
if (maxlen > I2C_RXTX_LEN)
maxlen = I2C_RXTX_LEN;
- len = end - offset;
if (len > maxlen)
len = maxlen;
+#endif
+
#ifdef CONFIG_SPI
spi_read (addr, alen, buffer, len);
#else
buffer += len;
offset += len;
}
+
return rcode;
}
int i;
#endif
+#if defined(CFG_EEPROM_WREN)
+ eeprom_write_enable (dev_addr,1);
+#endif
/* Write data until done or would cross a write page boundary.
* We must write the address again when changing pages
* because the address counter only increments within a page.
*/
while (offset < end) {
- unsigned alen, len, maxlen;
+ unsigned alen, len;
+#if !defined(CFG_I2C_FRAM)
+ unsigned maxlen;
+#endif
+
#if CFG_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
uchar addr[2];
addr[0] |= dev_addr; /* insert device address */
+ len = end - offset;
+
+ /*
+ * For a FRAM device there is no limit on the number of the
+ * bytes that can be ccessed with the single read or write
+ * operation.
+ */
+#if !defined(CFG_I2C_FRAM)
+
#if defined(CFG_EEPROM_PAGE_WRITE_BITS)
#define EEPROM_PAGE_SIZE (1 << CFG_EEPROM_PAGE_WRITE_BITS)
if (maxlen > I2C_RXTX_LEN)
maxlen = I2C_RXTX_LEN;
- len = end - offset;
if (len > maxlen)
len = maxlen;
+#endif
+
#ifdef CONFIG_SPI
spi_write (addr, alen, buffer, len);
#else
udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
#endif
}
+#if defined(CFG_EEPROM_WREN)
+ eeprom_write_enable (dev_addr,0);
+#endif
return rcode;
}
U_BOOT_CMD(
ext2ls, 4, 1, do_ext2ls,
- "ext2ls- list files in a directory (default /)\n",
+ "ext2ls - list files in a directory (default /)\n",
"<interface> <dev[:part]> [directory]\n"
" - list files from 'dev' on 'interface' in a 'directory'\n"
);
return(1);
}
- if (strncmp(info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) {
+ if (strncmp((char *)info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) {
printf ("\n** Invalid partition type \"%.32s\""
" (expect \"" BOOT_PART_TYPE "\")\n",
info.type);
{
flash_info_t *info;
ulong bank;
+#ifdef CFG_MAX_FLASH_BANKS_DETECT
+ int s_first[CFG_MAX_FLASH_BANKS_DETECT], s_last[CFG_MAX_FLASH_BANKS_DETECT];
+#else
int s_first[CFG_MAX_FLASH_BANKS], s_last[CFG_MAX_FLASH_BANKS];
+#endif
int erased = 0;
int planned;
int rcode = 0;
{
flash_info_t *info;
ulong bank;
+#ifdef CFG_MAX_FLASH_BANKS_DETECT
+ int s_first[CFG_MAX_FLASH_BANKS_DETECT], s_last[CFG_MAX_FLASH_BANKS_DETECT];
+#else
int s_first[CFG_MAX_FLASH_BANKS], s_last[CFG_MAX_FLASH_BANKS];
+#endif
int protected, i;
int planned;
int rcode;
unsigned int i;
int rc;
- dataptr = fpgadata;
+ dataptr = (unsigned char *)fpgadata;
#if CFG_FPGA_XILINX
/* skip the first bytes of the bitsteam, their meaning is unknown */
* chip doesn't respond. This apparently isn't a
* universal feature so we don't take advantage of it.
*/
+/*
+ * No write delay with FRAM devices.
+ */
+#if !defined(CFG_I2C_FRAM)
udelay(11000);
+#endif
+
#if 0
for(timeout = 0; timeout < 10; timeout++) {
udelay(2000);
*/
do {
printf("%08lx:", addr);
- if(i2c_read(chip, addr, alen, (char *)&data, size) != 0) {
+ if(i2c_read(chip, addr, alen, (uchar *)&data, size) != 0) {
puts ("\nError reading the chip,\n");
} else {
data = cpu_to_be32(data);
*/
reset_cmd_timeout();
#endif
- if(i2c_write(chip, addr, alen, (char *)&data, size) != 0) {
+ if(i2c_write(chip, addr, alen, (uchar *)&data, size) != 0) {
puts ("Error writing the chip.\n");
}
#ifdef CFG_EEPROM_PAGE_WRITE_DELAY_MS
#include <asm/io.h>
#ifdef __MIPS__
/* Macros depend on this variable */
-static unsigned long mips_io_port_base = 0;
+unsigned long mips_io_port_base = 0;
#endif
#endif
SHOW_BOOT_PROGRESS (-1);
return 1;
}
- if ((strncmp(info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) &&
- (strncmp(info.type, BOOT_PART_COMP, sizeof(info.type)) != 0)) {
+ if ((strncmp((char *)info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) &&
+ (strncmp((char *)info.type, BOOT_PART_COMP, sizeof(info.type)) != 0)) {
printf ("\n** Invalid partition type \"%.32s\""
" (expect \"" BOOT_PART_TYPE "\")\n",
info.type);
checksum = ntohl(hdr->ih_hcrc);
hdr->ih_hcrc = 0;
- if (crc32 (0, (char *)hdr, sizeof(image_header_t)) != checksum) {
+ if (crc32 (0, (uchar *)hdr, sizeof(image_header_t)) != checksum) {
puts ("\n** Bad Header Checksum **\n");
SHOW_BOOT_PROGRESS (-2);
return 1;
#if defined(CONFIG_8xx)
#include <asm/8xx_immap.h>
#include <commproc.h>
+#include <asm/iopin_8xx.h>
#elif defined(CONFIG_8260)
#include <asm/immap_8260.h>
#include <asm/cpm_8260.h>
int
do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
-#if defined(CONFIG_8260)
uint rcode = 0;
+ iopin_t iopin;
static uint port = 0;
static uint pin = 0;
static uint value = 0;
- static enum { DIR, PAR, SOR, ODR, DAT } cmd = DAT;
- iopin_t iopin;
+ static enum {
+ DIR,
+ PAR,
+ SOR,
+ ODR,
+ DAT,
+#if defined(CONFIG_8xx)
+ INT
+#endif
+ } cmd = DAT;
if (argc != 5) {
puts ("iopset PORT PIN CMD VALUE\n");
case 's':
cmd = SOR;
break;
+#if defined(CONFIG_8xx)
+ case 'i':
+ cmd = INT;
+ break;
+#endif
default:
printf ("iopset: unknown command %s\n", argv[3]);
rcode = 1;
if (rcode == 0) {
iopin.port = port;
iopin.pin = pin;
+ iopin.flag = 0;
switch (cmd) {
case DIR:
if (value)
else
iopin_set_low (&iopin);
break;
+#if defined(CONFIG_8xx)
+ case INT:
+ if (value)
+ iopin_set_falledge (&iopin);
+ else
+ iopin_set_anyedge (&iopin);
+ break;
+#endif
}
}
return rcode;
-#else
- unimplemented (cmdtp, flag, argc, argv);
- return 0;
-#endif
}
int
#endif
/* enable/disable debugging messages */
-#define DEBUG
-#undef DEBUG
+#define DEBUG_JFFS
+#undef DEBUG_JFFS
-#ifdef DEBUG
+#ifdef DEBUG_JFFS
# define DEBUGF(fmt, args...) printf(fmt ,##args)
#else
# define DEBUGF(fmt, args...)
/* this flag needs to be set in part_info struct mask_flags
* field for read-only partitions */
-#define MTD_WRITEABLE 1
+#define MTD_WRITEABLE_CMD 1
#ifdef CONFIG_JFFS2_CMDLINE
/* default values for mtdids and mtdparts variables */
}
/**
+ * This routine does global indexing of all partitions. Resulting index for
+ * current partition is saved in 'mtddevnum'. Current partition name in
+ * 'mtddevname'.
+ */
+static void index_partitions(void)
+{
+ char buf[16];
+ u16 mtddevnum;
+ struct part_info *part;
+ struct list_head *dentry;
+ struct mtd_device *dev;
+
+ DEBUGF("--- index partitions ---\n");
+
+ if (current_dev) {
+ mtddevnum = 0;
+ list_for_each(dentry, &devices) {
+ dev = list_entry(dentry, struct mtd_device, link);
+ if (dev == current_dev) {
+ mtddevnum += current_partnum;
+ sprintf(buf, "%d", mtddevnum);
+ setenv("mtddevnum", buf);
+ break;
+ }
+ mtddevnum += dev->num_parts;
+ }
+
+ part = jffs2_part_info(current_dev, current_partnum);
+ setenv("mtddevname", part->name);
+
+ DEBUGF("=> mtddevnum %d,\n=> mtddevname %s\n", mtddevnum, part->name);
+ } else {
+ setenv("mtddevnum", NULL);
+ setenv("mtddevname", NULL);
+
+ DEBUGF("=> mtddevnum NULL\n=> mtddevname NULL\n");
+ }
+}
+
+/**
* Save current device and partition in environment variable 'partition'.
*/
static void current_save(void)
DEBUGF("=> partition NULL\n");
}
+ index_partitions();
}
/**
{
#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
/* info for FLASH chips */
- extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+ extern flash_info_t flash_info[];
flash_info_t *flash;
int offset_aligned;
u32 end_offset;
*/
static int part_del(struct mtd_device *dev, struct part_info *part)
{
+ u8 current_save_needed = 0;
+
/* if there is only one partition, remove whole device */
if (dev->num_parts == 1)
return device_del(dev);
if (curr_pi == part) {
printf("current partition deleted, resetting current to 0\n");
current_partnum = 0;
- current_save();
} else if (part->offset <= curr_pi->offset) {
current_partnum--;
- current_save();
}
+ current_save_needed = 1;
}
}
free(part);
dev->num_parts--;
+ if (current_save_needed > 0)
+ current_save();
+ else
+ index_partitions();
+
return 0;
}
if (list_empty(&dev->parts)) {
DEBUGF("part_sort_add: list empty\n");
list_add(&part->link, &dev->parts);
+ dev->num_parts++;
+ index_partitions();
return 0;
}
if (new_pi->offset <= pi->offset) {
list_add_tail(&part->link, entry);
+ dev->num_parts++;
if (curr_pi && (pi->offset <= curr_pi->offset)) {
/* we are modyfing partitions for the current
* device, update current */
current_partnum++;
current_save();
+ } else {
+ index_partitions();
}
-
return 0;
}
}
+
list_add_tail(&part->link, &dev->parts);
+ dev->num_parts++;
+ index_partitions();
return 0;
}
if (part_sort_add(dev, part) != 0)
return 1;
- dev->num_parts++;
return 0;
}
/* test for options */
mask_flags = 0;
if (strncmp(p, "ro", 2) == 0) {
- mask_flags |= MTD_WRITEABLE;
+ mask_flags |= MTD_WRITEABLE_CMD;
p += 2;
}
if (type == MTD_DEV_TYPE_NOR) {
#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
if (num < CFG_MAX_FLASH_BANKS) {
- extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+ extern flash_info_t flash_info[];
*size = flash_info[num].size;
return 0;
current_partnum = 0;
}
current_save();
+ return 0;
}
-
+ index_partitions();
return 0;
}
*/
static void device_add(struct mtd_device *dev)
{
+ u8 current_save_needed = 0;
+
if (list_empty(&devices)) {
current_dev = dev;
current_partnum = 0;
- current_save();
+ current_save_needed = 1;
}
list_add_tail(&dev->link, &devices);
+
+ if (current_save_needed > 0)
+ current_save();
+ else
+ index_partitions();
}
/**
}
memset(dev, 0, sizeof(struct mtd_device));
dev->id = id;
- dev->num_parts = num_parts;
+ dev->num_parts = 0; /* part_sort_add increments num_parts */
INIT_LIST_HEAD(&dev->parts);
INIT_LIST_HEAD(&dev->link);
}
/* ro mask flag */
- if (part->mask_flags && MTD_WRITEABLE) {
+ if (part->mask_flags && MTD_WRITEABLE_CMD) {
len = 2;
if (len > maxlen)
goto cleanup;
ids_changed = 1;
if (parse_mtdids(ids) != 0) {
- device_delall(&devices);
+ devices_init();
return 1;
}
if (addr2info(store_addr)) {
int rc;
- rc = flash_write((uchar *)binbuf,store_addr,binlen);
+ rc = flash_write((char *)binbuf,store_addr,binlen);
if (rc != 0) {
flash_perror (rc);
return (~0);
case 2:
if (strcmp(argv[1],"show") == 0) {
for (i=0; i < (log_size&LOGBUFF_MASK); i++) {
- s = log_buf+((log_start+i)&LOGBUFF_MASK);
+ s = (char *)log_buf+((log_start+i)&LOGBUFF_MASK);
putc (*s);
}
return 0;
}
#endif
puts (" ");
- cp = linebuf;
+ cp = (u_char *)linebuf;
for (i=0; i<linebytes; i++) {
if ((*cp < 0x20) || (*cp > 0x7e))
putc ('.');
puts ("Copy to Flash... ");
- rc = flash_write ((uchar *)addr, dest, count*size);
+ rc = flash_write ((char *)addr, dest, count*size);
if (rc != 0) {
flash_perror (rc);
return (1);
uint last_reg;
/*
- * MII read/write
+ * MII device/info/read/write
*
* Syntax:
- * mii read {addr} {reg}
- * mii write {addr} {reg} {data}
+ * mii device {devname}
+ * mii info {addr}
+ * mii read {addr} {reg}
+ * mii write {addr} {reg} {data}
*/
-
int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
char op;
unsigned char addr, reg;
unsigned short data;
int rcode = 0;
+ char *devname;
#if defined(CONFIG_8xx) || defined(CONFIG_MCF52x2)
mii_init ();
data = simple_strtoul (argv[4], NULL, 16);
}
+ /* use current device */
+ devname = miiphy_get_current_dev();
+
/*
- * check info/read/write.
+ * check device/read/write/list.
*/
if (op == 'i') {
unsigned char j, start, end;
if (argc >= 3) {
start = addr; end = addr + 1;
} else {
- start = 0; end = 32;
+ start = 0; end = 31;
}
for (j = start; j < end; j++) {
- if (miiphy_info (j, &oui, &model, &rev) == 0) {
+ if (miiphy_info (devname, j, &oui, &model, &rev) == 0) {
printf ("PHY 0x%02X: "
"OUI = 0x%04X, "
"Model = 0x%02X, "
"Rev = 0x%02X, "
"%3dbaseT, %s\n",
j, oui, model, rev,
- miiphy_speed (j),
- miiphy_duplex (j) == FULL ? "FDX" : "HDX");
+ miiphy_speed (devname, j),
+ (miiphy_duplex (devname, j) == FULL)
+ ? "FDX" : "HDX");
+ } else {
+ puts ("Error reading info from the PHY\n");
}
}
} else if (op == 'r') {
- if (miiphy_read (addr, reg, &data) != 0) {
+ if (miiphy_read (devname, addr, reg, &data) != 0) {
puts ("Error reading from the PHY\n");
rcode = 1;
+ } else {
+ printf ("%04X\n", data & 0x0000FFFF);
}
- printf ("%04X\n", data & 0x0000FFFF);
} else if (op == 'w') {
- if (miiphy_write (addr, reg, data) != 0) {
+ if (miiphy_write (devname, addr, reg, data) != 0) {
puts ("Error writing to the PHY\n");
rcode = 1;
}
+ } else if (op == 'd') {
+ if (argc == 2)
+ miiphy_listdev ();
+ else
+ miiphy_set_current_dev (argv[2]);
} else {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
U_BOOT_CMD(
mii, 5, 1, do_mii,
"mii - MII utility commands\n",
- "info <addr> - display MII PHY info\n"
- "mii read <addr> <reg> - read MII PHY <addr> register <reg>\n"
- "mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n"
+ "device - list available devices\n"
+ "mii device <devname> - set current device\n"
+ "mii info <addr> - display MII PHY info\n"
+ "mii read <addr> <reg> - read MII PHY <addr> register <reg>\n"
+ "mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n"
);
#else /* ! CONFIG_TERSE_MII ================================================= */
return 0;
}
-uint last_op;
+char last_op[2];
uint last_data;
uint last_addr_lo;
uint last_addr_hi;
/* ---------------------------------------------------------------- */
int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
- char op;
+ char op[2];
unsigned char addrlo, addrhi, reglo, reghi;
- unsigned char addr = 0, reg = 0;
+ unsigned char addr, reg;
unsigned short data;
int rcode = 0;
+ char *devname;
#ifdef CONFIG_8xx
mii_init ();
* We use the last specified parameters, unless new ones are
* entered.
*/
- op = last_op;
+ op[0] = last_op[0];
+ op[1] = last_op[1];
addrlo = last_addr_lo;
addrhi = last_addr_hi;
reglo = last_reg_lo;
data = last_data;
if ((flag & CMD_FLAG_REPEAT) == 0) {
- op = argv[1][0];
+ op[0] = argv[1][0];
+ if (strlen(argv[1]) > 1)
+ op[1] = argv[1][1];
+ else
+ op[1] = '\0';
+
if (argc >= 3)
extract_range(argv[2], &addrlo, &addrhi);
if (argc >= 4)
data = simple_strtoul (argv[4], NULL, 16);
}
+ /* use current device */
+ devname = miiphy_get_current_dev();
+
/*
* check info/read/write.
*/
- if (op == 'i') {
+ if (op[0] == 'i') {
unsigned char j, start, end;
unsigned int oui;
unsigned char model;
* Look for any and all PHYs. Valid addresses are 0..31.
*/
if (argc >= 3) {
- start = addr; end = addr + 1;
+ start = addrlo; end = addrhi;
} else {
- start = 0; end = 32;
+ start = 0; end = 31;
}
- for (j = start; j < end; j++) {
- if (miiphy_info (j, &oui, &model, &rev) == 0) {
+ for (j = start; j <= end; j++) {
+ if (miiphy_info (devname, j, &oui, &model, &rev) == 0) {
printf("PHY 0x%02X: "
"OUI = 0x%04X, "
"Model = 0x%02X, "
"Rev = 0x%02X, "
"%3dbaseT, %s\n",
j, oui, model, rev,
- miiphy_speed (j),
- miiphy_duplex (j) == FULL ? "FDX" : "HDX");
+ miiphy_speed (devname, j),
+ (miiphy_duplex (devname, j) == FULL)
+ ? "FDX" : "HDX");
+ } else {
+ puts ("Error reading info from the PHY\n");
}
}
- } else if (op == 'r') {
+ } else if (op[0] == 'r') {
for (addr = addrlo; addr <= addrhi; addr++) {
for (reg = reglo; reg <= reghi; reg++) {
data = 0xffff;
- if (miiphy_read (addr, reg, &data) != 0) {
+ if (miiphy_read (devname, addr, reg, &data) != 0) {
printf(
"Error reading from the PHY addr=%02x reg=%02x\n",
addr, reg);
rcode = 1;
- }
- else {
+ } else {
if ((addrlo != addrhi) || (reglo != reghi))
printf("addr=%02x reg=%02x data=",
(uint)addr, (uint)reg);
if ((addrlo != addrhi) && (reglo != reghi))
printf("\n");
}
- } else if (op == 'w') {
+ } else if (op[0] == 'w') {
for (addr = addrlo; addr <= addrhi; addr++) {
for (reg = reglo; reg <= reghi; reg++) {
- if (miiphy_write (addr, reg, data) != 0) {
+ if (miiphy_write (devname, addr, reg, data) != 0) {
printf("Error writing to the PHY addr=%02x reg=%02x\n",
addr, reg);
rcode = 1;
}
}
}
- } else if (op == 'd') {
+ } else if (strncmp(op, "du", 2) == 0) {
ushort regs[6];
int ok = 1;
if ((reglo > 5) || (reghi > 5)) {
return 1;
}
for (addr = addrlo; addr <= addrhi; addr++) {
- for (reg = 0; reg < 6; reg++) {
- if (miiphy_read(addr, reg, ®s[reg]) != 0) {
+ for (reg = reglo; reg < reghi + 1; reg++) {
+ if (miiphy_read(devname, addr, reg, ®s[reg]) != 0) {
ok = 0;
printf(
"Error reading from the PHY addr=%02x reg=%02x\n",
MII_dump_0_to_5(regs, reglo, reghi);
printf("\n");
}
+ } else if (strncmp(op, "de", 2) == 0) {
+ if (argc == 2)
+ miiphy_listdev ();
+ else
+ miiphy_set_current_dev (argv[2]);
} else {
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
/*
* Save the parameters for repeats.
*/
- last_op = op;
+ last_op[0] = op[0];
+ last_op[1] = op[1];
last_addr_lo = addrlo;
last_addr_hi = addrhi;
last_reg_lo = reglo;
U_BOOT_CMD(
mii, 5, 1, do_mii,
"mii - MII utility commands\n",
- "info <addr> - display MII PHY info\n"
- "mii read <addr> <reg> - read MII PHY <addr> register <reg>\n"
- "mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n"
- "mii dump <addr> <reg> - pretty-print <addr> <reg> (0-5 only)\n"
+ "device - list available devices\n"
+ "mii device <devname> - set current device\n"
+ "mii info <addr> - display MII PHY info\n"
+ "mii read <addr> <reg> - read MII PHY <addr> register <reg>\n"
+ "mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n"
+ "mii dump <addr> <reg> - pretty-print <addr> <reg> (0-5 only)\n"
"Addr and/or reg may be ranges, e.g. 2-7.\n"
);
int do_sleep (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
+ ulong start = get_timer(0);
ulong delay;
if (argc != 2) {
return 1;
}
- delay = simple_strtoul(argv[1], NULL, 10);
+ delay = simple_strtoul(argv[1], NULL, 10) * CFG_HZ;
- while (delay) {
- int i;
- for (i=0; i<1000; ++i) {
- if (ctrlc ()) {
- return (-1);
- }
- udelay (1000);
+ while (get_timer(start) < delay) {
+ if (ctrlc ()) {
+ return (-1);
}
- --delay;
+ udelay (100);
}
+
return 0;
}
+
/* Implemented in $(CPU)/interrupts.c */
#if (CONFIG_COMMANDS & CFG_CMD_IRQ)
int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
# define SHOW_BOOT_PROGRESS(arg)
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined CONFIG_NEW_NAND_CODE
+#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CONFIG_NEW_NAND_CODE)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ids.h>
/* read out-of-band data */
if (cmd & NANDRW_READ) {
ret = nand_read_oob(nand_dev_desc + curr_device,
- off, size, &total,
+ off, size, (size_t *)&total,
(u_char*)addr);
}
else {
ret = nand_write_oob(nand_dev_desc + curr_device,
- off, size, &total,
+ off, size, (size_t *)&total,
(u_char*)addr);
}
return ret;
curr_device, off, size);
ret = nand_rw(nand_dev_desc + curr_device, cmd, off, size,
- &total, (u_char*)addr);
+ (size_t *)&total, (u_char*)addr);
printf (" %d bytes %s: %s\n", total,
(cmd & NANDRW_READ) ? "read" : "written",
*/
int check_block (struct nand_chip *nand, unsigned long pos)
{
- int retlen;
+ size_t retlen;
uint8_t oob_data;
uint16_t oob_data16[6];
int page0 = pos & (-nand->erasesize);
return 1;
} else {
/* Note - bad block marker can be on first or second page */
- if (nand_read_oob(nand, page0 + badpos, 1, &retlen, &oob_data)
+ if (nand_read_oob(nand, page0 + badpos, 1, &retlen, (unsigned char *)&oob_data)
|| oob_data != 0xff
- || nand_read_oob (nand, page1 + badpos, 1, &retlen, &oob_data)
+ || nand_read_oob (nand, page1 + badpos, 1, &retlen, (unsigned char *)&oob_data)
|| oob_data != 0xff)
return 1;
}
if (cmd & NANDRW_READ) {
ret = nand_read_ecc(nand, start,
min(len, eblk + erasesize - start),
- &n, (u_char*)buf, eccbuf);
+ (size_t *)&n, (u_char*)buf, (u_char *)eccbuf);
} else {
ret = nand_write_ecc(nand, start,
min(len, eblk + erasesize - start),
- &n, (u_char*)buf, eccbuf);
+ (size_t *)&n, (u_char*)buf, (u_char *)eccbuf);
}
if (ret)
l = NAND_JFFS2_OOB16_FSDALEN;
}
- ret = nand_write_oob(nand, ofs + p, l, &n,
+ ret = nand_write_oob(nand, ofs + p, l, (size_t *)&n,
(u_char *)&clean_marker);
/* quit here if write failed */
if (ret)
for (nxt=j; env_get_char(nxt) != '\0'; ++nxt)
;
- k = envmatch(name, j);
+ k = envmatch((uchar *)name, j);
if (k < 0) {
continue;
}
int i, len, oldval;
int console = -1;
uchar *env, *nxt = NULL;
- uchar *name;
+ char *name;
bd_t *bd = gd->bd;
uchar *env_data = env_get_addr(0);
for (env=env_data; *env; env=nxt+1) {
for (nxt=env; *nxt; ++nxt)
;
- if ((oldval = envmatch(name, env-env_data)) >= 0)
+ if ((oldval = envmatch((uchar *)name, env-env_data)) >= 0)
break;
}
if ( (strcmp (name, "serial#") == 0) ||
((strcmp (name, "ethaddr") == 0)
#if defined(CONFIG_OVERWRITE_ETHADDR_ONCE) && defined(CONFIG_ETHADDR)
- && (strcmp (env_get_addr(oldval),MK_STR(CONFIG_ETHADDR)) != 0)
+ && (strcmp ((char *)env_get_addr(oldval),MK_STR(CONFIG_ETHADDR)) != 0)
#endif /* CONFIG_OVERWRITE_ETHADDR_ONCE && CONFIG_ETHADDR */
) ) {
printf ("Can't overwrite \"%s\"\n", name);
* or NULL if not found
*/
-char *getenv (uchar *name)
+char *getenv (char *name)
{
int i, nxt;
return (NULL);
}
}
- if ((val=envmatch(name, i)) < 0)
+ if ((val=envmatch((uchar *)name, i)) < 0)
continue;
- return (env_get_addr(val));
+ return ((char *)env_get_addr(val));
}
return (NULL);
}
-int getenv_r (uchar *name, uchar *buf, unsigned len)
+int getenv_r (char *name, char *buf, unsigned len)
{
int i, nxt;
return (-1);
}
}
- if ((val=envmatch(name, i)) < 0)
+ if ((val=envmatch((uchar *)name, i)) < 0)
continue;
/* found; copy out */
n = 0;
#define MAX_IDENT_FIELDS 4
static uchar *known_cards[] = {
- "ARGOSY PnPIDE D5",
+ (uchar *)"ARGOSY PnPIDE D5",
NULL
};
else
break;
}
- puts (id_str);
+ puts ((char *)id_str);
putc ('\n');
for (card=known_cards; *card; ++card) {
debug ("## Compare against \"%s\"\n", *card);
- if (strcmp(*card, id_str) == 0) { /* found! */
+ if (strcmp((char *)*card, (char *)id_str) == 0) { /* found! */
debug ("## CARD FOUND ##\n");
return (1);
}
printf("error reading partinfo\n");
return 1;
}
- if ((strncmp(info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) &&
- (strncmp(info.type, BOOT_PART_COMP, sizeof(info.type)) != 0)) {
+ if ((strncmp((char *)(info.type), BOOT_PART_TYPE, sizeof(info.type)) != 0) &&
+ (strncmp((char *)(info.type), BOOT_PART_COMP, sizeof(info.type)) != 0)) {
printf ("\n** Invalid partition type \"%.32s\""
" (expect \"" BOOT_PART_TYPE "\")\n",
info.type);
checksum = ntohl(hdr->ih_hcrc);
hdr->ih_hcrc = 0;
- if (crc32 (0, (char *)hdr, sizeof(image_header_t)) != checksum) {
+ if (crc32 (0, (uchar *)hdr, sizeof(image_header_t)) != checksum) {
puts ("\n** Bad Header Checksum **\n");
return 1;
}
printf("Error with the SPI transaction.\n");
rcode = 1;
} else {
- cp = din;
+ cp = (char *)din;
for(j = 0; j < ((bitlen + 7) / 8); j++) {
printf("%02X", *cp++);
}
if (get_partition_info (stor_dev, part, &info)) {
/* try to boot raw .... */
- strncpy(&info.type[0], BOOT_PART_TYPE, sizeof(BOOT_PART_TYPE));
- strncpy(&info.name[0], "Raw", 4);
+ strncpy((char *)&info.type[0], BOOT_PART_TYPE, sizeof(BOOT_PART_TYPE));
+ strncpy((char *)&info.name[0], "Raw", 4);
info.start=0;
info.blksz=0x200;
info.size=2880;
printf("error reading partinfo...try to boot raw\n");
}
- if ((strncmp(info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) &&
- (strncmp(info.type, BOOT_PART_COMP, sizeof(info.type)) != 0)) {
+ if ((strncmp((char *)info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) &&
+ (strncmp((char *)info.type, BOOT_PART_COMP, sizeof(info.type)) != 0)) {
printf ("\n** Invalid partition type \"%.32s\""
" (expect \"" BOOT_PART_TYPE "\")\n",
info.type);
checksum = ntohl(hdr->ih_hcrc);
hdr->ih_hcrc = 0;
- if (crc32 (0, (char *)hdr, sizeof(image_header_t)) != checksum) {
+ if (crc32 (0, (uchar *)hdr, sizeof(image_header_t)) != checksum) {
puts ("\n** Bad Header Checksum **\n");
return 1;
}
for (nxt=i; env_get_char(nxt) != '\0'; ++nxt)
;
- lval = env_get_addr(i);
+ lval = (char *)env_get_addr(i);
rval = strchr(lval, '=');
if (rval != NULL) {
vallen = rval - lval;
#include <command.h>
#include <environment.h>
#include <linux/stddef.h>
-#include <malloc.h>
#include <dataflash.h>
env_t *env_ptr = NULL;
#include <command.h>
#include <environment.h>
#include <linux/stddef.h>
-#include <malloc.h>
env_t *env_ptr = NULL;
debug (" %08lX ... %08lX ...",
(ulong)&(flash_addr_new->data),
sizeof(env_ptr->data)+(ulong)&(flash_addr_new->data));
- if ((rc = flash_write(env_ptr->data,
+ if ((rc = flash_write((char *)env_ptr->data,
(ulong)&(flash_addr_new->data),
sizeof(env_ptr->data))) ||
(rc = flash_write((char *)&(env_ptr->crc),
ulong flash_offset;
uchar env_buffer[CFG_ENV_SECT_SIZE];
#else
- uchar *env_buffer = (char *)env_ptr;
+ uchar *env_buffer = (uchar *)env_ptr;
#endif /* CFG_ENV_SECT_SIZE */
int rcode = 0;
return 1;
puts ("Writing to Flash... ");
- rc = flash_write(env_buffer, flash_sect_addr, len);
+ rc = flash_write((char *)env_buffer, flash_sect_addr, len);
if (rc != 0) {
flash_perror (rc);
rcode = 1;
#include <command.h>
#include <environment.h>
#include <linux/stddef.h>
-#include <malloc.h>
#include <linux/mtd/nand.h>
#if ((CONFIG_COMMANDS&(CFG_CMD_ENV|CFG_CMD_NAND)) == (CFG_CMD_ENV|CFG_CMD_NAND))
#include <command.h>
#include <environment.h>
#include <linux/stddef.h>
-#include <malloc.h>
env_t *env_ptr = NULL;
#include <command.h>
#include <environment.h>
#include <linux/stddef.h>
-#include <malloc.h>
#ifdef CFG_NVRAM_ACCESS_ROUTINE
extern void *nvram_read(void *dest, const long src, size_t count);
#if !defined(CFG_NO_FLASH)
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+extern flash_info_t flash_info[]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
* (only some targets require alignment)
*/
int
-flash_write (uchar *src, ulong addr, ulong cnt)
+flash_write (char *src, ulong addr, ulong cnt)
{
#ifdef CONFIG_SPD823TS
return (ERR_TIMOUT); /* any other error codes are possible as well */
len = info->start[0] + info->size - addr;
if (len > cnt)
len = cnt;
- if ((i = write_buff(info, src, addr, len)) != 0) {
+ if ((i = write_buff(info, (uchar *)src, addr, len)) != 0) {
return (i);
}
cnt -= len;
static fpga_desc desc_table[CONFIG_MAX_FPGA_DEVICES];
/* Local static functions */
-static const fpga_desc * const fpga_get_desc( int devnum );
-static const fpga_desc * const fpga_validate( int devnum, void *buf,
+static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_get_desc( int devnum );
+static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate( int devnum, void *buf,
size_t bsize, char *fn );
static int fpga_dev_info( int devnum );
/* fpga_get_desc
* map a device number to a descriptor
*/
-static const fpga_desc * const fpga_get_desc( int devnum )
+static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_get_desc( int devnum )
{
fpga_desc *desc = (fpga_desc * )NULL;
/* fpga_validate
* generic parameter checking code
*/
-static const fpga_desc * const fpga_validate( int devnum, void *buf,
+static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate( int devnum, void *buf,
size_t bsize, char *fn )
{
- const fpga_desc * const desc = fpga_get_desc( devnum );
+ fpga_desc * desc = fpga_get_desc( devnum );
if ( !desc ) {
printf( "%s: Invalid device number %d\n", fn, devnum );
printf( "Altera Device\nDescriptor @ 0x%p\n", desc );
ret_val = altera_info( desc->devdesc );
#else
- fpga_no_sup( __FUNCTION__, "Altera devices" );
+ fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
#endif
break;
default:
#if CONFIG_FPGA & CFG_FPGA_ALTERA
ret_val = altera_reloc( desc, reloc_off );
#else
- fpga_no_sup( __FUNCTION__, "Altera devices" );
+ fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
#endif
break;
default:
/* fpga_count
* Basic interface function to get the current number of devices available.
*/
-const int fpga_count( void )
+int fpga_count( void )
{
return next_desc;
}
int fpga_load( int devnum, void *buf, size_t bsize )
{
int ret_val = FPGA_FAIL; /* assume failure */
- const fpga_desc * const desc = fpga_validate( devnum, buf, bsize, __FUNCTION__ );
+ fpga_desc * desc = fpga_validate( devnum, buf, bsize, (char *)__FUNCTION__ );
if ( desc ) {
switch ( desc->devtype ) {
#if CONFIG_FPGA & CFG_FPGA_ALTERA
ret_val = altera_load( desc->devdesc, buf, bsize );
#else
- fpga_no_sup( __FUNCTION__, "Altera devices" );
+ fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
#endif
break;
default:
int fpga_dump( int devnum, void *buf, size_t bsize )
{
int ret_val = FPGA_FAIL; /* assume failure */
- const fpga_desc * const desc = fpga_validate( devnum, buf, bsize, __FUNCTION__ );
+ fpga_desc * desc = fpga_validate( devnum, buf, bsize, (char *)__FUNCTION__ );
if ( desc ) {
switch ( desc->devtype ) {
#if CONFIG_FPGA & CFG_FPGA_ALTERA
ret_val = altera_dump( desc->devdesc, buf, bsize );
#else
- fpga_no_sup( __FUNCTION__, "Altera devices" );
+ fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
#endif
break;
default:
--- /dev/null
+/*
+ * OF flat tree builder
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <environment.h>
+
+#ifdef CONFIG_OF_FLAT_TREE
+
+#include <asm/errno.h>
+#include <stddef.h>
+
+#include <ft_build.h>
+
+/* align addr on a size boundary - adjust address up if needed -- Cort */
+#define _ALIGN(addr,size) (((addr)+(size)-1)&(~((size)-1)))
+
+static void ft_put_word(struct ft_cxt *cxt, u32 v)
+{
+ if (cxt->overflow) /* do nothing */
+ return;
+
+ /* check for overflow */
+ if (cxt->p + 4 > cxt->pstr) {
+ cxt->overflow = 1;
+ return;
+ }
+
+ *(u32 *) cxt->p = cpu_to_be32(v);
+ cxt->p += 4;
+}
+
+static inline void ft_put_bin(struct ft_cxt *cxt, const void *data, int sz)
+{
+ u8 *p;
+
+ if (cxt->overflow) /* do nothing */
+ return;
+
+ /* next pointer pos */
+ p = (u8 *) _ALIGN((unsigned long)cxt->p + sz, 4);
+
+ /* check for overflow */
+ if (p > cxt->pstr) {
+ cxt->overflow = 1;
+ return;
+ }
+
+ memcpy(cxt->p, data, sz);
+ if ((sz & 3) != 0)
+ memset(cxt->p + sz, 0, 4 - (sz & 3));
+ cxt->p = p;
+}
+
+void ft_begin_node(struct ft_cxt *cxt, const char *name)
+{
+ ft_put_word(cxt, OF_DT_BEGIN_NODE);
+ ft_put_bin(cxt, name, strlen(name) + 1);
+}
+
+void ft_end_node(struct ft_cxt *cxt)
+{
+ ft_put_word(cxt, OF_DT_END_NODE);
+}
+
+void ft_nop(struct ft_cxt *cxt)
+{
+ ft_put_word(cxt, OF_DT_NOP);
+}
+
+static int lookup_string(struct ft_cxt *cxt, const char *name)
+{
+ u8 *p;
+
+ p = cxt->pstr;
+ while (p < cxt->pstr_begin) {
+ if (strcmp(p, name) == 0)
+ return p - cxt->p_begin;
+ p += strlen(p) + 1;
+ }
+
+ return -1;
+}
+
+void ft_prop(struct ft_cxt *cxt, const char *name, const void *data, int sz)
+{
+ int len, off;
+
+ if (cxt->overflow)
+ return;
+
+ len = strlen(name) + 1;
+
+ off = lookup_string(cxt, name);
+ if (off == -1) {
+ /* check if we have space */
+ if (cxt->p + 12 + sz + len > cxt->pstr) {
+ cxt->overflow = 1;
+ return;
+ }
+
+ cxt->pstr -= len;
+ memcpy(cxt->pstr, name, len);
+ off = cxt->pstr - cxt->p_begin;
+ }
+
+ /* now put offset from beginning of *STRUCTURE* */
+ /* will be fixed up at the end */
+ ft_put_word(cxt, OF_DT_PROP);
+ ft_put_word(cxt, sz);
+ ft_put_word(cxt, off);
+ ft_put_bin(cxt, data, sz);
+}
+
+void ft_prop_str(struct ft_cxt *cxt, const char *name, const char *str)
+{
+ ft_prop(cxt, name, str, strlen(str) + 1);
+}
+
+void ft_prop_int(struct ft_cxt *cxt, const char *name, int val)
+{
+ u32 v = cpu_to_be32((u32) val);
+
+ ft_prop(cxt, name, &v, 4);
+}
+
+/* start construction of the flat OF tree */
+void ft_begin(struct ft_cxt *cxt, void *blob, int max_size)
+{
+ struct boot_param_header *bph = blob;
+ u32 off;
+
+ /* clear the cxt */
+ memset(cxt, 0, sizeof(*cxt));
+
+ cxt->bph = bph;
+ cxt->max_size = max_size;
+
+ /* zero everything in the header area */
+ memset(bph, 0, sizeof(*bph));
+
+ bph->magic = cpu_to_be32(OF_DT_HEADER);
+ bph->version = cpu_to_be32(0x10);
+ bph->last_comp_version = cpu_to_be32(0x10);
+
+ /* start pointers */
+ cxt->pres_begin = (u8 *) _ALIGN((unsigned long)(bph + 1), 8);
+ cxt->pres = cxt->pres_begin;
+
+ off = (unsigned long)cxt->pres_begin - (unsigned long)bph;
+ bph->off_mem_rsvmap = cpu_to_be32(off);
+
+ ((u64 *) cxt->pres)[0] = 0; /* phys = 0, size = 0, terminate */
+ ((u64 *) cxt->pres)[1] = 0;
+
+ cxt->p_anchor = cxt->pres + 16; /* over the terminator */
+}
+
+/* add a reserver physical area to the rsvmap */
+void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size)
+{
+ ((u64 *) cxt->pres)[0] = cpu_to_be64(physaddr); /* phys = 0, size = 0, terminate */
+ ((u64 *) cxt->pres)[1] = cpu_to_be64(size);
+
+ cxt->pres += 18; /* advance */
+
+ ((u64 *) cxt->pres)[0] = 0; /* phys = 0, size = 0, terminate */
+ ((u64 *) cxt->pres)[1] = 0;
+
+ /* keep track of size */
+ cxt->res_size = cxt->pres + 16 - cxt->pres_begin;
+
+ cxt->p_anchor = cxt->pres + 16; /* over the terminator */
+}
+
+void ft_begin_tree(struct ft_cxt *cxt)
+{
+ cxt->p_begin = cxt->p_anchor;
+ cxt->pstr_begin = (char *)cxt->bph + cxt->max_size; /* point at the end */
+
+ cxt->p = cxt->p_begin;
+ cxt->pstr = cxt->pstr_begin;
+}
+
+int ft_end_tree(struct ft_cxt *cxt)
+{
+ struct boot_param_header *bph = cxt->bph;
+ int off, sz, sz1;
+ u32 tag, v;
+ u8 *p;
+
+ ft_put_word(cxt, OF_DT_END);
+
+ if (cxt->overflow)
+ return -ENOMEM;
+
+ /* size of the areas */
+ cxt->struct_size = cxt->p - cxt->p_begin;
+ cxt->strings_size = cxt->pstr_begin - cxt->pstr;
+
+ /* the offset we must move */
+ off = (cxt->pstr_begin - cxt->p_begin) - cxt->strings_size;
+
+ /* the new strings start */
+ cxt->pstr_begin = cxt->p_begin + cxt->struct_size;
+
+ /* move the whole string area */
+ memmove(cxt->pstr_begin, cxt->pstr, cxt->strings_size);
+
+ /* now perform the fixup of the strings */
+ p = cxt->p_begin;
+ while ((tag = be32_to_cpu(*(u32 *) p)) != OF_DT_END) {
+ p += 4;
+
+ if (tag == OF_DT_BEGIN_NODE) {
+ p = (u8 *) _ALIGN((unsigned long)p + strlen(p) + 1, 4);
+ continue;
+ }
+
+ if (tag == OF_DT_END_NODE || tag == OF_DT_NOP)
+ continue;
+
+ if (tag != OF_DT_PROP)
+ return -EINVAL;
+
+ sz = be32_to_cpu(*(u32 *) p);
+ p += 4;
+
+ v = be32_to_cpu(*(u32 *) p);
+ v -= off;
+ *(u32 *) p = cpu_to_be32(v); /* move down */
+ p += 4;
+
+ p = (u8 *) _ALIGN((unsigned long)p + sz, 4);
+ }
+
+ /* fix sizes */
+ p = (char *)cxt->bph;
+ sz = (cxt->pstr_begin + cxt->strings_size) - p;
+ sz1 = _ALIGN(sz, 16); /* align at 16 bytes */
+ if (sz != sz1)
+ memset(p + sz, 0, sz1 - sz);
+ bph->totalsize = cpu_to_be32(sz1);
+ bph->off_dt_struct = cpu_to_be32(cxt->p_begin - p);
+ bph->off_dt_strings = cpu_to_be32(cxt->pstr_begin - p);
+
+ /* the new strings start */
+ cxt->pstr_begin = cxt->p_begin + cxt->struct_size;
+ cxt->pstr = cxt->pstr_begin + cxt->strings_size;
+
+ return 0;
+}
+
+/**********************************************************************/
+
+static inline int isprint(int c)
+{
+ return c >= 0x20 && c <= 0x7e;
+}
+
+static int is_printable_string(const void *data, int len)
+{
+ const char *s = data;
+ const char *ss;
+
+ /* zero length is not */
+ if (len == 0)
+ return 0;
+
+ /* must terminate with zero */
+ if (s[len - 1] != '\0')
+ return 0;
+
+ ss = s;
+ while (*s && isprint(*s))
+ s++;
+
+ /* not zero, or not done yet */
+ if (*s != '\0' || (s + 1 - ss) < len)
+ return 0;
+
+ return 1;
+}
+
+static void print_data(const void *data, int len)
+{
+ int i;
+ const u8 *s;
+
+ /* no data, don't print */
+ if (len == 0)
+ return;
+
+ if (is_printable_string(data, len)) {
+ printf(" = \"%s\"", (char *)data);
+ return;
+ }
+
+ switch (len) {
+ case 1: /* byte */
+ printf(" = <0x%02x>", (*(u8 *) data) & 0xff);
+ break;
+ case 2: /* half-word */
+ printf(" = <0x%04x>", be16_to_cpu(*(u16 *) data) & 0xffff);
+ break;
+ case 4: /* word */
+ printf(" = <0x%08x>", be32_to_cpu(*(u32 *) data) & 0xffffffffU);
+ break;
+ case 8: /* double-word */
+ printf(" = <0x%16llx>", be64_to_cpu(*(uint64_t *) data));
+ break;
+ default: /* anything else... hexdump */
+ printf(" = [");
+ for (i = 0, s = data; i < len; i++)
+ printf("%02x%s", s[i], i < len - 1 ? " " : "");
+ printf("]");
+
+ break;
+ }
+}
+
+void ft_dump_blob(const void *bphp)
+{
+ const struct boot_param_header *bph = bphp;
+ const uint64_t *p_rsvmap = (const uint64_t *)
+ ((const char *)bph + be32_to_cpu(bph->off_mem_rsvmap));
+ const u32 *p_struct = (const u32 *)
+ ((const char *)bph + be32_to_cpu(bph->off_dt_struct));
+ const u32 *p_strings = (const u32 *)
+ ((const char *)bph + be32_to_cpu(bph->off_dt_strings));
+ u32 tag;
+ const u32 *p;
+ const char *s, *t;
+ int depth, sz, shift;
+ int i;
+ uint64_t addr, size;
+
+ if (be32_to_cpu(bph->magic) != OF_DT_HEADER) {
+ /* not valid tree */
+ return;
+ }
+
+ depth = 0;
+ shift = 4;
+
+ for (i = 0;; i++) {
+ addr = be64_to_cpu(p_rsvmap[i * 2]);
+ size = be64_to_cpu(p_rsvmap[i * 2 + 1]);
+ if (addr == 0 && size == 0)
+ break;
+
+ printf("/memreserve/ 0x%llx 0x%llx;\n", addr, size);
+ }
+
+ p = p_struct;
+ while ((tag = be32_to_cpu(*p++)) != OF_DT_END) {
+
+ /* printf("tag: 0x%08x (%d)\n", tag, p - p_struct); */
+
+ if (tag == OF_DT_BEGIN_NODE) {
+ s = (const char *)p;
+ p = (u32 *) _ALIGN((unsigned long)p + strlen(s) + 1, 4);
+
+ printf("%*s%s {\n", depth * shift, "", s);
+
+ depth++;
+ continue;
+ }
+
+ if (tag == OF_DT_END_NODE) {
+ depth--;
+
+ printf("%*s};\n", depth * shift, "");
+ continue;
+ }
+
+ if (tag == OF_DT_NOP) {
+ printf("%*s[NOP]\n", depth * shift, "");
+ continue;
+ }
+
+ if (tag != OF_DT_PROP) {
+ fprintf(stderr, "%*s ** Unknown tag 0x%08x\n",
+ depth * shift, "", tag);
+ break;
+ }
+ sz = be32_to_cpu(*p++);
+ s = (const char *)p_strings + be32_to_cpu(*p++);
+ t = (const char *)p;
+ p = (const u32 *)_ALIGN((unsigned long)p + sz, 4);
+ printf("%*s%s", depth * shift, "", s);
+ print_data(t, sz);
+ printf(";\n");
+ }
+}
+
+void ft_backtrack_node(struct ft_cxt *cxt)
+{
+ if (be32_to_cpu(*(u32 *) (cxt->p - 4)) != OF_DT_END_NODE)
+ return; /* XXX only for node */
+
+ cxt->p -= 4;
+}
+
+/* note that the root node of the blob is "peeled" off */
+void ft_merge_blob(struct ft_cxt *cxt, void *blob)
+{
+ struct boot_param_header *bph = (struct boot_param_header *)blob;
+ u32 *p_struct = (u32 *) ((char *)bph + be32_to_cpu(bph->off_dt_struct));
+ u32 *p_strings =
+ (u32 *) ((char *)bph + be32_to_cpu(bph->off_dt_strings));
+ u32 tag, *p;
+ char *s, *t;
+ int depth, sz;
+
+ if (be32_to_cpu(*(u32 *) (cxt->p - 4)) != OF_DT_END_NODE)
+ return; /* XXX only for node */
+
+ cxt->p -= 4;
+
+ depth = 0;
+ p = p_struct;
+ while ((tag = be32_to_cpu(*p++)) != OF_DT_END) {
+
+ /* printf("tag: 0x%08x (%d) - %d\n", tag, p - p_struct, depth); */
+
+ if (tag == OF_DT_BEGIN_NODE) {
+ s = (char *)p;
+ p = (u32 *) _ALIGN((unsigned long)p + strlen(s) + 1, 4);
+
+ if (depth++ > 0)
+ ft_begin_node(cxt, s);
+
+ continue;
+ }
+
+ if (tag == OF_DT_END_NODE) {
+ ft_end_node(cxt);
+ if (--depth == 0)
+ break;
+ continue;
+ }
+
+ if (tag == OF_DT_NOP)
+ continue;
+
+ if (tag != OF_DT_PROP)
+ break;
+
+ sz = be32_to_cpu(*p++);
+ s = (char *)p_strings + be32_to_cpu(*p++);
+ t = (char *)p;
+ p = (u32 *) _ALIGN((unsigned long)p + sz, 4);
+
+ ft_prop(cxt, s, t, sz);
+ }
+}
+
+void *ft_get_prop(void *bphp, const char *propname, int *szp)
+{
+ struct boot_param_header *bph = bphp;
+ uint32_t *p_struct =
+ (uint32_t *) ((char *)bph + be32_to_cpu(bph->off_dt_struct));
+ uint32_t *p_strings =
+ (uint32_t *) ((char *)bph + be32_to_cpu(bph->off_dt_strings));
+ uint32_t version = be32_to_cpu(bph->version);
+ uint32_t tag;
+ uint32_t *p;
+ char *s, *t;
+ char *ss;
+ int sz;
+ static char path[256], prop[256];
+
+ path[0] = '\0';
+
+ p = p_struct;
+ while ((tag = be32_to_cpu(*p++)) != OF_DT_END) {
+
+ if (tag == OF_DT_BEGIN_NODE) {
+ s = (char *)p;
+ p = (uint32_t *) _ALIGN((unsigned long)p + strlen(s) +
+ 1, 4);
+ strcat(path, s);
+ strcat(path, "/");
+ continue;
+ }
+
+ if (tag == OF_DT_END_NODE) {
+ path[strlen(path) - 1] = '\0';
+ ss = strrchr(path, '/');
+ if (ss != NULL)
+ ss[1] = '\0';
+ continue;
+ }
+
+ if (tag == OF_DT_NOP)
+ continue;
+
+ if (tag != OF_DT_PROP)
+ break;
+
+ sz = be32_to_cpu(*p++);
+ s = (char *)p_strings + be32_to_cpu(*p++);
+ if (version < 0x10 && sz >= 8)
+ p = (uint32_t *) _ALIGN((unsigned long)p, 8);
+ t = (char *)p;
+ p = (uint32_t *) _ALIGN((unsigned long)p + sz, 4);
+
+ strcpy(prop, path);
+ strcat(prop, s);
+
+ if (strcmp(prop, propname) == 0) {
+ *szp = sz;
+ return t;
+ }
+ }
+
+ return NULL;
+}
+
+/********************************************************************/
+
+extern unsigned char oftree_dtb[];
+extern unsigned int oftree_dtb_len;
+
+/* Function that returns a character from the environment */
+extern uchar(*env_get_char) (int);
+
+#define BDM(x) { .name = #x, .offset = offsetof(bd_t, bi_ ##x ) }
+
+static const struct {
+ const char *name;
+ int offset;
+} bd_map[] = {
+ BDM(memstart),
+ BDM(memsize),
+ BDM(flashstart),
+ BDM(flashsize),
+ BDM(flashoffset),
+ BDM(sramstart),
+ BDM(sramsize),
+#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \
+ || defined(CONFIG_E500)
+ BDM(immr_base),
+#endif
+#if defined(CONFIG_MPC5xxx)
+ BDM(mbar_base),
+#endif
+#if defined(CONFIG_MPC83XX)
+ BDM(immrbar),
+#endif
+#if defined(CONFIG_MPC8220)
+ BDM(mbar_base),
+ BDM(inpfreq),
+ BDM(pcifreq),
+ BDM(pevfreq),
+ BDM(flbfreq),
+ BDM(vcofreq),
+#endif
+ BDM(bootflags),
+ BDM(ip_addr),
+ BDM(intfreq),
+ BDM(busfreq),
+#ifdef CONFIG_CPM2
+ BDM(cpmfreq),
+ BDM(brgfreq),
+ BDM(sccfreq),
+ BDM(vco),
+#endif
+#if defined(CONFIG_MPC5xxx)
+ BDM(ipbfreq),
+ BDM(pcifreq),
+#endif
+ BDM(baudrate),
+};
+
+void ft_setup(void *blob, int size, bd_t * bd)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ u8 *end;
+ u32 *p;
+ int len;
+ struct ft_cxt cxt;
+ int i, k, nxt;
+ static char tmpenv[256];
+ char *s, *lval, *rval;
+ ulong clock;
+ uint32_t v;
+
+ /* disable OF tree; booting old kernel */
+ if (getenv("disable_of") != NULL) {
+ memcpy(blob, bd, sizeof(*bd));
+ return;
+ }
+
+ ft_begin(&cxt, blob, size);
+
+ /* fs_add_rsvmap not used */
+
+ ft_begin_tree(&cxt);
+
+ ft_begin_node(&cxt, "");
+
+ ft_end_node(&cxt);
+
+ /* copy RO tree */
+ ft_merge_blob(&cxt, oftree_dtb);
+
+ /* back into root */
+ ft_backtrack_node(&cxt);
+
+ ft_begin_node(&cxt, "u-boot-env");
+
+ for (i = 0; env_get_char(i) != '\0'; i = nxt + 1) {
+ for (nxt = i; env_get_char(nxt) != '\0'; ++nxt) ;
+ s = tmpenv;
+ for (k = i; k < nxt && s < &tmpenv[sizeof(tmpenv) - 1]; ++k)
+ *s++ = env_get_char(k);
+ *s++ = '\0';
+ lval = tmpenv;
+ s = strchr(tmpenv, '=');
+ if (s != NULL) {
+ *s++ = '\0';
+ rval = s;
+ } else
+ continue;
+ ft_prop_str(&cxt, lval, rval);
+ }
+
+ ft_end_node(&cxt);
+
+ ft_begin_node(&cxt, "chosen");
+
+ ft_prop_str(&cxt, "name", "chosen");
+ ft_prop_str(&cxt, "bootargs", getenv("bootargs"));
+ ft_prop_int(&cxt, "linux,platform", 0x600); /* what is this? */
+
+ ft_end_node(&cxt);
+
+ ft_end_node(&cxt); /* end root */
+
+ ft_end_tree(&cxt);
+
+ /*
+ printf("merged OF-tree\n");
+ ft_dump_blob(blob);
+ */
+
+ /* paste the bd_t at the end of the flat tree */
+ end = (char *)blob +
+ be32_to_cpu(((struct boot_param_header *)blob)->totalsize);
+ memcpy(end, bd, sizeof(*bd));
+
+#ifdef CONFIG_PPC
+
+ for (i = 0; i < sizeof(bd_map)/sizeof(bd_map[0]); i++) {
+ sprintf(tmpenv, "/bd_t/%s", bd_map[i].name);
+ v = *(uint32_t *)((char *)bd + bd_map[i].offset);
+
+ p = ft_get_prop(blob, tmpenv, &len);
+ if (p != NULL)
+ *p = cpu_to_be32(v);
+ }
+
+ p = ft_get_prop(blob, "/bd_t/enetaddr", &len);
+ if (p != NULL)
+ memcpy(p, bd->bi_enetaddr, 6);
+
+ p = ft_get_prop(blob, "/bd_t/ethspeed", &len);
+ if (p != NULL)
+ *p = cpu_to_be32((uint32_t) bd->bi_ethspeed);
+
+ clock = bd->bi_intfreq;
+ p = ft_get_prop(blob, "/cpus/" OF_CPU "/clock-frequency", &len);
+ if (p != NULL)
+ *p = cpu_to_be32(clock);
+
+#ifdef OF_TBCLK
+ clock = OF_TBCLK;
+ p = ft_get_prop(blob, "/cpus/" OF_CPU "/timebase-frequency", &len);
+ if (p != NULL)
+ *p = cpu_to_be32(OF_TBCLK);
+#endif
+
+#endif /* __powerpc__ */
+
+ /*
+ printf("final OF-tree\n");
+ ft_dump_blob(blob);
+ */
+
+}
+
+#endif
#endif
/* "globals" within this file */
-static char *ifs;
+static uchar *ifs;
static char map[256];
#ifndef __U_BOOT__
static int fake_mode;
pi->progs = NULL;
pi->next = NULL;
pi->followup = 0; /* invalid */
+ pi->r_mode = RES_NONE;
return pi;
}
void update_ifs_map(void)
{
/* char *ifs and char map[256] are both globals. */
- ifs = getenv("IFS");
- if (ifs == NULL) ifs=" \t\n";
+ ifs = (uchar *)getenv("IFS");
+ if (ifs == NULL) ifs=(uchar *)" \t\n";
/* Precompute a list of 'flow through' behavior so it can be treated
* quickly up front. Computation is necessary because of IFS.
* Special case handling of IFS == " \t\n" is not implemented.
*/
memset(map,0,sizeof(map)); /* most characters flow through always */
#ifndef __U_BOOT__
- mapset("\\$'\"`", 3); /* never flow through */
- mapset("<>;&|(){}#", 1); /* flow through if quoted */
+ mapset((uchar *)"\\$'\"`", 3); /* never flow through */
+ mapset((uchar *)"<>;&|(){}#", 1); /* flow through if quoted */
#else
- mapset("\\$'\"", 3); /* never flow through */
- mapset(";&|#", 1); /* flow through if quoted */
+ mapset((uchar *)"\\$'\"", 3); /* never flow through */
+ mapset((uchar *)";&|#", 1); /* flow through if quoted */
#endif
mapset(ifs, 2); /* also flow through if quoted */
}
ctx.type = flag;
initialize_context(&ctx);
update_ifs_map();
- if (!(flag & FLAG_PARSE_SEMICOLON) || (flag & FLAG_REPARSING)) mapset(";$&|", 0);
+ if (!(flag & FLAG_PARSE_SEMICOLON) || (flag & FLAG_REPARSING)) mapset((uchar *)";$&|", 0);
inp->promptmode=1;
rcode = parse_stream(&temp, &ctx, inp, '\n');
#ifdef __U_BOOT__
}
*buf = 0;
longjmp_on_fault = 0;
- return buf;
+ return (unsigned char *)buf;
}
/* convert the hex array pointed to by buf into binary to be placed in mem
*ptr++ = hexchars[rp->num >> 4];
*ptr++ = hexchars[rp->num & 0xf];
*ptr++ = ':';
- ptr = mem2hex((char *)&rp->val, ptr, 4);
+ ptr = (char *)mem2hex((char *)&rp->val, ptr, 4);
*ptr++ = ';';
}
printf("kgdb: remcomOutBuffer: %s\n", remcomOutBuffer);
#endif
- putpacket(remcomOutBuffer);
+ putpacket((unsigned char *)&remcomOutBuffer);
while (1) {
volatile int errnum;
#endif
/* reply to the request */
- putpacket(remcomOutBuffer);
+ putpacket((unsigned char *)&remcomOutBuffer);
} /* while(1) */
}
buffer[0] = 'O';
mem2hex ((char *)s, &buffer[1], count);
- putpacket(buffer);
+ putpacket((unsigned char *)&buffer);
return 1;
}
static inline void lcd_puts_xy (ushort x, ushort y, uchar *s)
{
#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
- lcd_drawchars (x, y+BMP_LOGO_HEIGHT, s, strlen (s));
+ lcd_drawchars (x, y+BMP_LOGO_HEIGHT, s, strlen ((char *)s));
#else
- lcd_drawchars (x, y, s, strlen (s));
+ lcd_drawchars (x, y, s, strlen ((char *)s));
#endif
}
sizeof(bmp_logo_palette)/(sizeof(ushort)));
bmap = &bmp_logo_bitmap[0];
- fb = (char *)(lcd_base + y * lcd_line_length + x);
+ fb = (uchar *)(lcd_base + y * lcd_line_length + x);
if (NBITS(panel_info.vl_bpix) < 12) {
/* Leave room for default color map */
bmp_color_table_entry_t cte = bmp->color_table[i];
ushort colreg =
( ((cte.red) << 8) & 0xf800) |
- ( ((cte.green) << 4) & 0x07e0) |
- ( (cte.blue) & 0x001f) ;
-
+ ( ((cte.green) << 3) & 0x07e0) |
+ ( ((cte.blue) >> 3) & 0x001f) ;
#ifdef CFG_INVERT_COLORS
*cmap = 0xffff - colreg;
#else
#ifdef CONFIG_MPC823
# ifdef CONFIG_LCD_INFO
sprintf (info, "%s (%s - %s) ", U_BOOT_VERSION, __DATE__, __TIME__);
- lcd_drawchars (LCD_INFO_X, LCD_INFO_Y, info, strlen(info));
+ lcd_drawchars (LCD_INFO_X, LCD_INFO_Y, (uchar *)info, strlen(info));
sprintf (info, "(C) 2004 DENX Software Engineering");
lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT,
- info, strlen(info));
+ (uchar *)info, strlen(info));
sprintf (info, " Wolfgang DENK, wd@denx.de");
lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 2,
- info, strlen(info));
+ (uchar *)info, strlen(info));
# ifdef CONFIG_LCD_INFO_BELOW_LOGO
sprintf (info, "MPC823 CPU at %s MHz",
strmhz(temp, gd->cpu_clk));
gd->ram_size >> 20,
gd->bd->bi_flashsize >> 20 );
lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 4,
- info, strlen(info));
+ (uchar *)info, strlen(info));
# endif /* CONFIG_LCD_INFO_BELOW_LOGO */
# endif /* CONFIG_LCD_INFO */
#include <common.h>
#include <watchdog.h>
#include <command.h>
-#include <malloc.h>
+#ifdef CONFIG_MODEM_SUPPORT
+#include <malloc.h> /* for free() prototype */
+#endif
#ifdef CFG_HUSH_PARSER
#include <hush.h>
#ifdef CONFIG_MODEM_SUPPORT
debug ("DEBUG: main_loop: do_mdm_init=%d\n", do_mdm_init);
if (do_mdm_init) {
- uchar *str = strdup(getenv("mdm_cmd"));
+ char *str = strdup(getenv("mdm_cmd"));
setenv ("preboot", str); /* set or delete definition */
if (str != NULL)
free (str);
* Returns:
* 0 on success
*/
-int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
+int bb_miiphy_read (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value)
{
short rdreg; /* register working value */
int j; /* counter */
* Returns:
* 0 on success
*/
-int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
+int bb_miiphy_write (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value)
{
int j; /* counter */
#ifndef CONFIG_EP8248
#include <miiphy.h>
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+#include <asm/types.h>
+#include <linux/list.h>
+#include <malloc.h>
+#include <net.h>
+
+/* local debug macro */
+#define MII_DEBUG
+#undef MII_DEBUG
+
+#undef debug
+#ifdef MII_DEBUG
+#define debug(fmt,args...) printf (fmt ,##args)
+#else
+#define debug(fmt,args...)
+#endif /* MII_DEBUG */
+
+struct mii_dev {
+ struct list_head link;
+ char *name;
+ int (* read)(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value);
+ int (* write)(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value);
+};
+
+static struct list_head mii_devs;
+static struct mii_dev *current_mii;
+
+/*****************************************************************************
+ *
+ * Initialize global data. Need to be called before any other miiphy routine.
+ */
+void miiphy_init()
+{
+ INIT_LIST_HEAD(&mii_devs);
+ current_mii = NULL;
+}
+
+/*****************************************************************************
+ *
+ * Register read and write MII access routines for the device <name>.
+ */
+void miiphy_register(char *name,
+ int (* read)(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value),
+ int (* write)(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value))
+{
+ struct list_head *entry;
+ struct mii_dev *new_dev;
+ struct mii_dev *miidev;
+ unsigned int name_len;
+
+ /* check if we have unique name */
+ list_for_each(entry, &mii_devs) {
+ miidev = list_entry(entry, struct mii_dev, link);
+ if (strcmp(miidev->name, name) == 0) {
+ printf("miiphy_register: non unique device name '%s'\n",
+ name);
+ return;
+ }
+ }
+
+ /* allocate memory */
+ name_len = strlen(name);
+ new_dev = (struct mii_dev *)malloc(sizeof(struct mii_dev) + name_len + 1);
+
+ if(new_dev == NULL) {
+ printf("miiphy_register: cannot allocate memory for '%s'\n",
+ name);
+ return;
+ }
+ memset(new_dev, 0, sizeof(struct mii_dev) + name_len);
+
+ /* initalize mii_dev struct fields */
+ INIT_LIST_HEAD(&new_dev->link);
+ new_dev->read = read;
+ new_dev->write = write;
+ new_dev->name = (char *)(new_dev + 1);
+ strncpy(new_dev->name, name, name_len);
+ new_dev->name[name_len] = '\0';
+
+ debug("miiphy_register: added '%s', read=0x%08lx, write=0x%08lx\n",
+ new_dev->name, new_dev->read, new_dev->write);
+
+ /* add it to the list */
+ list_add_tail(&new_dev->link, &mii_devs);
+
+ if (!current_mii)
+ current_mii = new_dev;
+}
+
+int miiphy_set_current_dev(char *devname)
+{
+ struct list_head *entry;
+ struct mii_dev *dev;
+
+ list_for_each(entry, &mii_devs) {
+ dev = list_entry(entry, struct mii_dev, link);
+
+ if (strcmp(devname, dev->name) == 0) {
+ current_mii = dev;
+ return 0;
+ }
+ }
+
+ printf("No such device: %s\n", devname);
+ return 1;
+}
+
+char *miiphy_get_current_dev()
+{
+ if (current_mii)
+ return current_mii->name;
+
+ return NULL;
+}
+
+/*****************************************************************************
+ *
+ * Read to variable <value> from the PHY attached to device <devname>,
+ * use PHY address <addr> and register <reg>.
+ *
+ * Returns:
+ * 0 on success
+ */
+int miiphy_read(char *devname, unsigned char addr, unsigned char reg,
+ unsigned short *value)
+{
+ struct list_head *entry;
+ struct mii_dev *dev;
+ int found_dev = 0;
+ int read_ret = 0;
+
+ if (!devname) {
+ printf("NULL device name!\n");
+ return 1;
+ }
+
+ list_for_each(entry, &mii_devs) {
+ dev = list_entry(entry, struct mii_dev, link);
+
+ if (strcmp(devname, dev->name) == 0) {
+ found_dev = 1;
+ read_ret = dev->read(devname, addr, reg, value);
+ break;
+ }
+ }
+
+ if (found_dev == 0)
+ printf("No such device: %s\n", devname);
+
+ return ((found_dev) ? read_ret : 1);
+}
+
+/*****************************************************************************
+ *
+ * Write <value> to the PHY attached to device <devname>,
+ * use PHY address <addr> and register <reg>.
+ *
+ * Returns:
+ * 0 on success
+ */
+int miiphy_write(char *devname, unsigned char addr, unsigned char reg,
+ unsigned short value)
+{
+ struct list_head *entry;
+ struct mii_dev *dev;
+ int found_dev = 0;
+ int write_ret = 0;
+
+ if (!devname) {
+ printf("NULL device name!\n");
+ return 1;
+ }
+
+ list_for_each(entry, &mii_devs) {
+ dev = list_entry(entry, struct mii_dev, link);
+
+ if (strcmp(devname, dev->name) == 0) {
+ found_dev = 1;
+ write_ret = dev->write(devname, addr, reg, value);
+ break;
+ }
+ }
+
+ if (found_dev == 0)
+ printf("No such device: %s\n", devname);
+
+ return ((found_dev) ? write_ret : 1);
+}
+
+/*****************************************************************************
+ *
+ * Print out list of registered MII capable devices.
+ */
+void miiphy_listdev(void)
+{
+ struct list_head *entry;
+ struct mii_dev *dev;
+
+ puts("MII devices: ");
+ list_for_each(entry, &mii_devs) {
+ dev = list_entry(entry, struct mii_dev, link);
+ printf("'%s' ", dev->name);
+ }
+ puts("\n");
+
+ if (current_mii)
+ printf("Current device: '%s'\n", current_mii->name);
+}
+
/*****************************************************************************
*
* Returns:
* 0 on success
*/
-int miiphy_info (unsigned char addr,
+int miiphy_info (char *devname,
+ unsigned char addr,
unsigned int *oui,
unsigned char *model, unsigned char *rev)
{
unsigned int reg = 0;
unsigned short tmp;
- if (miiphy_read (addr, PHY_PHYIDR2, &tmp) != 0) {
+ if (miiphy_read (devname, addr, PHY_PHYIDR2, &tmp) != 0) {
#ifdef DEBUG
puts ("PHY ID register 2 read failed\n");
#endif
return (-1);
}
- if (miiphy_read (addr, PHY_PHYIDR1, &tmp) != 0) {
+ if (miiphy_read (devname, addr, PHY_PHYIDR1, &tmp) != 0) {
#ifdef DEBUG
puts ("PHY ID register 1 read failed\n");
#endif
* Returns:
* 0 on success
*/
-int miiphy_reset (unsigned char addr)
+int miiphy_reset (char *devname, unsigned char addr)
{
unsigned short reg;
int loop_cnt;
- if (miiphy_read (addr, PHY_BMCR, ®) != 0) {
+ if (miiphy_read (devname, addr, PHY_BMCR, ®) != 0) {
#ifdef DEBUG
printf ("PHY status read failed\n");
#endif
return (-1);
}
- if (miiphy_write (addr, PHY_BMCR, reg | 0x8000) != 0) {
+ if (miiphy_write (devname, addr, PHY_BMCR, reg | 0x8000) != 0) {
#ifdef DEBUG
puts ("PHY reset failed\n");
#endif
loop_cnt = 0;
reg = 0x8000;
while (((reg & 0x8000) != 0) && (loop_cnt++ < 1000000)) {
- if (miiphy_read (addr, PHY_BMCR, ®) != 0) {
+ if (miiphy_read (devname, addr, PHY_BMCR, ®) != 0) {
# ifdef DEBUG
puts ("PHY status read failed\n");
# endif
*
* Determine the ethernet speed (10/100).
*/
-int miiphy_speed (unsigned char addr)
+int miiphy_speed (char *devname, unsigned char addr)
{
unsigned short reg;
#if defined(CONFIG_PHY_GIGE)
- if (miiphy_read (addr, PHY_1000BTSR, ®)) {
+ if (miiphy_read (devname, addr, PHY_1000BTSR, ®)) {
printf ("PHY 1000BT Status read failed\n");
} else {
if (reg != 0xFFFF) {
#endif /* CONFIG_PHY_GIGE */
/* Check Basic Management Control Register first. */
- if (miiphy_read (addr, PHY_BMCR, ®)) {
+ if (miiphy_read (devname, addr, PHY_BMCR, ®)) {
puts ("PHY speed read failed, assuming 10bT\n");
return (_10BASET);
}
/* Check if auto-negotiation is on. */
if ((reg & PHY_BMCR_AUTON) != 0) {
/* Get auto-negotiation results. */
- if (miiphy_read (addr, PHY_ANLPAR, ®)) {
+ if (miiphy_read (devname, addr, PHY_ANLPAR, ®)) {
puts ("PHY AN speed read failed, assuming 10bT\n");
return (_10BASET);
}
*
* Determine full/half duplex.
*/
-int miiphy_duplex (unsigned char addr)
+int miiphy_duplex (char *devname, unsigned char addr)
{
unsigned short reg;
#if defined(CONFIG_PHY_GIGE)
- if (miiphy_read (addr, PHY_1000BTSR, ®)) {
+ if (miiphy_read (devname, addr, PHY_1000BTSR, ®)) {
printf ("PHY 1000BT Status read failed\n");
} else {
if ( (reg != 0xFFFF) &&
#endif /* CONFIG_PHY_GIGE */
/* Check Basic Management Control Register first. */
- if (miiphy_read (addr, PHY_BMCR, ®)) {
+ if (miiphy_read (devname, addr, PHY_BMCR, ®)) {
puts ("PHY duplex read failed, assuming half duplex\n");
return (HALF);
}
/* Check if auto-negotiation is on. */
if ((reg & PHY_BMCR_AUTON) != 0) {
/* Get auto-negotiation results. */
- if (miiphy_read (addr, PHY_ANLPAR, ®)) {
+ if (miiphy_read (devname, addr, PHY_ANLPAR, ®)) {
puts ("PHY AN duplex read failed, assuming half duplex\n");
return (HALF);
}
*
* Determine link status
*/
-int miiphy_link (unsigned char addr)
+int miiphy_link (char *devname, unsigned char addr)
{
unsigned short reg;
/* dummy read; needed to latch some phys */
- (void)miiphy_read(addr, PHY_BMSR, ®);
- if (miiphy_read (addr, PHY_BMSR, ®)) {
+ (void)miiphy_read(devname, addr, PHY_BMSR, ®);
+ if (miiphy_read (devname, addr, PHY_BMSR, ®)) {
puts ("PHY_BMSR read failed, assuming no link\n");
return (0);
}
*/
uchar i2c_reg_read(uchar i2c_addr, uchar reg)
{
- char buf;
+ uchar buf;
i2c_read(i2c_addr, reg, 1, &buf, 1);
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * Configuration support for Xilinx Spartan3 devices. Based
+ * on spartan2.c (Rich Ireland, rireland@enterasys.com).
+ */
+
+#include <common.h> /* core U-Boot definitions */
+#include <spartan3.h> /* Spartan-II device family */
+
+#if (CONFIG_FPGA & (CFG_XILINX | CFG_SPARTAN3))
+
+/* Define FPGA_DEBUG to get debug printf's */
+#ifdef FPGA_DEBUG
+#define PRINTF(fmt,args...) printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+#undef CFG_FPGA_CHECK_BUSY
+#undef CFG_FPGA_PROG_FEEDBACK
+
+/* Note: The assumption is that we cannot possibly run fast enough to
+ * overrun the device (the Slave Parallel mode can free run at 50MHz).
+ * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
+ * the board config file to slow things down.
+ */
+#ifndef CONFIG_FPGA_DELAY
+#define CONFIG_FPGA_DELAY()
+#endif
+
+#ifndef CFG_FPGA_WAIT
+#define CFG_FPGA_WAIT CFG_HZ/100 /* 10 ms */
+#endif
+
+static int Spartan3_sp_load( Xilinx_desc *desc, void *buf, size_t bsize );
+static int Spartan3_sp_dump( Xilinx_desc *desc, void *buf, size_t bsize );
+/* static int Spartan3_sp_info( Xilinx_desc *desc ); */
+static int Spartan3_sp_reloc( Xilinx_desc *desc, ulong reloc_offset );
+
+static int Spartan3_ss_load( Xilinx_desc *desc, void *buf, size_t bsize );
+static int Spartan3_ss_dump( Xilinx_desc *desc, void *buf, size_t bsize );
+/* static int Spartan3_ss_info( Xilinx_desc *desc ); */
+static int Spartan3_ss_reloc( Xilinx_desc *desc, ulong reloc_offset );
+
+/* ------------------------------------------------------------------------- */
+/* Spartan-II Generic Implementation */
+int Spartan3_load (Xilinx_desc * desc, void *buf, size_t bsize)
+{
+ int ret_val = FPGA_FAIL;
+
+ switch (desc->iface) {
+ case slave_serial:
+ PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
+ ret_val = Spartan3_ss_load (desc, buf, bsize);
+ break;
+
+ case slave_parallel:
+ PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
+ ret_val = Spartan3_sp_load (desc, buf, bsize);
+ break;
+
+ default:
+ printf ("%s: Unsupported interface type, %d\n",
+ __FUNCTION__, desc->iface);
+ }
+
+ return ret_val;
+}
+
+int Spartan3_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+{
+ int ret_val = FPGA_FAIL;
+
+ switch (desc->iface) {
+ case slave_serial:
+ PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
+ ret_val = Spartan3_ss_dump (desc, buf, bsize);
+ break;
+
+ case slave_parallel:
+ PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
+ ret_val = Spartan3_sp_dump (desc, buf, bsize);
+ break;
+
+ default:
+ printf ("%s: Unsupported interface type, %d\n",
+ __FUNCTION__, desc->iface);
+ }
+
+ return ret_val;
+}
+
+int Spartan3_info( Xilinx_desc *desc )
+{
+ return FPGA_SUCCESS;
+}
+
+
+int Spartan3_reloc (Xilinx_desc * desc, ulong reloc_offset)
+{
+ int ret_val = FPGA_FAIL; /* assume a failure */
+
+ if (desc->family != Xilinx_Spartan3) {
+ printf ("%s: Unsupported family type, %d\n",
+ __FUNCTION__, desc->family);
+ return FPGA_FAIL;
+ } else
+ switch (desc->iface) {
+ case slave_serial:
+ ret_val = Spartan3_ss_reloc (desc, reloc_offset);
+ break;
+
+ case slave_parallel:
+ ret_val = Spartan3_sp_reloc (desc, reloc_offset);
+ break;
+
+ default:
+ printf ("%s: Unsupported interface type, %d\n",
+ __FUNCTION__, desc->iface);
+ }
+
+ return ret_val;
+}
+
+
+/* ------------------------------------------------------------------------- */
+/* Spartan-II Slave Parallel Generic Implementation */
+
+static int Spartan3_sp_load (Xilinx_desc * desc, void *buf, size_t bsize)
+{
+ int ret_val = FPGA_FAIL; /* assume the worst */
+ Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns;
+
+ PRINTF ("%s: start with interface functions @ 0x%p\n",
+ __FUNCTION__, fn);
+
+ if (fn) {
+ size_t bytecount = 0;
+ unsigned char *data = (unsigned char *) buf;
+ int cookie = desc->cookie; /* make a local copy */
+ unsigned long ts; /* timestamp */
+
+ PRINTF ("%s: Function Table:\n"
+ "ptr:\t0x%p\n"
+ "struct: 0x%p\n"
+ "pre: 0x%p\n"
+ "pgm:\t0x%p\n"
+ "init:\t0x%p\n"
+ "err:\t0x%p\n"
+ "clk:\t0x%p\n"
+ "cs:\t0x%p\n"
+ "wr:\t0x%p\n"
+ "read data:\t0x%p\n"
+ "write data:\t0x%p\n"
+ "busy:\t0x%p\n"
+ "abort:\t0x%p\n",
+ "post:\t0x%p\n\n",
+ __FUNCTION__, &fn, fn, fn->pre, fn->pgm, fn->init, fn->err,
+ fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, fn->busy,
+ fn->abort, fn->post);
+
+ /*
+ * This code is designed to emulate the "Express Style"
+ * Continuous Data Loading in Slave Parallel Mode for
+ * the Spartan-II Family.
+ */
+#ifdef CFG_FPGA_PROG_FEEDBACK
+ printf ("Loading FPGA Device %d...\n", cookie);
+#endif
+ /*
+ * Run the pre configuration function if there is one.
+ */
+ if (*fn->pre) {
+ (*fn->pre) (cookie);
+ }
+
+ /* Establish the initial state */
+ (*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */
+
+ /* Get ready for the burn */
+ CONFIG_FPGA_DELAY ();
+ (*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */
+
+ ts = get_timer (0); /* get current time */
+ /* Now wait for INIT and BUSY to go high */
+ do {
+ CONFIG_FPGA_DELAY ();
+ if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
+ puts ("** Timeout waiting for INIT to clear.\n");
+ (*fn->abort) (cookie); /* abort the burn */
+ return FPGA_FAIL;
+ }
+ } while ((*fn->init) (cookie) && (*fn->busy) (cookie));
+
+ (*fn->wr) (TRUE, TRUE, cookie); /* Assert write, commit */
+ (*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
+ (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
+
+ /* Load the data */
+ while (bytecount < bsize) {
+ /* XXX - do we check for an Ctrl-C press in here ??? */
+ /* XXX - Check the error bit? */
+
+ (*fn->wdata) (data[bytecount++], TRUE, cookie); /* write the data */
+ CONFIG_FPGA_DELAY ();
+ (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
+ CONFIG_FPGA_DELAY ();
+ (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
+
+#ifdef CFG_FPGA_CHECK_BUSY
+ ts = get_timer (0); /* get current time */
+ while ((*fn->busy) (cookie)) {
+ /* XXX - we should have a check in here somewhere to
+ * make sure we aren't busy forever... */
+
+ CONFIG_FPGA_DELAY ();
+ (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
+ CONFIG_FPGA_DELAY ();
+ (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
+
+ if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
+ puts ("** Timeout waiting for BUSY to clear.\n");
+ (*fn->abort) (cookie); /* abort the burn */
+ return FPGA_FAIL;
+ }
+ }
+#endif
+
+#ifdef CFG_FPGA_PROG_FEEDBACK
+ if (bytecount % (bsize / 40) == 0)
+ putc ('.'); /* let them know we are alive */
+#endif
+ }
+
+ CONFIG_FPGA_DELAY ();
+ (*fn->cs) (FALSE, TRUE, cookie); /* Deassert the chip select */
+ (*fn->wr) (FALSE, TRUE, cookie); /* Deassert the write pin */
+
+#ifdef CFG_FPGA_PROG_FEEDBACK
+ putc ('\n'); /* terminate the dotted line */
+#endif
+
+ /* now check for done signal */
+ ts = get_timer (0); /* get current time */
+ ret_val = FPGA_SUCCESS;
+ while ((*fn->done) (cookie) == FPGA_FAIL) {
+ /* XXX - we should have a check in here somewhere to
+ * make sure we aren't busy forever... */
+
+ CONFIG_FPGA_DELAY ();
+ (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
+ CONFIG_FPGA_DELAY ();
+ (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
+
+ if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
+ puts ("** Timeout waiting for DONE to clear.\n");
+ (*fn->abort) (cookie); /* abort the burn */
+ ret_val = FPGA_FAIL;
+ break;
+ }
+ }
+
+ if (ret_val == FPGA_SUCCESS) {
+#ifdef CFG_FPGA_PROG_FEEDBACK
+ puts ("Done.\n");
+#endif
+ }
+ /*
+ * Run the post configuration function if there is one.
+ */
+ if (*fn->post) {
+ (*fn->post) (cookie);
+ }
+
+ else {
+#ifdef CFG_FPGA_PROG_FEEDBACK
+ puts ("Fail.\n");
+#endif
+ }
+
+ } else {
+ printf ("%s: NULL Interface function table!\n", __FUNCTION__);
+ }
+
+ return ret_val;
+}
+
+static int Spartan3_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+{
+ int ret_val = FPGA_FAIL; /* assume the worst */
+ Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns;
+
+ if (fn) {
+ unsigned char *data = (unsigned char *) buf;
+ size_t bytecount = 0;
+ int cookie = desc->cookie; /* make a local copy */
+
+ printf ("Starting Dump of FPGA Device %d...\n", cookie);
+
+ (*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
+ (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
+
+ /* dump the data */
+ while (bytecount < bsize) {
+ /* XXX - do we check for an Ctrl-C press in here ??? */
+
+ (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
+ (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
+ (*fn->rdata) (&(data[bytecount++]), cookie); /* read the data */
+#ifdef CFG_FPGA_PROG_FEEDBACK
+ if (bytecount % (bsize / 40) == 0)
+ putc ('.'); /* let them know we are alive */
+#endif
+ }
+
+ (*fn->cs) (FALSE, FALSE, cookie); /* Deassert the chip select */
+ (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
+ (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
+
+#ifdef CFG_FPGA_PROG_FEEDBACK
+ putc ('\n'); /* terminate the dotted line */
+#endif
+ puts ("Done.\n");
+
+ /* XXX - checksum the data? */
+ } else {
+ printf ("%s: NULL Interface function table!\n", __FUNCTION__);
+ }
+
+ return ret_val;
+}
+
+
+static int Spartan3_sp_reloc (Xilinx_desc * desc, ulong reloc_offset)
+{
+ int ret_val = FPGA_FAIL; /* assume the worst */
+ Xilinx_Spartan3_Slave_Parallel_fns *fn_r, *fn =
+ (Xilinx_Spartan3_Slave_Parallel_fns *) (desc->iface_fns);
+
+ if (fn) {
+ ulong addr;
+
+ /* Get the relocated table address */
+ addr = (ulong) fn + reloc_offset;
+ fn_r = (Xilinx_Spartan3_Slave_Parallel_fns *) addr;
+
+ if (!fn_r->relocated) {
+
+ if (memcmp (fn_r, fn,
+ sizeof (Xilinx_Spartan3_Slave_Parallel_fns))
+ == 0) {
+ /* good copy of the table, fix the descriptor pointer */
+ desc->iface_fns = fn_r;
+ } else {
+ PRINTF ("%s: Invalid function table at 0x%p\n",
+ __FUNCTION__, fn_r);
+ return FPGA_FAIL;
+ }
+
+ PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
+ desc);
+
+ addr = (ulong) (fn->pre) + reloc_offset;
+ fn_r->pre = (Xilinx_pre_fn) addr;
+
+ addr = (ulong) (fn->pgm) + reloc_offset;
+ fn_r->pgm = (Xilinx_pgm_fn) addr;
+
+ addr = (ulong) (fn->init) + reloc_offset;
+ fn_r->init = (Xilinx_init_fn) addr;
+
+ addr = (ulong) (fn->done) + reloc_offset;
+ fn_r->done = (Xilinx_done_fn) addr;
+
+ addr = (ulong) (fn->clk) + reloc_offset;
+ fn_r->clk = (Xilinx_clk_fn) addr;
+
+ addr = (ulong) (fn->err) + reloc_offset;
+ fn_r->err = (Xilinx_err_fn) addr;
+
+ addr = (ulong) (fn->cs) + reloc_offset;
+ fn_r->cs = (Xilinx_cs_fn) addr;
+
+ addr = (ulong) (fn->wr) + reloc_offset;
+ fn_r->wr = (Xilinx_wr_fn) addr;
+
+ addr = (ulong) (fn->rdata) + reloc_offset;
+ fn_r->rdata = (Xilinx_rdata_fn) addr;
+
+ addr = (ulong) (fn->wdata) + reloc_offset;
+ fn_r->wdata = (Xilinx_wdata_fn) addr;
+
+ addr = (ulong) (fn->busy) + reloc_offset;
+ fn_r->busy = (Xilinx_busy_fn) addr;
+
+ addr = (ulong) (fn->abort) + reloc_offset;
+ fn_r->abort = (Xilinx_abort_fn) addr;
+
+ addr = (ulong) (fn->post) + reloc_offset;
+ fn_r->post = (Xilinx_post_fn) addr;
+
+ fn_r->relocated = TRUE;
+
+ } else {
+ /* this table has already been moved */
+ /* XXX - should check to see if the descriptor is correct */
+ desc->iface_fns = fn_r;
+ }
+
+ ret_val = FPGA_SUCCESS;
+ } else {
+ printf ("%s: NULL Interface function table!\n", __FUNCTION__);
+ }
+
+ return ret_val;
+
+}
+
+/* ------------------------------------------------------------------------- */
+
+static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
+{
+ int ret_val = FPGA_FAIL; /* assume the worst */
+ Xilinx_Spartan3_Slave_Serial_fns *fn = desc->iface_fns;
+ int i;
+ char val;
+
+ PRINTF ("%s: start with interface functions @ 0x%p\n",
+ __FUNCTION__, fn);
+
+ if (fn) {
+ size_t bytecount = 0;
+ unsigned char *data = (unsigned char *) buf;
+ int cookie = desc->cookie; /* make a local copy */
+ unsigned long ts; /* timestamp */
+
+ PRINTF ("%s: Function Table:\n"
+ "ptr:\t0x%p\n"
+ "struct: 0x%p\n"
+ "pgm:\t0x%p\n"
+ "init:\t0x%p\n"
+ "clk:\t0x%p\n"
+ "wr:\t0x%p\n"
+ "done:\t0x%p\n\n",
+ __FUNCTION__, &fn, fn, fn->pgm, fn->init,
+ fn->clk, fn->wr, fn->done);
+#ifdef CFG_FPGA_PROG_FEEDBACK
+ printf ("Loading FPGA Device %d...\n", cookie);
+#endif
+
+ /*
+ * Run the pre configuration function if there is one.
+ */
+ if (*fn->pre) {
+ (*fn->pre) (cookie);
+ }
+
+ /* Establish the initial state */
+ (*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */
+
+ /* Wait for INIT state (init low) */
+ ts = get_timer (0); /* get current time */
+ do {
+ CONFIG_FPGA_DELAY ();
+ if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
+ puts ("** Timeout waiting for INIT to start.\n");
+ return FPGA_FAIL;
+ }
+ } while (!(*fn->init) (cookie));
+
+ /* Get ready for the burn */
+ CONFIG_FPGA_DELAY ();
+ (*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */
+
+ ts = get_timer (0); /* get current time */
+ /* Now wait for INIT to go high */
+ do {
+ CONFIG_FPGA_DELAY ();
+ if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
+ puts ("** Timeout waiting for INIT to clear.\n");
+ return FPGA_FAIL;
+ }
+ } while ((*fn->init) (cookie));
+
+ /* Load the data */
+ while (bytecount < bsize) {
+
+ /* Xilinx detects an error if INIT goes low (active)
+ while DONE is low (inactive) */
+ if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
+ puts ("** CRC error during FPGA load.\n");
+ return (FPGA_FAIL);
+ }
+ val = data [bytecount ++];
+ i = 8;
+ do {
+ /* Deassert the clock */
+ (*fn->clk) (FALSE, TRUE, cookie);
+ CONFIG_FPGA_DELAY ();
+ /* Write data */
+ (*fn->wr) ((val < 0), TRUE, cookie);
+ CONFIG_FPGA_DELAY ();
+ /* Assert the clock */
+ (*fn->clk) (TRUE, TRUE, cookie);
+ CONFIG_FPGA_DELAY ();
+ val <<= 1;
+ i --;
+ } while (i > 0);
+
+#ifdef CFG_FPGA_PROG_FEEDBACK
+ if (bytecount % (bsize / 40) == 0)
+ putc ('.'); /* let them know we are alive */
+#endif
+ }
+
+ CONFIG_FPGA_DELAY ();
+
+#ifdef CFG_FPGA_PROG_FEEDBACK
+ putc ('\n'); /* terminate the dotted line */
+#endif
+
+ /* now check for done signal */
+ ts = get_timer (0); /* get current time */
+ ret_val = FPGA_SUCCESS;
+ (*fn->wr) (TRUE, TRUE, cookie);
+
+ while (! (*fn->done) (cookie)) {
+ /* XXX - we should have a check in here somewhere to
+ * make sure we aren't busy forever... */
+
+ CONFIG_FPGA_DELAY ();
+ (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
+ CONFIG_FPGA_DELAY ();
+ (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
+
+ putc ('*');
+
+ if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
+ puts ("** Timeout waiting for DONE to clear.\n");
+ ret_val = FPGA_FAIL;
+ break;
+ }
+ }
+ putc ('\n'); /* terminate the dotted line */
+
+#ifdef CFG_FPGA_PROG_FEEDBACK
+ if (ret_val == FPGA_SUCCESS) {
+ puts ("Done.\n");
+ }
+ else {
+ puts ("Fail.\n");
+ }
+#endif
+
+ } else {
+ printf ("%s: NULL Interface function table!\n", __FUNCTION__);
+ }
+
+ return ret_val;
+}
+
+static int Spartan3_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+{
+ /* Readback is only available through the Slave Parallel and */
+ /* boundary-scan interfaces. */
+ printf ("%s: Slave Serial Dumping is unavailable\n",
+ __FUNCTION__);
+ return FPGA_FAIL;
+}
+
+static int Spartan3_ss_reloc (Xilinx_desc * desc, ulong reloc_offset)
+{
+ int ret_val = FPGA_FAIL; /* assume the worst */
+ Xilinx_Spartan3_Slave_Serial_fns *fn_r, *fn =
+ (Xilinx_Spartan3_Slave_Serial_fns *) (desc->iface_fns);
+
+ if (fn) {
+ ulong addr;
+
+ /* Get the relocated table address */
+ addr = (ulong) fn + reloc_offset;
+ fn_r = (Xilinx_Spartan3_Slave_Serial_fns *) addr;
+
+ if (!fn_r->relocated) {
+
+ if (memcmp (fn_r, fn,
+ sizeof (Xilinx_Spartan3_Slave_Serial_fns))
+ == 0) {
+ /* good copy of the table, fix the descriptor pointer */
+ desc->iface_fns = fn_r;
+ } else {
+ PRINTF ("%s: Invalid function table at 0x%p\n",
+ __FUNCTION__, fn_r);
+ return FPGA_FAIL;
+ }
+
+ PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
+ desc);
+
+ addr = (ulong) (fn->pre) + reloc_offset;
+ fn_r->pre = (Xilinx_pre_fn) addr;
+
+ addr = (ulong) (fn->pgm) + reloc_offset;
+ fn_r->pgm = (Xilinx_pgm_fn) addr;
+
+ addr = (ulong) (fn->init) + reloc_offset;
+ fn_r->init = (Xilinx_init_fn) addr;
+
+ addr = (ulong) (fn->done) + reloc_offset;
+ fn_r->done = (Xilinx_done_fn) addr;
+
+ addr = (ulong) (fn->clk) + reloc_offset;
+ fn_r->clk = (Xilinx_clk_fn) addr;
+
+ addr = (ulong) (fn->wr) + reloc_offset;
+ fn_r->wr = (Xilinx_wr_fn) addr;
+
+ fn_r->relocated = TRUE;
+
+ } else {
+ /* this table has already been moved */
+ /* XXX - should check to see if the descriptor is correct */
+ desc->iface_fns = fn_r;
+ }
+
+ ret_val = FPGA_SUCCESS;
+ } else {
+ printf ("%s: NULL Interface function table!\n", __FUNCTION__);
+ }
+
+ return ret_val;
+
+}
+
+#endif
*/
int usb_stor_CB_comdat(ccb *srb, struct us_data *us)
{
- int result;
+ int result = 0;
int dir_in,retry;
unsigned int pipe;
unsigned long status;
USB_STOR_PRINTF("CB_transport: control msg returned %d, direction is %s to go 0x%lx\n",result,dir_in ? "IN" : "OUT",srb->datalen);
if (srb->datalen) {
- result = us_one_transfer(us, pipe, srb->pdata,srb->datalen);
+ result = us_one_transfer(us, pipe, (char *)srb->pdata,srb->datalen);
USB_STOR_PRINTF("CBI attempted to transfer data, result is %d status %lX, len %d\n", result,us->pusb_dev->status,us->pusb_dev->act_len);
if(!(us->pusb_dev->status & USB_ST_NAK_REC))
break;
{
char *ptr;
- ptr=srb->pdata;
+ ptr=(char *)srb->pdata;
memset(&srb->cmd[0],0,12);
srb->cmd[0]=SCSI_REQ_SENSE;
srb->cmd[1]=srb->lun<<5;
srb->cmdlen=12;
ss->transport(srb,ss);
USB_STOR_PRINTF("Request Sense returned %02X %02X %02X\n",srb->sense_buf[2],srb->sense_buf[12],srb->sense_buf[13]);
- srb->pdata=ptr;
+ srb->pdata=(uchar *)ptr;
return 0;
}
#if (CONFIG_FPGA & (CFG_XILINX | CFG_VIRTEX2))
+#if 0
+#define FPGA_DEBUG
+#endif
+
#ifdef FPGA_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
* this process, a configuration error (most likely CRC failure) has
* ocurred. At this point a status word may be read from the
* SelectMap interface to determine the source of the problem (You
- * could, for instance, put this in you 'abort' function handler).
+ * could, for instance, put this in your 'abort' function handler).
* 4. After all data has been written, test the state of the FPGA
* INIT_B and DONE lines. If both are high, configuration has
* succeeded. Congratulations!
ts = get_timer (0);
do {
if (get_timer (ts) > CFG_FPGA_WAIT_INIT) {
- printf ("%s:%d: ** Timeout after %d mS waiting for INIT"
+ printf ("%s:%d: ** Timeout after %d ticks waiting for INIT"
" to assert.\n", __FUNCTION__, __LINE__,
CFG_FPGA_WAIT_INIT);
(*fn->abort) (cookie);
do {
CONFIG_FPGA_DELAY ();
if (get_timer (ts) > CFG_FPGA_WAIT_INIT) {
- printf ("%s:%d: ** Timeout after %d mS waiting for INIT"
+ printf ("%s:%d: ** Timeout after %d ticks waiting for INIT"
" to deassert.\n", __FUNCTION__, __LINE__,
CFG_FPGA_WAIT_INIT);
(*fn->abort) (cookie);
return FPGA_FAIL;
}
#endif
+
+ if ((*fn->done) (cookie) == FPGA_SUCCESS) {
+ PRINTF ("%s:%d:done went active early, bytecount = %d\n",
+ __FUNCTION__, __LINE__, bytecount);
+ break;
+ }
+
#ifdef CFG_FPGA_CHECK_ERROR
if ((*fn->init) (cookie)) {
- printf ("%s:%d: ** Error: INIT asserted during"
+ printf ("\n%s:%d: ** Error: INIT asserted during"
" configuration\n", __FUNCTION__, __LINE__);
+ printf ("%d = buffer offset, %d = buffer size\n",
+ bytecount, bsize);
(*fn->abort) (cookie);
return FPGA_FAIL;
}
#endif
+
(*fn->wdata) (data[bytecount++], TRUE, cookie);
CONFIG_FPGA_DELAY ();
ts = get_timer (0);
while ((*fn->busy) (cookie)) {
if (get_timer (ts) > CFG_FPGA_WAIT_BUSY) {
- printf ("%s:%d: ** Timeout after %d mS waiting for"
+ printf ("%s:%d: ** Timeout after %d ticks waiting for"
" BUSY to deassert\n",
__FUNCTION__, __LINE__, CFG_FPGA_WAIT_BUSY);
(*fn->abort) (cookie);
ret_val = FPGA_SUCCESS;
while (((*fn->done) (cookie) == FPGA_FAIL) || (*fn->init) (cookie)) {
if (get_timer (ts) > CFG_FPGA_WAIT_CONFIG) {
- printf ("%s:%d: ** Timeout after %d mS waiting for DONE to"
+ printf ("%s:%d: ** Timeout after %d ticks waiting for DONE to"
"assert and INIT to deassert\n",
__FUNCTION__, __LINE__, CFG_FPGA_WAIT_CONFIG);
(*fn->abort) (cookie);
#include <common.h>
#include <virtex2.h>
#include <spartan2.h>
+#include <spartan3.h>
#if (CONFIG_FPGA & CFG_FPGA_XILINX)
{
int ret_val = FPGA_FAIL; /* assume a failure */
- if (!xilinx_validate (desc, __FUNCTION__)) {
+ if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
printf ("%s: Invalid device descriptor\n", __FUNCTION__);
} else
switch (desc->family) {
__FUNCTION__);
#endif
break;
+ case Xilinx_Spartan3:
+#if (CONFIG_FPGA & CFG_SPARTAN3)
+ PRINTF ("%s: Launching the Spartan-III Loader...\n",
+ __FUNCTION__);
+ ret_val = Spartan3_load (desc, buf, bsize);
+#else
+ printf ("%s: No support for Spartan-III devices.\n",
+ __FUNCTION__);
+#endif
+ break;
case Xilinx_Virtex2:
#if (CONFIG_FPGA & CFG_VIRTEX2)
PRINTF ("%s: Launching the Virtex-II Loader...\n",
{
int ret_val = FPGA_FAIL; /* assume a failure */
- if (!xilinx_validate (desc, __FUNCTION__)) {
+ if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
printf ("%s: Invalid device descriptor\n", __FUNCTION__);
} else
switch (desc->family) {
__FUNCTION__);
#endif
break;
+ case Xilinx_Spartan3:
+#if (CONFIG_FPGA & CFG_SPARTAN3)
+ PRINTF ("%s: Launching the Spartan-III Reader...\n",
+ __FUNCTION__);
+ ret_val = Spartan3_dump (desc, buf, bsize);
+#else
+ printf ("%s: No support for Spartan-III devices.\n",
+ __FUNCTION__);
+#endif
+ break;
case Xilinx_Virtex2:
#if (CONFIG_FPGA & CFG_VIRTEX2)
PRINTF ("%s: Launching the Virtex-II Reader...\n",
{
int ret_val = FPGA_FAIL;
- if (xilinx_validate (desc, __FUNCTION__)) {
+ if (xilinx_validate (desc, (char *)__FUNCTION__)) {
printf ("Family: \t");
switch (desc->family) {
case Xilinx_Spartan2:
printf ("Spartan-II\n");
break;
+ case Xilinx_Spartan3:
+ printf ("Spartan-III\n");
+ break;
case Xilinx_Virtex2:
printf ("Virtex-II\n");
break;
__FUNCTION__);
#endif
break;
+ case Xilinx_Spartan3:
+#if (CONFIG_FPGA & CFG_SPARTAN3)
+ Spartan3_info (desc);
+#else
+ /* just in case */
+ printf ("%s: No support for Spartan-III devices.\n",
+ __FUNCTION__);
+#endif
+ break;
case Xilinx_Virtex2:
#if (CONFIG_FPGA & CFG_VIRTEX2)
Virtex2_info (desc);
{
int ret_val = FPGA_FAIL; /* assume a failure */
- if (!xilinx_validate (desc, __FUNCTION__)) {
+ if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
printf ("%s: Invalid device descriptor\n", __FUNCTION__);
} else
switch (desc->family) {
__FUNCTION__);
#endif
break;
+ case Xilinx_Spartan3:
+#if (CONFIG_FPGA & CFG_SPARTAN3)
+ ret_val = Spartan3_reloc (desc, reloc_offset);
+#else
+ printf ("%s: No support for Spartan-III devices.\n",
+ __FUNCTION__);
+#endif
+ break;
case Xilinx_Virtex2:
#if (CONFIG_FPGA & CFG_VIRTEX2)
ret_val = Virtex2_reloc (desc, reloc_offset);
HOSTSTRIP = strip
#########################################################################
+#
+# Option checker (courtesy linux kernel) to ensure
+# only supported compiler options are used
+#
+cc-option = $(shell if $(CC) $(CFLAGS) $(1) -S -o /dev/null -xc /dev/null \
+ > /dev/null 2>&1; then echo "$(1)"; else echo "$(2)"; fi ;)
#
# Include the make variables (CC, etc...)
# MA 02111-1307 USA
#
PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
+ -msoft-float
# Make ARMv5 to allow more compilers to work, even though its v6.
-PLATFORM_CPPFLAGS += -mapcs-32 -march=armv5
+PLATFORM_CPPFLAGS += -march=armv5
+# =========================================================================
+#
+# Supply options according to compiler version
+#
+# =========================================================================
+PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
+PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
#include <common.h>
#include <command.h>
+#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR)
#include <asm/arch/omap2420.h>
+#endif
/* read co-processor 15, register #1 (control register) */
static unsigned long read_p15_c1 (void)
#include <common.h>
#include <asm/arch/bits.h>
-#include <asm/arch/omap2420.h>
+
+#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR)
+# include <asm/arch/omap2420.h>
+#endif
+
#include <asm/proc-armv/ptrace.h>
#define TIMER_LOAD_VAL 0
bad_mode ();
}
+#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR)
+/* Use the IntegratorCP function from board/integratorcp.c */
+#else
+
static ulong timestamp;
static ulong lastinc;
return(0);
}
-
/*
* timer without interrupts
*/
{
return get_timer(0);
}
-
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
tbclk = CFG_HZ;
return tbclk;
}
+#endif /* !Integrator/CP */
#include <config.h>
#include <version.h>
+#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR)
#include <asm/arch/omap2420.h>
-
+#endif
.globl _start
_start: b reset
ldr pc, _undefined_instruction
* basic memory. Go here to bump up clock rate and handle wake up conditions.
*/
mov ip, lr /* persevere link reg across call */
- bl platformsetup /* go setup pll,mux,memory */
+ bl lowlevel_init /* go setup pll,mux,memory */
mov lr, ip /* restore link */
mov pc, lr /* back to my caller */
/*
mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
mov pc, lr @ back to caller
+#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR)
+/* Use the IntegratorCP function from board/integratorcp/platform.S */
+#else
+
.align 5
.globl reset_cpu
reset_cpu:
b _loop_forever
rstctl:
.word PM_RSTCTRL_WKUP
+
+#endif
#
PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
- -mshort-load-bytes -msoft-float
+ -msoft-float
-PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=arm7tdmi
+PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi
+# =========================================================================
+#
+# Supply options according to compiler version
+#
+# =========================================================================
+PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
+PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
* and we set the CPU-speed to 73 MHz - see start.S for details
*/
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312)
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
unsigned long i;
disable_interrupts ();
#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B)
disable_interrupts ();
/* Nothing more needed */
+#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+ /* No cleanup before linux for IntegratorAP/CM720T as yet */
#else
#error No cleanup_before_linux() defined for this CPU type
#endif
*
*/
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM)
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO)
/* read co-processor 15, register #1 (control register) */
static unsigned long read_p15_c1(void)
{
return icache_status();
}
+#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+ /* No specific cache setup for IntegratorAP/CM720T as yet */
+ void icache_enable (void)
+ {
+ }
#else
#error No icache/dcache enable/disable functions defined for this CPU type
#endif
void do_irq (struct pt_regs *pt_regs)
{
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM)
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO)
printf ("interrupt request\n");
show_regs (pt_regs);
bad_mode ();
/* clear pending interrupt */
PUT_REG( REG_INTPEND, (1<<(pending>>2)));
}
+#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+ /* No do_irq() for IntegratorAP/CM720T as yet */
#else
#error do_irq() not defined for this CPU type
#endif
}
#endif
+#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+ /* Use IntegratorAP routines in board/integratorap.c */
+#else
+
static ulong timestamp;
static ulong lastdec;
/* set timer 2 counter */
lastdec = TIMER_LOAD_VAL;
-#elif defined(CONFIG_IMPA7) || defined(CONFIG_EP7312)
+#elif defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
/* disable all interrupts */
IO_INTMR1 = 0;
return (0);
}
+#endif /* ! IntegratorAP */
+
/*
* timer without interrupts
*/
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM)
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO)
void reset_timer (void)
{
}
+#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+ /* No timer routines for IntegratorAP/CM720T as yet */
#else
#error Timer routines not defined for this CPU type
#endif
#include <common.h>
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312)
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
#include <clps7111.h>
#include <asm/hardware.h>
#define PORTA (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTA))
+#if !defined(CONFIG_NETARM_NS7520)
#define PORTB (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTB))
+#else
+#define PORTC (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTC))
+#endif
/* wait until transmitter is ready for another character */
#define TXWAITRDY(registers) \
}
+#ifndef CONFIG_UART1_CONSOLE
volatile netarm_serial_channel_t *serial_reg_ch1 = get_serial_channel(0);
volatile netarm_serial_channel_t *serial_reg_ch2 = get_serial_channel(1);
+#else
+volatile netarm_serial_channel_t *serial_reg_ch1 = get_serial_channel(1);
+volatile netarm_serial_channel_t *serial_reg_ch2 = get_serial_channel(0);
+#endif
extern void _netarm_led_FAIL1(void);
DECLARE_GLOBAL_DATA_PTR;
/* set 0 ... make sure pins are configured for serial */
+#if !defined(CONFIG_NETARM_NS7520)
PORTA = PORTB =
NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0);
+#else
+ PORTA = NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0);
+ PORTC = NETARM_GEN_PORT_CSF (0xef) | NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0);
+#endif
/* first turn em off */
serial_reg_ch1->ctrl_a = serial_reg_ch2->ctrl_a = 0;
*************************************************************************
*/
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312)
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
/* Interupt-Controller base addresses */
INTMR1: .word 0x80000280 @ 32 bit size
#endif
cpu_init_crit:
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312)
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
/*
* mask all IRQs by clearing all bits in the INTMRs
str r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL]
+#ifndef CONFIG_NETARM_PLL_BYPASS
ldr r1, =( NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \
NETARM_GEN_PLL_CTL_POLTST_DEF | \
NETARM_GEN_PLL_CTL_INDIV(1) | \
NETARM_GEN_PLL_CTL_ICP_DEF | \
NETARM_GEN_PLL_CTL_OUTDIV(2) )
str r1, [r0, #+NETARM_GEN_PLL_CONTROL]
+#endif
+
/*
* mask all IRQs by clearing all bits in the INTMRs
*/
ldr r1, =0x83ffffa0 /* cache-disabled */
str r1, [r0]
+#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+ /* No specific initialisation for IntegratorAP/CM720T as yet */
#else
#error No cpu_init_crit() defined for current CPU type
#endif
str r1, [r0]
#endif
+ mov ip, lr
/*
* before relocating, we have to setup RAM timing
* because memory timing is board-dependent, you will
* find a lowlevel_init.S in your board directory.
*/
- mov ip, lr
bl lowlevel_init
mov lr, ip
#endif
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312)
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
.align 5
.globl reset_cpu
reset_cpu:
#elif defined(CONFIG_S3C4510B)
/* Nothing done here as reseting the CPU is board specific, depending
* on external peripherals such as watchdog timers, etc. */
+#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+ /* No specific reset actions for IntegratorAP/CM720T as yet */
#else
#error No reset_cpu() defined for current CPU type
#endif
LIB = lib$(SOC).a
-OBJS = ether.o i2c.o interrupts.o serial.o
+OBJS = bcm5221.o dm9161.o ether.o i2c.o interrupts.o \
+ lxt972.o serial.o usb_ohci.o
SOBJS = lowlevel_init.o
all: .depend $(LIB)
#########################################################################
-.depend: Makefile $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
/*
+ * Broadcom BCM5221 Ethernet PHY
+ *
+ * (C) Copyright 2005 REA Elektronik GmbH <www.rea.de>
+ * Anders Larsen <alarsen@rea.de>
+ *
* (C) Copyright 2003
* Author : Hamid Ikdoumi (Atmel)
*
#include <at91rm9200_net.h>
#include <net.h>
-#include <dm9161.h>
+#include <bcm5221.h>
#ifdef CONFIG_DRIVER_ETHER
/*
* Name:
- * dm9161_IsPhyConnected
+ * bcm5221_IsPhyConnected
* Description:
* Reads the 2 PHY ID registers
* Arguments:
* TRUE - if id read successfully
* FALSE- if error
*/
-static unsigned int dm9161_IsPhyConnected (AT91PS_EMAC p_mac)
+unsigned int bcm5221_IsPhyConnected (AT91PS_EMAC p_mac)
{
unsigned short Id1, Id2;
at91rm9200_EmacEnableMDIO (p_mac);
- at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID1, &Id1);
- at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID2, &Id2);
+ at91rm9200_EmacReadPhy (p_mac, BCM5221_PHYID1, &Id1);
+ at91rm9200_EmacReadPhy (p_mac, BCM5221_PHYID2, &Id2);
at91rm9200_EmacDisableMDIO (p_mac);
- if ((Id1 == (DM9161_PHYID1_OUI >> 6)) &&
- ((Id2 >> 10) == (DM9161_PHYID1_OUI & DM9161_LSB_MASK)))
+ if ((Id1 == (BCM5221_PHYID1_OUI >> 6)) &&
+ ((Id2 >> 10) == (BCM5221_PHYID1_OUI & BCM5221_LSB_MASK)))
return TRUE;
return FALSE;
/*
* Name:
- * dm9161_GetLinkSpeed
+ * bcm5221_GetLinkSpeed
* Description:
* Link parallel detection status of MAC is checked and set in the
* MAC configuration registers
* TRUE - if link status set succesfully
* FALSE - if link status not set
*/
-static UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac)
+unsigned char bcm5221_GetLinkSpeed (AT91PS_EMAC p_mac)
{
unsigned short stat1, stat2;
- if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &stat1))
+ if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMSR, &stat1))
return FALSE;
- if (!(stat1 & DM9161_LINK_STATUS)) /* link status up? */
+ if (!(stat1 & BCM5221_LINK_STATUS)) /* link status up? */
return FALSE;
- if (!at91rm9200_EmacReadPhy (p_mac, DM9161_DSCSR, &stat2))
+ if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_ACSR, &stat2))
return FALSE;
- if ((stat1 & DM9161_100BASE_TX_FD) && (stat2 & DM9161_100FDX)) {
+ if ((stat1 & BCM5221_100BASE_TX_FD) && (stat2 & BCM5221_100) && (stat2 & BCM5221_FDX)) {
/*set Emac for 100BaseTX and Full Duplex */
p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
return TRUE;
}
- if ((stat1 & DM9161_10BASE_T_FD) && (stat2 & DM9161_10FDX)) {
+ if ((stat1 & BCM5221_10BASE_T_FD) && !(stat2 & BCM5221_100) && (stat2 & BCM5221_FDX)) {
/*set MII for 10BaseT and Full Duplex */
p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
return TRUE;
}
- if ((stat1 & DM9161_100BASE_T4_HD) && (stat2 & DM9161_100HDX)) {
+ if ((stat1 & BCM5221_100BASE_TX_HD) && (stat2 & BCM5221_100) && !(stat2 & BCM5221_FDX)) {
/*set MII for 100BaseTX and Half Duplex */
p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
return TRUE;
}
- if ((stat1 & DM9161_10BASE_T_HD) && (stat2 & DM9161_10HDX)) {
+ if ((stat1 & BCM5221_10BASE_T_HD) && !(stat2 & BCM5221_100) && !(stat2 & BCM5221_FDX)) {
/*set MII for 10BaseT and Half Duplex */
p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
return TRUE;
/*
* Name:
- * dm9161_InitPhy
+ * bcm5221_InitPhy
* Description:
* MAC starts checking its link by using parallel detection and
* Autonegotiation and the same is set in the MAC configuration registers
* TRUE - if link status set succesfully
* FALSE - if link status not set
*/
-static UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac)
+unsigned char bcm5221_InitPhy (AT91PS_EMAC p_mac)
{
- UCHAR ret = TRUE;
+ unsigned char ret = TRUE;
unsigned short IntValue;
at91rm9200_EmacEnableMDIO (p_mac);
- if (!dm9161_GetLinkSpeed (p_mac)) {
+ if (!bcm5221_GetLinkSpeed (p_mac)) {
/* Try another time */
- ret = dm9161_GetLinkSpeed (p_mac);
+ ret = bcm5221_GetLinkSpeed (p_mac);
}
/* Disable PHY Interrupts */
- at91rm9200_EmacReadPhy (p_mac, DM9161_MDINTR, &IntValue);
- /* clear FDX, SPD, Link, INTR masks */
- IntValue &= ~(DM9161_FDX_MASK | DM9161_SPD_MASK |
- DM9161_LINK_MASK | DM9161_INTR_MASK);
- at91rm9200_EmacWritePhy (p_mac, DM9161_MDINTR, &IntValue);
+ at91rm9200_EmacReadPhy (p_mac, BCM5221_INTR, &IntValue);
+ /* clear FDX LED and INTR Enable */
+ IntValue &= ~(BCM5221_FDX_LED | BCM5221_INTR_ENABLE);
+ /* set FDX, SPD, Link, INTR masks */
+ IntValue |= (BCM5221_FDX_MASK | BCM5221_SPD_MASK |
+ BCM5221_LINK_MASK | BCM5221_INTR_MASK);
+ at91rm9200_EmacWritePhy (p_mac, BCM5221_INTR, &IntValue);
at91rm9200_EmacDisableMDIO (p_mac);
return (ret);
/*
* Name:
- * dm9161_AutoNegotiate
+ * bcm5221_AutoNegotiate
* Description:
* MAC Autonegotiates with the partner status of same is set in the
* MAC configuration registers
* TRUE - if link status set successfully
* FALSE - if link status not set
*/
-static UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
+unsigned char bcm5221_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
{
unsigned short value;
unsigned short PhyAnar;
unsigned short PhyAnalpar;
- /* Set dm9161 control register */
- if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
+ /* Set bcm5221 control register */
+ if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMCR, &value))
return FALSE;
- value &= ~DM9161_AUTONEG; /* remove autonegotiation enable */
- value |= DM9161_ISOLATE; /* Electrically isolate PHY */
- if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
+ value &= ~BCM5221_AUTONEG; /* remove autonegotiation enable */
+ value |= BCM5221_ISOLATE; /* Electrically isolate PHY */
+ if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value))
return FALSE;
/* Set the Auto_negotiation Advertisement Register */
- /* MII advertising for Next page, 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */
- PhyAnar = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX |
- DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3;
- if (!at91rm9200_EmacWritePhy (p_mac, DM9161_ANAR, &PhyAnar))
+ /* MII advertising for 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */
+ PhyAnar = BCM5221_TX_FDX | BCM5221_TX_HDX |
+ BCM5221_10_FDX | BCM5221_10_HDX | BCM5221_AN_IEEE_802_3;
+ if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_ANAR, &PhyAnar))
return FALSE;
/* Read the Control Register */
- if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
+ if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMCR, &value))
return FALSE;
- value |= DM9161_SPEED_SELECT | DM9161_AUTONEG | DM9161_DUPLEX_MODE;
- if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
+ value |= BCM5221_SPEED_SELECT | BCM5221_AUTONEG | BCM5221_DUPLEX_MODE;
+ if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value))
return FALSE;
/* Restart Auto_negotiation */
- value |= DM9161_RESTART_AUTONEG;
- if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
+ value |= BCM5221_RESTART_AUTONEG;
+ value &= ~BCM5221_ISOLATE;
+ if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value))
return FALSE;
/*check AutoNegotiate complete */
udelay (10000);
- at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &value);
- if (!(value & DM9161_AUTONEG_COMP))
+ at91rm9200_EmacReadPhy (p_mac, BCM5221_BMSR, &value);
+ if (!(value & BCM5221_AUTONEG_COMP))
return FALSE;
/* Get the AutoNeg Link partner base page */
- if (!at91rm9200_EmacReadPhy (p_mac, DM9161_ANLPAR, &PhyAnalpar))
+ if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_ANLPAR, &PhyAnalpar))
return FALSE;
- if ((PhyAnar & DM9161_TX_FDX) && (PhyAnalpar & DM9161_TX_FDX)) {
+ if ((PhyAnar & BCM5221_TX_FDX) && (PhyAnalpar & BCM5221_TX_FDX)) {
/*set MII for 100BaseTX and Full Duplex */
p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
return TRUE;
}
- if ((PhyAnar & DM9161_10_FDX) && (PhyAnalpar & DM9161_10_FDX)) {
+ if ((PhyAnar & BCM5221_10_FDX) && (PhyAnalpar & BCM5221_10_FDX)) {
/*set MII for 10BaseT and Full Duplex */
p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
return FALSE;
}
-
-/*
- * Name:
- * at91rm92000_GetPhyInterface
- * Description:
- * Initialise the interface functions to the PHY
- * Arguments:
- * None
- * Return value:
- * None
- */
-void at91rm92000_GetPhyInterface(AT91PS_PhyOps p_phyops)
-{
- p_phyops->Init = dm9161_InitPhy;
- p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
- p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
- p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
-}
-
#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
#endif /* CONFIG_DRIVER_ETHER */
* TRUE - if id read successfully
* FALSE- if error
*/
-static unsigned int dm9161_IsPhyConnected (AT91PS_EMAC p_mac)
+unsigned int dm9161_IsPhyConnected (AT91PS_EMAC p_mac)
{
unsigned short Id1, Id2;
* TRUE - if link status set succesfully
* FALSE - if link status not set
*/
-static UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac)
+UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac)
{
unsigned short stat1, stat2;
* TRUE - if link status set succesfully
* FALSE - if link status not set
*/
-static UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac)
+UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac)
{
UCHAR ret = TRUE;
unsigned short IntValue;
/* Disable PHY Interrupts */
at91rm9200_EmacReadPhy (p_mac, DM9161_MDINTR, &IntValue);
- /* clear FDX, SPD, Link, INTR masks */
- IntValue &= ~(DM9161_FDX_MASK | DM9161_SPD_MASK |
- DM9161_LINK_MASK | DM9161_INTR_MASK);
+ /* set FDX, SPD, Link, INTR masks */
+ IntValue |= (DM9161_FDX_MASK | DM9161_SPD_MASK |
+ DM9161_LINK_MASK | DM9161_INTR_MASK);
at91rm9200_EmacWritePhy (p_mac, DM9161_MDINTR, &IntValue);
at91rm9200_EmacDisableMDIO (p_mac);
* TRUE - if link status set successfully
* FALSE - if link status not set
*/
-static UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
+UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
{
unsigned short value;
unsigned short PhyAnar;
return FALSE;
/* Restart Auto_negotiation */
value |= DM9161_RESTART_AUTONEG;
+ value &= ~DM9161_ISOLATE;
if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
return FALSE;
return FALSE;
}
-
-/*
- * Name:
- * at91rm92000_GetPhyInterface
- * Description:
- * Initialise the interface functions to the PHY
- * Arguments:
- * None
- * Return value:
- * None
- */
-void at91rm92000_GetPhyInterface(AT91PS_PhyOps p_phyops)
-{
- p_phyops->Init = dm9161_InitPhy;
- p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
- p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
- p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
-}
-
#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
#endif /* CONFIG_DRIVER_ETHER */
#include <at91rm9200_net.h>
#include <net.h>
+#include <miiphy.h>
/* ----- Ethernet Buffer definitions ----- */
#define RBF_LOCAL2 (1<<24)
#define RBF_LOCAL1 (1<<23)
-/* Emac Buffers in last 512KBytes of SDRAM*/
-/* Be careful, buffer size is limited to 512KBytes !!! */
-#define RBF_FRAMEMAX 100
-/*#define RBF_FRAMEMEM 0x200000 */
-#define RBF_FRAMEMEM 0x21F80000
+#define RBF_FRAMEMAX 64
#define RBF_FRAMELEN 0x600
-#define RBF_FRAMEBTD RBF_FRAMEMEM
-#define RBF_FRAMEBUF (RBF_FRAMEMEM + RBF_FRAMEMAX*sizeof(rbf_t))
-
-
#ifdef CONFIG_DRIVER_ETHER
#if (CONFIG_COMMANDS & CFG_CMD_NET)
+/* alignment as per Errata #11 (64 bytes) is insufficient! */
+rbf_t rbfdt[RBF_FRAMEMAX] __attribute((aligned(512)));
+rbf_t *rbfp;
+
+unsigned char rbf_framebuf[RBF_FRAMEMAX][RBF_FRAMELEN] __attribute((aligned(4)));
+
/* structure to interface the PHY */
AT91S_PhyOps PhyOps;
return TRUE;
}
-
-rbf_t *rbfdt;
-rbf_t *rbfp;
-
int eth_init (bd_t * bd)
{
int ret;
p_mac->EMAC_CFG |= AT91C_EMAC_CSR; /* Clear statistics */
/* Init Ehternet buffers */
- rbfdt = (rbf_t *) RBF_FRAMEBTD;
for (i = 0; i < RBF_FRAMEMAX; i++) {
- rbfdt[i].addr = RBF_FRAMEBUF + RBF_FRAMELEN * i;
+ rbfdt[i].addr = (unsigned long)rbf_framebuf[i];
rbfdt[i].size = 0;
}
rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP;
p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE;
- at91rm92000_GetPhyInterface (& PhyOps);
+ at91rm9200_GetPhyInterface (& PhyOps);
if (!PhyOps.IsPhyConnected (p_mac))
printf ("PHY not connected!!\n\r");
{
};
-#if (CONFIG_COMMANDS & CFG_CMD_MII)
-int miiphy_read(unsigned char addr, unsigned char reg, unsigned short * value)
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+int at91rm9200_miiphy_read(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short * value)
{
at91rm9200_EmacEnableMDIO (p_mac);
at91rm9200_EmacReadPhy (p_mac, reg, value);
return 0;
}
-int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
+int at91rm9200_miiphy_write(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value)
{
at91rm9200_EmacEnableMDIO (p_mac);
at91rm9200_EmacWritePhy (p_mac, reg, &value);
at91rm9200_EmacDisableMDIO (p_mac);
return 0;
}
-#endif /* CONFIG_COMMANDS & CFG_CMD_MII */
+
+#endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) */
+
+int at91rm9200_miiphy_initialize(bd_t *bis)
+{
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+ miiphy_register("at91rm9200phy", at91rm9200_miiphy_read, at91rm9200_miiphy_write);
+#endif
+ return 0;
+}
#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
| ((rw == 1) ? AT91C_TWI_MREAD : 0);
/* Set TWI Internal Address Register with first messages data field */
- /* only one address byte is supported */
if (alen > 0)
- twi->TWI_IADR = addr & 0xff;
+ twi->TWI_IADR = addr;
length = len;
buf = buffer;
cmp r2, r0
bne 2b
+ /* switch from FastBus to Asynchronous clock mode */
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, r0, #0xC0000000 @ set bit 31 (iA) and 30 (nF)
+ mcr p15, 0, r0, c1, c0, 0
+
/* everything is fine now */
mov pc, lr
--- /dev/null
+/*
+ *
+ * (C) Copyright 2003
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Adapted for KwikByte KB920x board: 22APR2005
+ */
+
+#include <common.h>
+#include <at91rm9200_net.h>
+#include <net.h>
+#include <lxt971a.h>
+
+#ifdef CONFIG_DRIVER_ETHER
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+
+/*
+ * Name:
+ * lxt972_IsPhyConnected
+ * Description:
+ * Reads the 2 PHY ID registers
+ * Arguments:
+ * p_mac - pointer to AT91S_EMAC struct
+ * Return value:
+ * TRUE - if id read successfully
+ * FALSE- if error
+ */
+unsigned int lxt972_IsPhyConnected (AT91PS_EMAC p_mac)
+{
+ unsigned short Id1, Id2;
+
+ at91rm9200_EmacEnableMDIO (p_mac);
+ at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_ID1, &Id1);
+ at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_ID2, &Id2);
+ at91rm9200_EmacDisableMDIO (p_mac);
+
+ if ((Id1 == (0x0013)) && ((Id2 & 0xFFF0) == 0x78E0))
+ return TRUE;
+
+ return FALSE;
+}
+
+/*
+ * Name:
+ * lxt972_GetLinkSpeed
+ * Description:
+ * Link parallel detection status of MAC is checked and set in the
+ * MAC configuration registers
+ * Arguments:
+ * p_mac - pointer to MAC
+ * Return value:
+ * TRUE - if link status set succesfully
+ * FALSE - if link status not set
+ */
+UCHAR lxt972_GetLinkSpeed (AT91PS_EMAC p_mac)
+{
+ unsigned short stat1;
+
+ if (!at91rm9200_EmacReadPhy (p_mac, PHY_LXT971_STAT2, &stat1))
+ return FALSE;
+
+ if (!(stat1 & PHY_LXT971_STAT2_LINK)) /* link status up? */
+ return FALSE;
+
+ if (stat1 & PHY_LXT971_STAT2_100BTX) {
+
+ if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) {
+
+ /*set Emac for 100BaseTX and Full Duplex */
+ p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
+ } else {
+
+ /*set Emac for 100BaseTX and Half Duplex */
+ p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+ ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+ | AT91C_EMAC_SPD;
+ }
+
+ return TRUE;
+
+ } else {
+
+ if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) {
+
+ /*set MII for 10BaseT and Full Duplex */
+ p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+ ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+ | AT91C_EMAC_FD;
+ } else {
+
+ /*set MII for 10BaseT and Half Duplex */
+ p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
+ }
+
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+
+/*
+ * Name:
+ * lxt972_InitPhy
+ * Description:
+ * MAC starts checking its link by using parallel detection and
+ * Autonegotiation and the same is set in the MAC configuration registers
+ * Arguments:
+ * p_mac - pointer to struct AT91S_EMAC
+ * Return value:
+ * TRUE - if link status set succesfully
+ * FALSE - if link status not set
+ */
+UCHAR lxt972_InitPhy (AT91PS_EMAC p_mac)
+{
+ UCHAR ret = TRUE;
+
+ at91rm9200_EmacEnableMDIO (p_mac);
+
+ if (!lxt972_GetLinkSpeed (p_mac)) {
+ /* Try another time */
+ ret = lxt972_GetLinkSpeed (p_mac);
+ }
+
+ /* Disable PHY Interrupts */
+ at91rm9200_EmacWritePhy (p_mac, PHY_LXT971_INT_ENABLE, 0);
+
+ at91rm9200_EmacDisableMDIO (p_mac);
+
+ return (ret);
+}
+
+
+/*
+ * Name:
+ * lxt972_AutoNegotiate
+ * Description:
+ * MAC Autonegotiates with the partner status of same is set in the
+ * MAC configuration registers
+ * Arguments:
+ * dev - pointer to struct net_device
+ * Return value:
+ * TRUE - if link status set successfully
+ * FALSE - if link status not set
+ */
+UCHAR lxt972_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
+{
+ unsigned short value;
+
+ /* Set lxt972 control register */
+ if (!at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_CTRL, &value))
+ return FALSE;
+
+ /* Restart Auto_negotiation */
+ value |= PHY_COMMON_CTRL_RES_AUTO;
+ if (!at91rm9200_EmacWritePhy (p_mac, PHY_COMMON_CTRL, &value))
+ return FALSE;
+
+ /*check AutoNegotiate complete */
+ udelay (10000);
+ at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_STAT, &value);
+ if (!(value & PHY_COMMON_STAT_AN_COMP))
+ return FALSE;
+
+ return (lxt972_GetLinkSpeed (p_mac));
+}
+
+#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
+
+#endif /* CONFIG_DRIVER_ETHER */
--- /dev/null
+/*
+ * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200.
+ *
+ * (C) Copyright 2003
+ * Gary Jennejohn, DENX Software Engineering <gj@denx.de>
+ *
+ * Note: Much of this code has been derived from Linux 2.4
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2002 David Brownell
+ *
+ * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
+ * ebenard@eukrea.com - based on s3c24x0's driver
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+/*
+ * IMPORTANT NOTES
+ * 1 - you MUST define LITTLEENDIAN in the configuration file for the
+ * board or this driver will NOT work!
+ * 2 - this driver is intended for use with USB Mass Storage Devices
+ * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
+ * 3 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG
+ * to activate workaround for bug #41 or this driver will NOT work!
+ */
+
+#include <common.h>
+/* #include <pci.h> no PCI on the S3C24X0 */
+
+#ifdef CONFIG_USB_OHCI
+
+#include <asm/arch/hardware.h>
+
+#include <malloc.h>
+#include <usb.h>
+#include "usb_ohci.h"
+
+#define OHCI_USE_NPS /* force NoPowerSwitching mode */
+#undef OHCI_VERBOSE_DEBUG /* not always helpful */
+
+/* For initializing controller (mask in an HCFS mode too) */
+#define OHCI_CONTROL_INIT \
+ (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
+
+#define readl(a) (*((vu_long *)(a)))
+#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))
+
+#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
+
+#undef DEBUG
+#ifdef DEBUG
+#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
+#else
+#define dbg(format, arg...) do {} while(0)
+#endif /* DEBUG */
+#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
+#undef SHOW_INFO
+#ifdef SHOW_INFO
+#define info(format, arg...) printf("INFO: " format "\n", ## arg)
+#else
+#define info(format, arg...) do {} while(0)
+#endif
+
+#define m16_swap(x) swap_16(x)
+#define m32_swap(x) swap_32(x)
+
+/* global ohci_t */
+static ohci_t gohci;
+/* this must be aligned to a 256 byte boundary */
+struct ohci_hcca ghcca[1];
+/* a pointer to the aligned storage */
+struct ohci_hcca *phcca;
+/* this allocates EDs for all possible endpoints */
+struct ohci_device ohci_dev;
+/* urb_priv */
+urb_priv_t urb_priv;
+/* RHSC flag */
+int got_rhsc;
+/* device which was disconnected */
+struct usb_device *devgone;
+
+/*-------------------------------------------------------------------------*/
+
+/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
+ * The erratum (#4) description is incorrect. AMD's workaround waits
+ * till some bits (mostly reserved) are clear; ok for all revs.
+ */
+#define OHCI_QUIRK_AMD756 0xabcd
+#define read_roothub(hc, register, mask) ({ \
+ u32 temp = readl (&hc->regs->roothub.register); \
+ if (hc->flags & OHCI_QUIRK_AMD756) \
+ while (temp & mask) \
+ temp = readl (&hc->regs->roothub.register); \
+ temp; })
+
+static u32 roothub_a (struct ohci *hc)
+ { return read_roothub (hc, a, 0xfc0fe000); }
+static inline u32 roothub_b (struct ohci *hc)
+ { return readl (&hc->regs->roothub.b); }
+static inline u32 roothub_status (struct ohci *hc)
+ { return readl (&hc->regs->roothub.status); }
+static u32 roothub_portstatus (struct ohci *hc, int i)
+ { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
+
+
+/* forward declaration */
+static int hc_interrupt (void);
+static void
+td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
+ int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
+
+/*-------------------------------------------------------------------------*
+ * URB support functions
+ *-------------------------------------------------------------------------*/
+
+/* free HCD-private data associated with this URB */
+
+static void urb_free_priv (urb_priv_t * urb)
+{
+ int i;
+ int last;
+ struct td * td;
+
+ last = urb->length - 1;
+ if (last >= 0) {
+ for (i = 0; i <= last; i++) {
+ td = urb->td[i];
+ if (td) {
+ td->usb_dev = NULL;
+ urb->td[i] = NULL;
+ }
+ }
+ }
+}
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef DEBUG
+static int sohci_get_current_frame_number (struct usb_device * dev);
+
+/* debug| print the main components of an URB
+ * small: 0) header + data packets 1) just header */
+
+static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
+ int transfer_len, struct devrequest * setup, char * str, int small)
+{
+ urb_priv_t * purb = &urb_priv;
+
+ dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
+ str,
+ sohci_get_current_frame_number (dev),
+ usb_pipedevice (pipe),
+ usb_pipeendpoint (pipe),
+ usb_pipeout (pipe)? 'O': 'I',
+ usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
+ (usb_pipecontrol (pipe)? "CTRL": "BULK"),
+ purb->actual_length,
+ transfer_len, dev->status);
+#ifdef OHCI_VERBOSE_DEBUG
+ if (!small) {
+ int i, len;
+
+ if (usb_pipecontrol (pipe)) {
+ printf (__FILE__ ": cmd(8):");
+ for (i = 0; i < 8 ; i++)
+ printf (" %02x", ((__u8 *) setup) [i]);
+ printf ("\n");
+ }
+ if (transfer_len > 0 && buffer) {
+ printf (__FILE__ ": data(%d/%d):",
+ purb->actual_length,
+ transfer_len);
+ len = usb_pipeout (pipe)?
+ transfer_len: purb->actual_length;
+ for (i = 0; i < 16 && i < len; i++)
+ printf (" %02x", ((__u8 *) buffer) [i]);
+ printf ("%s\n", i < len? "...": "");
+ }
+ }
+#endif
+}
+
+/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
+void ep_print_int_eds (ohci_t *ohci, char * str) {
+ int i, j;
+ __u32 * ed_p;
+ for (i= 0; i < 32; i++) {
+ j = 5;
+ ed_p = &(ohci->hcca->int_table [i]);
+ if (*ed_p == 0)
+ continue;
+ printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
+ while (*ed_p != 0 && j--) {
+ ed_t *ed = (ed_t *)m32_swap(ed_p);
+ printf (" ed: %4x;", ed->hwINFO);
+ ed_p = &ed->hwNextED;
+ }
+ printf ("\n");
+ }
+}
+
+static void ohci_dump_intr_mask (char *label, __u32 mask)
+{
+ dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
+ label,
+ mask,
+ (mask & OHCI_INTR_MIE) ? " MIE" : "",
+ (mask & OHCI_INTR_OC) ? " OC" : "",
+ (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
+ (mask & OHCI_INTR_FNO) ? " FNO" : "",
+ (mask & OHCI_INTR_UE) ? " UE" : "",
+ (mask & OHCI_INTR_RD) ? " RD" : "",
+ (mask & OHCI_INTR_SF) ? " SF" : "",
+ (mask & OHCI_INTR_WDH) ? " WDH" : "",
+ (mask & OHCI_INTR_SO) ? " SO" : ""
+ );
+}
+
+static void maybe_print_eds (char *label, __u32 value)
+{
+ ed_t *edp = (ed_t *)value;
+
+ if (value) {
+ dbg ("%s %08x", label, value);
+ dbg ("%08x", edp->hwINFO);
+ dbg ("%08x", edp->hwTailP);
+ dbg ("%08x", edp->hwHeadP);
+ dbg ("%08x", edp->hwNextED);
+ }
+}
+
+static char * hcfs2string (int state)
+{
+ switch (state) {
+ case OHCI_USB_RESET: return "reset";
+ case OHCI_USB_RESUME: return "resume";
+ case OHCI_USB_OPER: return "operational";
+ case OHCI_USB_SUSPEND: return "suspend";
+ }
+ return "?";
+}
+
+/* dump control and status registers */
+static void ohci_dump_status (ohci_t *controller)
+{
+ struct ohci_regs *regs = controller->regs;
+ __u32 temp;
+
+ temp = readl (®s->revision) & 0xff;
+ if (temp != 0x10)
+ dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
+
+ temp = readl (®s->control);
+ dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
+ (temp & OHCI_CTRL_RWE) ? " RWE" : "",
+ (temp & OHCI_CTRL_RWC) ? " RWC" : "",
+ (temp & OHCI_CTRL_IR) ? " IR" : "",
+ hcfs2string (temp & OHCI_CTRL_HCFS),
+ (temp & OHCI_CTRL_BLE) ? " BLE" : "",
+ (temp & OHCI_CTRL_CLE) ? " CLE" : "",
+ (temp & OHCI_CTRL_IE) ? " IE" : "",
+ (temp & OHCI_CTRL_PLE) ? " PLE" : "",
+ temp & OHCI_CTRL_CBSR
+ );
+
+ temp = readl (®s->cmdstatus);
+ dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
+ (temp & OHCI_SOC) >> 16,
+ (temp & OHCI_OCR) ? " OCR" : "",
+ (temp & OHCI_BLF) ? " BLF" : "",
+ (temp & OHCI_CLF) ? " CLF" : "",
+ (temp & OHCI_HCR) ? " HCR" : ""
+ );
+
+ ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus));
+ ohci_dump_intr_mask ("intrenable", readl (®s->intrenable));
+
+ maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent));
+
+ maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead));
+ maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent));
+
+ maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead));
+ maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent));
+
+ maybe_print_eds ("donehead", readl (®s->donehead));
+}
+
+static void ohci_dump_roothub (ohci_t *controller, int verbose)
+{
+ __u32 temp, ndp, i;
+
+ temp = roothub_a (controller);
+ ndp = (temp & RH_A_NDP);
+#ifdef CONFIG_AT91C_PQFP_UHPBUG
+ ndp = (ndp == 2) ? 1:0;
+#endif
+ if (verbose) {
+ dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
+ ((temp & RH_A_POTPGT) >> 24) & 0xff,
+ (temp & RH_A_NOCP) ? " NOCP" : "",
+ (temp & RH_A_OCPM) ? " OCPM" : "",
+ (temp & RH_A_DT) ? " DT" : "",
+ (temp & RH_A_NPS) ? " NPS" : "",
+ (temp & RH_A_PSM) ? " PSM" : "",
+ ndp
+ );
+ temp = roothub_b (controller);
+ dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
+ temp,
+ (temp & RH_B_PPCM) >> 16,
+ (temp & RH_B_DR)
+ );
+ temp = roothub_status (controller);
+ dbg ("roothub.status: %08x%s%s%s%s%s%s",
+ temp,
+ (temp & RH_HS_CRWE) ? " CRWE" : "",
+ (temp & RH_HS_OCIC) ? " OCIC" : "",
+ (temp & RH_HS_LPSC) ? " LPSC" : "",
+ (temp & RH_HS_DRWE) ? " DRWE" : "",
+ (temp & RH_HS_OCI) ? " OCI" : "",
+ (temp & RH_HS_LPS) ? " LPS" : ""
+ );
+ }
+
+ for (i = 0; i < ndp; i++) {
+ temp = roothub_portstatus (controller, i);
+ dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
+ i,
+ temp,
+ (temp & RH_PS_PRSC) ? " PRSC" : "",
+ (temp & RH_PS_OCIC) ? " OCIC" : "",
+ (temp & RH_PS_PSSC) ? " PSSC" : "",
+ (temp & RH_PS_PESC) ? " PESC" : "",
+ (temp & RH_PS_CSC) ? " CSC" : "",
+
+ (temp & RH_PS_LSDA) ? " LSDA" : "",
+ (temp & RH_PS_PPS) ? " PPS" : "",
+ (temp & RH_PS_PRS) ? " PRS" : "",
+ (temp & RH_PS_POCI) ? " POCI" : "",
+ (temp & RH_PS_PSS) ? " PSS" : "",
+
+ (temp & RH_PS_PES) ? " PES" : "",
+ (temp & RH_PS_CCS) ? " CCS" : ""
+ );
+ }
+}
+
+static void ohci_dump (ohci_t *controller, int verbose)
+{
+ dbg ("OHCI controller usb-%s state", controller->slot_name);
+
+ /* dumps some of the state we know about */
+ ohci_dump_status (controller);
+ if (verbose)
+ ep_print_int_eds (controller, "hcca");
+ dbg ("hcca frame #%04x", controller->hcca->frame_no);
+ ohci_dump_roothub (controller, 1);
+}
+
+
+#endif /* DEBUG */
+
+/*-------------------------------------------------------------------------*
+ * Interface functions (URB)
+ *-------------------------------------------------------------------------*/
+
+/* get a transfer request */
+
+int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, struct devrequest *setup, int interval)
+{
+ ohci_t *ohci;
+ ed_t * ed;
+ urb_priv_t *purb_priv;
+ int i, size = 0;
+
+ ohci = &gohci;
+
+ /* when controller's hung, permit only roothub cleanup attempts
+ * such as powering down ports */
+ if (ohci->disabled) {
+ err("sohci_submit_job: EPIPE");
+ return -1;
+ }
+
+ /* every endpoint has a ed, locate and fill it */
+ if (!(ed = ep_add_ed (dev, pipe))) {
+ err("sohci_submit_job: ENOMEM");
+ return -1;
+ }
+
+ /* for the private part of the URB we need the number of TDs (size) */
+ switch (usb_pipetype (pipe)) {
+ case PIPE_BULK: /* one TD for every 4096 Byte */
+ size = (transfer_len - 1) / 4096 + 1;
+ break;
+ case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
+ size = (transfer_len == 0)? 2:
+ (transfer_len - 1) / 4096 + 3;
+ break;
+ }
+
+ if (size >= (N_URB_TD - 1)) {
+ err("need %d TDs, only have %d", size, N_URB_TD);
+ return -1;
+ }
+ purb_priv = &urb_priv;
+ purb_priv->pipe = pipe;
+
+ /* fill the private part of the URB */
+ purb_priv->length = size;
+ purb_priv->ed = ed;
+ purb_priv->actual_length = 0;
+
+ /* allocate the TDs */
+ /* note that td[0] was allocated in ep_add_ed */
+ for (i = 0; i < size; i++) {
+ purb_priv->td[i] = td_alloc (dev);
+ if (!purb_priv->td[i]) {
+ purb_priv->length = i;
+ urb_free_priv (purb_priv);
+ err("sohci_submit_job: ENOMEM");
+ return -1;
+ }
+ }
+
+ if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
+ urb_free_priv (purb_priv);
+ err("sohci_submit_job: EINVAL");
+ return -1;
+ }
+
+ /* link the ed into a chain if is not already */
+ if (ed->state != ED_OPER)
+ ep_link (ohci, ed);
+
+ /* fill the TDs and link it to the ed */
+ td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
+
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef DEBUG
+/* tell us the current USB frame number */
+
+static int sohci_get_current_frame_number (struct usb_device *usb_dev)
+{
+ ohci_t *ohci = &gohci;
+
+ return m16_swap (ohci->hcca->frame_no);
+}
+#endif
+
+/*-------------------------------------------------------------------------*
+ * ED handling functions
+ *-------------------------------------------------------------------------*/
+
+/* link an ed into one of the HC chains */
+
+static int ep_link (ohci_t *ohci, ed_t *edi)
+{
+ volatile ed_t *ed = edi;
+
+ ed->state = ED_OPER;
+
+ switch (ed->type) {
+ case PIPE_CONTROL:
+ ed->hwNextED = 0;
+ if (ohci->ed_controltail == NULL) {
+ writel (ed, &ohci->regs->ed_controlhead);
+ } else {
+ ohci->ed_controltail->hwNextED = m32_swap (ed);
+ }
+ ed->ed_prev = ohci->ed_controltail;
+ if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
+ !ohci->ed_rm_list[1] && !ohci->sleeping) {
+ ohci->hc_control |= OHCI_CTRL_CLE;
+ writel (ohci->hc_control, &ohci->regs->control);
+ }
+ ohci->ed_controltail = edi;
+ break;
+
+ case PIPE_BULK:
+ ed->hwNextED = 0;
+ if (ohci->ed_bulktail == NULL) {
+ writel (ed, &ohci->regs->ed_bulkhead);
+ } else {
+ ohci->ed_bulktail->hwNextED = m32_swap (ed);
+ }
+ ed->ed_prev = ohci->ed_bulktail;
+ if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
+ !ohci->ed_rm_list[1] && !ohci->sleeping) {
+ ohci->hc_control |= OHCI_CTRL_BLE;
+ writel (ohci->hc_control, &ohci->regs->control);
+ }
+ ohci->ed_bulktail = edi;
+ break;
+ }
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* unlink an ed from one of the HC chains.
+ * just the link to the ed is unlinked.
+ * the link from the ed still points to another operational ed or 0
+ * so the HC can eventually finish the processing of the unlinked ed */
+
+static int ep_unlink (ohci_t *ohci, ed_t *ed)
+{
+ ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
+
+ switch (ed->type) {
+ case PIPE_CONTROL:
+ if (ed->ed_prev == NULL) {
+ if (!ed->hwNextED) {
+ ohci->hc_control &= ~OHCI_CTRL_CLE;
+ writel (ohci->hc_control, &ohci->regs->control);
+ }
+ writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
+ } else {
+ ed->ed_prev->hwNextED = ed->hwNextED;
+ }
+ if (ohci->ed_controltail == ed) {
+ ohci->ed_controltail = ed->ed_prev;
+ } else {
+ ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
+ }
+ break;
+
+ case PIPE_BULK:
+ if (ed->ed_prev == NULL) {
+ if (!ed->hwNextED) {
+ ohci->hc_control &= ~OHCI_CTRL_BLE;
+ writel (ohci->hc_control, &ohci->regs->control);
+ }
+ writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
+ } else {
+ ed->ed_prev->hwNextED = ed->hwNextED;
+ }
+ if (ohci->ed_bulktail == ed) {
+ ohci->ed_bulktail = ed->ed_prev;
+ } else {
+ ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
+ }
+ break;
+ }
+ ed->state = ED_UNLINK;
+ return 0;
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+/* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
+ * but the USB stack is a little bit stateless so we do it at every transaction
+ * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
+ * in all other cases the state is left unchanged
+ * the ed info fields are setted anyway even though most of them should not change */
+
+static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
+{
+ td_t *td;
+ ed_t *ed_ret;
+ volatile ed_t *ed;
+
+ ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
+ (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
+
+ if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
+ err("ep_add_ed: pending delete");
+ /* pending delete request */
+ return NULL;
+ }
+
+ if (ed->state == ED_NEW) {
+ ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
+ /* dummy td; end of td list for ed */
+ td = td_alloc (usb_dev);
+ ed->hwTailP = m32_swap (td);
+ ed->hwHeadP = ed->hwTailP;
+ ed->state = ED_UNLINK;
+ ed->type = usb_pipetype (pipe);
+ ohci_dev.ed_cnt++;
+ }
+
+ ed->hwINFO = m32_swap (usb_pipedevice (pipe)
+ | usb_pipeendpoint (pipe) << 7
+ | (usb_pipeisoc (pipe)? 0x8000: 0)
+ | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
+ | usb_pipeslow (pipe) << 13
+ | usb_maxpacket (usb_dev, pipe) << 16);
+
+ return ed_ret;
+}
+
+/*-------------------------------------------------------------------------*
+ * TD handling functions
+ *-------------------------------------------------------------------------*/
+
+/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
+
+static void td_fill (ohci_t *ohci, unsigned int info,
+ void *data, int len,
+ struct usb_device *dev, int index, urb_priv_t *urb_priv)
+{
+ volatile td_t *td, *td_pt;
+#ifdef OHCI_FILL_TRACE
+ int i;
+#endif
+
+ if (index > urb_priv->length) {
+ err("index > length");
+ return;
+ }
+ /* use this td as the next dummy */
+ td_pt = urb_priv->td [index];
+ td_pt->hwNextTD = 0;
+
+ /* fill the old dummy TD */
+ td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
+
+ td->ed = urb_priv->ed;
+ td->next_dl_td = NULL;
+ td->index = index;
+ td->data = (__u32)data;
+#ifdef OHCI_FILL_TRACE
+ if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {
+ for (i = 0; i < len; i++)
+ printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
+ printf("\n");
+ }
+#endif
+ if (!len)
+ data = 0;
+
+ td->hwINFO = m32_swap (info);
+ td->hwCBP = m32_swap (data);
+ if (data)
+ td->hwBE = m32_swap (data + len - 1);
+ else
+ td->hwBE = 0;
+ td->hwNextTD = m32_swap (td_pt);
+ td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000);
+
+ /* append to queue */
+ td->ed->hwTailP = td->hwNextTD;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* prepare all TDs of a transfer */
+
+static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
+{
+ ohci_t *ohci = &gohci;
+ int data_len = transfer_len;
+ void *data;
+ int cnt = 0;
+ __u32 info = 0;
+ unsigned int toggle = 0;
+
+ /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
+ if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
+ toggle = TD_T_TOGGLE;
+ } else {
+ toggle = TD_T_DATA0;
+ usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
+ }
+ urb->td_cnt = 0;
+ if (data_len)
+ data = buffer;
+ else
+ data = 0;
+
+ switch (usb_pipetype (pipe)) {
+ case PIPE_BULK:
+ info = usb_pipeout (pipe)?
+ TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
+ while(data_len > 4096) {
+ td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
+ data += 4096; data_len -= 4096; cnt++;
+ }
+ info = usb_pipeout (pipe)?
+ TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
+ td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
+ cnt++;
+
+ if (!ohci->sleeping)
+ writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
+ break;
+
+ case PIPE_CONTROL:
+ info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
+ td_fill (ohci, info, setup, 8, dev, cnt++, urb);
+ if (data_len > 0) {
+ info = usb_pipeout (pipe)?
+ TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
+ /* NOTE: mishandles transfers >8K, some >4K */
+ td_fill (ohci, info, data, data_len, dev, cnt++, urb);
+ }
+ info = usb_pipeout (pipe)?
+ TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
+ td_fill (ohci, info, data, 0, dev, cnt++, urb);
+ if (!ohci->sleeping)
+ writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
+ break;
+ }
+ if (urb->length != cnt)
+ dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
+}
+
+/*-------------------------------------------------------------------------*
+ * Done List handling functions
+ *-------------------------------------------------------------------------*/
+
+
+/* calculate the transfer length and update the urb */
+
+static void dl_transfer_length(td_t * td)
+{
+ __u32 tdINFO, tdBE, tdCBP;
+ urb_priv_t *lurb_priv = &urb_priv;
+
+ tdINFO = m32_swap (td->hwINFO);
+ tdBE = m32_swap (td->hwBE);
+ tdCBP = m32_swap (td->hwCBP);
+
+
+ if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
+ ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
+ if (tdBE != 0) {
+ if (td->hwCBP == 0)
+ lurb_priv->actual_length += tdBE - td->data + 1;
+ else
+ lurb_priv->actual_length += tdCBP - td->data;
+ }
+ }
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* replies to the request have to be on a FIFO basis so
+ * we reverse the reversed done-list */
+
+static td_t * dl_reverse_done_list (ohci_t *ohci)
+{
+ __u32 td_list_hc;
+ td_t *td_rev = NULL;
+ td_t *td_list = NULL;
+ urb_priv_t *lurb_priv = NULL;
+
+ td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
+ ohci->hcca->done_head = 0;
+
+ while (td_list_hc) {
+ td_list = (td_t *)td_list_hc;
+
+ if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
+ lurb_priv = &urb_priv;
+ dbg(" USB-error/status: %x : %p",
+ TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
+ if (td_list->ed->hwHeadP & m32_swap (0x1)) {
+ if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
+ td_list->ed->hwHeadP =
+ (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
+ (td_list->ed->hwHeadP & m32_swap (0x2));
+ lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
+ } else
+ td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
+ }
+ }
+
+ td_list->next_dl_td = td_rev;
+ td_rev = td_list;
+ td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
+ }
+ return td_list;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* td done list */
+static int dl_done_list (ohci_t *ohci, td_t *td_list)
+{
+ td_t *td_list_next = NULL;
+ ed_t *ed;
+ int cc = 0;
+ int stat = 0;
+ /* urb_t *urb; */
+ urb_priv_t *lurb_priv;
+ __u32 tdINFO, edHeadP, edTailP;
+
+ while (td_list) {
+ td_list_next = td_list->next_dl_td;
+
+ lurb_priv = &urb_priv;
+ tdINFO = m32_swap (td_list->hwINFO);
+
+ ed = td_list->ed;
+
+ dl_transfer_length(td_list);
+
+ /* error code of transfer */
+ cc = TD_CC_GET (tdINFO);
+ if (cc != 0) {
+ dbg("ConditionCode %#x", cc);
+ stat = cc_to_error[cc];
+ }
+
+ if (ed->state != ED_NEW) {
+ edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
+ edTailP = m32_swap (ed->hwTailP);
+
+ /* unlink eds if they are not busy */
+ if ((edHeadP == edTailP) && (ed->state == ED_OPER))
+ ep_unlink (ohci, ed);
+ }
+
+ td_list = td_list_next;
+ }
+ return stat;
+}
+
+/*-------------------------------------------------------------------------*
+ * Virtual Root Hub
+ *-------------------------------------------------------------------------*/
+
+/* Device descriptor */
+static __u8 root_hub_dev_des[] =
+{
+ 0x12, /* __u8 bLength; */
+ 0x01, /* __u8 bDescriptorType; Device */
+ 0x10, /* __u16 bcdUSB; v1.1 */
+ 0x01,
+ 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
+ 0x00, /* __u8 bDeviceSubClass; */
+ 0x00, /* __u8 bDeviceProtocol; */
+ 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
+ 0x00, /* __u16 idVendor; */
+ 0x00,
+ 0x00, /* __u16 idProduct; */
+ 0x00,
+ 0x00, /* __u16 bcdDevice; */
+ 0x00,
+ 0x00, /* __u8 iManufacturer; */
+ 0x01, /* __u8 iProduct; */
+ 0x00, /* __u8 iSerialNumber; */
+ 0x01 /* __u8 bNumConfigurations; */
+};
+
+
+/* Configuration descriptor */
+static __u8 root_hub_config_des[] =
+{
+ 0x09, /* __u8 bLength; */
+ 0x02, /* __u8 bDescriptorType; Configuration */
+ 0x19, /* __u16 wTotalLength; */
+ 0x00,
+ 0x01, /* __u8 bNumInterfaces; */
+ 0x01, /* __u8 bConfigurationValue; */
+ 0x00, /* __u8 iConfiguration; */
+ 0x40, /* __u8 bmAttributes;
+ Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
+ 0x00, /* __u8 MaxPower; */
+
+ /* interface */
+ 0x09, /* __u8 if_bLength; */
+ 0x04, /* __u8 if_bDescriptorType; Interface */
+ 0x00, /* __u8 if_bInterfaceNumber; */
+ 0x00, /* __u8 if_bAlternateSetting; */
+ 0x01, /* __u8 if_bNumEndpoints; */
+ 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
+ 0x00, /* __u8 if_bInterfaceSubClass; */
+ 0x00, /* __u8 if_bInterfaceProtocol; */
+ 0x00, /* __u8 if_iInterface; */
+
+ /* endpoint */
+ 0x07, /* __u8 ep_bLength; */
+ 0x05, /* __u8 ep_bDescriptorType; Endpoint */
+ 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
+ 0x03, /* __u8 ep_bmAttributes; Interrupt */
+ 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
+ 0x00,
+ 0xff /* __u8 ep_bInterval; 255 ms */
+};
+
+static unsigned char root_hub_str_index0[] =
+{
+ 0x04, /* __u8 bLength; */
+ 0x03, /* __u8 bDescriptorType; String-descriptor */
+ 0x09, /* __u8 lang ID */
+ 0x04, /* __u8 lang ID */
+};
+
+static unsigned char root_hub_str_index1[] =
+{
+ 28, /* __u8 bLength; */
+ 0x03, /* __u8 bDescriptorType; String-descriptor */
+ 'O', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'H', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'C', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'I', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ ' ', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'R', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'o', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'o', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 't', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ ' ', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'H', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'u', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'b', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+};
+
+/* Hub class-specific descriptor is constructed dynamically */
+
+
+/*-------------------------------------------------------------------------*/
+
+#define OK(x) len = (x); break
+#ifdef DEBUG
+#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
+#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
+#else
+#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
+#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
+#endif
+#define RD_RH_STAT roothub_status(&gohci)
+#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
+
+/* request to virtual root hub */
+
+int rh_check_port_status(ohci_t *controller)
+{
+ __u32 temp, ndp, i;
+ int res;
+
+ res = -1;
+ temp = roothub_a (controller);
+ ndp = (temp & RH_A_NDP);
+#ifdef CONFIG_AT91C_PQFP_UHPBUG
+ ndp = (ndp == 2) ? 1:0;
+#endif
+
+ for (i = 0; i < ndp; i++) {
+ temp = roothub_portstatus (controller, i);
+ /* check for a device disconnect */
+ if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
+ (RH_PS_PESC | RH_PS_CSC)) &&
+ ((temp & RH_PS_CCS) == 0)) {
+ res = i;
+ break;
+ }
+ }
+ return res;
+}
+
+static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
+ void *buffer, int transfer_len, struct devrequest *cmd)
+{
+ void * data = buffer;
+ int leni = transfer_len;
+ int len = 0;
+ int stat = 0;
+ __u32 datab[4];
+ __u8 *data_buf = (__u8 *)datab;
+ __u16 bmRType_bReq;
+ __u16 wValue;
+ __u16 wIndex;
+ __u16 wLength;
+
+#ifdef DEBUG
+urb_priv.actual_length = 0;
+pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
+#else
+ wait_ms(1);
+#endif
+ if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
+ info("Root-Hub submit IRQ: NOT implemented");
+ return 0;
+ }
+
+ bmRType_bReq = cmd->requesttype | (cmd->request << 8);
+ wValue = m16_swap (cmd->value);
+ wIndex = m16_swap (cmd->index);
+ wLength = m16_swap (cmd->length);
+
+ info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
+ dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
+
+ switch (bmRType_bReq) {
+ /* Request Destination:
+ without flags: Device,
+ RH_INTERFACE: interface,
+ RH_ENDPOINT: endpoint,
+ RH_CLASS means HUB here,
+ RH_OTHER | RH_CLASS almost ever means HUB_PORT here
+ */
+
+ case RH_GET_STATUS:
+ *(__u16 *) data_buf = m16_swap (1); OK (2);
+ case RH_GET_STATUS | RH_INTERFACE:
+ *(__u16 *) data_buf = m16_swap (0); OK (2);
+ case RH_GET_STATUS | RH_ENDPOINT:
+ *(__u16 *) data_buf = m16_swap (0); OK (2);
+ case RH_GET_STATUS | RH_CLASS:
+ *(__u32 *) data_buf = m32_swap (
+ RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
+ OK (4);
+ case RH_GET_STATUS | RH_OTHER | RH_CLASS:
+ *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
+
+ case RH_CLEAR_FEATURE | RH_ENDPOINT:
+ switch (wValue) {
+ case (RH_ENDPOINT_STALL): OK (0);
+ }
+ break;
+
+ case RH_CLEAR_FEATURE | RH_CLASS:
+ switch (wValue) {
+ case RH_C_HUB_LOCAL_POWER:
+ OK(0);
+ case (RH_C_HUB_OVER_CURRENT):
+ WR_RH_STAT(RH_HS_OCIC); OK (0);
+ }
+ break;
+
+ case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
+ switch (wValue) {
+ case (RH_PORT_ENABLE):
+ WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
+ case (RH_PORT_SUSPEND):
+ WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
+ case (RH_PORT_POWER):
+ WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
+ case (RH_C_PORT_CONNECTION):
+ WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
+ case (RH_C_PORT_ENABLE):
+ WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
+ case (RH_C_PORT_SUSPEND):
+ WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
+ case (RH_C_PORT_OVER_CURRENT):
+ WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
+ case (RH_C_PORT_RESET):
+ WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
+ }
+ break;
+
+ case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
+ switch (wValue) {
+ case (RH_PORT_SUSPEND):
+ WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
+ case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
+ if (RD_RH_PORTSTAT & RH_PS_CCS)
+ WR_RH_PORTSTAT (RH_PS_PRS);
+ OK (0);
+ case (RH_PORT_POWER):
+ WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
+ case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
+ if (RD_RH_PORTSTAT & RH_PS_CCS)
+ WR_RH_PORTSTAT (RH_PS_PES );
+ OK (0);
+ }
+ break;
+
+ case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
+
+ case RH_GET_DESCRIPTOR:
+ switch ((wValue & 0xff00) >> 8) {
+ case (0x01): /* device descriptor */
+ len = min_t(unsigned int,
+ leni,
+ min_t(unsigned int,
+ sizeof (root_hub_dev_des),
+ wLength));
+ data_buf = root_hub_dev_des; OK(len);
+ case (0x02): /* configuration descriptor */
+ len = min_t(unsigned int,
+ leni,
+ min_t(unsigned int,
+ sizeof (root_hub_config_des),
+ wLength));
+ data_buf = root_hub_config_des; OK(len);
+ case (0x03): /* string descriptors */
+ if(wValue==0x0300) {
+ len = min_t(unsigned int,
+ leni,
+ min_t(unsigned int,
+ sizeof (root_hub_str_index0),
+ wLength));
+ data_buf = root_hub_str_index0;
+ OK(len);
+ }
+ if(wValue==0x0301) {
+ len = min_t(unsigned int,
+ leni,
+ min_t(unsigned int,
+ sizeof (root_hub_str_index1),
+ wLength));
+ data_buf = root_hub_str_index1;
+ OK(len);
+ }
+ default:
+ stat = USB_ST_STALLED;
+ }
+ break;
+
+ case RH_GET_DESCRIPTOR | RH_CLASS:
+ {
+ __u32 temp = roothub_a (&gohci);
+
+ data_buf [0] = 9; /* min length; */
+ data_buf [1] = 0x29;
+ data_buf [2] = temp & RH_A_NDP;
+#ifdef CONFIG_AT91C_PQFP_UHPBUG
+ data_buf [2] = (data_buf [2] == 2) ? 1:0;
+#endif
+ data_buf [3] = 0;
+ if (temp & RH_A_PSM) /* per-port power switching? */
+ data_buf [3] |= 0x1;
+ if (temp & RH_A_NOCP) /* no overcurrent reporting? */
+ data_buf [3] |= 0x10;
+ else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
+ data_buf [3] |= 0x8;
+
+ /* corresponds to data_buf[4-7] */
+ datab [1] = 0;
+ data_buf [5] = (temp & RH_A_POTPGT) >> 24;
+ temp = roothub_b (&gohci);
+ data_buf [7] = temp & RH_B_DR;
+ if (data_buf [2] < 7) {
+ data_buf [8] = 0xff;
+ } else {
+ data_buf [0] += 2;
+ data_buf [8] = (temp & RH_B_DR) >> 8;
+ data_buf [10] = data_buf [9] = 0xff;
+ }
+
+ len = min_t(unsigned int, leni,
+ min_t(unsigned int, data_buf [0], wLength));
+ OK (len);
+ }
+
+ case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
+
+ case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
+
+ default:
+ dbg ("unsupported root hub command");
+ stat = USB_ST_STALLED;
+ }
+
+#ifdef DEBUG
+ ohci_dump_roothub (&gohci, 1);
+#else
+ wait_ms(1);
+#endif
+
+ len = min_t(int, len, leni);
+ if (data != data_buf)
+ memcpy (data, data_buf, len);
+ dev->act_len = len;
+ dev->status = stat;
+
+#ifdef DEBUG
+ if (transfer_len)
+ urb_priv.actual_length = transfer_len;
+ pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
+#else
+ wait_ms(1);
+#endif
+
+ return stat;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* common code for handling submit messages - used for all but root hub */
+/* accesses. */
+int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, struct devrequest *setup, int interval)
+{
+ int stat = 0;
+ int maxsize = usb_maxpacket(dev, pipe);
+ int timeout;
+
+ /* device pulled? Shortcut the action. */
+ if (devgone == dev) {
+ dev->status = USB_ST_CRC_ERR;
+ return 0;
+ }
+
+#ifdef DEBUG
+ urb_priv.actual_length = 0;
+ pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
+#else
+ wait_ms(1);
+#endif
+ if (!maxsize) {
+ err("submit_common_message: pipesize for pipe %lx is zero",
+ pipe);
+ return -1;
+ }
+
+ if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
+ err("sohci_submit_job failed");
+ return -1;
+ }
+
+ wait_ms(10);
+ /* ohci_dump_status(&gohci); */
+
+ /* allow more time for a BULK device to react - some are slow */
+#define BULK_TO 5000 /* timeout in milliseconds */
+ if (usb_pipetype (pipe) == PIPE_BULK)
+ timeout = BULK_TO;
+ else
+ timeout = 100;
+
+ /* wait for it to complete */
+ for (;;) {
+ /* check whether the controller is done */
+ stat = hc_interrupt();
+ if (stat < 0) {
+ stat = USB_ST_CRC_ERR;
+ break;
+ }
+ if (stat >= 0 && stat != 0xff) {
+ /* 0xff is returned for an SF-interrupt */
+ break;
+ }
+ if (--timeout) {
+ wait_ms(1);
+ } else {
+ err("CTL:TIMEOUT ");
+ stat = USB_ST_CRC_ERR;
+ break;
+ }
+ }
+ /* we got an Root Hub Status Change interrupt */
+ if (got_rhsc) {
+#ifdef DEBUG
+ ohci_dump_roothub (&gohci, 1);
+#endif
+ got_rhsc = 0;
+ /* abuse timeout */
+ timeout = rh_check_port_status(&gohci);
+ if (timeout >= 0) {
+#if 0 /* this does nothing useful, but leave it here in case that changes */
+ /* the called routine adds 1 to the passed value */
+ usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
+#endif
+ /*
+ * XXX
+ * This is potentially dangerous because it assumes
+ * that only one device is ever plugged in!
+ */
+ devgone = dev;
+ }
+ }
+
+ dev->status = stat;
+ dev->act_len = transfer_len;
+
+#ifdef DEBUG
+ pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
+#else
+ wait_ms(1);
+#endif
+
+ /* free TDs in urb_priv */
+ urb_free_priv (&urb_priv);
+ return 0;
+}
+
+/* submit routines called from usb.c */
+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len)
+{
+ info("submit_bulk_msg");
+ return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
+}
+
+int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, struct devrequest *setup)
+{
+ int maxsize = usb_maxpacket(dev, pipe);
+
+ info("submit_control_msg");
+#ifdef DEBUG
+ urb_priv.actual_length = 0;
+ pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
+#else
+ wait_ms(1);
+#endif
+ if (!maxsize) {
+ err("submit_control_message: pipesize for pipe %lx is zero",
+ pipe);
+ return -1;
+ }
+ if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
+ gohci.rh.dev = dev;
+ /* root hub - redirect */
+ return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
+ setup);
+ }
+
+ return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
+}
+
+int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, int interval)
+{
+ info("submit_int_msg");
+ return -1;
+}
+
+/*-------------------------------------------------------------------------*
+ * HC functions
+ *-------------------------------------------------------------------------*/
+
+/* reset the HC and BUS */
+
+static int hc_reset (ohci_t *ohci)
+{
+ int timeout = 30;
+ int smm_timeout = 50; /* 0,5 sec */
+
+ dbg("%s\n", __FUNCTION__);
+
+ if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
+ writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
+ info("USB HC TakeOver from SMM");
+ while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
+ wait_ms (10);
+ if (--smm_timeout == 0) {
+ err("USB HC TakeOver failed!");
+ return -1;
+ }
+ }
+ }
+
+ /* Disable HC interrupts */
+ writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
+
+ dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n",
+ ohci->slot_name,
+ readl(&ohci->regs->control));
+
+ /* Reset USB (needed by some controllers) */
+ writel (0, &ohci->regs->control);
+
+ /* HC Reset requires max 10 us delay */
+ writel (OHCI_HCR, &ohci->regs->cmdstatus);
+ while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
+ if (--timeout == 0) {
+ err("USB HC reset timed out!");
+ return -1;
+ }
+ udelay (1);
+ }
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* Start an OHCI controller, set the BUS operational
+ * enable interrupts
+ * connect the virtual root hub */
+
+static int hc_start (ohci_t * ohci)
+{
+ __u32 mask;
+ unsigned int fminterval;
+
+ ohci->disabled = 1;
+
+ /* Tell the controller where the control and bulk lists are
+ * The lists are empty now. */
+
+ writel (0, &ohci->regs->ed_controlhead);
+ writel (0, &ohci->regs->ed_bulkhead);
+
+ writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
+
+ fminterval = 0x2edf;
+ writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
+ fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
+ writel (fminterval, &ohci->regs->fminterval);
+ writel (0x628, &ohci->regs->lsthresh);
+
+ /* start controller operations */
+ ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
+ ohci->disabled = 0;
+ writel (ohci->hc_control, &ohci->regs->control);
+
+ /* disable all interrupts */
+ mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
+ OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
+ OHCI_INTR_OC | OHCI_INTR_MIE);
+ writel (mask, &ohci->regs->intrdisable);
+ /* clear all interrupts */
+ mask &= ~OHCI_INTR_MIE;
+ writel (mask, &ohci->regs->intrstatus);
+ /* Choose the interrupts we care about now - but w/o MIE */
+ mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
+ writel (mask, &ohci->regs->intrenable);
+
+#ifdef OHCI_USE_NPS
+ /* required for AMD-756 and some Mac platforms */
+ writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
+ &ohci->regs->roothub.a);
+ writel (RH_HS_LPSC, &ohci->regs->roothub.status);
+#endif /* OHCI_USE_NPS */
+
+#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
+ /* POTPGT delay is bits 24-31, in 2 ms units. */
+ mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
+
+ /* connect the virtual root hub */
+ ohci->rh.devnum = 0;
+
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* an interrupt happens */
+
+static int
+hc_interrupt (void)
+{
+ ohci_t *ohci = &gohci;
+ struct ohci_regs *regs = ohci->regs;
+ int ints;
+ int stat = -1;
+
+ if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
+ ints = OHCI_INTR_WDH;
+ } else {
+ ints = readl (®s->intrstatus);
+ }
+
+ /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
+
+ if (ints & OHCI_INTR_RHSC) {
+ got_rhsc = 1;
+ }
+
+ if (ints & OHCI_INTR_UE) {
+ ohci->disabled++;
+ err ("OHCI Unrecoverable Error, controller usb-%s disabled",
+ ohci->slot_name);
+ /* e.g. due to PCI Master/Target Abort */
+
+#ifdef DEBUG
+ ohci_dump (ohci, 1);
+#else
+ wait_ms(1);
+#endif
+ /* FIXME: be optimistic, hope that bug won't repeat often. */
+ /* Make some non-interrupt context restart the controller. */
+ /* Count and limit the retries though; either hardware or */
+ /* software errors can go forever... */
+ hc_reset (ohci);
+ return -1;
+ }
+
+ if (ints & OHCI_INTR_WDH) {
+ wait_ms(1);
+ writel (OHCI_INTR_WDH, ®s->intrdisable);
+ stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
+ writel (OHCI_INTR_WDH, ®s->intrenable);
+ }
+
+ if (ints & OHCI_INTR_SO) {
+ dbg("USB Schedule overrun\n");
+ writel (OHCI_INTR_SO, ®s->intrenable);
+ stat = -1;
+ }
+
+ /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
+ if (ints & OHCI_INTR_SF) {
+ unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
+ wait_ms(1);
+ writel (OHCI_INTR_SF, ®s->intrdisable);
+ if (ohci->ed_rm_list[frame] != NULL)
+ writel (OHCI_INTR_SF, ®s->intrenable);
+ stat = 0xff;
+ }
+
+ writel (ints, ®s->intrstatus);
+ return stat;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*-------------------------------------------------------------------------*/
+
+/* De-allocate all resources.. */
+
+static void hc_release_ohci (ohci_t *ohci)
+{
+ dbg ("USB HC release ohci usb-%s", ohci->slot_name);
+
+ if (!ohci->disabled)
+ hc_reset (ohci);
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * low level initalisation routine, called from usb.c
+ */
+static char ohci_inited = 0;
+
+int usb_lowlevel_init(void)
+{
+ /*
+ * Enable USB host clock.
+ */
+ *AT91C_PMC_SCER = AT91C_PMC_UHP; /* 48MHz clock enabled for UHP */
+ *AT91C_PMC_PCER = 1 << AT91C_ID_UHP; /* Peripheral Clock Enable Register */
+
+ memset (&gohci, 0, sizeof (ohci_t));
+ memset (&urb_priv, 0, sizeof (urb_priv_t));
+
+ /* align the storage */
+ if ((__u32)&ghcca[0] & 0xff) {
+ err("HCCA not aligned!!");
+ return -1;
+ }
+ phcca = &ghcca[0];
+ info("aligned ghcca %p", phcca);
+ memset(&ohci_dev, 0, sizeof(struct ohci_device));
+ if ((__u32)&ohci_dev.ed[0] & 0x7) {
+ err("EDs not aligned!!");
+ return -1;
+ }
+ memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
+ if ((__u32)gtd & 0x7) {
+ err("TDs not aligned!!");
+ return -1;
+ }
+ ptd = gtd;
+ gohci.hcca = phcca;
+ memset (phcca, 0, sizeof (struct ohci_hcca));
+
+ gohci.disabled = 1;
+ gohci.sleeping = 0;
+ gohci.irq = -1;
+ gohci.regs = (struct ohci_regs *)AT91_USB_HOST_BASE;
+
+ gohci.flags = 0;
+ gohci.slot_name = "at91rm9200";
+
+ if (hc_reset (&gohci) < 0) {
+ hc_release_ohci (&gohci);
+ /* Initialization failed */
+ *AT91C_PMC_PCER = AT91C_ID_UHP;
+ *AT91C_PMC_SCDR = 1 << AT91C_PMC_UHP; /* 48MHz clock disabled for UHP */
+ return -1;
+ }
+
+ /* FIXME this is a second HC reset; why?? */
+/* writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
+ wait_ms (10);*/
+
+ if (hc_start (&gohci) < 0) {
+ err ("can't start usb-%s", gohci.slot_name);
+ hc_release_ohci (&gohci);
+ /* Initialization failed */
+ *AT91C_PMC_PCER = AT91C_ID_UHP;
+ *AT91C_PMC_SCDR = 1 << AT91C_PMC_UHP; /* 48MHz clock disabled for UHP */
+ return -1;
+ }
+
+#ifdef DEBUG
+ ohci_dump (&gohci, 1);
+#else
+ wait_ms(1);
+#endif
+ ohci_inited = 1;
+ return 0;
+}
+
+int usb_lowlevel_stop(void)
+{
+ /* this gets called really early - before the controller has */
+ /* even been initialized! */
+ if (!ohci_inited)
+ return 0;
+ /* TODO release any interrupts, etc. */
+ /* call hc_release_ohci() here ? */
+ hc_reset (&gohci);
+ /* may not want to do this */
+ *AT91C_PMC_PCER = 1 << AT91C_ID_UHP;
+ *AT91C_PMC_SCDR = 1 << AT91C_PMC_UHP; /* 48MHz clock disabled for UHP */
+ return 0;
+}
+
+#endif /* CONFIG_USB_OHCI */
--- /dev/null
+/*
+ * URB OHCI HCD (Host Controller Driver) for USB.
+ *
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
+ *
+ * usb-ohci.h
+ */
+
+
+static int cc_to_error[16] = {
+
+/* mapping of the OHCI CC status to error codes */
+ /* No Error */ 0,
+ /* CRC Error */ USB_ST_CRC_ERR,
+ /* Bit Stuff */ USB_ST_BIT_ERR,
+ /* Data Togg */ USB_ST_CRC_ERR,
+ /* Stall */ USB_ST_STALLED,
+ /* DevNotResp */ -1,
+ /* PIDCheck */ USB_ST_BIT_ERR,
+ /* UnExpPID */ USB_ST_BIT_ERR,
+ /* DataOver */ USB_ST_BUF_ERR,
+ /* DataUnder */ USB_ST_BUF_ERR,
+ /* reservd */ -1,
+ /* reservd */ -1,
+ /* BufferOver */ USB_ST_BUF_ERR,
+ /* BuffUnder */ USB_ST_BUF_ERR,
+ /* Not Access */ -1,
+ /* Not Access */ -1
+};
+
+/* ED States */
+
+#define ED_NEW 0x00
+#define ED_UNLINK 0x01
+#define ED_OPER 0x02
+#define ED_DEL 0x04
+#define ED_URB_DEL 0x08
+
+/* usb_ohci_ed */
+struct ed {
+ __u32 hwINFO;
+ __u32 hwTailP;
+ __u32 hwHeadP;
+ __u32 hwNextED;
+
+ struct ed *ed_prev;
+ __u8 int_period;
+ __u8 int_branch;
+ __u8 int_load;
+ __u8 int_interval;
+ __u8 state;
+ __u8 type;
+ __u16 last_iso;
+ struct ed *ed_rm_list;
+
+ struct usb_device *usb_dev;
+ __u32 unused[3];
+} __attribute((aligned(16)));
+typedef struct ed ed_t;
+
+
+/* TD info field */
+#define TD_CC 0xf0000000
+#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
+#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
+#define TD_EC 0x0C000000
+#define TD_T 0x03000000
+#define TD_T_DATA0 0x02000000
+#define TD_T_DATA1 0x03000000
+#define TD_T_TOGGLE 0x00000000
+#define TD_R 0x00040000
+#define TD_DI 0x00E00000
+#define TD_DI_SET(X) (((X) & 0x07)<< 21)
+#define TD_DP 0x00180000
+#define TD_DP_SETUP 0x00000000
+#define TD_DP_IN 0x00100000
+#define TD_DP_OUT 0x00080000
+
+#define TD_ISO 0x00010000
+#define TD_DEL 0x00020000
+
+/* CC Codes */
+#define TD_CC_NOERROR 0x00
+#define TD_CC_CRC 0x01
+#define TD_CC_BITSTUFFING 0x02
+#define TD_CC_DATATOGGLEM 0x03
+#define TD_CC_STALL 0x04
+#define TD_DEVNOTRESP 0x05
+#define TD_PIDCHECKFAIL 0x06
+#define TD_UNEXPECTEDPID 0x07
+#define TD_DATAOVERRUN 0x08
+#define TD_DATAUNDERRUN 0x09
+#define TD_BUFFEROVERRUN 0x0C
+#define TD_BUFFERUNDERRUN 0x0D
+#define TD_NOTACCESSED 0x0F
+
+
+#define MAXPSW 1
+
+struct td {
+ __u32 hwINFO;
+ __u32 hwCBP; /* Current Buffer Pointer */
+ __u32 hwNextTD; /* Next TD Pointer */
+ __u32 hwBE; /* Memory Buffer End Pointer */
+
+ __u16 hwPSW[MAXPSW];
+ __u8 unused;
+ __u8 index;
+ struct ed *ed;
+ struct td *next_dl_td;
+ struct usb_device *usb_dev;
+ int transfer_len;
+ __u32 data;
+
+ __u32 unused2[2];
+} __attribute((aligned(32)));
+typedef struct td td_t;
+
+#define OHCI_ED_SKIP (1 << 14)
+
+/*
+ * The HCCA (Host Controller Communications Area) is a 256 byte
+ * structure defined in the OHCI spec. that the host controller is
+ * told the base address of. It must be 256-byte aligned.
+ */
+
+#define NUM_INTS 32 /* part of the OHCI standard */
+struct ohci_hcca {
+ __u32 int_table[NUM_INTS]; /* Interrupt ED table */
+ __u16 frame_no; /* current frame number */
+ __u16 pad1; /* set to 0 on each frame_no change */
+ __u32 done_head; /* info returned for an interrupt */
+ u8 reserved_for_hc[116];
+} __attribute((aligned(256)));
+
+
+/*
+ * Maximum number of root hub ports.
+ */
+#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */
+
+/*
+ * This is the structure of the OHCI controller's memory mapped I/O
+ * region. This is Memory Mapped I/O. You must use the readl() and
+ * writel() macros defined in asm/io.h to access these!!
+ */
+struct ohci_regs {
+ /* control and status registers */
+ __u32 revision;
+ __u32 control;
+ __u32 cmdstatus;
+ __u32 intrstatus;
+ __u32 intrenable;
+ __u32 intrdisable;
+ /* memory pointers */
+ __u32 hcca;
+ __u32 ed_periodcurrent;
+ __u32 ed_controlhead;
+ __u32 ed_controlcurrent;
+ __u32 ed_bulkhead;
+ __u32 ed_bulkcurrent;
+ __u32 donehead;
+ /* frame counters */
+ __u32 fminterval;
+ __u32 fmremaining;
+ __u32 fmnumber;
+ __u32 periodicstart;
+ __u32 lsthresh;
+ /* Root hub ports */
+ struct ohci_roothub_regs {
+ __u32 a;
+ __u32 b;
+ __u32 status;
+ __u32 portstatus[MAX_ROOT_PORTS];
+ } roothub;
+} __attribute((aligned(32)));
+
+
+/* OHCI CONTROL AND STATUS REGISTER MASKS */
+
+/*
+ * HcControl (control) register masks
+ */
+#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */
+#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */
+#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */
+#define OHCI_CTRL_CLE (1 << 4) /* control list enable */
+#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */
+#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
+#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
+#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
+#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
+
+/* pre-shifted values for HCFS */
+# define OHCI_USB_RESET (0 << 6)
+# define OHCI_USB_RESUME (1 << 6)
+# define OHCI_USB_OPER (2 << 6)
+# define OHCI_USB_SUSPEND (3 << 6)
+
+/*
+ * HcCommandStatus (cmdstatus) register masks
+ */
+#define OHCI_HCR (1 << 0) /* host controller reset */
+#define OHCI_CLF (1 << 1) /* control list filled */
+#define OHCI_BLF (1 << 2) /* bulk list filled */
+#define OHCI_OCR (1 << 3) /* ownership change request */
+#define OHCI_SOC (3 << 16) /* scheduling overrun count */
+
+/*
+ * masks used with interrupt registers:
+ * HcInterruptStatus (intrstatus)
+ * HcInterruptEnable (intrenable)
+ * HcInterruptDisable (intrdisable)
+ */
+#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
+#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
+#define OHCI_INTR_SF (1 << 2) /* start frame */
+#define OHCI_INTR_RD (1 << 3) /* resume detect */
+#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
+#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
+#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
+#define OHCI_INTR_OC (1 << 30) /* ownership change */
+#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
+
+
+/* Virtual Root HUB */
+struct virt_root_hub {
+ int devnum; /* Address of Root Hub endpoint */
+ void *dev; /* was urb */
+ void *int_addr;
+ int send;
+ int interval;
+};
+
+/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
+
+/* destination of request */
+#define RH_INTERFACE 0x01
+#define RH_ENDPOINT 0x02
+#define RH_OTHER 0x03
+
+#define RH_CLASS 0x20
+#define RH_VENDOR 0x40
+
+/* Requests: bRequest << 8 | bmRequestType */
+#define RH_GET_STATUS 0x0080
+#define RH_CLEAR_FEATURE 0x0100
+#define RH_SET_FEATURE 0x0300
+#define RH_SET_ADDRESS 0x0500
+#define RH_GET_DESCRIPTOR 0x0680
+#define RH_SET_DESCRIPTOR 0x0700
+#define RH_GET_CONFIGURATION 0x0880
+#define RH_SET_CONFIGURATION 0x0900
+#define RH_GET_STATE 0x0280
+#define RH_GET_INTERFACE 0x0A80
+#define RH_SET_INTERFACE 0x0B00
+#define RH_SYNC_FRAME 0x0C80
+/* Our Vendor Specific Request */
+#define RH_SET_EP 0x2000
+
+
+/* Hub port features */
+#define RH_PORT_CONNECTION 0x00
+#define RH_PORT_ENABLE 0x01
+#define RH_PORT_SUSPEND 0x02
+#define RH_PORT_OVER_CURRENT 0x03
+#define RH_PORT_RESET 0x04
+#define RH_PORT_POWER 0x08
+#define RH_PORT_LOW_SPEED 0x09
+
+#define RH_C_PORT_CONNECTION 0x10
+#define RH_C_PORT_ENABLE 0x11
+#define RH_C_PORT_SUSPEND 0x12
+#define RH_C_PORT_OVER_CURRENT 0x13
+#define RH_C_PORT_RESET 0x14
+
+/* Hub features */
+#define RH_C_HUB_LOCAL_POWER 0x00
+#define RH_C_HUB_OVER_CURRENT 0x01
+
+#define RH_DEVICE_REMOTE_WAKEUP 0x00
+#define RH_ENDPOINT_STALL 0x01
+
+#define RH_ACK 0x01
+#define RH_REQ_ERR -1
+#define RH_NACK 0x00
+
+
+/* OHCI ROOT HUB REGISTER MASKS */
+
+/* roothub.portstatus [i] bits */
+#define RH_PS_CCS 0x00000001 /* current connect status */
+#define RH_PS_PES 0x00000002 /* port enable status*/
+#define RH_PS_PSS 0x00000004 /* port suspend status */
+#define RH_PS_POCI 0x00000008 /* port over current indicator */
+#define RH_PS_PRS 0x00000010 /* port reset status */
+#define RH_PS_PPS 0x00000100 /* port power status */
+#define RH_PS_LSDA 0x00000200 /* low speed device attached */
+#define RH_PS_CSC 0x00010000 /* connect status change */
+#define RH_PS_PESC 0x00020000 /* port enable status change */
+#define RH_PS_PSSC 0x00040000 /* port suspend status change */
+#define RH_PS_OCIC 0x00080000 /* over current indicator change */
+#define RH_PS_PRSC 0x00100000 /* port reset status change */
+
+/* roothub.status bits */
+#define RH_HS_LPS 0x00000001 /* local power status */
+#define RH_HS_OCI 0x00000002 /* over current indicator */
+#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
+#define RH_HS_LPSC 0x00010000 /* local power status change */
+#define RH_HS_OCIC 0x00020000 /* over current indicator change */
+#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
+
+/* roothub.b masks */
+#define RH_B_DR 0x0000ffff /* device removable flags */
+#define RH_B_PPCM 0xffff0000 /* port power control mask */
+
+/* roothub.a masks */
+#define RH_A_NDP (0xff << 0) /* number of downstream ports */
+#define RH_A_PSM (1 << 8) /* power switching mode */
+#define RH_A_NPS (1 << 9) /* no power switching */
+#define RH_A_DT (1 << 10) /* device type (mbz) */
+#define RH_A_OCPM (1 << 11) /* over current protection mode */
+#define RH_A_NOCP (1 << 12) /* no over current protection */
+#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
+
+/* urb */
+#define N_URB_TD 48
+typedef struct
+{
+ ed_t *ed;
+ __u16 length; /* number of tds associated with this request */
+ __u16 td_cnt; /* number of tds already serviced */
+ int state;
+ unsigned long pipe;
+ int actual_length;
+ td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */
+} urb_priv_t;
+#define URB_DEL 1
+
+/*
+ * This is the full ohci controller description
+ *
+ * Note how the "proper" USB information is just
+ * a subset of what the full implementation needs. (Linus)
+ */
+
+
+typedef struct ohci {
+ struct ohci_hcca *hcca; /* hcca */
+ /*dma_addr_t hcca_dma;*/
+
+ int irq;
+ int disabled; /* e.g. got a UE, we're hung */
+ int sleeping;
+ unsigned long flags; /* for HC bugs */
+
+ struct ohci_regs *regs; /* OHCI controller's memory */
+
+ ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */
+ ed_t *ed_bulktail; /* last endpoint of bulk list */
+ ed_t *ed_controltail; /* last endpoint of control list */
+ int intrstatus;
+ __u32 hc_control; /* copy of the hc control reg */
+ struct usb_device *dev[32];
+ struct virt_root_hub rh;
+
+ const char *slot_name;
+} ohci_t;
+
+#define NUM_EDS 8 /* num of preallocated endpoint descriptors */
+
+struct ohci_device {
+ ed_t ed[NUM_EDS];
+ int ed_cnt;
+};
+
+/* hcd */
+/* endpoint */
+static int ep_link(ohci_t * ohci, ed_t * ed);
+static int ep_unlink(ohci_t * ohci, ed_t * ed);
+static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe);
+
+/*-------------------------------------------------------------------------*/
+
+/* we need more TDs than EDs */
+#define NUM_TD 64
+
+/* +1 so we can align the storage */
+td_t gtd[NUM_TD+1];
+/* pointers to aligned storage */
+td_t *ptd;
+
+/* TDs ... */
+static inline struct td *
+td_alloc (struct usb_device *usb_dev)
+{
+ int i;
+ struct td *td;
+
+ td = NULL;
+ for (i = 0; i < NUM_TD; i++)
+ {
+ if (ptd[i].usb_dev == NULL)
+ {
+ td = &ptd[i];
+ td->usb_dev = usb_dev;
+ break;
+ }
+ }
+
+ return td;
+}
+
+static inline void
+ed_free (struct ed *ed)
+{
+ ed->usb_dev = NULL;
+}
#
PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
- -mshort-load-bytes -msoft-float
+ -msoft-float
-PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4
+PLATFORM_CPPFLAGS += -march=armv4
+# =========================================================================
+#
+# Supply options according to compiler version
+#
+# =========================================================================
+PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
+PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
unsigned long value;
__asm__ __volatile__(
- "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
+ "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
: "=r" (value)
:
: "memory");
printf ("write %08lx to p15/c1\n", value);
#endif
__asm__ __volatile__(
- "mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
+ "mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
:
: "r" (value)
: "memory");
for (i = 0; i < 100; i++);
}
-/* See also ARM Ref. Man. */
+/* See also ARM920T Technical reference Manual */
#define C1_MMU (1<<0) /* mmu off/on */
#define C1_ALIGN (1<<1) /* alignment faults off/on */
#define C1_DC (1<<2) /* dcache off/on */
-#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
+
+#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
#define C1_SYS_PROT (1<<8) /* system protection */
#define C1_ROM_PROT (1<<9) /* ROM protection */
#define C1_IC (1<<12) /* icache off/on */
-#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
-#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */
+#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
+
int cpu_init (void)
{
/* flush I/D-cache */
i = 0;
asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
+
return (0);
}
{
ulong reg;
- reg = read_p15_c1 ();
+ reg = read_p15_c1 (); /* get control reg. */
cp_delay ();
write_p15_c1 (reg | C1_IC);
}
*/
#include <common.h>
-
#include <arm920t.h>
#include <asm/proc-armv/ptrace.h>
void do_irq (struct pt_regs *pt_regs)
{
+#if defined (CONFIG_USE_IRQ) && defined (CONFIG_ARCH_INTEGRATOR)
+ /* ASSUMED to be a timer interrupt */
+ /* Just clear it - count handled in */
+ /* integratorap.c */
+ *(volatile ulong *)(CFG_TIMERBASE + 0x0C) = 0;
+#else
printf ("interrupt request\n");
show_regs (pt_regs);
bad_mode ();
+#endif
}
#########################################################################
-.depend: Makefile $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
mcr p15, 0, r0, c1, c0, 0
-
/*
* before relocating, we have to setup RAM timing
* because memory timing is board-dependend, you will
mov ip, lr
bl lowlevel_init
mov lr, ip
-
mov pc, lr
PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
-msoft-float
-PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4
+PLATFORM_CPPFLAGS += -march=armv4
+# =========================================================================
+#
+# Supply options according to compiler version
+#
+# =========================================================================
+PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
+PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
* Go setup Memory and board specific bits prior to relocation.
*/
mov ip, lr /* perserve link reg across call */
- bl platformsetup /* go setup pll,mux,memory */
+ bl lowlevel_init /* go setup pll,mux,memory */
mov lr, ip /* restore link */
mov pc, lr /* back to my caller */
/*
#
PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
- -mshort-load-bytes -msoft-float
+ -msoft-float
-PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4
+PLATFORM_CPPFLAGS += -march=armv4
+# =========================================================================
+#
+# Supply options according to compiler version
+#
+# =========================================================================
+PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
+PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
{
volatile int i;
- /* Many OMAP regs need at least 2 nops */
+ /* copro seems to need some delay between reading and writing */
for (i = 0; i < 100; i++);
}
-/* See also ARM Ref. Man. */
+/* See also ARM926EJ-S Technical Reference Manual */
#define C1_MMU (1<<0) /* mmu off/on */
#define C1_ALIGN (1<<1) /* alignment faults off/on */
#define C1_DC (1<<2) /* dcache off/on */
-#define C1_WB (1<<3) /* merging write buffer on/off */
-#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
+
+#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
#define C1_SYS_PROT (1<<8) /* system protection */
#define C1_ROM_PROT (1<<9) /* ROM protection */
#define C1_IC (1<<12) /* icache off/on */
-#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
-#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */
+#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
+
int cpu_init (void)
{
/* flush I/D-cache */
i = 0;
asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
+
return (0);
}
*/
#include <common.h>
-#include <arm925t.h>
-
+#include <arm926ejs.h>
#include <asm/proc-armv/ptrace.h>
#define TIMER_LOAD_VAL 0xffffffff
#ifdef CONFIG_OMAP
#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8))
#endif
-#ifdef CONFIG_INTEGRATOR
-#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+4))
-#endif
#ifdef CONFIG_VERSATILE
#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+4))
#endif
bad_mode ();
}
+#ifdef CONFIG_INTEGRATOR
+
+ /* Timer functionality supplied by Integrator board (AP or CP) */
+
+#else
+
static ulong timestamp;
static ulong lastdec;
val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CFG_PVT << MPUTIM_PTV_BIT);
*((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val;
#endif /* CONFIG_OMAP */
-#ifdef CONFIG_INTEGRATOR
- /* Load timer with initial value */
- *(volatile ulong *)(CFG_TIMERBASE + 0) = TIMER_LOAD_VAL;
- /* Set timer to be enabled, free-running, no interrupts, 256 divider */
- *(volatile ulong *)(CFG_TIMERBASE + 8) = 0x8C;
-#endif /* CONFIG_INTEGRATOR */
+
#ifdef CONFIG_VERSATILE
*(volatile ulong *)(CFG_TIMERBASE + 0) = CFG_TIMER_RELOAD; /* TimerLoad */
*(volatile ulong *)(CFG_TIMERBASE + 4) = CFG_TIMER_RELOAD; /* TimerValue */
tbclk = CFG_HZ;
return tbclk;
}
+
+#endif /* CONFIG_INTEGRATOR */
* Go setup Memory and board specific bits prior to relocation.
*/
mov ip, lr /* perserve link reg across call */
- bl platformsetup /* go setup pll,mux,memory */
+ bl lowlevel_init /* go setup pll,mux,memory */
mov lr, ip /* restore link */
mov pc, lr /* back to my caller */
/*
#endif
+# ifdef CONFIG_INTEGRATOR
+
+ /* Satisfied by Integrator routine (AP or CP) */
+
+#else
+
.align 5
.globl reset_cpu
reset_cpu:
_loop_forever:
b _loop_forever
-
rstctl1:
.word 0xfffece10
+
+#endif /* #ifdef CONFIG_INTEGRATOR */
--- /dev/null
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(CPU).a
+
+START = start.o
+OBJS = interrupts.o cpu.o
+
+all: .depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
+ -msoft-float
+
+PLATFORM_CPPFLAGS += -march=armv4
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * CPU specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <arm946es.h>
+
+/* read co-processor 15, register #1 (control register) */
+static unsigned long read_p15_c1 (void)
+{
+ unsigned long value;
+
+ __asm__ __volatile__(
+ "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
+ : "=r" (value)
+ :
+ : "memory");
+
+#ifdef MMU_DEBUG
+ printf ("p15/c1 is = %08lx\n", value);
+#endif
+ return value;
+}
+
+/* write to co-processor 15, register #1 (control register) */
+static void write_p15_c1 (unsigned long value)
+{
+#ifdef MMU_DEBUG
+ printf ("write %08lx to p15/c1\n", value);
+#endif
+ __asm__ __volatile__(
+ "mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
+ :
+ : "r" (value)
+ : "memory");
+
+ read_p15_c1 ();
+}
+
+static void cp_delay (void)
+{
+ volatile int i;
+
+ /* copro seems to need some delay between reading and writing */
+ for (i = 0; i < 100; i++);
+}
+
+/* See also ARM946E-S Technical Reference Manual */
+#define C1_MMU (1<<0) /* mmu off/on */
+#define C1_ALIGN (1<<1) /* alignment faults off/on */
+#define C1_DC (1<<2) /* dcache off/on */
+
+#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
+#define C1_SYS_PROT (1<<8) /* system protection */
+#define C1_ROM_PROT (1<<9) /* ROM protection */
+#define C1_IC (1<<12) /* icache off/on */
+#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
+
+
+int cpu_init (void)
+{
+ /*
+ * setup up stacks if necessary
+ */
+#ifdef CONFIG_USE_IRQ
+ DECLARE_GLOBAL_DATA_PTR;
+
+ IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
+ FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
+#endif
+ return 0;
+}
+
+int cleanup_before_linux (void)
+{
+ /*
+ * this function is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we turn off caches etc ...
+ */
+
+ unsigned long i;
+
+ disable_interrupts ();
+
+ /* ARM926E-S needs the protection unit enabled for the icache to have
+ * been enabled - left for possible later use
+ * should turn off the protection unit as well....
+ */
+ /* turn off I/D-cache */
+ asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+ i &= ~(C1_DC | C1_IC);
+ asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+
+ /* flush I/D-cache */
+ i = 0;
+ asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
+ asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (i));
+ return (0);
+}
+
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ extern void reset_cpu (ulong addr);
+
+ disable_interrupts ();
+ reset_cpu (0);
+ /*NOTREACHED*/
+ return (0);
+}
+/* ARM926E-S needs the protection unit enabled for this to have any effect
+ - left for possible later use */
+void icache_enable (void)
+{
+ ulong reg;
+
+ reg = read_p15_c1 (); /* get control reg. */
+ cp_delay ();
+ write_p15_c1 (reg | C1_IC);
+}
+
+void icache_disable (void)
+{
+ ulong reg;
+
+ reg = read_p15_c1 ();
+ cp_delay ();
+ write_p15_c1 (reg & ~C1_IC);
+}
+
+int icache_status (void)
+{
+ return (read_p15_c1 () & C1_IC) != 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Texas Instruments <www.ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <arm946es.h>
+#include <asm/proc-armv/ptrace.h>
+
+#define TIMER_LOAD_VAL 0xffffffff
+extern void reset_cpu(ulong addr);
+
+#ifdef CONFIG_USE_IRQ
+/* enable IRQ interrupts */
+void enable_interrupts (void)
+{
+ unsigned long temp;
+ __asm__ __volatile__("mrs %0, cpsr\n"
+ "bic %0, %0, #0x80\n"
+ "msr cpsr_c, %0"
+ : "=r" (temp)
+ :
+ : "memory");
+}
+
+
+/*
+ * disable IRQ/FIQ interrupts
+ * returns true if interrupts had been enabled before we disabled them
+ */
+int disable_interrupts (void)
+{
+ unsigned long old,temp;
+ __asm__ __volatile__("mrs %0, cpsr\n"
+ "orr %1, %0, #0xc0\n"
+ "msr cpsr_c, %1"
+ : "=r" (old), "=r" (temp)
+ :
+ : "memory");
+ return (old & 0x80) == 0;
+}
+#else
+void enable_interrupts (void)
+{
+ return;
+}
+int disable_interrupts (void)
+{
+ return 0;
+}
+#endif
+
+
+void bad_mode (void)
+{
+ panic ("Resetting CPU ...\n");
+ reset_cpu (0);
+}
+
+void show_regs (struct pt_regs *regs)
+{
+ unsigned long flags;
+ const char *processor_modes[] = {
+ "USER_26", "FIQ_26", "IRQ_26", "SVC_26",
+ "UK4_26", "UK5_26", "UK6_26", "UK7_26",
+ "UK8_26", "UK9_26", "UK10_26", "UK11_26",
+ "UK12_26", "UK13_26", "UK14_26", "UK15_26",
+ "USER_32", "FIQ_32", "IRQ_32", "SVC_32",
+ "UK4_32", "UK5_32", "UK6_32", "ABT_32",
+ "UK8_32", "UK9_32", "UK10_32", "UND_32",
+ "UK12_32", "UK13_32", "UK14_32", "SYS_32",
+ };
+
+ flags = condition_codes (regs);
+
+ printf ("pc : [<%08lx>] lr : [<%08lx>]\n"
+ "sp : %08lx ip : %08lx fp : %08lx\n",
+ instruction_pointer (regs),
+ regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
+ printf ("r10: %08lx r9 : %08lx r8 : %08lx\n",
+ regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
+ printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
+ regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
+ printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
+ regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
+ printf ("Flags: %c%c%c%c",
+ flags & CC_N_BIT ? 'N' : 'n',
+ flags & CC_Z_BIT ? 'Z' : 'z',
+ flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
+ printf (" IRQs %s FIQs %s Mode %s%s\n",
+ interrupts_enabled (regs) ? "on" : "off",
+ fast_interrupts_enabled (regs) ? "on" : "off",
+ processor_modes[processor_mode (regs)],
+ thumb_mode (regs) ? " (T)" : "");
+}
+
+void do_undefined_instruction (struct pt_regs *pt_regs)
+{
+ printf ("undefined instruction\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_software_interrupt (struct pt_regs *pt_regs)
+{
+ printf ("software interrupt\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_prefetch_abort (struct pt_regs *pt_regs)
+{
+ printf ("prefetch abort\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_data_abort (struct pt_regs *pt_regs)
+{
+ printf ("data abort\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_not_used (struct pt_regs *pt_regs)
+{
+ printf ("not used\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_fiq (struct pt_regs *pt_regs)
+{
+ printf ("fast interrupt request\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_irq (struct pt_regs *pt_regs)
+{
+ printf ("interrupt request\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+#ifdef CONFIG_INTEGRATOR
+ /* Timer functionality supplied by Integrator board (AP or CP) */
+#else
+
+static ulong timestamp;
+static ulong lastdec;
+
+/* nothing really to do with interrupts, just starts up a counter. */
+int interrupt_init (void)
+{
+ /* init the timestamp and lastdec value */
+ reset_timer_masked();
+
+ return (0);
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer (void)
+{
+ reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+ return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+ timestamp = t;
+}
+
+/* delay x useconds AND perserve advance timstamp value */
+void udelay(unsigned long usec)
+{
+ udelay_masked(usec);
+}
+
+void reset_timer_masked (void)
+{
+ /* reset time */
+ lastdec = READ_TIMER; /* capure current decrementer value time */
+ timestamp = 0; /* start "advancing" time stamp from 0 */
+}
+
+ulong get_timer_raw (void)
+{
+ ulong now = READ_TIMER; /* current tick value */
+
+ if (lastdec >= now) { /* normal mode (non roll) */
+ /* normal mode */
+ timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */
+ } else { /* we have overflow of the count down timer */
+ /* nts = ts + ld + (TLV - now)
+ * ts=old stamp, ld=time that passed before passing through -1
+ * (TLV-now) amount of time after passing though -1
+ * nts = new "advancing time stamp"...it could also roll and cause problems.
+ */
+ timestamp += lastdec + TIMER_LOAD_VAL - now;
+ }
+ lastdec = now;
+
+ return timestamp;
+}
+
+ulong get_timer_masked (void)
+{
+ return get_timer_raw() / TIMER_LOAD_VAL;
+}
+
+/* waits specified delay value and resets timestamp */
+void udelay_masked (unsigned long usec)
+{
+ ulong tmo;
+
+ if(usec >= 1000){ /* if "big" number, spread normalization to seconds */
+ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
+ tmo *= CFG_HZ_CLOCK; /* find number of "ticks" to wait to achieve target */
+ tmo /= 1000; /* finish normalize. */
+ }else{ /* else small number, don't kill it prior to HZ multiply */
+ tmo = usec * CFG_HZ_CLOCK;
+ tmo /= (1000*1000);
+ }
+
+ reset_timer_masked (); /* set "advancing" timestamp to 0, set lastdec vaule */
+
+ while (get_timer_raw () < tmo) /* wait for time stamp to overtake tick number.*/
+ /*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+ ulong tbclk;
+
+ tbclk = CFG_HZ;
+ return tbclk;
+}
+
+#endif /* CONFIG_INTEGRATOR */
--- /dev/null
+/*
+ * armboot - Startup Code for ARM926EJS CPU-core
+ *
+ * Copyright (c) 2003 Texas Instruments
+ *
+ * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
+ *
+ * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
+ * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
+ * Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
+ * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
+ * Copyright (c) 2003 Kshitij <kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+/*
+ *************************************************************************
+ *
+ * Jump vector table as in table 3.1 in [1]
+ *
+ *************************************************************************
+ */
+
+
+.globl _start
+_start:
+ b reset
+ ldr pc, _undefined_instruction
+ ldr pc, _software_interrupt
+ ldr pc, _prefetch_abort
+ ldr pc, _data_abort
+ ldr pc, _not_used
+ ldr pc, _irq
+ ldr pc, _fiq
+
+_undefined_instruction:
+ .word undefined_instruction
+_software_interrupt:
+ .word software_interrupt
+_prefetch_abort:
+ .word prefetch_abort
+_data_abort:
+ .word data_abort
+_not_used:
+ .word not_used
+_irq:
+ .word irq
+_fiq:
+ .word fiq
+
+ .balignl 16,0xdeadbeef
+
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * setup Memory and board specific bits prior to relocation.
+ * relocate armboot to ram
+ * setup stack
+ *
+ *************************************************************************
+ */
+
+_TEXT_BASE:
+ .word TEXT_BASE
+
+.globl _armboot_start
+_armboot_start:
+ .word _start
+
+/*
+ * These are defined in the board-specific linker script.
+ */
+.globl _bss_start
+_bss_start:
+ .word __bss_start
+
+.globl _bss_end
+_bss_end:
+ .word _end
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+ .word 0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+ .word 0x0badc0de
+#endif
+
+
+/*
+ * the actual reset code
+ */
+
+reset:
+ /*
+ * set the cpu to SVC32 mode
+ */
+ mrs r0,cpsr
+ bic r0,r0,#0x1f
+ orr r0,r0,#0xd3
+ msr cpsr,r0
+
+ /*
+ * we do sys-critical inits only at reboot,
+ * not when booting from ram!
+ */
+#ifdef CONFIG_INIT_CRITICAL
+ bl cpu_init_crit
+#endif
+
+relocate: /* relocate U-Boot to RAM */
+ adr r0, _start /* r0 <- current position of code */
+ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
+ cmp r0, r1 /* don't reloc during debug */
+ beq stack_setup
+
+ ldr r2, _armboot_start
+ ldr r3, _bss_start
+ sub r2, r3, r2 /* r2 <- size of armboot */
+ add r2, r0, r2 /* r2 <- source end address */
+
+copy_loop:
+ ldmia r0!, {r3-r10} /* copy from source address [r0] */
+ stmia r1!, {r3-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end addreee [r2] */
+ ble copy_loop
+
+ /* Set up the stack */
+stack_setup:
+ ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
+ sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
+ sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
+#ifdef CONFIG_USE_IRQ
+ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
+#endif
+ sub sp, r0, #12 /* leave 3 words for abort-stack */
+
+clear_bss:
+ ldr r0, _bss_start /* find start of bss segment */
+ ldr r1, _bss_end /* stop here */
+ mov r2, #0x00000000 /* clear */
+
+clbss_l:str r2, [r0] /* clear loop... */
+ add r0, r0, #4
+ cmp r0, r1
+ bne clbss_l
+
+ ldr pc, _start_armboot
+
+_start_armboot:
+ .word start_armboot
+
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+
+
+cpu_init_crit:
+ /*
+ * flush v4 I/D caches
+ */
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 /* flush v4 I-cache */
+ mcr p15, 0, r0, c7, c6, 0 /* flush v4 D-cache */
+
+ /*
+ * disable MMU stuff and caches
+ */
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
+ bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
+ orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
+ orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
+ mcr p15, 0, r0, c1, c0, 0
+
+ /*
+ * Go setup Memory and board specific bits prior to relocation.
+ */
+ mov ip, lr /* perserve link reg across call */
+ bl lowlevel_init /* go setup memory */
+ mov lr, ip /* restore link */
+ mov pc, lr /* back to my caller */
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE 72
+
+#define S_OLD_R0 68
+#define S_PSR 64
+#define S_PC 60
+#define S_LR 56
+#define S_SP 52
+
+#define S_IP 48
+#define S_FP 44
+#define S_R10 40
+#define S_R9 36
+#define S_R8 32
+#define S_R7 28
+#define S_R6 24
+#define S_R5 20
+#define S_R4 16
+#define S_R3 12
+#define S_R2 8
+#define S_R1 4
+#define S_R0 0
+
+#define MODE_SVC 0x13
+#define I_BIT 0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
+ */
+
+ .macro bad_save_user_regs
+ @ carve out a frame on current user stack
+ sub sp, sp, #S_FRAME_SIZE
+ stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
+
+ ldr r2, _armboot_start
+ sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+ sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
+ @ get values for "aborted" pc and cpsr (into parm regs)
+ ldmia r2, {r2 - r3}
+ add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
+ add r5, sp, #S_SP
+ mov r1, lr
+ stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
+ mov r0, sp @ save current stack into r0 (param register)
+ .endm
+
+ .macro irq_save_user_regs
+ sub sp, sp, #S_FRAME_SIZE
+ stmia sp, {r0 - r12} @ Calling r0-r12
+ @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
+ add r8, sp, #S_PC
+ stmdb r8, {sp, lr}^ @ Calling SP, LR
+ str lr, [r8, #0] @ Save calling PC
+ mrs r6, spsr
+ str r6, [r8, #4] @ Save CPSR
+ str r0, [r8, #8] @ Save OLD_R0
+ mov r0, sp
+ .endm
+
+ .macro irq_restore_user_regs
+ ldmia sp, {r0 - lr}^ @ Calling r0 - lr
+ mov r0, r0
+ ldr lr, [sp, #S_PC] @ Get PC
+ add sp, sp, #S_FRAME_SIZE
+ subs pc, lr, #4 @ return & move spsr_svc into cpsr
+ .endm
+
+ .macro get_bad_stack
+ ldr r13, _armboot_start @ setup our mode stack
+ sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+ sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
+
+ str lr, [r13] @ save caller lr in position 0 of saved stack
+ mrs lr, spsr @ get the spsr
+ str lr, [r13, #4] @ save spsr in position 1 of saved stack
+ mov r13, #MODE_SVC @ prepare SVC-Mode
+ @ msr spsr_c, r13
+ msr spsr, r13 @ switch modes, make sure moves will execute
+ mov lr, pc @ capture return pc
+ movs pc, lr @ jump to next instruction & switch modes.
+ .endm
+
+ .macro get_irq_stack @ setup IRQ stack
+ ldr sp, IRQ_STACK_START
+ .endm
+
+ .macro get_fiq_stack @ setup FIQ stack
+ ldr sp, FIQ_STACK_START
+ .endm
+
+/*
+ * exception handlers
+ */
+ .align 5
+undefined_instruction:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_undefined_instruction
+
+ .align 5
+software_interrupt:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_software_interrupt
+
+ .align 5
+prefetch_abort:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_prefetch_abort
+
+ .align 5
+data_abort:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_data_abort
+
+ .align 5
+not_used:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_not_used
+
+#ifdef CONFIG_USE_IRQ
+
+ .align 5
+irq:
+ get_irq_stack
+ irq_save_user_regs
+ bl do_irq
+ irq_restore_user_regs
+
+ .align 5
+fiq:
+ get_fiq_stack
+ /* someone ought to write a more effiction fiq_save_user_regs */
+ irq_save_user_regs
+ bl do_fiq
+ irq_restore_user_regs
+
+#else
+
+ .align 5
+irq:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_irq
+
+ .align 5
+fiq:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_fiq
+
+#endif
+
+# ifdef CONFIG_INTEGRATOR
+
+ /* Satisfied by general board level routine */
+
+#else
+
+ .align 5
+.globl reset_cpu
+reset_cpu:
+
+ ldr r1, rstctl1 /* get clkm1 reset ctl */
+ mov r3, #0x0
+ strh r3, [r1] /* clear it */
+ mov r3, #0x8
+ strh r3, [r1] /* force dsp+arm reset */
+_loop_forever:
+ b _loop_forever
+
+rstctl1:
+ .word 0xfffece10
+
+#endif /* #ifdef CONFIG_INTEGRATOR */
--- /dev/null
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(CPU).a
+
+START = start.o
+OBJS = interrupts.o cpu.o
+
+all: .depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
+ -msoft-float
+
+PLATFORM_CPPFLAGS += -march=armv4
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * CPU specific code for an unknown cpu
+ * - hence fairly empty......
+ */
+
+#include <common.h>
+#include <command.h>
+
+int cpu_init (void)
+{
+ /*
+ * setup up stacks if necessary
+ */
+#ifdef CONFIG_USE_IRQ
+ DECLARE_GLOBAL_DATA_PTR;
+
+ IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
+ FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
+#endif
+ return 0;
+}
+
+int cleanup_before_linux (void)
+{
+ /*
+ * this function is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we turn off caches etc ...
+ */
+
+ disable_interrupts ();
+
+ /* Since the CM has unknown processor we do not support
+ * cache operations
+ */
+
+ return (0);
+}
+
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ extern void reset_cpu (ulong addr);
+
+ disable_interrupts ();
+ reset_cpu (0);
+ /*NOTREACHED*/
+ return (0);
+}
+
+/* May not be cahed processor on the CM - do nothing */
+void icache_enable (void)
+{
+}
+
+void icache_disable (void)
+{
+}
+
+/* return "disabled" */
+int icache_status (void)
+{
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Texas Instruments <www.ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/proc-armv/ptrace.h>
+
+#ifndef CONFIG_INTEGRATOR
+/* Only to be used for integrator/AP or /CP */
+/* Allows U-Boot to be used with any ARM supplied core module (CM),
+ * provided the ARM boot monitor, or similar software,
+ * runs first to set up the platform e.g. map writeable memory to 0x00000000
+ * - see Integrator User Guides
+ * Versatile has a supported cpu - arm926ejs
+ * Some integrator CMs cpus are supported
+ * CM926EJ-S, CM946E-S
+ * For platforms with supported cpus U-Boot can be used as the sole boot
+ * monitor/loader - it will configure the platform itself
+ * Also U-Boot may be faster/smaller in those cases since specific
+ * qualities of the cpu and/or CM can be used e.g i and/or d caches etc.
+ */
+#endif
+extern void reset_cpu(ulong addr);
+
+#ifdef CONFIG_USE_IRQ
+/* enable IRQ interrupts */
+void enable_interrupts (void)
+{
+ unsigned long temp;
+ __asm__ __volatile__("mrs %0, cpsr\n"
+ "bic %0, %0, #0x80\n"
+ "msr cpsr_c, %0"
+ : "=r" (temp)
+ :
+ : "memory");
+}
+
+
+/*
+ * disable IRQ/FIQ interrupts
+ * returns true if interrupts had been enabled before we disabled them
+ */
+int disable_interrupts (void)
+{
+ unsigned long old,temp;
+ __asm__ __volatile__("mrs %0, cpsr\n"
+ "orr %1, %0, #0xc0\n"
+ "msr cpsr_c, %1"
+ : "=r" (old), "=r" (temp)
+ :
+ : "memory");
+ return (old & 0x80) == 0;
+}
+#else
+void enable_interrupts (void)
+{
+ return;
+}
+int disable_interrupts (void)
+{
+ return 0;
+}
+#endif
+
+
+void bad_mode (void)
+{
+ panic ("Resetting CPU ...\n");
+ reset_cpu (0);
+}
+
+void show_regs (struct pt_regs *regs)
+{
+ unsigned long flags;
+ const char *processor_modes[] = {
+ "USER_26", "FIQ_26", "IRQ_26", "SVC_26",
+ "UK4_26", "UK5_26", "UK6_26", "UK7_26",
+ "UK8_26", "UK9_26", "UK10_26", "UK11_26",
+ "UK12_26", "UK13_26", "UK14_26", "UK15_26",
+ "USER_32", "FIQ_32", "IRQ_32", "SVC_32",
+ "UK4_32", "UK5_32", "UK6_32", "ABT_32",
+ "UK8_32", "UK9_32", "UK10_32", "UND_32",
+ "UK12_32", "UK13_32", "UK14_32", "SYS_32",
+ };
+
+ flags = condition_codes (regs);
+
+ printf ("pc : [<%08lx>] lr : [<%08lx>]\n"
+ "sp : %08lx ip : %08lx fp : %08lx\n",
+ instruction_pointer (regs),
+ regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
+ printf ("r10: %08lx r9 : %08lx r8 : %08lx\n",
+ regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
+ printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
+ regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
+ printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
+ regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
+ printf ("Flags: %c%c%c%c",
+ flags & CC_N_BIT ? 'N' : 'n',
+ flags & CC_Z_BIT ? 'Z' : 'z',
+ flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
+ printf (" IRQs %s FIQs %s Mode %s%s\n",
+ interrupts_enabled (regs) ? "on" : "off",
+ fast_interrupts_enabled (regs) ? "on" : "off",
+ processor_modes[processor_mode (regs)],
+ thumb_mode (regs) ? " (T)" : "");
+}
+
+void do_undefined_instruction (struct pt_regs *pt_regs)
+{
+ printf ("undefined instruction\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_software_interrupt (struct pt_regs *pt_regs)
+{
+ printf ("software interrupt\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_prefetch_abort (struct pt_regs *pt_regs)
+{
+ printf ("prefetch abort\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_data_abort (struct pt_regs *pt_regs)
+{
+ printf ("data abort\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_not_used (struct pt_regs *pt_regs)
+{
+ printf ("not used\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_fiq (struct pt_regs *pt_regs)
+{
+ printf ("fast interrupt request\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_irq (struct pt_regs *pt_regs)
+{
+ printf ("interrupt request\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+/* The timer functionality is supplied by the Integrator board */
+/* - see board/integrator<>.c */
--- /dev/null
+/*
+ * armboot - Startup Code for ARM926EJS CPU-core
+ *
+ * Copyright (c) 2003 Texas Instruments
+ *
+ * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
+ *
+ * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
+ * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
+ * Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
+ * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
+ * Copyright (c) 2003 Kshitij <kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+/*
+ *************************************************************************
+ *
+ * Jump vector table
+ *
+ *************************************************************************
+ */
+
+.globl _start
+_start:
+ b reset
+ ldr pc, _undefined_instruction
+ ldr pc, _software_interrupt
+ ldr pc, _prefetch_abort
+ ldr pc, _data_abort
+ ldr pc, _not_used
+ ldr pc, _irq
+ ldr pc, _fiq
+
+_undefined_instruction:
+ .word undefined_instruction
+_software_interrupt:
+ .word software_interrupt
+_prefetch_abort:
+ .word prefetch_abort
+_data_abort:
+ .word data_abort
+_not_used:
+ .word not_used
+_irq:
+ .word irq
+_fiq:
+ .word fiq
+
+ .balignl 16,0xdeadbeef
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * setup memory and board specific bits prior to relocation.
+ * relocate armboot to ram
+ * setup stack
+ *
+ *************************************************************************
+ */
+
+_TEXT_BASE:
+ .word TEXT_BASE /* address of _start in the linked image */
+
+.globl _armboot_start
+_armboot_start:
+ .word _start
+
+/*
+ * These are defined in the board-specific linker script.
+ */
+.globl _bss_start
+_bss_start:
+ .word __bss_start
+
+.globl _bss_end
+_bss_end:
+ .word _end
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+ .word 0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+ .word 0x0badc0de
+#endif
+
+
+/*
+ * the actual reset code
+ */
+.globl reset
+reset:
+ /*
+ * set the cpu to SVC32 mode
+ */
+ mrs r0,cpsr
+ bic r0,r0,#0x1f
+ orr r0,r0,#0xd3
+ msr cpsr,r0
+
+ /*
+ * we do sys-critical inits only at reboot,
+ * not when booting from ram!
+ */
+#ifdef CONFIG_INIT_CRITICAL
+ bl cpu_init_crit
+#endif
+
+relocate: /* relocate U-Boot to RAM */
+ adr r0, _start /* pc relative address of label */
+ ldr r1, _TEXT_BASE /* linked image address of label */
+ cmp r0, r1 /* test if we run from flash or RAM */
+ beq stack_setup /* ifeq we are in the RAM copy */
+
+ ldr r2, _armboot_start
+ ldr r3, _bss_start
+ sub r2, r3, r2 /* r2 <- size of armboot */
+ add r2, r0, r2 /* r2 <- source end address */
+
+copy_loop:
+ ldmia r0!, {r3-r10} /* copy from source address [r0] */
+ stmia r1!, {r3-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end addreee [r2] */
+ ble copy_loop
+
+ /* Set up the stack */
+stack_setup:
+ ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
+ sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
+ sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
+#ifdef CONFIG_USE_IRQ
+ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
+#endif
+ sub sp, r0, #12 /* leave 3 words for abort-stack */
+
+clear_bss:
+ ldr r0, _bss_start /* find start of bss segment */
+ ldr r1, _bss_end /* stop here */
+ mov r2, #0x00000000 /* clear */
+
+clbss_l:str r2, [r0] /* clear loop... */
+ add r0, r0, #4
+ cmp r0, r1
+ ble clbss_l
+
+ ldr pc, _start_armboot
+
+_start_armboot:
+ .word start_armboot
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+
+cpu_init_crit:
+ /* arm_int_generic assumes the ARM boot monitor, or user software,
+ * has initialized the platform
+ */
+ mov pc, lr /* back to my caller */
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE 72
+
+#define S_OLD_R0 68
+#define S_PSR 64
+#define S_PC 60
+#define S_LR 56
+#define S_SP 52
+
+#define S_IP 48
+#define S_FP 44
+#define S_R10 40
+#define S_R9 36
+#define S_R8 32
+#define S_R7 28
+#define S_R6 24
+#define S_R5 20
+#define S_R4 16
+#define S_R3 12
+#define S_R2 8
+#define S_R1 4
+#define S_R0 0
+
+#define MODE_SVC 0x13
+#define I_BIT 0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
+ */
+
+ .macro bad_save_user_regs
+ @ carve out a frame on current user stack
+ sub sp, sp, #S_FRAME_SIZE
+ stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
+
+ ldr r2, _armboot_start
+ sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+ sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
+ @ get values for "aborted" pc and cpsr (into parm regs)
+ ldmia r2, {r2 - r3}
+ add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
+ add r5, sp, #S_SP
+ mov r1, lr
+ stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
+ mov r0, sp @ save current stack into r0 (param register)
+ .endm
+
+ .macro irq_save_user_regs
+ sub sp, sp, #S_FRAME_SIZE
+ stmia sp, {r0 - r12} @ Calling r0-r12
+ @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
+ add r8, sp, #S_PC
+ stmdb r8, {sp, lr}^ @ Calling SP, LR
+ str lr, [r8, #0] @ Save calling PC
+ mrs r6, spsr
+ str r6, [r8, #4] @ Save CPSR
+ str r0, [r8, #8] @ Save OLD_R0
+ mov r0, sp
+ .endm
+
+ .macro irq_restore_user_regs
+ ldmia sp, {r0 - lr}^ @ Calling r0 - lr
+ mov r0, r0
+ ldr lr, [sp, #S_PC] @ Get PC
+ add sp, sp, #S_FRAME_SIZE
+ subs pc, lr, #4 @ return & move spsr_svc into cpsr
+ .endm
+
+ .macro get_bad_stack
+ ldr r13, _armboot_start @ setup our mode stack
+ sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+ sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
+
+ str lr, [r13] @ save caller lr in position 0 of saved stack
+ mrs lr, spsr @ get the spsr
+ str lr, [r13, #4] @ save spsr in position 1 of saved stack
+ mov r13, #MODE_SVC @ prepare SVC-Mode
+ @ msr spsr_c, r13
+ msr spsr, r13 @ switch modes, make sure moves will execute
+ mov lr, pc @ capture return pc
+ movs pc, lr @ jump to next instruction & switch modes.
+ .endm
+
+ .macro get_irq_stack @ setup IRQ stack
+ ldr sp, IRQ_STACK_START
+ .endm
+
+ .macro get_fiq_stack @ setup FIQ stack
+ ldr sp, FIQ_STACK_START
+ .endm
+
+/*
+ * exception handlers
+ */
+ .align 5
+.globl undefined_instruction
+undefined_instruction:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_undefined_instruction
+
+ .align 5
+.globl software_interrupt
+software_interrupt:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_software_interrupt
+
+ .align 5
+.globl prefetch_abort
+prefetch_abort:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_prefetch_abort
+
+ .align 5
+.globl data_abort
+data_abort:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_data_abort
+
+ .align 5
+.globl not_used
+not_used:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_not_used
+
+#ifdef CONFIG_USE_IRQ
+ .align 5
+.globl irq
+irq:
+ get_irq_stack
+ irq_save_user_regs
+ bl do_irq
+ irq_restore_user_regs
+
+ .align 5
+.globl fiq
+fiq:
+ get_fiq_stack
+ /* someone ought to write a more effiction fiq_save_user_regs */
+ irq_save_user_regs
+ bl do_fiq
+ irq_restore_user_regs
+
+#else
+
+ .align 5
+.globl irq
+irq:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_irq
+
+ .align 5
+.globl fiq
+fiq:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_fiq
+
+#endif
BIG_ENDIAN = y
PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
- -mshort-load-bytes -msoft-float -mbig-endian
+ -msoft-float -mbig-endian
-PLATFORM_CPPFLAGS += -mbig-endian -mapcs-32 -march=armv4 -mtune=strongarm1100
+PLATFORM_CPPFLAGS += -mbig-endian -march=armv4 -mtune=strongarm1100
+# =========================================================================
+#
+# Supply options according to compiler version
+#
+# =========================================================================
+PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
+PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
PciBar *ioBars[IXP425_PCI_MAX_BAR];
PciDevice devices[IXP425_PCI_MAX_FUNC_ON_BUS];
-void out_8 (volatile unsigned *addr, char val)
-{
- *addr = val;
-}
-
-void out_le16 (volatile unsigned *addr, unsigned short val)
-{
- *addr = cpu_to_le16 (val);
-}
-
-void out_le32 (volatile unsigned *addr, unsigned int val)
-{
- *addr = cpu_to_le32 (val);
-}
-
-unsigned char in_8 (volatile unsigned *addr)
-{
- unsigned char val;
-
- val = *addr;
- return val;
-}
-
-unsigned short in_le16 (volatile unsigned *addr)
-{
- unsigned short val;
-
- val = *addr;
- val = le16_to_cpu (val);
- return val;
-}
-
-unsigned in_le32 (volatile unsigned *addr)
-{
- unsigned int val;
-
- val = *addr;
- val = le32_to_cpu (val);
- return val;
-}
-
int pci_read_config_dword (pci_dev_t dev, int where, unsigned int *val)
{
unsigned int retval;
pci_write_config_dword (devices[i].device,
PCI_CFG_BASE_ADDRESS_0,
devices[i].bar[0].address);
- addr = (BIT (31 - devices[i].device) |
+ addr = BIT (31 - devices[i].device) |
(0 << PCI_NP_AD_FUNCSL) |
- (PCI_CFG_BASE_ADDRESS_0) ) & ~3;
+ (PCI_CFG_BASE_ADDRESS_0 & ~3);
pci_write_config_dword (devices[i].device,
PCI_CFG_DEV_INT_LINE, devices[i].irq);
#
PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
- -mshort-load-bytes -msoft-float
+ -msoft-float
-PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4
+PLATFORM_CPPFLAGS += -march=armv4
+# =========================================================================
+#
+# Supply options according to compiler version
+#
+# ========================================================================
+PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
+PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
* Otherwise they hang in mii_send() !!! Sorry!
*****************************************************************************/
-int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
+int mcf52x2_miiphy_read (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value)
{
short rdreg; /* register working value */
return 0;
}
-int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
+int mcf52x2_miiphy_write (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value)
{
short rdreg; /* register working value */
return 0;
}
#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII) */
-
#endif /* CFG_CMD_NET, FEC_ENET */
+
+int mcf52x2_miiphy_initialize(bd_t *bis)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
+#if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)
+ miiphy_register("mcf52x2phy", mcf52x2_miiphy_read, mcf52x2_miiphy_write);
+#endif
+#endif
+ return 0;
+}
LIB = lib$(CPU).a
START = start.o
-OBJS = asc_serial.o au1x00_serial.o au1x00_eth.o \
+OBJS = asc_serial.o au1x00_serial.o au1x00_eth.o au1x00_usb_ohci.o \
cpu.o interrupts.o incaip_clock.o
SOBJS = incaip_wdt.o cache.o
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
#ifdef CONFIG_AU1X00
-#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII)
-#error "PHY and MII not supported yet"
+#if defined(CFG_DISCOVER_PHY)
+#error "PHY not supported yet"
/* We just assume that we are running 100FD for now */
/* We all use switches, right? ;-) */
#endif
#include <asm/io.h>
#include <asm/au1x00.h>
+#if (CONFIG_COMMANDS & CFG_CMD_MII)
+#include <miiphy.h>
+#endif
+
/* Ethernet Transmit and Receive Buffers */
#define DBUF_LENGTH 1520
#define PKT_MAXBUF_SIZE 1518
(volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
int i;
- next_tx = 0;
- next_rx = 0;
+ next_tx = TX_GET_DMA_BUFFER(fifo_tx[0].addr);
+ next_rx = RX_GET_DMA_BUFFER(fifo_rx[0].addr);
/* We have to enable clocks before releasing reset */
*macen = MAC_EN_CLOCK_ENABLE;
/* Put mac addr in little endian */
#define ea eth_get_dev()->enetaddr
- *mac_addr_high = (ea[5] << 8) | (ea[4] ) ;
- *mac_addr_low = (ea[3] << 24) | (ea[2] << 16) |
- (ea[1] << 8) | (ea[0] ) ;
+ *mac_addr_high = (ea[5] << 8) | (ea[4] ) ;
+ *mac_addr_low = (ea[3] << 24) | (ea[2] << 16) |
+ (ea[1] << 8) | (ea[0] ) ;
#undef ea
*mac_mcast_low = 0;
*mac_mcast_high = 0;
eth_register(dev);
+#if (CONFIG_COMMANDS & CFG_CMD_MII)
+ miiphy_register(dev->name,
+ au1x00_miiphy_read, au1x00_miiphy_write);
+#endif
+
return 1;
}
+#if (CONFIG_COMMANDS & CFG_CMD_MII)
+int au1x00_miiphy_read(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short * value)
+{
+ volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
+ volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
+ u32 mii_control;
+ unsigned int timedout = 20;
+
+ while (*mii_control_reg & MAC_MII_BUSY) {
+ udelay(1000);
+ if (--timedout == 0) {
+ printf("au1x00_eth: miiphy_read busy timeout!!\n");
+ return -1;
+ }
+ }
+
+ mii_control = MAC_SET_MII_SELECT_REG(reg) |
+ MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
+
+ *mii_control_reg = mii_control;
+
+ timedout = 20;
+ while (*mii_control_reg & MAC_MII_BUSY) {
+ udelay(1000);
+ if (--timedout == 0) {
+ printf("au1x00_eth: miiphy_read busy timeout!!\n");
+ return -1;
+ }
+ }
+ *value = *mii_data_reg;
+ return 0;
+}
+
+int au1x00_miiphy_write(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value)
+{
+ volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
+ volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
+ u32 mii_control;
+ unsigned int timedout = 20;
+
+ while (*mii_control_reg & MAC_MII_BUSY) {
+ udelay(1000);
+ if (--timedout == 0) {
+ printf("au1x00_eth: miiphy_write busy timeout!!\n");
+ return;
+ }
+ }
+
+ mii_control = MAC_SET_MII_SELECT_REG(reg) |
+ MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
+
+ *mii_data_reg = value;
+ *mii_control_reg = mii_control;
+ return 0;
+}
+#endif /* CONFIG_COMMANDS & CFG_CMD_MII */
+
#endif /* CONFIG_AU1X00 */
{
volatile u32 *uart_clk = (volatile u32*)(UART0_ADDR+UART_CLK);
volatile u32 *uart_lcr = (volatile u32*)(UART0_ADDR+UART_LCR);
+ volatile u32 *sys_powerctrl = (u32 *)SYS_POWERCTRL;
+ int sd;
+ int divisorx2;
- /* Set baudrate - FIXME for bus speeds != CPU/2 */
- *uart_clk = ((CFG_HZ/(CONFIG_BAUDRATE * 64)));
+ /* sd is system clock divisor */
+ /* see section 10.4.5 in au1550 datasheet */
+ sd = (*sys_powerctrl & 0x03) + 2;
+
+ /* calulate 2x baudrate and round */
+ divisorx2 = ((CFG_HZ/(sd * 16 * CONFIG_BAUDRATE)));
+
+ if (divisorx2 & 0x01)
+ divisorx2 = divisorx2 + 1;
+
+ *uart_clk = divisorx2 / 2;
/* Set parity, stop bits and word length to 8N1 */
*uart_lcr = UART_LCR_WLEN8;
--- /dev/null
+/*
+ * URB OHCI HCD (Host Controller Driver) for USB on the AU1x00.
+ *
+ * (C) Copyright 2003
+ * Gary Jennejohn, DENX Software Engineering <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Note: Part of this code has been derived from linux
+ *
+ */
+/*
+ * IMPORTANT NOTES
+ * 1 - you MUST define LITTLEENDIAN in the configuration file for the
+ * board or this driver will NOT work!
+ * 2 - this driver is intended for use with USB Mass Storage Devices
+ * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
+ */
+
+#include <config.h>
+
+#if defined(CONFIG_AU1X00) && defined(CONFIG_USB_OHCI)
+
+/* #include <pci.h> no PCI on the AU1x00 */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/au1x00.h>
+#include <usb.h>
+#include "au1x00_usb_ohci.h"
+
+#define OHCI_USE_NPS /* force NoPowerSwitching mode */
+#define OHCI_VERBOSE_DEBUG /* not always helpful */
+#define OHCI_FILL_TRACE
+
+#define USBH_ENABLE_BE (1<<0)
+#define USBH_ENABLE_C (1<<1)
+#define USBH_ENABLE_E (1<<2)
+#define USBH_ENABLE_CE (1<<3)
+#define USBH_ENABLE_RD (1<<4)
+
+#ifdef LITTLEENDIAN
+#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C)
+#else
+#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C | USBH_ENABLE_BE)
+#endif
+
+
+/* For initializing controller (mask in an HCFS mode too) */
+#define OHCI_CONTROL_INIT \
+ (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
+
+#undef readl
+#undef writel
+
+#define readl(a) au_readl((long)(a))
+#define writel(v,a) au_writel((v),(int)(a))
+
+#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
+
+#define DEBUG
+#ifdef DEBUG
+#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
+#else
+#define dbg(format, arg...) do {} while(0)
+#endif /* DEBUG */
+#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
+#define SHOW_INFO
+#ifdef SHOW_INFO
+#define info(format, arg...) printf("INFO: " format "\n", ## arg)
+#else
+#define info(format, arg...) do {} while(0)
+#endif
+
+#define m16_swap(x) swap_16(x)
+#define m32_swap(x) swap_32(x)
+
+/* global ohci_t */
+static ohci_t gohci;
+/* this must be aligned to a 256 byte boundary */
+struct ohci_hcca ghcca[1];
+/* a pointer to the aligned storage */
+struct ohci_hcca *phcca;
+/* this allocates EDs for all possible endpoints */
+struct ohci_device ohci_dev;
+/* urb_priv */
+urb_priv_t urb_priv;
+/* RHSC flag */
+int got_rhsc;
+/* device which was disconnected */
+struct usb_device *devgone;
+
+/*-------------------------------------------------------------------------*/
+
+/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
+ * The erratum (#4) description is incorrect. AMD's workaround waits
+ * till some bits (mostly reserved) are clear; ok for all revs.
+ */
+#define OHCI_QUIRK_AMD756 0xabcd
+#define read_roothub(hc, register, mask) ({ \
+ u32 temp = readl (&hc->regs->roothub.register); \
+ if (hc->flags & OHCI_QUIRK_AMD756) \
+ while (temp & mask) \
+ temp = readl (&hc->regs->roothub.register); \
+ temp; })
+
+static u32 roothub_a (struct ohci *hc)
+ { return read_roothub (hc, a, 0xfc0fe000); }
+static inline u32 roothub_b (struct ohci *hc)
+ { return readl (&hc->regs->roothub.b); }
+static inline u32 roothub_status (struct ohci *hc)
+ { return readl (&hc->regs->roothub.status); }
+static u32 roothub_portstatus (struct ohci *hc, int i)
+ { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
+
+
+/* forward declaration */
+static int hc_interrupt (void);
+static void
+td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
+ int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
+
+/*-------------------------------------------------------------------------*
+ * URB support functions
+ *-------------------------------------------------------------------------*/
+
+/* free HCD-private data associated with this URB */
+
+static void urb_free_priv (urb_priv_t * urb)
+{
+ int i;
+ int last;
+ struct td * td;
+
+ last = urb->length - 1;
+ if (last >= 0) {
+ for (i = 0; i <= last; i++) {
+ td = urb->td[i];
+ if (td) {
+ td->usb_dev = NULL;
+ urb->td[i] = NULL;
+ }
+ }
+ }
+}
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef DEBUG
+static int sohci_get_current_frame_number (struct usb_device * dev);
+
+/* debug| print the main components of an URB
+ * small: 0) header + data packets 1) just header */
+
+static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
+ int transfer_len, struct devrequest * setup, char * str, int small)
+{
+ urb_priv_t * purb = &urb_priv;
+
+ dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
+ str,
+ sohci_get_current_frame_number (dev),
+ usb_pipedevice (pipe),
+ usb_pipeendpoint (pipe),
+ usb_pipeout (pipe)? 'O': 'I',
+ usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
+ (usb_pipecontrol (pipe)? "CTRL": "BULK"),
+ purb->actual_length,
+ transfer_len, dev->status);
+#ifdef OHCI_VERBOSE_DEBUG
+ if (!small) {
+ int i, len;
+
+ if (usb_pipecontrol (pipe)) {
+ printf (__FILE__ ": cmd(8):");
+ for (i = 0; i < 8 ; i++)
+ printf (" %02x", ((__u8 *) setup) [i]);
+ printf ("\n");
+ }
+ if (transfer_len > 0 && buffer) {
+ printf (__FILE__ ": data(%d/%d):",
+ purb->actual_length,
+ transfer_len);
+ len = usb_pipeout (pipe)?
+ transfer_len: purb->actual_length;
+ for (i = 0; i < 16 && i < len; i++)
+ printf (" %02x", ((__u8 *) buffer) [i]);
+ printf ("%s\n", i < len? "...": "");
+ }
+ }
+#endif
+}
+
+/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
+void ep_print_int_eds (ohci_t *ohci, char * str) {
+ int i, j;
+ __u32 * ed_p;
+ for (i= 0; i < 32; i++) {
+ j = 5;
+ ed_p = &(ohci->hcca->int_table [i]);
+ if (*ed_p == 0)
+ continue;
+ printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
+ while (*ed_p != 0 && j--) {
+ ed_t *ed = (ed_t *)m32_swap(ed_p);
+ printf (" ed: %4x;", ed->hwINFO);
+ ed_p = &ed->hwNextED;
+ }
+ printf ("\n");
+ }
+}
+
+static void ohci_dump_intr_mask (char *label, __u32 mask)
+{
+ dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
+ label,
+ mask,
+ (mask & OHCI_INTR_MIE) ? " MIE" : "",
+ (mask & OHCI_INTR_OC) ? " OC" : "",
+ (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
+ (mask & OHCI_INTR_FNO) ? " FNO" : "",
+ (mask & OHCI_INTR_UE) ? " UE" : "",
+ (mask & OHCI_INTR_RD) ? " RD" : "",
+ (mask & OHCI_INTR_SF) ? " SF" : "",
+ (mask & OHCI_INTR_WDH) ? " WDH" : "",
+ (mask & OHCI_INTR_SO) ? " SO" : ""
+ );
+}
+
+static void maybe_print_eds (char *label, __u32 value)
+{
+ ed_t *edp = (ed_t *)value;
+
+ if (value) {
+ dbg ("%s %08x", label, value);
+ dbg ("%08x", edp->hwINFO);
+ dbg ("%08x", edp->hwTailP);
+ dbg ("%08x", edp->hwHeadP);
+ dbg ("%08x", edp->hwNextED);
+ }
+}
+
+static char * hcfs2string (int state)
+{
+ switch (state) {
+ case OHCI_USB_RESET: return "reset";
+ case OHCI_USB_RESUME: return "resume";
+ case OHCI_USB_OPER: return "operational";
+ case OHCI_USB_SUSPEND: return "suspend";
+ }
+ return "?";
+}
+
+/* dump control and status registers */
+static void ohci_dump_status (ohci_t *controller)
+{
+ struct ohci_regs *regs = controller->regs;
+ __u32 temp;
+
+ temp = readl (®s->revision) & 0xff;
+ if (temp != 0x10)
+ dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
+
+ temp = readl (®s->control);
+ dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
+ (temp & OHCI_CTRL_RWE) ? " RWE" : "",
+ (temp & OHCI_CTRL_RWC) ? " RWC" : "",
+ (temp & OHCI_CTRL_IR) ? " IR" : "",
+ hcfs2string (temp & OHCI_CTRL_HCFS),
+ (temp & OHCI_CTRL_BLE) ? " BLE" : "",
+ (temp & OHCI_CTRL_CLE) ? " CLE" : "",
+ (temp & OHCI_CTRL_IE) ? " IE" : "",
+ (temp & OHCI_CTRL_PLE) ? " PLE" : "",
+ temp & OHCI_CTRL_CBSR
+ );
+
+ temp = readl (®s->cmdstatus);
+ dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
+ (temp & OHCI_SOC) >> 16,
+ (temp & OHCI_OCR) ? " OCR" : "",
+ (temp & OHCI_BLF) ? " BLF" : "",
+ (temp & OHCI_CLF) ? " CLF" : "",
+ (temp & OHCI_HCR) ? " HCR" : ""
+ );
+
+ ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus));
+ ohci_dump_intr_mask ("intrenable", readl (®s->intrenable));
+
+ maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent));
+
+ maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead));
+ maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent));
+
+ maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead));
+ maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent));
+
+ maybe_print_eds ("donehead", readl (®s->donehead));
+}
+
+static void ohci_dump_roothub (ohci_t *controller, int verbose)
+{
+ __u32 temp, ndp, i;
+
+ temp = roothub_a (controller);
+ ndp = (temp & RH_A_NDP);
+
+ if (verbose) {
+ dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
+ ((temp & RH_A_POTPGT) >> 24) & 0xff,
+ (temp & RH_A_NOCP) ? " NOCP" : "",
+ (temp & RH_A_OCPM) ? " OCPM" : "",
+ (temp & RH_A_DT) ? " DT" : "",
+ (temp & RH_A_NPS) ? " NPS" : "",
+ (temp & RH_A_PSM) ? " PSM" : "",
+ ndp
+ );
+ temp = roothub_b (controller);
+ dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
+ temp,
+ (temp & RH_B_PPCM) >> 16,
+ (temp & RH_B_DR)
+ );
+ temp = roothub_status (controller);
+ dbg ("roothub.status: %08x%s%s%s%s%s%s",
+ temp,
+ (temp & RH_HS_CRWE) ? " CRWE" : "",
+ (temp & RH_HS_OCIC) ? " OCIC" : "",
+ (temp & RH_HS_LPSC) ? " LPSC" : "",
+ (temp & RH_HS_DRWE) ? " DRWE" : "",
+ (temp & RH_HS_OCI) ? " OCI" : "",
+ (temp & RH_HS_LPS) ? " LPS" : ""
+ );
+ }
+
+ for (i = 0; i < ndp; i++) {
+ temp = roothub_portstatus (controller, i);
+ dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
+ i,
+ temp,
+ (temp & RH_PS_PRSC) ? " PRSC" : "",
+ (temp & RH_PS_OCIC) ? " OCIC" : "",
+ (temp & RH_PS_PSSC) ? " PSSC" : "",
+ (temp & RH_PS_PESC) ? " PESC" : "",
+ (temp & RH_PS_CSC) ? " CSC" : "",
+
+ (temp & RH_PS_LSDA) ? " LSDA" : "",
+ (temp & RH_PS_PPS) ? " PPS" : "",
+ (temp & RH_PS_PRS) ? " PRS" : "",
+ (temp & RH_PS_POCI) ? " POCI" : "",
+ (temp & RH_PS_PSS) ? " PSS" : "",
+
+ (temp & RH_PS_PES) ? " PES" : "",
+ (temp & RH_PS_CCS) ? " CCS" : ""
+ );
+ }
+}
+
+static void ohci_dump (ohci_t *controller, int verbose)
+{
+ dbg ("OHCI controller usb-%s state", controller->slot_name);
+
+ /* dumps some of the state we know about */
+ ohci_dump_status (controller);
+ if (verbose)
+ ep_print_int_eds (controller, "hcca");
+ dbg ("hcca frame #%04x", controller->hcca->frame_no);
+ ohci_dump_roothub (controller, 1);
+}
+
+
+#endif /* DEBUG */
+
+/*-------------------------------------------------------------------------*
+ * Interface functions (URB)
+ *-------------------------------------------------------------------------*/
+
+/* get a transfer request */
+
+int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, struct devrequest *setup, int interval)
+{
+ ohci_t *ohci;
+ ed_t * ed;
+ urb_priv_t *purb_priv;
+ int i, size = 0;
+
+ ohci = &gohci;
+
+ /* when controller's hung, permit only roothub cleanup attempts
+ * such as powering down ports */
+ if (ohci->disabled) {
+ err("sohci_submit_job: EPIPE");
+ return -1;
+ }
+
+ /* every endpoint has a ed, locate and fill it */
+ if (!(ed = ep_add_ed (dev, pipe))) {
+ err("sohci_submit_job: ENOMEM");
+ return -1;
+ }
+
+ /* for the private part of the URB we need the number of TDs (size) */
+ switch (usb_pipetype (pipe)) {
+ case PIPE_BULK: /* one TD for every 4096 Byte */
+ size = (transfer_len - 1) / 4096 + 1;
+ break;
+ case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
+ size = (transfer_len == 0)? 2:
+ (transfer_len - 1) / 4096 + 3;
+ break;
+ }
+
+ if (size >= (N_URB_TD - 1)) {
+ err("need %d TDs, only have %d", size, N_URB_TD);
+ return -1;
+ }
+ purb_priv = &urb_priv;
+ purb_priv->pipe = pipe;
+
+ /* fill the private part of the URB */
+ purb_priv->length = size;
+ purb_priv->ed = ed;
+ purb_priv->actual_length = 0;
+
+ /* allocate the TDs */
+ /* note that td[0] was allocated in ep_add_ed */
+ for (i = 0; i < size; i++) {
+ purb_priv->td[i] = td_alloc (dev);
+ if (!purb_priv->td[i]) {
+ purb_priv->length = i;
+ urb_free_priv (purb_priv);
+ err("sohci_submit_job: ENOMEM");
+ return -1;
+ }
+ }
+
+ if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
+ urb_free_priv (purb_priv);
+ err("sohci_submit_job: EINVAL");
+ return -1;
+ }
+
+ /* link the ed into a chain if is not already */
+ if (ed->state != ED_OPER)
+ ep_link (ohci, ed);
+
+ /* fill the TDs and link it to the ed */
+ td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
+
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef DEBUG
+/* tell us the current USB frame number */
+
+static int sohci_get_current_frame_number (struct usb_device *usb_dev)
+{
+ ohci_t *ohci = &gohci;
+
+ return m16_swap (ohci->hcca->frame_no);
+}
+#endif
+
+/*-------------------------------------------------------------------------*
+ * ED handling functions
+ *-------------------------------------------------------------------------*/
+
+/* link an ed into one of the HC chains */
+
+static int ep_link (ohci_t *ohci, ed_t *edi)
+{
+ volatile ed_t *ed = edi;
+
+ ed->state = ED_OPER;
+
+ switch (ed->type) {
+ case PIPE_CONTROL:
+ ed->hwNextED = 0;
+ if (ohci->ed_controltail == NULL) {
+ writel ((long)ed, &ohci->regs->ed_controlhead);
+ } else {
+ ohci->ed_controltail->hwNextED = m32_swap (ed);
+ }
+ ed->ed_prev = ohci->ed_controltail;
+ if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
+ !ohci->ed_rm_list[1] && !ohci->sleeping) {
+ ohci->hc_control |= OHCI_CTRL_CLE;
+ writel (ohci->hc_control, &ohci->regs->control);
+ }
+ ohci->ed_controltail = edi;
+ break;
+
+ case PIPE_BULK:
+ ed->hwNextED = 0;
+ if (ohci->ed_bulktail == NULL) {
+ writel ((long)ed, &ohci->regs->ed_bulkhead);
+ } else {
+ ohci->ed_bulktail->hwNextED = m32_swap (ed);
+ }
+ ed->ed_prev = ohci->ed_bulktail;
+ if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
+ !ohci->ed_rm_list[1] && !ohci->sleeping) {
+ ohci->hc_control |= OHCI_CTRL_BLE;
+ writel (ohci->hc_control, &ohci->regs->control);
+ }
+ ohci->ed_bulktail = edi;
+ break;
+ }
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* unlink an ed from one of the HC chains.
+ * just the link to the ed is unlinked.
+ * the link from the ed still points to another operational ed or 0
+ * so the HC can eventually finish the processing of the unlinked ed */
+
+static int ep_unlink (ohci_t *ohci, ed_t *ed)
+{
+ ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
+
+ switch (ed->type) {
+ case PIPE_CONTROL:
+ if (ed->ed_prev == NULL) {
+ if (!ed->hwNextED) {
+ ohci->hc_control &= ~OHCI_CTRL_CLE;
+ writel (ohci->hc_control, &ohci->regs->control);
+ }
+ writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
+ } else {
+ ed->ed_prev->hwNextED = ed->hwNextED;
+ }
+ if (ohci->ed_controltail == ed) {
+ ohci->ed_controltail = ed->ed_prev;
+ } else {
+ ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
+ }
+ break;
+
+ case PIPE_BULK:
+ if (ed->ed_prev == NULL) {
+ if (!ed->hwNextED) {
+ ohci->hc_control &= ~OHCI_CTRL_BLE;
+ writel (ohci->hc_control, &ohci->regs->control);
+ }
+ writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
+ } else {
+ ed->ed_prev->hwNextED = ed->hwNextED;
+ }
+ if (ohci->ed_bulktail == ed) {
+ ohci->ed_bulktail = ed->ed_prev;
+ } else {
+ ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
+ }
+ break;
+ }
+ ed->state = ED_UNLINK;
+ return 0;
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+/* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
+ * but the USB stack is a little bit stateless so we do it at every transaction
+ * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
+ * in all other cases the state is left unchanged
+ * the ed info fields are setted anyway even though most of them should not change */
+
+static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
+{
+ td_t *td;
+ ed_t *ed_ret;
+ volatile ed_t *ed;
+
+ ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
+ (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
+
+ if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
+ err("ep_add_ed: pending delete");
+ /* pending delete request */
+ return NULL;
+ }
+
+ if (ed->state == ED_NEW) {
+ ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
+ /* dummy td; end of td list for ed */
+ td = td_alloc (usb_dev);
+ ed->hwTailP = m32_swap (td);
+ ed->hwHeadP = ed->hwTailP;
+ ed->state = ED_UNLINK;
+ ed->type = usb_pipetype (pipe);
+ ohci_dev.ed_cnt++;
+ }
+
+ ed->hwINFO = m32_swap (usb_pipedevice (pipe)
+ | usb_pipeendpoint (pipe) << 7
+ | (usb_pipeisoc (pipe)? 0x8000: 0)
+ | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
+ | usb_pipeslow (pipe) << 13
+ | usb_maxpacket (usb_dev, pipe) << 16);
+
+ return ed_ret;
+}
+
+/*-------------------------------------------------------------------------*
+ * TD handling functions
+ *-------------------------------------------------------------------------*/
+
+/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
+
+static void td_fill (ohci_t *ohci, unsigned int info,
+ void *data, int len,
+ struct usb_device *dev, int index, urb_priv_t *urb_priv)
+{
+ volatile td_t *td, *td_pt;
+#ifdef OHCI_FILL_TRACE
+ int i;
+#endif
+
+ if (index > urb_priv->length) {
+ err("index > length");
+ return;
+ }
+ /* use this td as the next dummy */
+ td_pt = urb_priv->td [index];
+ td_pt->hwNextTD = 0;
+
+ /* fill the old dummy TD */
+ td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
+
+ td->ed = urb_priv->ed;
+ td->next_dl_td = NULL;
+ td->index = index;
+ td->data = (__u32)data;
+#ifdef OHCI_FILL_TRACE
+ if (1 || ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe))) {
+ for (i = 0; i < len; i++)
+ printf("td->data[%d] %#2x\n",i, ((unsigned char *)(td->data+0x80000000))[i]);
+ }
+#endif
+ if (!len)
+ data = 0;
+
+ td->hwINFO = m32_swap (info);
+ td->hwCBP = m32_swap (data);
+ if (data)
+ td->hwBE = m32_swap (data + len - 1);
+ else
+ td->hwBE = 0;
+ td->hwNextTD = m32_swap (td_pt);
+ td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000);
+
+ /* append to queue */
+ td->ed->hwTailP = td->hwNextTD;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* prepare all TDs of a transfer */
+
+#define kseg_to_phys(x) ((void *)((__u32)(x) - 0x80000000))
+
+static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
+{
+ ohci_t *ohci = &gohci;
+ int data_len = transfer_len;
+ void *data;
+ int cnt = 0;
+ __u32 info = 0;
+ unsigned int toggle = 0;
+
+ /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
+ if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
+ toggle = TD_T_TOGGLE;
+ } else {
+ toggle = TD_T_DATA0;
+ usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
+ }
+ urb->td_cnt = 0;
+ if (data_len)
+ data = kseg_to_phys(buffer);
+ else
+ data = 0;
+
+ switch (usb_pipetype (pipe)) {
+ case PIPE_BULK:
+ info = usb_pipeout (pipe)?
+ TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
+ while(data_len > 4096) {
+ td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
+ data += 4096; data_len -= 4096; cnt++;
+ }
+ info = usb_pipeout (pipe)?
+ TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
+ td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
+ cnt++;
+
+ if (!ohci->sleeping)
+ writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
+ break;
+
+ case PIPE_CONTROL:
+ info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
+ td_fill (ohci, info, kseg_to_phys(setup), 8, dev, cnt++, urb);
+ if (data_len > 0) {
+ info = usb_pipeout (pipe)?
+ TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
+ /* NOTE: mishandles transfers >8K, some >4K */
+ td_fill (ohci, info, data, data_len, dev, cnt++, urb);
+ }
+ info = usb_pipeout (pipe)?
+ TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
+ td_fill (ohci, info, data, 0, dev, cnt++, urb);
+ if (!ohci->sleeping)
+ writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
+ break;
+ }
+ if (urb->length != cnt)
+ dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
+}
+
+/*-------------------------------------------------------------------------*
+ * Done List handling functions
+ *-------------------------------------------------------------------------*/
+
+
+/* calculate the transfer length and update the urb */
+
+static void dl_transfer_length(td_t * td)
+{
+ __u32 tdINFO, tdBE, tdCBP;
+ urb_priv_t *lurb_priv = &urb_priv;
+
+ tdINFO = m32_swap (td->hwINFO);
+ tdBE = m32_swap (td->hwBE);
+ tdCBP = m32_swap (td->hwCBP);
+
+
+ if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
+ ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
+ if (tdBE != 0) {
+ if (td->hwCBP == 0)
+ lurb_priv->actual_length += tdBE - td->data + 1;
+ else
+ lurb_priv->actual_length += tdCBP - td->data;
+ }
+ }
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* replies to the request have to be on a FIFO basis so
+ * we reverse the reversed done-list */
+
+static td_t * dl_reverse_done_list (ohci_t *ohci)
+{
+ __u32 td_list_hc;
+ td_t *td_rev = NULL;
+ td_t *td_list = NULL;
+ urb_priv_t *lurb_priv = NULL;
+
+ td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
+ ohci->hcca->done_head = 0;
+
+ while (td_list_hc) {
+ td_list = (td_t *)td_list_hc;
+
+ if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
+ lurb_priv = &urb_priv;
+ dbg(" USB-error/status: %x : %p",
+ TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
+ if (td_list->ed->hwHeadP & m32_swap (0x1)) {
+ if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
+ td_list->ed->hwHeadP =
+ (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
+ (td_list->ed->hwHeadP & m32_swap (0x2));
+ lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
+ } else
+ td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
+ }
+ }
+
+ td_list->next_dl_td = td_rev;
+ td_rev = td_list;
+ td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
+ }
+ return td_list;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* td done list */
+static int dl_done_list (ohci_t *ohci, td_t *td_list)
+{
+ td_t *td_list_next = NULL;
+ ed_t *ed;
+ int cc = 0;
+ int stat = 0;
+ /* urb_t *urb; */
+ urb_priv_t *lurb_priv;
+ __u32 tdINFO, edHeadP, edTailP;
+
+ while (td_list) {
+ td_list_next = td_list->next_dl_td;
+
+ lurb_priv = &urb_priv;
+ tdINFO = m32_swap (td_list->hwINFO);
+
+ ed = td_list->ed;
+
+ dl_transfer_length(td_list);
+
+ /* error code of transfer */
+ cc = TD_CC_GET (tdINFO);
+ if (cc != 0) {
+ dbg("ConditionCode %#x", cc);
+ stat = cc_to_error[cc];
+ }
+
+ if (ed->state != ED_NEW) {
+ edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
+ edTailP = m32_swap (ed->hwTailP);
+
+ /* unlink eds if they are not busy */
+ if ((edHeadP == edTailP) && (ed->state == ED_OPER))
+ ep_unlink (ohci, ed);
+ }
+
+ td_list = td_list_next;
+ }
+ return stat;
+}
+
+/*-------------------------------------------------------------------------*
+ * Virtual Root Hub
+ *-------------------------------------------------------------------------*/
+
+/* Device descriptor */
+static __u8 root_hub_dev_des[] =
+{
+ 0x12, /* __u8 bLength; */
+ 0x01, /* __u8 bDescriptorType; Device */
+ 0x10, /* __u16 bcdUSB; v1.1 */
+ 0x01,
+ 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
+ 0x00, /* __u8 bDeviceSubClass; */
+ 0x00, /* __u8 bDeviceProtocol; */
+ 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
+ 0x00, /* __u16 idVendor; */
+ 0x00,
+ 0x00, /* __u16 idProduct; */
+ 0x00,
+ 0x00, /* __u16 bcdDevice; */
+ 0x00,
+ 0x00, /* __u8 iManufacturer; */
+ 0x01, /* __u8 iProduct; */
+ 0x00, /* __u8 iSerialNumber; */
+ 0x01 /* __u8 bNumConfigurations; */
+};
+
+
+/* Configuration descriptor */
+static __u8 root_hub_config_des[] =
+{
+ 0x09, /* __u8 bLength; */
+ 0x02, /* __u8 bDescriptorType; Configuration */
+ 0x19, /* __u16 wTotalLength; */
+ 0x00,
+ 0x01, /* __u8 bNumInterfaces; */
+ 0x01, /* __u8 bConfigurationValue; */
+ 0x00, /* __u8 iConfiguration; */
+ 0x40, /* __u8 bmAttributes;
+ Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
+ 0x00, /* __u8 MaxPower; */
+
+ /* interface */
+ 0x09, /* __u8 if_bLength; */
+ 0x04, /* __u8 if_bDescriptorType; Interface */
+ 0x00, /* __u8 if_bInterfaceNumber; */
+ 0x00, /* __u8 if_bAlternateSetting; */
+ 0x01, /* __u8 if_bNumEndpoints; */
+ 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
+ 0x00, /* __u8 if_bInterfaceSubClass; */
+ 0x00, /* __u8 if_bInterfaceProtocol; */
+ 0x00, /* __u8 if_iInterface; */
+
+ /* endpoint */
+ 0x07, /* __u8 ep_bLength; */
+ 0x05, /* __u8 ep_bDescriptorType; Endpoint */
+ 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
+ 0x03, /* __u8 ep_bmAttributes; Interrupt */
+ 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
+ 0x00,
+ 0xff /* __u8 ep_bInterval; 255 ms */
+};
+
+static unsigned char root_hub_str_index0[] =
+{
+ 0x04, /* __u8 bLength; */
+ 0x03, /* __u8 bDescriptorType; String-descriptor */
+ 0x09, /* __u8 lang ID */
+ 0x04, /* __u8 lang ID */
+};
+
+static unsigned char root_hub_str_index1[] =
+{
+ 28, /* __u8 bLength; */
+ 0x03, /* __u8 bDescriptorType; String-descriptor */
+ 'O', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'H', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'C', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'I', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ ' ', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'R', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'o', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'o', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 't', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ ' ', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'H', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'u', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'b', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+};
+
+/* Hub class-specific descriptor is constructed dynamically */
+
+
+/*-------------------------------------------------------------------------*/
+
+#define OK(x) len = (x); break
+#ifdef DEBUG
+#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
+#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
+#else
+#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
+#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
+#endif
+#define RD_RH_STAT roothub_status(&gohci)
+#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
+
+/* request to virtual root hub */
+
+int rh_check_port_status(ohci_t *controller)
+{
+ __u32 temp, ndp, i;
+ int res;
+
+ res = -1;
+ temp = roothub_a (controller);
+ ndp = (temp & RH_A_NDP);
+ for (i = 0; i < ndp; i++) {
+ temp = roothub_portstatus (controller, i);
+ /* check for a device disconnect */
+ if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
+ (RH_PS_PESC | RH_PS_CSC)) &&
+ ((temp & RH_PS_CCS) == 0)) {
+ res = i;
+ break;
+ }
+ }
+ return res;
+}
+
+static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
+ void *buffer, int transfer_len, struct devrequest *cmd)
+{
+ void * data = buffer;
+ int leni = transfer_len;
+ int len = 0;
+ int stat = 0;
+ __u32 datab[4];
+ __u8 *data_buf = (__u8 *)datab;
+ __u16 bmRType_bReq;
+ __u16 wValue;
+ __u16 wIndex;
+ __u16 wLength;
+
+#ifdef DEBUG
+urb_priv.actual_length = 0;
+pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
+#else
+ wait_ms(1);
+#endif
+ if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
+ info("Root-Hub submit IRQ: NOT implemented");
+ return 0;
+ }
+
+ bmRType_bReq = cmd->requesttype | (cmd->request << 8);
+ wValue = m16_swap (cmd->value);
+ wIndex = m16_swap (cmd->index);
+ wLength = m16_swap (cmd->length);
+
+ info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
+ dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
+
+ switch (bmRType_bReq) {
+ /* Request Destination:
+ without flags: Device,
+ RH_INTERFACE: interface,
+ RH_ENDPOINT: endpoint,
+ RH_CLASS means HUB here,
+ RH_OTHER | RH_CLASS almost ever means HUB_PORT here
+ */
+
+ case RH_GET_STATUS:
+ *(__u16 *) data_buf = m16_swap (1); OK (2);
+ case RH_GET_STATUS | RH_INTERFACE:
+ *(__u16 *) data_buf = m16_swap (0); OK (2);
+ case RH_GET_STATUS | RH_ENDPOINT:
+ *(__u16 *) data_buf = m16_swap (0); OK (2);
+ case RH_GET_STATUS | RH_CLASS:
+ *(__u32 *) data_buf = m32_swap (
+ RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
+ OK (4);
+ case RH_GET_STATUS | RH_OTHER | RH_CLASS:
+ *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
+
+ case RH_CLEAR_FEATURE | RH_ENDPOINT:
+ switch (wValue) {
+ case (RH_ENDPOINT_STALL): OK (0);
+ }
+ break;
+
+ case RH_CLEAR_FEATURE | RH_CLASS:
+ switch (wValue) {
+ case RH_C_HUB_LOCAL_POWER:
+ OK(0);
+ case (RH_C_HUB_OVER_CURRENT):
+ WR_RH_STAT(RH_HS_OCIC); OK (0);
+ }
+ break;
+
+ case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
+ switch (wValue) {
+ case (RH_PORT_ENABLE):
+ WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
+ case (RH_PORT_SUSPEND):
+ WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
+ case (RH_PORT_POWER):
+ WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
+ case (RH_C_PORT_CONNECTION):
+ WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
+ case (RH_C_PORT_ENABLE):
+ WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
+ case (RH_C_PORT_SUSPEND):
+ WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
+ case (RH_C_PORT_OVER_CURRENT):
+ WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
+ case (RH_C_PORT_RESET):
+ WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
+ }
+ break;
+
+ case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
+ switch (wValue) {
+ case (RH_PORT_SUSPEND):
+ WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
+ case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
+ if (RD_RH_PORTSTAT & RH_PS_CCS)
+ WR_RH_PORTSTAT (RH_PS_PRS);
+ OK (0);
+ case (RH_PORT_POWER):
+ WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
+ case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
+ if (RD_RH_PORTSTAT & RH_PS_CCS)
+ WR_RH_PORTSTAT (RH_PS_PES );
+ OK (0);
+ }
+ break;
+
+ case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
+
+ case RH_GET_DESCRIPTOR:
+ switch ((wValue & 0xff00) >> 8) {
+ case (0x01): /* device descriptor */
+ len = min_t(unsigned int,
+ leni,
+ min_t(unsigned int,
+ sizeof (root_hub_dev_des),
+ wLength));
+ data_buf = root_hub_dev_des; OK(len);
+ case (0x02): /* configuration descriptor */
+ len = min_t(unsigned int,
+ leni,
+ min_t(unsigned int,
+ sizeof (root_hub_config_des),
+ wLength));
+ data_buf = root_hub_config_des; OK(len);
+ case (0x03): /* string descriptors */
+ if(wValue==0x0300) {
+ len = min_t(unsigned int,
+ leni,
+ min_t(unsigned int,
+ sizeof (root_hub_str_index0),
+ wLength));
+ data_buf = root_hub_str_index0;
+ OK(len);
+ }
+ if(wValue==0x0301) {
+ len = min_t(unsigned int,
+ leni,
+ min_t(unsigned int,
+ sizeof (root_hub_str_index1),
+ wLength));
+ data_buf = root_hub_str_index1;
+ OK(len);
+ }
+ default:
+ stat = USB_ST_STALLED;
+ }
+ break;
+
+ case RH_GET_DESCRIPTOR | RH_CLASS:
+ {
+ __u32 temp = roothub_a (&gohci);
+
+ data_buf [0] = 9; /* min length; */
+ data_buf [1] = 0x29;
+ data_buf [2] = temp & RH_A_NDP;
+ data_buf [3] = 0;
+ if (temp & RH_A_PSM) /* per-port power switching? */
+ data_buf [3] |= 0x1;
+ if (temp & RH_A_NOCP) /* no overcurrent reporting? */
+ data_buf [3] |= 0x10;
+ else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
+ data_buf [3] |= 0x8;
+
+ /* corresponds to data_buf[4-7] */
+ datab [1] = 0;
+ data_buf [5] = (temp & RH_A_POTPGT) >> 24;
+ temp = roothub_b (&gohci);
+ data_buf [7] = temp & RH_B_DR;
+ if (data_buf [2] < 7) {
+ data_buf [8] = 0xff;
+ } else {
+ data_buf [0] += 2;
+ data_buf [8] = (temp & RH_B_DR) >> 8;
+ data_buf [10] = data_buf [9] = 0xff;
+ }
+
+ len = min_t(unsigned int, leni,
+ min_t(unsigned int, data_buf [0], wLength));
+ OK (len);
+ }
+
+ case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
+
+ case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
+
+ default:
+ dbg ("unsupported root hub command");
+ stat = USB_ST_STALLED;
+ }
+
+#ifdef DEBUG
+ ohci_dump_roothub (&gohci, 1);
+#else
+ wait_ms(1);
+#endif
+
+ len = min_t(int, len, leni);
+ if (data != data_buf)
+ memcpy (data, data_buf, len);
+ dev->act_len = len;
+ dev->status = stat;
+
+#ifdef DEBUG
+ if (transfer_len)
+ urb_priv.actual_length = transfer_len;
+ pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
+#else
+ wait_ms(1);
+#endif
+
+ return stat;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* common code for handling submit messages - used for all but root hub */
+/* accesses. */
+int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, struct devrequest *setup, int interval)
+{
+ int stat = 0;
+ int maxsize = usb_maxpacket(dev, pipe);
+ int timeout;
+
+ /* device pulled? Shortcut the action. */
+ if (devgone == dev) {
+ dev->status = USB_ST_CRC_ERR;
+ return 0;
+ }
+
+#ifdef DEBUG
+ urb_priv.actual_length = 0;
+ pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
+#else
+ wait_ms(1);
+#endif
+ if (!maxsize) {
+ err("submit_common_message: pipesize for pipe %lx is zero",
+ pipe);
+ return -1;
+ }
+
+ if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
+ err("sohci_submit_job failed");
+ return -1;
+ }
+
+ wait_ms(10);
+ /* ohci_dump_status(&gohci); */
+
+ /* allow more time for a BULK device to react - some are slow */
+#define BULK_TO 5000 /* timeout in milliseconds */
+ if (usb_pipetype (pipe) == PIPE_BULK)
+ timeout = BULK_TO;
+ else
+ timeout = 100;
+
+ timeout *= 4;
+ /* wait for it to complete */
+ for (;;) {
+ /* check whether the controller is done */
+ stat = hc_interrupt();
+ if (stat < 0) {
+ stat = USB_ST_CRC_ERR;
+ break;
+ }
+ if (stat >= 0 && stat != 0xff) {
+ /* 0xff is returned for an SF-interrupt */
+ break;
+ }
+ if (--timeout) {
+ udelay(250); /* wait_ms(1); */
+ } else {
+ err("CTL:TIMEOUT ");
+ stat = USB_ST_CRC_ERR;
+ break;
+ }
+ }
+ /* we got an Root Hub Status Change interrupt */
+ if (got_rhsc) {
+#ifdef DEBUG
+ ohci_dump_roothub (&gohci, 1);
+#endif
+ got_rhsc = 0;
+ /* abuse timeout */
+ timeout = rh_check_port_status(&gohci);
+ if (timeout >= 0) {
+#if 0 /* this does nothing useful, but leave it here in case that changes */
+ /* the called routine adds 1 to the passed value */
+ usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
+#endif
+ /*
+ * XXX
+ * This is potentially dangerous because it assumes
+ * that only one device is ever plugged in!
+ */
+ devgone = dev;
+ }
+ }
+
+ dev->status = stat;
+ dev->act_len = transfer_len;
+
+#ifdef DEBUG
+ pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
+#else
+ wait_ms(1);
+#endif
+
+ /* free TDs in urb_priv */
+ urb_free_priv (&urb_priv);
+ return 0;
+}
+
+/* submit routines called from usb.c */
+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len)
+{
+ info("submit_bulk_msg");
+ return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
+}
+
+int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, struct devrequest *setup)
+{
+ int maxsize = usb_maxpacket(dev, pipe);
+
+ info("submit_control_msg");
+#ifdef DEBUG
+ urb_priv.actual_length = 0;
+ pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
+#else
+ wait_ms(1);
+#endif
+ if (!maxsize) {
+ err("submit_control_message: pipesize for pipe %lx is zero",
+ pipe);
+ return -1;
+ }
+ if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
+ gohci.rh.dev = dev;
+ /* root hub - redirect */
+ return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
+ setup);
+ }
+
+ return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
+}
+
+int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, int interval)
+{
+ info("submit_int_msg");
+ return -1;
+}
+
+/*-------------------------------------------------------------------------*
+ * HC functions
+ *-------------------------------------------------------------------------*/
+
+/* reset the HC and BUS */
+
+static int hc_reset (ohci_t *ohci)
+{
+ int timeout = 30;
+ int smm_timeout = 50; /* 0,5 sec */
+
+ if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
+ writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
+ info("USB HC TakeOver from SMM");
+ while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
+ wait_ms (10);
+ if (--smm_timeout == 0) {
+ err("USB HC TakeOver failed!");
+ return -1;
+ }
+ }
+ }
+
+ /* Disable HC interrupts */
+ writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
+
+ dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
+ ohci->slot_name,
+ readl (&ohci->regs->control));
+
+ /* Reset USB (needed by some controllers) */
+ writel (0, &ohci->regs->control);
+
+ /* HC Reset requires max 10 us delay */
+ writel (OHCI_HCR, &ohci->regs->cmdstatus);
+ while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
+ if (--timeout == 0) {
+ err("USB HC reset timed out!");
+ return -1;
+ }
+ udelay (1);
+ }
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* Start an OHCI controller, set the BUS operational
+ * enable interrupts
+ * connect the virtual root hub */
+
+static int hc_start (ohci_t * ohci)
+{
+ __u32 mask;
+ unsigned int fminterval;
+
+ ohci->disabled = 1;
+
+ /* Tell the controller where the control and bulk lists are
+ * The lists are empty now. */
+
+ writel (0, &ohci->regs->ed_controlhead);
+ writel (0, &ohci->regs->ed_bulkhead);
+
+ writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
+
+ fminterval = 0x2edf;
+ writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
+ fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
+ writel (fminterval, &ohci->regs->fminterval);
+ writel (0x628, &ohci->regs->lsthresh);
+
+ /* start controller operations */
+ ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
+ ohci->disabled = 0;
+ writel (ohci->hc_control, &ohci->regs->control);
+
+ /* disable all interrupts */
+ mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
+ OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
+ OHCI_INTR_OC | OHCI_INTR_MIE);
+ writel (mask, &ohci->regs->intrdisable);
+ /* clear all interrupts */
+ mask &= ~OHCI_INTR_MIE;
+ writel (mask, &ohci->regs->intrstatus);
+ /* Choose the interrupts we care about now - but w/o MIE */
+ mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
+ writel (mask, &ohci->regs->intrenable);
+
+#ifdef OHCI_USE_NPS
+ /* required for AMD-756 and some Mac platforms */
+ writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
+ &ohci->regs->roothub.a);
+ writel (RH_HS_LPSC, &ohci->regs->roothub.status);
+#endif /* OHCI_USE_NPS */
+
+#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
+ /* POTPGT delay is bits 24-31, in 2 ms units. */
+ mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
+
+ /* connect the virtual root hub */
+ ohci->rh.devnum = 0;
+
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* an interrupt happens */
+
+static int
+hc_interrupt (void)
+{
+ ohci_t *ohci = &gohci;
+ struct ohci_regs *regs = ohci->regs;
+ int ints;
+ int stat = -1;
+
+ if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
+ ints = OHCI_INTR_WDH;
+ } else {
+ ints = readl (®s->intrstatus);
+ }
+
+ /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
+
+ if (ints & OHCI_INTR_RHSC) {
+ got_rhsc = 1;
+ }
+
+ if (ints & OHCI_INTR_UE) {
+ ohci->disabled++;
+ err ("OHCI Unrecoverable Error, controller usb-%s disabled",
+ ohci->slot_name);
+ /* e.g. due to PCI Master/Target Abort */
+
+#ifdef DEBUG
+ ohci_dump (ohci, 1);
+#else
+ wait_ms(1);
+#endif
+ /* FIXME: be optimistic, hope that bug won't repeat often. */
+ /* Make some non-interrupt context restart the controller. */
+ /* Count and limit the retries though; either hardware or */
+ /* software errors can go forever... */
+ hc_reset (ohci);
+ return -1;
+ }
+
+ if (ints & OHCI_INTR_WDH) {
+ wait_ms(1);
+ writel (OHCI_INTR_WDH, ®s->intrdisable);
+ stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
+ writel (OHCI_INTR_WDH, ®s->intrenable);
+ }
+
+ if (ints & OHCI_INTR_SO) {
+ dbg("USB Schedule overrun\n");
+ writel (OHCI_INTR_SO, ®s->intrenable);
+ stat = -1;
+ }
+
+ /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
+ if (ints & OHCI_INTR_SF) {
+ unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
+ wait_ms(1);
+ writel (OHCI_INTR_SF, ®s->intrdisable);
+ if (ohci->ed_rm_list[frame] != NULL)
+ writel (OHCI_INTR_SF, ®s->intrenable);
+ stat = 0xff;
+ }
+
+ writel (ints, ®s->intrstatus);
+ return stat;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*-------------------------------------------------------------------------*/
+
+/* De-allocate all resources.. */
+
+static void hc_release_ohci (ohci_t *ohci)
+{
+ dbg ("USB HC release ohci usb-%s", ohci->slot_name);
+
+ if (!ohci->disabled)
+ hc_reset (ohci);
+}
+
+/*-------------------------------------------------------------------------*/
+
+#define __read_32bit_c0_register(source, sel) \
+({ int __res; \
+ if (sel == 0) \
+ __asm__ __volatile__( \
+ "mfc0\t%0, " #source "\n\t" \
+ : "=r" (__res)); \
+ else \
+ __asm__ __volatile__( \
+ ".set\tmips32\n\t" \
+ "mfc0\t%0, " #source ", " #sel "\n\t" \
+ ".set\tmips0\n\t" \
+ : "=r" (__res)); \
+ __res; \
+})
+
+#define read_c0_prid() __read_32bit_c0_register($15, 0)
+
+/*
+ * low level initalisation routine, called from usb.c
+ */
+static char ohci_inited = 0;
+
+int usb_lowlevel_init(void)
+{
+ u32 pin_func;
+ u32 sys_freqctrl, sys_clksrc;
+ u32 prid = read_c0_prid();
+
+ dbg("in usb_lowlevel_init\n");
+
+ /* zero and disable FREQ2 */
+ sys_freqctrl = au_readl(SYS_FREQCTRL0);
+ sys_freqctrl &= ~0xFFF00000;
+ au_writel(sys_freqctrl, SYS_FREQCTRL0);
+
+ /* zero and disable USBH/USBD clocks */
+ sys_clksrc = au_readl(SYS_CLKSRC);
+ sys_clksrc &= ~0x00007FE0;
+ au_writel(sys_clksrc, SYS_CLKSRC);
+
+ sys_freqctrl = au_readl(SYS_FREQCTRL0);
+ sys_freqctrl &= ~0xFFF00000;
+
+ sys_clksrc = au_readl(SYS_CLKSRC);
+ sys_clksrc &= ~0x00007FE0;
+
+ switch (prid & 0x000000FF) {
+ case 0x00: /* DA */
+ case 0x01: /* HA */
+ case 0x02: /* HB */
+ /* CPU core freq to 48MHz to slow it way down... */
+ au_writel(4, SYS_CPUPLL);
+
+ /*
+ * Setup 48MHz FREQ2 from CPUPLL for USB Host
+ */
+ /* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */
+ sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20));
+ au_writel(sys_freqctrl, SYS_FREQCTRL0);
+
+ /* CPU core freq to 384MHz */
+ au_writel(0x20, SYS_CPUPLL);
+
+ printf("Au1000: 48MHz OHCI workaround enabled\n");
+ break;
+
+ default: /* HC and newer */
+ /* FREQ2 = aux/2 = 48 MHz */
+ sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
+ au_writel(sys_freqctrl, SYS_FREQCTRL0);
+ break;
+ }
+
+ /*
+ * Route 48MHz FREQ2 into USB Host and/or Device
+ */
+ sys_clksrc |= ((4<<12) | (0<<11) | (0<<10));
+ au_writel(sys_clksrc, SYS_CLKSRC);
+
+ /* configure pins GPIO[14:9] as GPIO */
+ pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8080);
+
+ au_writel(pin_func, SYS_PINFUNC);
+ au_writel(0x2800, SYS_TRIOUTCLR);
+ au_writel(0x0030, SYS_OUTPUTCLR);
+
+ dbg("OHCI board setup complete\n");
+
+ /* enable host controller */
+ au_writel(USBH_ENABLE_CE, USB_HOST_CONFIG);
+ udelay(1000);
+ au_writel(USBH_ENABLE_INIT, USB_HOST_CONFIG);
+ udelay(1000);
+
+ /* wait for reset complete (read register twice; see au1500 errata) */
+ while (au_readl(USB_HOST_CONFIG),
+ !(au_readl(USB_HOST_CONFIG) & USBH_ENABLE_RD))
+ udelay(1000);
+
+ dbg("OHCI clock running\n");
+
+ memset (&gohci, 0, sizeof (ohci_t));
+ memset (&urb_priv, 0, sizeof (urb_priv_t));
+
+ /* align the storage */
+ if ((__u32)&ghcca[0] & 0xff) {
+ err("HCCA not aligned!!");
+ return -1;
+ }
+ phcca = &ghcca[0];
+ info("aligned ghcca %p", phcca);
+ memset(&ohci_dev, 0, sizeof(struct ohci_device));
+ if ((__u32)&ohci_dev.ed[0] & 0x7) {
+ err("EDs not aligned!!");
+ return -1;
+ }
+ memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
+ if ((__u32)gtd & 0x7) {
+ err("TDs not aligned!!");
+ return -1;
+ }
+ ptd = gtd;
+ gohci.hcca = phcca;
+ memset (phcca, 0, sizeof (struct ohci_hcca));
+
+ gohci.disabled = 1;
+ gohci.sleeping = 0;
+ gohci.irq = -1;
+ gohci.regs = (struct ohci_regs *)(USB_OHCI_BASE | 0xA0000000);
+
+ gohci.flags = 0;
+ gohci.slot_name = "au1x00";
+
+ dbg("OHCI revision: 0x%08x\n"
+ " RH: a: 0x%08x b: 0x%08x\n",
+ readl(&gohci.regs->revision),
+ readl(&gohci.regs->roothub.a), readl(&gohci.regs->roothub.b));
+
+ if (hc_reset (&gohci) < 0)
+ goto errout;
+
+ /* FIXME this is a second HC reset; why?? */
+ writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
+ wait_ms (10);
+
+ if (hc_start (&gohci) < 0)
+ goto errout;
+
+#ifdef DEBUG
+ ohci_dump (&gohci, 1);
+#else
+ wait_ms(1);
+#endif
+ ohci_inited = 1;
+ return 0;
+
+ errout:
+ err("OHCI initialization error\n");
+ hc_release_ohci (&gohci);
+ /* Initialization failed */
+ au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG);
+ return -1;
+}
+
+int usb_lowlevel_stop(void)
+{
+ /* this gets called really early - before the controller has */
+ /* even been initialized! */
+ if (!ohci_inited)
+ return 0;
+ /* TODO release any interrupts, etc. */
+ /* call hc_release_ohci() here ? */
+ hc_reset (&gohci);
+ /* may not want to do this */
+ /* Disable clock */
+ au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG);
+ return 0;
+}
+
+#endif /* CONFIG_USB_OHCI */
--- /dev/null
+/*
+ * URB OHCI HCD (Host Controller Driver) for USB.
+ *
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
+ *
+ * usb-ohci.h
+ */
+
+
+static int cc_to_error[16] = {
+
+/* mapping of the OHCI CC status to error codes */
+ /* No Error */ 0,
+ /* CRC Error */ USB_ST_CRC_ERR,
+ /* Bit Stuff */ USB_ST_BIT_ERR,
+ /* Data Togg */ USB_ST_CRC_ERR,
+ /* Stall */ USB_ST_STALLED,
+ /* DevNotResp */ -1,
+ /* PIDCheck */ USB_ST_BIT_ERR,
+ /* UnExpPID */ USB_ST_BIT_ERR,
+ /* DataOver */ USB_ST_BUF_ERR,
+ /* DataUnder */ USB_ST_BUF_ERR,
+ /* reservd */ -1,
+ /* reservd */ -1,
+ /* BufferOver */ USB_ST_BUF_ERR,
+ /* BuffUnder */ USB_ST_BUF_ERR,
+ /* Not Access */ -1,
+ /* Not Access */ -1
+};
+
+/* ED States */
+
+#define ED_NEW 0x00
+#define ED_UNLINK 0x01
+#define ED_OPER 0x02
+#define ED_DEL 0x04
+#define ED_URB_DEL 0x08
+
+/* usb_ohci_ed */
+struct ed {
+ __u32 hwINFO;
+ __u32 hwTailP;
+ __u32 hwHeadP;
+ __u32 hwNextED;
+
+ struct ed *ed_prev;
+ __u8 int_period;
+ __u8 int_branch;
+ __u8 int_load;
+ __u8 int_interval;
+ __u8 state;
+ __u8 type;
+ __u16 last_iso;
+ struct ed *ed_rm_list;
+
+ struct usb_device *usb_dev;
+ __u32 unused[3];
+} __attribute((aligned(16)));
+typedef struct ed ed_t;
+
+
+/* TD info field */
+#define TD_CC 0xf0000000
+#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
+#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
+#define TD_EC 0x0C000000
+#define TD_T 0x03000000
+#define TD_T_DATA0 0x02000000
+#define TD_T_DATA1 0x03000000
+#define TD_T_TOGGLE 0x00000000
+#define TD_R 0x00040000
+#define TD_DI 0x00E00000
+#define TD_DI_SET(X) (((X) & 0x07)<< 21)
+#define TD_DP 0x00180000
+#define TD_DP_SETUP 0x00000000
+#define TD_DP_IN 0x00100000
+#define TD_DP_OUT 0x00080000
+
+#define TD_ISO 0x00010000
+#define TD_DEL 0x00020000
+
+/* CC Codes */
+#define TD_CC_NOERROR 0x00
+#define TD_CC_CRC 0x01
+#define TD_CC_BITSTUFFING 0x02
+#define TD_CC_DATATOGGLEM 0x03
+#define TD_CC_STALL 0x04
+#define TD_DEVNOTRESP 0x05
+#define TD_PIDCHECKFAIL 0x06
+#define TD_UNEXPECTEDPID 0x07
+#define TD_DATAOVERRUN 0x08
+#define TD_DATAUNDERRUN 0x09
+#define TD_BUFFEROVERRUN 0x0C
+#define TD_BUFFERUNDERRUN 0x0D
+#define TD_NOTACCESSED 0x0F
+
+
+#define MAXPSW 1
+
+struct td {
+ __u32 hwINFO;
+ __u32 hwCBP; /* Current Buffer Pointer */
+ __u32 hwNextTD; /* Next TD Pointer */
+ __u32 hwBE; /* Memory Buffer End Pointer */
+
+ __u16 hwPSW[MAXPSW];
+ __u8 unused;
+ __u8 index;
+ struct ed *ed;
+ struct td *next_dl_td;
+ struct usb_device *usb_dev;
+ int transfer_len;
+ __u32 data;
+
+ __u32 unused2[2];
+} __attribute((aligned(32)));
+typedef struct td td_t;
+
+#define OHCI_ED_SKIP (1 << 14)
+
+/*
+ * The HCCA (Host Controller Communications Area) is a 256 byte
+ * structure defined in the OHCI spec. that the host controller is
+ * told the base address of. It must be 256-byte aligned.
+ */
+
+#define NUM_INTS 32 /* part of the OHCI standard */
+struct ohci_hcca {
+ __u32 int_table[NUM_INTS]; /* Interrupt ED table */
+ __u16 frame_no; /* current frame number */
+ __u16 pad1; /* set to 0 on each frame_no change */
+ __u32 done_head; /* info returned for an interrupt */
+ u8 reserved_for_hc[116];
+} __attribute((aligned(256)));
+
+
+/*
+ * Maximum number of root hub ports.
+ */
+#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */
+
+/*
+ * This is the structure of the OHCI controller's memory mapped I/O
+ * region. This is Memory Mapped I/O. You must use the readl() and
+ * writel() macros defined in asm/io.h to access these!!
+ */
+struct ohci_regs {
+ /* control and status registers */
+ __u32 revision;
+ __u32 control;
+ __u32 cmdstatus;
+ __u32 intrstatus;
+ __u32 intrenable;
+ __u32 intrdisable;
+ /* memory pointers */
+ __u32 hcca;
+ __u32 ed_periodcurrent;
+ __u32 ed_controlhead;
+ __u32 ed_controlcurrent;
+ __u32 ed_bulkhead;
+ __u32 ed_bulkcurrent;
+ __u32 donehead;
+ /* frame counters */
+ __u32 fminterval;
+ __u32 fmremaining;
+ __u32 fmnumber;
+ __u32 periodicstart;
+ __u32 lsthresh;
+ /* Root hub ports */
+ struct ohci_roothub_regs {
+ __u32 a;
+ __u32 b;
+ __u32 status;
+ __u32 portstatus[MAX_ROOT_PORTS];
+ } roothub;
+} __attribute((aligned(32)));
+
+
+/* OHCI CONTROL AND STATUS REGISTER MASKS */
+
+/*
+ * HcControl (control) register masks
+ */
+#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */
+#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */
+#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */
+#define OHCI_CTRL_CLE (1 << 4) /* control list enable */
+#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */
+#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
+#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
+#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
+#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
+
+/* pre-shifted values for HCFS */
+# define OHCI_USB_RESET (0 << 6)
+# define OHCI_USB_RESUME (1 << 6)
+# define OHCI_USB_OPER (2 << 6)
+# define OHCI_USB_SUSPEND (3 << 6)
+
+/*
+ * HcCommandStatus (cmdstatus) register masks
+ */
+#define OHCI_HCR (1 << 0) /* host controller reset */
+#define OHCI_CLF (1 << 1) /* control list filled */
+#define OHCI_BLF (1 << 2) /* bulk list filled */
+#define OHCI_OCR (1 << 3) /* ownership change request */
+#define OHCI_SOC (3 << 16) /* scheduling overrun count */
+
+/*
+ * masks used with interrupt registers:
+ * HcInterruptStatus (intrstatus)
+ * HcInterruptEnable (intrenable)
+ * HcInterruptDisable (intrdisable)
+ */
+#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
+#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
+#define OHCI_INTR_SF (1 << 2) /* start frame */
+#define OHCI_INTR_RD (1 << 3) /* resume detect */
+#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
+#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
+#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
+#define OHCI_INTR_OC (1 << 30) /* ownership change */
+#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
+
+
+/* Virtual Root HUB */
+struct virt_root_hub {
+ int devnum; /* Address of Root Hub endpoint */
+ void *dev; /* was urb */
+ void *int_addr;
+ int send;
+ int interval;
+};
+
+/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
+
+/* destination of request */
+#define RH_INTERFACE 0x01
+#define RH_ENDPOINT 0x02
+#define RH_OTHER 0x03
+
+#define RH_CLASS 0x20
+#define RH_VENDOR 0x40
+
+/* Requests: bRequest << 8 | bmRequestType */
+#define RH_GET_STATUS 0x0080
+#define RH_CLEAR_FEATURE 0x0100
+#define RH_SET_FEATURE 0x0300
+#define RH_SET_ADDRESS 0x0500
+#define RH_GET_DESCRIPTOR 0x0680
+#define RH_SET_DESCRIPTOR 0x0700
+#define RH_GET_CONFIGURATION 0x0880
+#define RH_SET_CONFIGURATION 0x0900
+#define RH_GET_STATE 0x0280
+#define RH_GET_INTERFACE 0x0A80
+#define RH_SET_INTERFACE 0x0B00
+#define RH_SYNC_FRAME 0x0C80
+/* Our Vendor Specific Request */
+#define RH_SET_EP 0x2000
+
+
+/* Hub port features */
+#define RH_PORT_CONNECTION 0x00
+#define RH_PORT_ENABLE 0x01
+#define RH_PORT_SUSPEND 0x02
+#define RH_PORT_OVER_CURRENT 0x03
+#define RH_PORT_RESET 0x04
+#define RH_PORT_POWER 0x08
+#define RH_PORT_LOW_SPEED 0x09
+
+#define RH_C_PORT_CONNECTION 0x10
+#define RH_C_PORT_ENABLE 0x11
+#define RH_C_PORT_SUSPEND 0x12
+#define RH_C_PORT_OVER_CURRENT 0x13
+#define RH_C_PORT_RESET 0x14
+
+/* Hub features */
+#define RH_C_HUB_LOCAL_POWER 0x00
+#define RH_C_HUB_OVER_CURRENT 0x01
+
+#define RH_DEVICE_REMOTE_WAKEUP 0x00
+#define RH_ENDPOINT_STALL 0x01
+
+#define RH_ACK 0x01
+#define RH_REQ_ERR -1
+#define RH_NACK 0x00
+
+
+/* OHCI ROOT HUB REGISTER MASKS */
+
+/* roothub.portstatus [i] bits */
+#define RH_PS_CCS 0x00000001 /* current connect status */
+#define RH_PS_PES 0x00000002 /* port enable status*/
+#define RH_PS_PSS 0x00000004 /* port suspend status */
+#define RH_PS_POCI 0x00000008 /* port over current indicator */
+#define RH_PS_PRS 0x00000010 /* port reset status */
+#define RH_PS_PPS 0x00000100 /* port power status */
+#define RH_PS_LSDA 0x00000200 /* low speed device attached */
+#define RH_PS_CSC 0x00010000 /* connect status change */
+#define RH_PS_PESC 0x00020000 /* port enable status change */
+#define RH_PS_PSSC 0x00040000 /* port suspend status change */
+#define RH_PS_OCIC 0x00080000 /* over current indicator change */
+#define RH_PS_PRSC 0x00100000 /* port reset status change */
+
+/* roothub.status bits */
+#define RH_HS_LPS 0x00000001 /* local power status */
+#define RH_HS_OCI 0x00000002 /* over current indicator */
+#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
+#define RH_HS_LPSC 0x00010000 /* local power status change */
+#define RH_HS_OCIC 0x00020000 /* over current indicator change */
+#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
+
+/* roothub.b masks */
+#define RH_B_DR 0x0000ffff /* device removable flags */
+#define RH_B_PPCM 0xffff0000 /* port power control mask */
+
+/* roothub.a masks */
+#define RH_A_NDP (0xff << 0) /* number of downstream ports */
+#define RH_A_PSM (1 << 8) /* power switching mode */
+#define RH_A_NPS (1 << 9) /* no power switching */
+#define RH_A_DT (1 << 10) /* device type (mbz) */
+#define RH_A_OCPM (1 << 11) /* over current protection mode */
+#define RH_A_NOCP (1 << 12) /* no over current protection */
+#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
+
+/* urb */
+#define N_URB_TD 48
+typedef struct
+{
+ ed_t *ed;
+ __u16 length; /* number of tds associated with this request */
+ __u16 td_cnt; /* number of tds already serviced */
+ int state;
+ unsigned long pipe;
+ int actual_length;
+ td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */
+} urb_priv_t;
+#define URB_DEL 1
+
+/*
+ * This is the full ohci controller description
+ *
+ * Note how the "proper" USB information is just
+ * a subset of what the full implementation needs. (Linus)
+ */
+
+
+typedef struct ohci {
+ struct ohci_hcca *hcca; /* hcca */
+ /*dma_addr_t hcca_dma;*/
+
+ int irq;
+ int disabled; /* e.g. got a UE, we're hung */
+ int sleeping;
+ unsigned long flags; /* for HC bugs */
+
+ struct ohci_regs *regs; /* OHCI controller's memory */
+
+ ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */
+ ed_t *ed_bulktail; /* last endpoint of bulk list */
+ ed_t *ed_controltail; /* last endpoint of control list */
+ int intrstatus;
+ __u32 hc_control; /* copy of the hc control reg */
+ struct usb_device *dev[32];
+ struct virt_root_hub rh;
+
+ const char *slot_name;
+} ohci_t;
+
+#define NUM_EDS 8 /* num of preallocated endpoint descriptors */
+
+struct ohci_device {
+ ed_t ed[NUM_EDS];
+ int ed_cnt;
+};
+
+/* hcd */
+/* endpoint */
+static int ep_link(ohci_t * ohci, ed_t * ed);
+static int ep_unlink(ohci_t * ohci, ed_t * ed);
+static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe);
+
+/*-------------------------------------------------------------------------*/
+
+/* we need more TDs than EDs */
+#define NUM_TD 64
+
+/* +1 so we can align the storage */
+td_t gtd[NUM_TD+1];
+/* pointers to aligned storage */
+td_t *ptd;
+
+/* TDs ... */
+static inline struct td *
+td_alloc (struct usb_device *usb_dev)
+{
+ int i;
+ struct td *td;
+
+ td = NULL;
+ for (i = 0; i < NUM_TD; i++) {
+ if (ptd[i].usb_dev == NULL) {
+ td = &ptd[i];
+ td->usb_dev = usb_dev;
+ break;
+ }
+ }
+ return td;
+}
+
+static inline void
+ed_free (struct ed *ed)
+{
+ ed->usb_dev = NULL;
+}
if [ "$v" -lt "14" ]; then \
echo "-mcpu=4kc"; \
else \
- echo "-march=4kc -mtune=4kc -Wa,-mips_allow_branch_to_undefined"; \
+ echo "-march=4kc -mtune=4kc"; \
fi)
ifneq (,$(findstring 4KCle,$(CROSS_COMPILE)))
extern void ebu_init(long);
extern void cgu_init(long);
extern void sdram_init(long);
- uchar tmp[64];
+ char tmp[64];
ulong cpuclk;
if (getenv_r ("cpuclk", tmp, sizeof (tmp)) > 0) {
li t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG
+ /* Initialize GOT pointer.
+ */
+ bal 1f
+ nop
+ .word _GLOBAL_OFFSET_TABLE_
+ 1:
+ move gp, ra
+ lw t1, 0(ra)
+ move gp, t1
+
#ifdef CONFIG_INCA_IP
/* Disable INCA-IP Watchdog.
*/
- bal disable_incaip_wdt
+ la t9, disable_incaip_wdt
+ jalr t9
nop
#endif
/* Initialize any external memory.
*/
- bal lowlevel_init
+ la t9, lowlevel_init
+ jalr t9
nop
/* Initialize caches...
*/
- bal mips_cache_reset
+ la t9, mips_cache_reset
+ jalr t9
nop
/* ... and enable them.
/* Set up temporary stack.
*/
li a0, CFG_INIT_SP_OFFSET
- bal mips_cache_lock
+ la t9, mips_cache_lock
+ jalr t9
nop
li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
la sp, 0(t0)
- /* Initialize GOT pointer.
- */
- bal 1f
- nop
- .word _GLOBAL_OFFSET_TABLE_ - 1f + 4
-1:
- move gp, ra
- lw t1, 0(ra)
- add gp, t1
la t9, board_init_f
j t9
nop
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
defined(CONFIG_MPC5xxx_FEC)
+#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
+#error "CONFIG_MII has to be defined!"
+#endif
+
#if (DEBUG & 0x60)
-static void tfifo_print(mpc5xxx_fec_priv *fec);
-static void rfifo_print(mpc5xxx_fec_priv *fec);
+static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec);
+static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec);
#endif /* DEBUG */
#if (DEBUG & 0x40)
uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
} NBUF;
+int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal);
+int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
+
/********************************************************************/
#if (DEBUG & 0x2)
-static void mpc5xxx_fec_phydump (void)
+static void mpc5xxx_fec_phydump (char *devname)
{
uint16 phyStatus, i;
uint8 phyAddr = CONFIG_PHY_ADDR;
for (i = 0; i < 32; i++) {
if (reg_mask[i]) {
- miiphy_read(phyAddr, i, &phyStatus);
+ miiphy_read(devname, phyAddr, i, &phyStatus);
printf("Mii reg %d: 0x%04x\n", i, phyStatus);
}
}
/*
* Set Rx FIFO alarm and granularity value
*/
- fec->eth->rfifo_cntrl = 0x0c000000;
+ fec->eth->rfifo_cntrl = 0x0c000000
+ | (fec->eth->rfifo_cntrl & ~0x0f000000);
fec->eth->rfifo_alarm = 0x0000030c;
#if (DEBUG & 0x22)
if (fec->eth->rfifo_status & 0x00700000 ) {
/*
* Set Tx FIFO granularity value
*/
- fec->eth->tfifo_cntrl = 0x0c000000;
+ fec->eth->tfifo_cntrl = 0x0c000000
+ | (fec->eth->tfifo_cntrl & ~0x0f000000);
#if (DEBUG & 0x2)
printf("tfifo_status: 0x%08x\n", fec->eth->tfifo_status);
printf("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm);
* Set individual address filter for unicast address
* and set physical address registers.
*/
- mpc5xxx_fec_set_hwaddr(fec, dev->enetaddr);
+ mpc5xxx_fec_set_hwaddr(fec, (char *)dev->enetaddr);
/*
* Set multicast address filter
/*
* Reset PHY, then delay 300ns
*/
- miiphy_write(phyAddr, 0x0, 0x8000);
+ miiphy_write(dev->name, phyAddr, 0x0, 0x8000);
udelay(1000);
if (fec->xcv_type == MII10) {
#if (DEBUG & 0x2)
printf("Forcing 10 Mbps ethernet link... ");
#endif
- miiphy_read(phyAddr, 0x1, &phyStatus);
+ miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
/*
- miiphy_write(fec, phyAddr, 0x0, 0x0100);
+ miiphy_write(dev->name, fec, phyAddr, 0x0, 0x0100);
*/
- miiphy_write(phyAddr, 0x0, 0x0180);
+ miiphy_write(dev->name, phyAddr, 0x0, 0x0180);
timeout = 20;
do { /* wait for link status to go down */
#endif
break;
}
- miiphy_read(phyAddr, 0x1, &phyStatus);
+ miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
#if (DEBUG & 0x2)
printf("=");
#endif
printf("failed. Link is down.\n");
break;
}
- miiphy_read(phyAddr, 0x1, &phyStatus);
+ miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
#if (DEBUG & 0x2)
printf("+");
#endif
/*
* Set the auto-negotiation advertisement register bits
*/
- miiphy_write(phyAddr, 0x4, 0x01e1);
+ miiphy_write(dev->name, phyAddr, 0x4, 0x01e1);
/*
* Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
*/
- miiphy_write(phyAddr, 0x0, 0x1200);
+ miiphy_write(dev->name, phyAddr, 0x0, 0x1200);
/*
* Wait for AN completion
return -1;
}
- if (miiphy_read(phyAddr, 0x1, &phyStatus) != 0) {
+ if (miiphy_read(dev->name, phyAddr, 0x1, &phyStatus) != 0) {
#if (DEBUG & 0x2)
printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
#endif
#if (DEBUG & 0x2)
if (fec->xcv_type != SEVENWIRE)
- mpc5xxx_fec_phydump ();
+ mpc5xxx_fec_phydump (dev->name);
#endif
#if (DEBUG & 0x60)
/********************************************************************/
-static void tfifo_print(mpc5xxx_fec_priv *fec)
+static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec)
{
uint16 phyAddr = CONFIG_PHY_ADDR;
uint16 phyStatus;
if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
|| (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
- miiphy_read(phyAddr, 0x1, &phyStatus);
+ miiphy_read(devname, phyAddr, 0x1, &phyStatus);
printf("\nphyStatus: 0x%04x\n", phyStatus);
printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
printf("ievent: 0x%08x\n", fec->eth->ievent);
}
}
-static void rfifo_print(mpc5xxx_fec_priv *fec)
+static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec)
{
uint16 phyAddr = CONFIG_PHY_ADDR;
uint16 phyStatus;
if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
|| (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
- miiphy_read(phyAddr, 0x1, &phyStatus);
+ miiphy_read(devname, phyAddr, 0x1, &phyStatus);
printf("\nphyStatus: 0x%04x\n", phyStatus);
printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
printf("ievent: 0x%08x\n", fec->eth->ievent);
#if (DEBUG & 0x20)
printf("tbd status: 0x%04x\n", fec->tbdBase[0].status);
- tfifo_print(fec);
+ tfifo_print(dev->name, fec);
#endif
/*
*/
if (fec->xcv_type != SEVENWIRE) {
uint16 phyStatus;
- miiphy_read(0, 0x1, &phyStatus);
+ miiphy_read(dev->name, 0, 0x1, &phyStatus);
}
/*
*/
#if (DEBUG & 0x20)
- tfifo_print(fec);
+ tfifo_print(dev->name, fec);
#endif
SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
#if (DEBUG & 0x20)
- tfifo_print(fec);
+ tfifo_print(dev->name, fec);
#endif
#if (DEBUG & 0x8)
printf( "+" );
unsigned long ievent;
int frame_length, len = 0;
NBUF *frame;
- char buff[FEC_MAX_PKT_SIZE];
+ uchar buff[FEC_MAX_PKT_SIZE];
#if (DEBUG & 0x1)
printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex);
#if defined(CONFIG_CANMB) || defined(CONFIG_HMI1001) || \
defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0) || \
defined(CONFIG_PM520) || defined(CONFIG_TOP5200) || \
- defined(CONFIG_TQM5200)
+ defined(CONFIG_TQM5200) || defined(CONFIG_O2DNT)
# ifndef CONFIG_FEC_10MBIT
fec->xcv_type = MII100;
# else
sprintf(dev->name, "FEC ETHERNET");
eth_register(dev);
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+ miiphy_register (dev->name,
+ fec5xxx_miiphy_read, fec5xxx_miiphy_write);
+#endif
+
/*
* Try to set the mac address now. The fec mac address is
* a garbage after reset. When not using fec for booting
}
mpc5xxx_fec_init_phy(dev, bis);
+
return 1;
}
/* MII-interface related functions */
/********************************************************************/
-int miiphy_read(uint8 phyAddr, uint8 regAddr, uint16 * retVal)
+int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal)
{
ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
uint32 reg; /* convenient holder for the PHY register */
}
/********************************************************************/
-int miiphy_write(uint8 phyAddr, uint8 regAddr, uint16 data)
+int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data)
{
ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
uint32 reg; /* convenient holder for the PHY register */
static int mpc_reg_in(volatile u32 *reg)
{
- return *reg >> 24;
+ int ret = *reg >> 24;
__asm__ __volatile__ ("eieio");
+ return ret;
}
static void mpc_reg_out(volatile u32 *reg, int val, int mask)
int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
{
- uchar xaddr[4];
+ char xaddr[4];
struct mpc5xxx_i2c * regs = (struct mpc5xxx_i2c *)I2C_BASE;
int ret = -1;
goto Done;
}
- if (receive_bytes(chip, buf, len)) {
+ if (receive_bytes(chip, (char *)buf, len)) {
printf("i2c_read: receive_bytes failed\n");
goto Done;
}
int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
{
- uchar xaddr[4];
+ char xaddr[4];
struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
int ret = -1;
goto Done;
}
- if (send_bytes(chip, buf, len)) {
+ if (send_bytes(chip, (char *)buf, len)) {
printf("i2c_write: send_bytes failed\n");
goto Done;
}
uchar i2c_reg_read(uchar chip, uchar reg)
{
- char buf;
+ uchar buf;
i2c_read(chip, reg, 1, &buf, 1);
*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
eieio();
udelay(10);
+#if (defined CONFIG_PF5200 || defined CONFIG_CPCI5200)
+ if (dev & 0x00ff0000) {
+ u32 val;
+ val = in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+2));
+ udelay(10);
+ val = val << 16;
+ val |= in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+0));
+ *value = val;
+ } else {
+ *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
+ }
+ udelay(10);
+#else
*value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
+#endif
eieio();
*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
udelay(10);
/* Disable interrupts from PCI controller */
*(vu_long *)MPC5XXX_PCI_GSCR &= ~(7 << 12);
- *(vu_long *)MPC5XXX_PCI_ICR &= ~(7 << 24);
+ *(vu_long *)MPC5XXX_PCI_ICR &= ~(7 << 24);
+
+ /* Set PCI retry counter to 0 = infinite retry. */
+ /* The default of 255 is too short for slow devices. */
+ *(vu_long *)MPC5XXX_PCI_ICR &= 0xFFFFFF00;
/* Disable initiator windows */
*(vu_long *)MPC5XXX_PCI_IWCR = 0;
unsigned long baseclk, div;
#if defined(CONFIG_MGT5100)
- baseclk = CFG_MPC5XXX_CLKIN / 32;
+ baseclk = (CFG_MPC5XXX_CLKIN + 16) / 32;
#elif defined(CONFIG_MPC5200)
baseclk = (gd->ipb_clk + 16) / 32;
#endif
/* set up UART divisor */
div = (baseclk + (gd->baudrate/2)) / gd->baudrate;
- psc->ctur = div >> 8;
- psc->ctlr = div & 0xff;
+ psc->ctur = (div >> 8) & 0xFF;
+ psc->ctlr = div & 0xff;
}
#endif /* CONFIG_PSC_CONSOLE */
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
defined(CONFIG_MPC8220_FEC)
-/*#if (CONFIG_COMMANDS & CFG_CMD_NET)*/
+#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
+#error "CONFIG_MII has to be defined!"
+#endif
#ifdef DEBUG
-static void tfifo_print (mpc8220_fec_priv * fec);
-static void rfifo_print (mpc8220_fec_priv * fec);
+static void tfifo_print (char *devname, mpc8220_fec_priv * fec);
+static void rfifo_print (char *devname, mpc8220_fec_priv * fec);
#endif /* DEBUG */
#ifdef DEBUG
u8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
} NBUF;
+int fec8220_miiphy_read (char *devname, u8 phyAddr, u8 regAddr, u16 * retVal);
+int fec8220_miiphy_write (char *devname, u8 phyAddr, u8 regAddr, u16 data);
+
/********************************************************************/
#ifdef DEBUG
-static void mpc8220_fec_phydump (void)
+static void mpc8220_fec_phydump (char *devname)
{
u16 phyStatus, i;
u8 phyAddr = CONFIG_PHY_ADDR;
for (i = 0; i < 32; i++) {
if (reg_mask[i]) {
- miiphy_read (phyAddr, i, &phyStatus);
+ miiphy_read (devname, phyAddr, i, &phyStatus);
printf ("Mii reg %d: 0x%04x\n", i, phyStatus);
}
}
* Set individual address filter for unicast address
* and set physical address registers.
*/
- mpc8220_fec_set_hwaddr (fec, dev->enetaddr);
+ mpc8220_fec_set_hwaddr (fec, (char *)(dev->enetaddr));
/*
* Set multicast address filter
/*
* Reset PHY, then delay 300ns
*/
- miiphy_write (phyAddr, 0x0, 0x8000);
+ miiphy_write (dev->name, phyAddr, 0x0, 0x8000);
udelay (1000);
if (fec->xcv_type == MII10) {
#ifdef DEBUG
printf ("Forcing 10 Mbps ethernet link... ");
#endif
- miiphy_read (phyAddr, 0x1, &phyStatus);
+ miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
/*
miiphy_write(fec, phyAddr, 0x0, 0x0100);
*/
- miiphy_write (phyAddr, 0x0, 0x0180);
+ miiphy_write (dev->name, phyAddr, 0x0, 0x0180);
timeout = 20;
do { /* wait for link status to go down */
#endif
break;
}
- miiphy_read (phyAddr, 0x1, &phyStatus);
+ miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
#ifdef DEBUG
printf ("=");
#endif
printf ("failed. Link is down.\n");
break;
}
- miiphy_read (phyAddr, 0x1, &phyStatus);
+ miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
#ifdef DEBUG
printf ("+");
#endif
/*
* Set the auto-negotiation advertisement register bits
*/
- miiphy_write (phyAddr, 0x4, 0x01e1);
+ miiphy_write (dev->name, phyAddr, 0x4, 0x01e1);
/*
* Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
*/
- miiphy_write (phyAddr, 0x0, 0x1200);
+ miiphy_write (dev->name, phyAddr, 0x0, 0x1200);
/*
* Wait for AN completion
return -1;
}
- if (miiphy_read (phyAddr, 0x1, &phyStatus) !=
+ if (miiphy_read (dev->name, phyAddr, 0x1, &phyStatus) !=
0) {
#ifdef DEBUG
printf ("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
#ifdef DEBUG
if (fec->xcv_type != SEVENWIRE)
- mpc8220_fec_phydump ();
+ mpc8220_fec_phydump (dev->name);
#endif
/*
#ifdef DEBUG
if (fec->xcv_type != SEVENWIRE)
- mpc8220_fec_phydump ();
+ mpc8220_fec_phydump (dev->name);
#endif
/*
#ifdef DEBUG
/********************************************************************/
-static void tfifo_print (mpc8220_fec_priv * fec)
+static void tfifo_print (char *devname, mpc8220_fec_priv * fec)
{
u16 phyAddr = CONFIG_PHY_ADDR;
u16 phyStatus;
if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
|| (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
- miiphy_read (phyAddr, 0x1, &phyStatus);
+ miiphy_read (devname, phyAddr, 0x1, &phyStatus);
printf ("\nphyStatus: 0x%04x\n", phyStatus);
printf ("ecntrl: 0x%08x\n", fec->eth->ecntrl);
printf ("ievent: 0x%08x\n", fec->eth->ievent);
}
}
-static void rfifo_print (mpc8220_fec_priv * fec)
+static void rfifo_print (char *devname, mpc8220_fec_priv * fec)
{
u16 phyAddr = CONFIG_PHY_ADDR;
u16 phyStatus;
if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
|| (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
- miiphy_read (phyAddr, 0x1, &phyStatus);
+ miiphy_read (devname, phyAddr, 0x1, &phyStatus);
printf ("\nphyStatus: 0x%04x\n", phyStatus);
printf ("ecntrl: 0x%08x\n", fec->eth->ecntrl);
printf ("ievent: 0x%08x\n", fec->eth->ievent);
#ifdef DEBUG
printf ("tbd status: 0x%04x\n", fec->tbdBase[0].status);
- tfifo_print (fec);
+ tfifo_print (dev->name, fec);
#endif
/*
if (fec->xcv_type != SEVENWIRE) {
u16 phyStatus;
- miiphy_read (0, 0x1, &phyStatus);
+ miiphy_read (dev->name, 0, 0x1, &phyStatus);
}
/*
*/
#ifdef DEBUG
- tfifo_print (fec);
+ tfifo_print (dev->name, fec);
#endif
DMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
#ifdef DEBUG
- tfifo_print (fec);
+ tfifo_print (dev->name, fec);
#endif
#ifdef DEBUG
sprintf (dev->name, "FEC ETHERNET");
eth_register (dev);
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+ miiphy_register (dev->name,
+ fec8220_miiphy_read, fec8220_miiphy_write);
+#endif
+
/*
* Try to set the mac address now. The fec mac address is
* a garbage after reset. When not using fec for booting
/* MII-interface related functions */
/********************************************************************/
-int miiphy_read (u8 phyAddr, u8 regAddr, u16 * retVal)
+int fec8220_miiphy_read (char *devname, u8 phyAddr, u8 regAddr, u16 * retVal)
{
ethernet_regs *eth = (ethernet_regs *) MMAP_FEC1;
u32 reg; /* convenient holder for the PHY register */
}
/********************************************************************/
-int miiphy_write (u8 phyAddr, u8 regAddr, u16 data)
+int fec8220_miiphy_write (char *devname, u8 phyAddr, u8 regAddr, u16 data)
{
ethernet_regs *eth = (ethernet_regs *) MMAP_FEC1;
u32 reg; /* convenient holder for the PHY register */
static int mpc_reg_in (volatile u32 * reg)
{
- return *reg >> 24;
+ int ret;
+ ret = *reg >> 24;
__asm__ __volatile__ ("eieio");
+ return ret;
}
static void mpc_reg_out (volatile u32 * reg, int val, int mask)
goto Done;
}
- if (send_bytes (chip, &xaddr[4 - alen], alen)) {
+ if (send_bytes (chip, (char *)&xaddr[4 - alen], alen)) {
printf ("i2c_read: send_bytes failed\n");
goto Done;
}
goto Done;
}
- if (receive_bytes (chip, buf, len)) {
+ if (receive_bytes (chip, (char *)buf, len)) {
printf ("i2c_read: receive_bytes failed\n");
goto Done;
}
goto Done;
}
- if (send_bytes (chip, &xaddr[4 - alen], alen)) {
+ if (send_bytes (chip, (char *)&xaddr[4 - alen], alen)) {
printf ("i2c_write: send_bytes failed\n");
goto Done;
}
- if (send_bytes (chip, buf, len)) {
+ if (send_bytes (chip, (char *)buf, len)) {
printf ("i2c_write: send_bytes failed\n");
goto Done;
}
uchar i2c_reg_read (uchar chip, uchar reg)
{
- char buf;
+ uchar buf;
i2c_read (chip, reg, 1, &buf, 1);
* and looking for an <ACK> back.
*/
udelay (10000);
- return i2c_read (chip, 0, 1, (char *) &tmp, 1);
+ return i2c_read (chip, 0, 1, (uchar *) &tmp, 1);
}
uchar i2c_reg_read (uchar i2c_addr, uchar reg)
{
- char buf[1];
+ uchar buf[1];
i2c_read (i2c_addr, reg, 1, buf, 1);
#include <config.h>
#include <net.h>
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+#include <miiphy.h>
+#endif
+
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \
defined(CONFIG_NET_MULTI)
dev->recv = fec_recv;
eth_register(dev);
+
+#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) \
+ && defined(CONFIG_BITBANGMII)
+ miiphy_register(dev->name,
+ bb_miiphy_read, bb_miiphy_write);
+#endif
}
return 1;
uchar
i2c_reg_read(uchar chip, uchar reg)
{
- char buf;
+ uchar buf;
i2c_read(chip, reg, 1, &buf, 1);
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
+ * Copyright (c) 2005 MontaVista Software, Inc.
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ * Added support for PCI bridge on MPC8272ADS
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
void pci_mpc8250_init (struct pci_controller *hose)
{
-#ifdef CONFIG_MPC8266ADS
+#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
DECLARE_GLOBAL_DATA_PTR;
#endif
u16 tempShort;
immap->im_siu_conf.sc_siumcr =
(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
| SIUMCR_LBPC01;
+#elif defined CONFIG_MPC8272
+ immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
+ ~SIUMCR_BBD &
+ ~SIUMCR_ESE &
+ ~SIUMCR_PBSE &
+ ~SIUMCR_CDIS &
+ ~SIUMCR_DPPC11 &
+ ~SIUMCR_L2CPC11 &
+ ~SIUMCR_LBPC11 &
+ ~SIUMCR_APPC11 &
+ ~SIUMCR_CS10PC11 &
+ ~SIUMCR_BCTLC11 &
+ ~SIUMCR_MMR11)
+ | SIUMCR_DPPC11
+ | SIUMCR_L2CPC01
+ | SIUMCR_LBPC00
+ | SIUMCR_APPC10
+ | SIUMCR_CS10PC00
+ | SIUMCR_BCTLC00
+ | SIUMCR_MMR11;
+
#else
/*
* Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK;
immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE;
-#ifdef CONFIG_MPC8266ADS
+#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
immap->im_memctl.memc_pcimsk1 = PCIMSK1_MASK;
immap->im_memctl.memc_pcibr1 = PCI_MSTR1_LOCAL | PCIBR_ENABLE;
#endif
/* give it some time */
{
-#ifdef CONFIG_MPC8266ADS
+#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
/* Give the PCI cards more time to initialize before query
This might be good for other boards also
*/
immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB); /* Size & attribute */
/* See above for description - puts PCI request as highest priority */
+#ifdef CONFIG_MPC8272
+ immap->im_siu_conf.sc_ppc_alrh = 0x01236745;
+#else
immap->im_siu_conf.sc_ppc_alrh = 0x03124567;
+#endif
/* Park the bus on the PCI */
immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
hose->last_busno = 0xff;
/* System memory space */
-#ifdef CONFIG_MPC8266ADS
+#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
pci_set_region (hose->regions + 0,
PCI_SLV_MEM_BUS,
PCI_SLV_MEM_LOCAL,
#endif
/* PCI memory space */
-#ifdef CONFIG_MPC8266ADS
+#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
pci_set_region (hose->regions + 1,
PCI_MSTR_MEMIO_BUS,
PCI_MSTR_MEMIO_LOCAL,
cpu_init.o \
speed.o \
interrupts.o \
- pci.o \
i2c.o \
spd_sdram.o
return -1;
}
- puts("CPU: MPC83xx, ");
+ puts("CPU: MPC83xx, ");
switch(pvr) {
case PVR_8349_REV10:
break;
puts("Rev: Unknown\n");
return -1; /* Not sure what this is */
}
- printf("Rev: %02x at %s MHz\n",pvr & 0x0000FFFF, strmhz(buf, clock));
+ printf("Rev: %d.%d at %s MHz\n", (pvr & 0xf0) >> 4,
+ (pvr & 0x0f), strmhz(buf, clock));
+
return 0;
}
#include <i2c.h>
#include <asm/i2c.h>
-#ifdef CONFIG_MPC8349ADS
+#if defined(CONFIG_MPC8349ADS) || defined(CONFIG_TQM834X)
i2c_t * mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET);
#endif
return 0;
} while (get_timer (timeval) < I2C_TIMEOUT);
+
debug("i2c_wait: timed out\n");
+ return -1;
}
static __inline__ int
* and looking for an <ACK> back.
*/
udelay(10000);
- return i2c_read (chip, 0, 1, (char *)&tmp, 1);
+ return i2c_read (chip, 0, 1, (uchar *)&tmp, 1);
}
uchar i2c_reg_read (uchar i2c_addr, uchar reg)
{
- char buf[1];
+ uchar buf[1];
i2c_read (i2c_addr, reg, 1, buf, 1);
+++ /dev/null
-/*
- * Copyright 2004 Freescale Semiconductor.
- * Copyright (C) 2003 Motorola Inc.
- * Xianghua Xiao (x.xiao@motorola.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Change log:
- *
- * 20050101: Eran Liberty (liberty@freescale.com)
- * Initial file creating (porting from 85XX & 8260)
- */
-
-/*
- * PCI Configuration space access support for MPC85xx PCI Bridge
- */
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <common.h>
-#include <pci.h>
-
-#ifdef CONFIG_MPC8349ADS
-#include <asm/i2c.h>
-#endif
-
-#if defined(CONFIG_PCI)
-
-void
-pci_mpc83xx_init(volatile struct pci_controller *hose)
-{
- volatile immap_t * immr;
- volatile clk8349_t * clk;
- volatile law8349_t * pci_law;
- volatile pot8349_t * pci_pot;
- volatile pcictrl8349_t * pci_ctrl;
- volatile pciconf8349_t * pci_conf;
-
- u8 val8,tmp8,ret;
- u16 reg16,tmp16;
- u32 val32,tmp32;
-
- immr = (immap_t *)CFG_IMMRBAR;
- clk = (clk8349_t *)&immr->clk;
- pci_law = immr->sysconf.pcilaw;
- pci_pot = immr->ios.pot;
- pci_ctrl = immr->pci_ctrl;
- pci_conf = immr->pci_conf;
-
- /*
- * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
- */
- val32 = clk->occr;
- udelay(2000);
- clk->occr = 0xff000000;
- udelay(2000);
-
- /*
- * Configure PCI Local Access Windows
- */
- pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
- pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
-
- /*
- * Configure PCI Outbound Translation Windows
- */
- pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK);
-
- /* mapped to PCI1 IO space 0x0 to local 0xe2000000 */
- pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
-
- pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[3].pocmr = POCMR_EN | POCMR_DST | (POCMR_CM_512M & POCMR_CM_MASK);
-
- /* mapped to PCI2 IO space 0x0 to local 0xe3000000 */
- pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[4].pocmr = POCMR_EN | POCMR_DST | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
-
- /*
- * Configure PCI Inbound Translation Windows
- */
- pci_ctrl[0].pitar1 = 0x0;
- pci_ctrl[0].pibar1 = 0x0;
- pci_ctrl[0].piebar1 = 0x0;
- pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
-
- pci_ctrl[1].pitar1 = 0x0;
- pci_ctrl[1].pibar1 = 0x0;
- pci_ctrl[1].piebar1 = 0x0;
- pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
- /*
- * Assign PIB PMC slot to desired PCI bus
- */
-#ifdef CONFIG_MPC8349ADS
- mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET);
- i2c_init(CFG_I2C_SPEED,CFG_I2C_SLAVE);
-#endif
- val8 = 0;
- ret = i2c_write(0x23,0x6,1,&val8,1);
- ret = i2c_write(0x23,0x7,1,&val8,1);
- val8 = 0xff;
- ret = i2c_write(0x23,0x2,1,&val8,1);
- ret = i2c_write(0x23,0x3,1,&val8,1);
-
- val8 = 0;
- ret = i2c_write(0x26,0x6,1,&val8,1);
- val8 = 0x34;
- ret = i2c_write(0x26,0x7,1,&val8,1);
-#if defined(PCI_64BIT)
- val8 = 0xf4; /* PMC2<->PCI1 64bit */
-#elif defined(PCI_ALL_PCI1)
- val8 = 0xf3; /* PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI1 32bit */
-#elif defined(PCI_ONE_PCI1)
- val8 = 0xf9; /* PMC1<->PCI1,PMC2<->PCI2,PMC3<->PCI2 32bit */
-#elif defined(PCI_TWO_PCI1)
- val8 = 0xf5; /* PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI2 32bit */
-#else
- val8 = 0xf5;
-#endif
- ret = i2c_write(0x26,0x2,1,&val8,1);
- val8 = 0xff;
- ret = i2c_write(0x26,0x3,1,&val8,1);
- val8 = 0;
- ret = i2c_write(0x27,0x6,1,&val8,1);
- ret = i2c_write(0x27,0x7,1,&val8,1);
- val8 = 0xff;
- ret = i2c_write(0x27,0x2,1,&val8,1);
- val8 = 0xef;
- ret = i2c_write(0x27,0x3,1,&val8,1);
- asm("eieio");
-
- /*
- * Release PCI RST Output signal
- */
- udelay(2000);
- pci_ctrl[0].gcr = 1;
-#ifndef PCI_64BIT
- pci_ctrl[1].gcr = 1;
-#endif
- udelay(2000);
-
- hose[0].first_busno = 0;
- hose[0].last_busno = 0xff;
-
- pci_set_region(hose[0].regions + 0,
- CFG_PCI1_MEM_BASE,
- CFG_PCI1_MEM_PHYS,
- CFG_PCI1_MEM_SIZE,
- PCI_REGION_MEM);
-
- pci_set_region(hose[0].regions + 1,
- CFG_PCI1_IO_BASE,
- CFG_PCI1_IO_PHYS,
- CFG_PCI1_IO_SIZE,
- PCI_REGION_IO);
-
- hose[0].region_count = 2;
-
- pci_setup_indirect(&hose[0],
- (CFG_IMMRBAR+0x8300),
- (CFG_IMMRBAR+0x8304));
-#define PCI_CLASS_BRIDGE 0x06
- reg16 = 0xff;
- tmp32 = 0xffff;
- pci_hose_write_config_byte(&hose[0],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE);
-
- pci_hose_read_config_word (&hose[0],PCI_BDF(0,0,0),PCI_COMMAND, ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(&hose[0],PCI_BDF(0,0,0), PCI_COMMAND, reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(&hose[0],PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
- pci_hose_write_config_byte(&hose[0],PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
-#ifndef PCI_64BIT
- hose[1].first_busno = 0;
- hose[1].last_busno = 0xff;
-
- pci_set_region(hose[1].regions + 0,
- CFG_PCI2_MEM_BASE,
- CFG_PCI2_MEM_PHYS,
- CFG_PCI2_MEM_SIZE,
- PCI_REGION_MEM);
-
- pci_set_region(hose[1].regions + 1,
- CFG_PCI2_IO_BASE,
- CFG_PCI2_IO_PHYS,
- CFG_PCI2_IO_SIZE,
- PCI_REGION_IO);
-
- hose[1].region_count = 2;
-
- pci_setup_indirect(&hose[1],
- (CFG_IMMRBAR+0x8380),
- (CFG_IMMRBAR+0x8384));
-
- pci_hose_write_config_byte(&hose[1],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE);
- pci_hose_read_config_word (&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(&hose[1],PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
- pci_hose_write_config_byte(&hose[1],PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
-#endif
-
-#if defined(PCI_64BIT)
- printf("PCI1 64bit on PMC2\n");
-#elif defined(PCI_ALL_PCI1)
- printf("PCI1 32bit on PMC1 & PMC2 & PMC3\n");
-#elif defined(PCI_ONE_PCI1)
- printf("PCI1 32bit on PMC1,PCI2 32bit on PMC2 & PMC3\n");
-#else
- printf("PCI1 32bit on PMC1 & PMC2 & PMC3 in default\n");
-#endif
-
-#if 1
- /*
- * Hose scan.
- */
- pci_register_hose(hose);
- hose->last_busno = pci_hose_scan(hose);
-#endif
-}
-
-#endif /* CONFIG_PCI */
return -1;
#ifndef CFG_HRCW_HIGH
-# error "CFG_HRCW_HIGH must be defined in include/configs/MCP83XXADS.h"
+# error "CFG_HRCW_HIGH must be defined in board config file"
#endif /* CFG_HCWD_HIGH */
#if (CFG_HRCW_HIGH & HRCWH_PCI_HOST)
+
# ifndef CONFIG_83XX_CLKIN
-# error "In PCI Host Mode, CONFIG_83XX_CLKIN must be defined in include/configs/MCP83XXADS.h"
+# error "In PCI Host Mode, CONFIG_83XX_CLKIN must be defined in board config file"
# endif /* CONFIG_83XX_CLKIN */
# ifdef CONFIG_83XX_PCICLK
-# warning "In PCI Host Mode, CONFIG_83XX_PCICLK in include/configs/MCP83XXADS.h is igonred."
+# warning "In PCI Host Mode, CONFIG_83XX_PCICLK in board config file is igonred"
# endif /* CONFIG_83XX_PCICLK */
-/* PCI Host Mode */
+
+ /* PCI Host Mode */
if (!(im->reset.rcwh & RCWH_PCIHOST)) {
- /* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH the im->reset.rcwhr PCI Host Mode is disabled */
- /* FIXME: findout if there is a way to issue some warning */
+ /* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH
+ * the im->reset.rcwhr PCI Host Mode is disabled
+ * FIXME: findout if there is a way to issue some warning */
return -2;
}
if (im->clk.spmr & SPMR_CKID) {
- pci_sync_in = CONFIG_83XX_CLKIN / 2; /* PCI Clock is half CONFIG_83XX_CLKIN */
+ /* PCI Clock is half CONFIG_83XX_CLKIN */
+ pci_sync_in = CONFIG_83XX_CLKIN / 2;
}
else {
pci_sync_in = CONFIG_83XX_CLKIN;
}
-#else
+
+#else /* (CFG_HRCW_HIGH & HRCWH_PCI_HOST) */
+
# ifdef CONFIG_83XX_CLKIN
-# warning "In PCI Agent Mode, CONFIG_83XX_CLKIN in include/configs/MCP83XXADS.h is igonred."
+# warning "In PCI Agent Mode, CONFIG_83XX_CLKIN in board config file is igonred"
# endif /* CONFIG_83XX_CLKIN */
# ifndef CONFIG_83XX_PCICLK
-# error "In PCI Agent Mode, CONFIG_83XX_PCICLK must be defined in include/configs/MCP83XXADS.h"
+# error "In PCI Agent Mode, CONFIG_83XX_PCICLK must be defined in board config file"
# endif /* CONFIG_83XX_PCICLK */
-/* PCI Agent Mode */
+
+ /* PCI Agent Mode */
if (im->reset.rcwh & RCWH_PCIHOST) {
- /* though RCWH_PCIHOST is not defined in CFG_HRCW_HIGH the im->reset.rcwhr PCI Host Mode is enabled */
+ /* though RCWH_PCIHOST is not defined in CFG_HRCW_HIGH
+ * the im->reset.rcwhr PCI Host Mode is enabled */
return -3;
}
pci_sync_in = CONFIG_83XX_PCICLK;
+
#endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) */
/* we have up to date pci_sync_in */
gd->lbiu_clk = lbiu_clk ;
gd->lclk_clk = lclk_clk ;
gd->ddr_clk = ddr_clk ;
+ gd->pci_clk = pci_sync_in;
gd->cpu_clk = gd->core_clk;
gd->bus_clk = gd->lbiu_clk;
printf("Clock configuration:\n");
printf(" Coherent System Bus: %4d MHz\n",gd->csb_clk/1000000);
printf(" Core: %4d MHz\n",gd->core_clk/1000000);
- printf(" Local Bus Controller:%4d MHz\n",gd->lbiu_clk/1000000);
+ debug(" Local Bus Controller:%4d MHz\n",gd->lbiu_clk/1000000);
printf(" Local Bus: %4d MHz\n",gd->lclk_clk/1000000);
- printf(" DDR: %4d MHz\n",gd->ddr_clk/1000000);
- printf(" I2C: %4d MHz\n",gd->i2c_clk/1000000);
- printf(" TSEC1: %4d MHz\n",gd->tsec1_clk/1000000);
- printf(" TSEC2: %4d MHz\n",gd->tsec2_clk/1000000);
- printf(" USB MPH: %4d MHz\n",gd->usbmph_clk/1000000);
- printf(" USB DR: %4d MHz\n",gd->usbdr_clk/1000000);
-
-#if 0
- DECLARE_GLOBAL_DATA_PTR;
-
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
- ulong sccr, dfbrg;
- ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf;
- corecnf_t *cp;
-
- sccr = immap->im_clkrst.car_sccr;
- dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
-
- scmr = immap->im_clkrst.car_scmr;
- corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT;
- busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT;
- cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT;
- plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
- pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
-
- cp = &corecnf_tab[corecnf];
-
- puts (CPU_ID_STR " Clock Configuration\n - Bus-to-Core Mult ");
-
- switch (cp->b2c_mult) {
- case _byp:
- puts ("BYPASS");
- break;
+ debug(" DDR: %4d MHz\n",gd->ddr_clk/1000000);
+ debug(" I2C: %4d MHz\n",gd->i2c_clk/1000000);
+ debug(" TSEC1: %4d MHz\n",gd->tsec1_clk/1000000);
+ debug(" TSEC2: %4d MHz\n",gd->tsec2_clk/1000000);
+ debug(" USB MPH: %4d MHz\n",gd->usbmph_clk/1000000);
+ debug(" USB DR: %4d MHz\n",gd->usbdr_clk/1000000);
- case _off:
- puts ("OFF");
- break;
-
- case _unk:
- puts ("UNKNOWN");
- break;
-
- default:
- printf ("%d%sx",
- cp->b2c_mult / 2,
- (cp->b2c_mult % 2) ? ".5" : "");
- break;
- }
-
- printf (", VCO Div %d, 60x Bus Freq %s, Core Freq %s\n",
- cp->vco_div, cp->freq_60x, cp->freq_core);
-
- printf (" - dfbrg %ld, corecnf 0x%02lx, busdf %ld, cpmdf %ld, "
- "plldf %ld, pllmf %ld\n", dfbrg, corecnf, busdf, cpmdf, plldf,
- pllmf);
-
- printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n",
- gd->vco_out, gd->scc_clk, gd->brg_clk);
-
- printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n",
- gd->cpu_clk, gd->cpm_clk, gd->bus_clk);
-
- if (sccr & SCCR_PCI_MODE) {
- uint pci_div;
-
- pci_div = ( (sccr & SCCR_PCI_MODCK) ? 2 : 1) *
- ( ( (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT) + 1);
-
- printf (" - pci_clk %10ld\n", (gd->cpm_clk * 2) / pci_div);
- }
- putc ('\n');
-#endif
return 0;
}
#include <config.h>
#include <net.h>
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+#include <miiphy.h>
+#endif
+
#if defined(CONFIG_CPM2)
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \
* Allocate space in the reserved FCC area of DPRAM for the
* internal buffers. No one uses this space (yet), so we
* can do this. Later, we will add resource management for
- * this area. CPM_FCC_SPECIAL_BASE: 0xb000.
+ * this area.
+ * CPM_FCC_SPECIAL_BASE: 0xB000 for MPC8540, MPC8560
+ * 0x9000 for MPC8541, MPC8555
*/
mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64);
pram_ptr->fen_genfcc.fcc_riptr = mem_addr;
dev->recv = fec_recv;
eth_register(dev);
+
+#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) \
+ && defined(CONFIG_BITBANGMII)
+ miiphy_register(dev->name,
+ bb_miiphy_read, bb_miiphy_write);
+#endif
}
return 1;
* and looking for an <ACK> back.
*/
udelay(10000);
- return i2c_read (chip, 0, 1, (char *)&tmp, 1);
+ return i2c_read (chip, 0, 1, (uchar *)&tmp, 1);
}
uchar i2c_reg_read (uchar i2c_addr, uchar reg)
{
- char buf[1];
+ uchar buf[1];
i2c_read (i2c_addr, reg, 1, buf, 1);
(CFG_IMMR+0x8000),
(CFG_IMMR+0x8004));
- pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
- pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
-
pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
pcix->potear1 = 0x00000000;
pcix->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
*/
pci_register_hose(hose);
+ pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16);
+ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
+
+ /*
+ * Clear non-reserved bits in status register.
+ */
+ pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
+ pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
+
#if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS)
/*
* This is a SW workaround for an apparent HW problem
7: sync /* Wait for all icbi to complete on bus */
isync
+ /*
+ * Re-point the IVPR at RAM
+ */
+ mtspr IVPR,r10
+
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
#if defined(WANT_MII)
#include <miiphy.h>
+
+#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
+#error "CONFIG_MII has to be defined!"
+#endif
+
#endif
#if defined(CONFIG_RMII) && !defined(WANT_MII)
static int mii_discover_phy(struct eth_device *dev);
#endif
+int fec8xx_miiphy_read(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value);
+int fec8xx_miiphy_write(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value);
+
static struct ether_fcc_info_s
{
int ether_index;
dev->recv = fec_recv;
eth_register(dev);
+
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+ miiphy_register(dev->name,
+ fec8xx_miiphy_read, fec8xx_miiphy_write);
+#endif
}
return 1;
}
/*
* adapt the RMII speed to the speed of the phy
*/
- if (miiphy_speed (efis->actual_phy_addr) == _100BASET) {
+ if (miiphy_speed (dev->name, efis->actual_phy_addr) == _100BASET) {
fec_100Mbps (dev);
} else {
fec_10Mbps (dev);
/*
* adapt to the half/full speed settings
*/
- if (miiphy_duplex (efis->actual_phy_addr) == FULL) {
+ if (miiphy_duplex (dev->name, efis->actual_phy_addr) == FULL) {
fec_full_duplex (dev);
} else {
fec_half_duplex (dev);
* Otherwise they hang in mii_send() !!! Sorry!
*****************************************************************************/
-int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value)
+int fec8xx_miiphy_read(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value)
{
short rdreg; /* register working value */
return 0;
}
-int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
+int fec8xx_miiphy_write(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
uchar
i2c_reg_read(uchar i2c_addr, uchar reg)
{
- char buf;
+ uchar buf;
i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
for (i = 0; i < TEST_NUM; i++) {
for (l = TEST_MIN_LENGTH; l <= TEST_MAX_LENGTH; l += 8) {
- packet_fill (txbuf, l);
+ packet_fill ((char *)txbuf, l);
spi_xfer (l);
- if (packet_check (rxbuf, l) < 0) {
+ if (packet_check ((char *)rxbuf, l) < 0) {
goto Done;
}
}
}
}
-static inline void video_drawstring (int xx, int yy, unsigned char *s)
+static inline void video_drawstring (int xx, int yy, char *s)
{
- video_drawchars (xx, yy, s, strlen (s));
+ video_drawchars (xx, yy, (unsigned char *)s, strlen (s));
}
/* Relative to console plotting functions */
static inline void video_putstring (int xx, int yy, unsigned char *s)
{
- video_putchars (xx, yy, s, strlen (s));
+ video_putchars (xx, yy, (unsigned char *)s, strlen ((char *)s));
}
/************************************************************************/
+++ /dev/null
-/*-----------------------------------------------------------------------------+
- *
- * This source code has been made available to you by IBM on an AS-IS
- * basis. Anyone receiving this source is licensed under IBM
- * copyrights to use it in any way he or she deems fit, including
- * copying it, modifying it, compiling it, and redistributing it either
- * with or without modifications. No license under IBM patents or
- * patent applications is to be implied by the copyright license.
- *
- * Any user of this software should understand that IBM cannot provide
- * technical support for this software and will not be responsible for
- * any consequences resulting from the use of this software.
- *
- * Any person who transfers this source code or any derivative work
- * must include the IBM copyright notice, this paragraph, and the
- * preceding two paragraphs in the transferred software.
- *
- * COPYRIGHT I B M CORPORATION 1995
- * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
- *-----------------------------------------------------------------------------*/
-/*-----------------------------------------------------------------------------+
- *
- * File Name: enetemac.c
- *
- * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
- *
- * Author: Mark Wisner
- *
- * Change Activity-
- *
- * Date Description of Change BY
- * --------- --------------------- ---
- * 05-May-99 Created MKW
- * 27-Jun-99 Clean up JWB
- * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
- * 29-Jul-99 Added Full duplex support MKW
- * 06-Aug-99 Changed names for Mal CR reg MKW
- * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
- * 24-Aug-99 Marked descriptor empty after call_xlc MKW
- * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
- * to avoid chaining maximum sized packets. Push starting
- * RX descriptor address up to the next cache line boundary.
- * 16-Jan-00 Added support for booting with IP of 0x0 MKW
- * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
- * EMAC_RXM register. JWB
- * 12-Mar-01 anne-sophie.harnois@nextream.fr
- * - Variables are compatible with those already defined in
- * include/net.h
- * - Receive buffer descriptor ring is used to send buffers
- * to the user
- * - Info print about send/received/handled packet number if
- * INFO_405_ENET is set
- * 17-Apr-01 stefan.roese@esd-electronics.com
- * - MAL reset in "eth_halt" included
- * - Enet speed and duplex output now in one line
- * 08-May-01 stefan.roese@esd-electronics.com
- * - MAL error handling added (eth_init called again)
- * 13-Nov-01 stefan.roese@esd-electronics.com
- * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
- * 04-Jan-02 stefan.roese@esd-electronics.com
- * - Wait for PHY auto negotiation to complete added
- * 06-Feb-02 stefan.roese@esd-electronics.com
- * - Bug fixed in waiting for auto negotiation to complete
- * 26-Feb-02 stefan.roese@esd-electronics.com
- * - rx and tx buffer descriptors now allocated (no fixed address
- * used anymore)
- * 17-Jun-02 stefan.roese@esd-electronics.com
- * - MAL error debug printf 'M' removed (rx de interrupt may
- * occur upon many incoming packets with only 4 rx buffers).
- * 21-Nov-03 pavel.bartusek@sysgo.com
- * - set ZMII bridge speed on 440
- *
- *-----------------------------------------------------------------------------*/
-
-#include <common.h>
-#include <asm/processor.h>
-#include <ppc4xx.h>
-#include <commproc.h>
-#include <405gp_enet.h>
-#include <405_mal.h>
-#include <miiphy.h>
-#include <net.h>
-#include <malloc.h>
-#include "vecnum.h"
-
-#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
- ( defined(CONFIG_440) && !defined(CONFIG_NET_MULTI))
-
-#if !defined(CONFIG_NET_MULTI) || !defined(CONFIG_405EP)
-/* 405GP, 440 with !CONFIG_NET_MULTI. For 440 only EMAC0 is supported */
-#define EMAC_NUM_DEV 1
-#else
-/* 440EP && CONFIG_NET_MULTI */
-#define EMAC_NUM_DEV 2
-#endif
-
-#define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
-#define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
-
-/* Ethernet Transmit and Receive Buffers */
-/* AS.HARNOIS
- * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
- * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
- */
-#define ENET_MAX_MTU PKTSIZE
-#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
-
-/* define the number of channels implemented */
-#define EMAC_RXCHL EMAC_NUM_DEV
-#define EMAC_TXCHL EMAC_NUM_DEV
-
-/*-----------------------------------------------------------------------------+
- * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
- * Interrupt Controller).
- *-----------------------------------------------------------------------------*/
-#define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
-#define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
-#define EMAC_UIC_DEF UIC_ENET
-#define EMAC_UIC_DEF1 UIC_ENET1
-#define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET )
-
-
-/*-----------------------------------------------------------------------------+
- * Global variables. TX and RX descriptors and buffers.
- *-----------------------------------------------------------------------------*/
-/* IER globals */
-static uint32_t mal_ier;
-
-#if !defined(CONFIG_NET_MULTI)
-struct eth_device *emac0_dev;
-#endif
-
-/*-----------------------------------------------------------------------------+
- * Prototypes and externals.
- *-----------------------------------------------------------------------------*/
-static void enet_rcv (struct eth_device *dev, unsigned long malisr);
-
-int enetInt (struct eth_device *dev);
-static void mal_err (struct eth_device *dev, unsigned long isr,
- unsigned long uic, unsigned long maldef,
- unsigned long mal_errr);
-static void emac_err (struct eth_device *dev, unsigned long isr);
-
-/*-----------------------------------------------------------------------------+
-| ppc_405x_eth_halt
-| Disable MAL channel, and EMACn
-|
-|
-+-----------------------------------------------------------------------------*/
-static void ppc_4xx_eth_halt (struct eth_device *dev)
-{
- EMAC_405_HW_PST hw_p = dev->priv;
- uint32_t failsafe = 10000;
-
- mtdcr (malier, 0x00000000); /* disable mal interrupts */
- out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
-
- /* 1st reset MAL channel */
- /* Note: writing a 0 to a channel has no effect */
- mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
- mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
-
- /* wait for reset */
- while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
- udelay (1000); /* Delay 1 MS so as not to hammer the register */
- failsafe--;
- if (failsafe == 0)
- break;
- }
-
- /* EMAC RESET */
- out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
-
- hw_p->print_speed = 1; /* print speed message again next time */
-
- return;
-}
-
-static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
-{
- int i;
- unsigned long reg;
- unsigned long msr;
- unsigned long speed;
- unsigned long duplex;
- unsigned long failsafe;
- unsigned mode_reg;
- unsigned short devnum;
- unsigned short reg_short;
-
- EMAC_405_HW_PST hw_p = dev->priv;
- /* before doing anything, figure out if we have a MAC address */
- /* if not, bail */
- if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0)
- return -1;
-
- msr = mfmsr ();
- mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
-
- devnum = hw_p->devnum;
-
-#ifdef INFO_405_ENET
- /* AS.HARNOIS
- * We should have :
- * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
- * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
- * is possible that new packets (without relationship with
- * current transfer) have got the time to arrived before
- * netloop calls eth_halt
- */
- printf ("About preceeding transfer (eth%d):\n"
- "- Sent packet number %d\n"
- "- Received packet number %d\n"
- "- Handled packet number %d\n",
- hw_p->devnum,
- hw_p->stats.pkts_tx,
- hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
-
- hw_p->stats.pkts_tx = 0;
- hw_p->stats.pkts_rx = 0;
- hw_p->stats.pkts_handled = 0;
-#endif
-
- /* MAL RESET */
- mtdcr (malmcr, MAL_CR_MMSR);
- /* wait for reset */
- while (mfdcr (malmcr) & MAL_CR_MMSR) {
- };
-
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
- out32 (ZMII_FER, 0);
- udelay(100);
- /* set RII mode */
- out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
-#elif defined(CONFIG_440)
- /* set RMII mode */
- out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
-#endif /* CONFIG_440 */
-
- /* MAL Channel RESET */
- /* 1st reset MAL channel */
- /* Note: writing a 0 to a channel has no effect */
- mtdcr (maltxcarr, (MAL_TXRX_CASR >> (hw_p->devnum * 2)));
- mtdcr (malrxcarr, (MAL_TXRX_CASR >> hw_p->devnum));
-
- /* wait for reset */
- /* TBS: should have udelay and failsafe here */
- failsafe = 10000;
- /* wait for reset */
- while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
- udelay (1000); /* Delay 1 MS so as not to hammer the register */
- failsafe--;
- if (failsafe == 0)
- break;
-
- }
-
- hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
- hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
-
- hw_p->rx_slot = 0; /* MAL Receive Slot */
- hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
- hw_p->rx_u_index = 0; /* Receive User Queue Index */
-
- hw_p->tx_slot = 0; /* MAL Transmit Slot */
- hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
- hw_p->tx_u_index = 0; /* Transmit User Queue Index */
-
- __asm__ volatile ("eieio");
-
- /* reset emac so we have access to the phy */
-
- out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
- __asm__ volatile ("eieio");
-
- failsafe = 1000;
- while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
- udelay (1000);
- failsafe--;
- }
-
-#if defined(CONFIG_NET_MULTI)
- reg = hw_p->devnum ? CONFIG_PHY1_ADDR : CONFIG_PHY_ADDR;
-#else
- reg = CONFIG_PHY_ADDR;
-#endif
- /* wait for PHY to complete auto negotiation */
- reg_short = 0;
-#ifndef CONFIG_CS8952_PHY
- miiphy_read (reg, PHY_BMSR, ®_short);
-
- /*
- * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
- */
- if ((reg_short & PHY_BMSR_AUTN_ABLE)
- && !(reg_short & PHY_BMSR_AUTN_COMP)) {
- puts ("Waiting for PHY auto negotiation to complete");
- i = 0;
- while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
- /*
- * Timeout reached ?
- */
- if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
- puts (" TIMEOUT !\n");
- break;
- }
-
- if ((i++ % 1000) == 0) {
- putc ('.');
- }
- udelay (1000); /* 1 ms */
- miiphy_read (reg, PHY_BMSR, ®_short);
- }
- puts (" done\n");
- udelay (500000); /* another 500 ms (results in faster booting) */
- }
-#endif
- speed = miiphy_speed (reg);
- duplex = miiphy_duplex (reg);
-
- if (hw_p->print_speed) {
- hw_p->print_speed = 0;
- printf ("ENET Speed is %d Mbps - %s duplex connection\n",
- (int) speed, (duplex == HALF) ? "HALF" : "FULL");
- }
-
- mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
- /* Errata 1.12: MAL_1 -- Disable MAL bursting */
- if (get_pvr() == PVR_440GP_RB) {
- mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
- }
-
- /* Free "old" buffers */
- if (hw_p->alloc_tx_buf)
- free (hw_p->alloc_tx_buf);
- if (hw_p->alloc_rx_buf)
- free (hw_p->alloc_rx_buf);
-
- /*
- * Malloc MAL buffer desciptors, make sure they are
- * aligned on cache line boundary size
- * (401/403/IOP480 = 16, 405 = 32)
- * and doesn't cross cache block boundaries.
- */
- hw_p->alloc_tx_buf =
- (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) +
- ((2 * CFG_CACHELINE_SIZE) - 2));
- if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) {
- hw_p->tx =
- (mal_desc_t *) ((int) hw_p->alloc_tx_buf +
- CFG_CACHELINE_SIZE -
- ((int) hw_p->
- alloc_tx_buf & CACHELINE_MASK));
- } else {
- hw_p->tx = hw_p->alloc_tx_buf;
- }
-
- hw_p->alloc_rx_buf =
- (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) +
- ((2 * CFG_CACHELINE_SIZE) - 2));
- if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) {
- hw_p->rx =
- (mal_desc_t *) ((int) hw_p->alloc_rx_buf +
- CFG_CACHELINE_SIZE -
- ((int) hw_p->
- alloc_rx_buf & CACHELINE_MASK));
- } else {
- hw_p->rx = hw_p->alloc_rx_buf;
- }
-
- for (i = 0; i < NUM_TX_BUFF; i++) {
- hw_p->tx[i].ctrl = 0;
- hw_p->tx[i].data_len = 0;
- if (hw_p->first_init == 0)
- hw_p->txbuf_ptr =
- (char *) malloc (ENET_MAX_MTU_ALIGNED);
- hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
- if ((NUM_TX_BUFF - 1) == i)
- hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
- hw_p->tx_run[i] = -1;
-#if 0
- printf ("TX_BUFF %d @ 0x%08lx\n", i,
- (ulong) hw_p->tx[i].data_ptr);
-#endif
- }
-
- for (i = 0; i < NUM_RX_BUFF; i++) {
- hw_p->rx[i].ctrl = 0;
- hw_p->rx[i].data_len = 0;
- /* rx[i].data_ptr = (char *) &rx_buff[i]; */
- hw_p->rx[i].data_ptr = (char *) NetRxPackets[i];
- if ((NUM_RX_BUFF - 1) == i)
- hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
- hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
- hw_p->rx_ready[i] = -1;
-#if 0
- printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr);
-#endif
- }
-
- reg = 0x00000000;
- reg |= dev->enetaddr[0]; /* set high address */
- reg = reg << 8;
- reg |= dev->enetaddr[1];
-
- out32 (EMAC_IAH + hw_p->hw_addr, reg);
-
- reg = 0x00000000;
- reg |= dev->enetaddr[2]; /* set low address */
- reg = reg << 8;
- reg |= dev->enetaddr[3];
- reg = reg << 8;
- reg |= dev->enetaddr[4];
- reg = reg << 8;
- reg |= dev->enetaddr[5];
-
- out32 (EMAC_IAL + hw_p->hw_addr, reg);
-
- switch (devnum) {
-#if defined(CONFIG_NET_MULTI)
- case 1:
- /* setup MAL tx & rx channel pointers */
- /* For 405EP, the EMAC1 tx channel 0 is MAL tx channel 2 */
- mtdcr (maltxctp2r, hw_p->tx);
- mtdcr (malrxctp1r, hw_p->rx);
- /* set RX buffer size */
- mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
- break;
-#endif
- case 0:
- default:
- /* setup MAL tx & rx channel pointers */
- mtdcr (maltxctp0r, hw_p->tx);
- mtdcr (malrxctp0r, hw_p->rx);
- /* set RX buffer size */
- mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
- break;
- }
-
- /* Enable MAL transmit and receive channels */
- mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum * 2)));
- mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
-
- /* set transmit enable & receive enable */
- out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
-
- /* set receive fifo to 4k and tx fifo to 2k */
- mode_reg = in32 (EMAC_M1 + hw_p->hw_addr);
- mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
-
- /* set speed */
- if (speed == _100BASET)
- mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
- else
- mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
- if (duplex == FULL)
- mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
-
- out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
-
-#if defined(CONFIG_440)
- /* set speed in the ZMII bridge */
- if (speed == _100BASET)
- out32(ZMII_SSR, in32(ZMII_SSR) | 0x10000000);
- else
- out32(ZMII_SSR, in32(ZMII_SSR) & ~0x10000000);
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
- mfsdr(sdr_mfr, reg);
- /* set speed */
- if (speed == _100BASET) {
- out32(ZMII_SSR, in32(ZMII_SSR) | 0x10000000);
- reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
- } else {
- reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
- out32(ZMII_SSR, in32(ZMII_SSR) & ~0x10000000);
- }
- mtsdr(sdr_mfr, reg);
-#endif
-#endif
-
- /* Enable broadcast and indvidual address */
- /* TBS: enabling runts as some misbehaved nics will send runts */
- out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
-
- /* we probably need to set the tx mode1 reg? maybe at tx time */
-
- /* set transmit request threshold register */
- out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
-
-#if defined(CONFIG_440)
- /* 440GP has a 64 byte burst length */
- out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
- out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
-#else
- /* 405s have a 16 byte burst length */
- out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
-#endif
-
- /* Frame gap set */
- out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
-
- /* Set EMAC IER */
- hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS |
- EMAC_ISR_ORE | EMAC_ISR_IRE;
- if (speed == _100BASET)
- hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
-
- out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
- out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
-
- if (hw_p->first_init == 0) {
- /*
- * Connect interrupt service routines
- */
- irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2),
- (interrupt_handler_t *) enetInt, dev);
- }
-
- mtmsr (msr); /* enable interrupts again */
-
- hw_p->bis = bis;
- hw_p->first_init = 1;
-
- return (1);
-}
-
-
-static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, int len)
-{
- struct enet_frame *ef_ptr;
- ulong time_start, time_now;
- unsigned long temp_txm0;
- EMAC_405_HW_PST hw_p = dev->priv;
-
- ef_ptr = (struct enet_frame *) ptr;
-
- /*-----------------------------------------------------------------------+
- * Copy in our address into the frame.
- *-----------------------------------------------------------------------*/
- (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
-
- /*-----------------------------------------------------------------------+
- * If frame is too long or too short, modify length.
- *-----------------------------------------------------------------------*/
- /* TBS: where does the fragment go???? */
- if (len > ENET_MAX_MTU)
- len = ENET_MAX_MTU;
-
- /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
- memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
-
- /*-----------------------------------------------------------------------+
- * set TX Buffer busy, and send it
- *-----------------------------------------------------------------------*/
- hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
- EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
- ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
- if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
- hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
-
- hw_p->tx[hw_p->tx_slot].data_len = (short) len;
- hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
-
- __asm__ volatile ("eieio");
-
- out32 (EMAC_TXM0 + hw_p->hw_addr,
- in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
-#ifdef INFO_405_ENET
- hw_p->stats.pkts_tx++;
-#endif
-
- /*-----------------------------------------------------------------------+
- * poll unitl the packet is sent and then make sure it is OK
- *-----------------------------------------------------------------------*/
- time_start = get_timer (0);
- while (1) {
- temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr);
- /* loop until either TINT turns on or 3 seconds elapse */
- if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
- /* transmit is done, so now check for errors
- * If there is an error, an interrupt should
- * happen when we return
- */
- time_now = get_timer (0);
- if ((time_now - time_start) > 3000) {
- return (-1);
- }
- } else {
- return (len);
- }
- }
-}
-
-#if defined(CONFIG_440)
-int enetInt (struct eth_device *dev)
-{
- int serviced;
- int rc = -1; /* default to not us */
- unsigned long mal_isr;
- unsigned long emac_isr = 0;
- unsigned long mal_rx_eob;
- unsigned long my_uic0msr, my_uic1msr;
- EMAC_405_HW_PST hw_p;
-
- /*
- * Because the mal is generic, we need to get the current
- * eth device
- */
-#if defined(CONFIG_NET_MULTI)
- dev = eth_get_dev();
-#else
- dev = emac0_dev;
-#endif
- hw_p = dev->priv;
-
- /* enter loop that stays in interrupt code until nothing to service */
- do {
- serviced = 0;
-
- my_uic0msr = mfdcr (uic0msr);
- my_uic1msr = mfdcr (uic1msr);
-
- if (!(my_uic0msr & UIC_MRE)
- && !(my_uic1msr & (UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE))) {
- /* not for us */
- return (rc);
- }
-
- /* get and clear controller status interrupts */
- /* look at Mal and EMAC interrupts */
- if ((my_uic0msr & UIC_MRE)
- || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
- /* we have a MAL interrupt */
- mal_isr = mfdcr (malesr);
- /* look for mal error */
- if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
- mal_err (dev, mal_isr, my_uic0msr, MAL_UIC_DEF, MAL_UIC_ERR);
- serviced = 1;
- rc = 0;
- }
- }
- if (UIC_ETH0 & my_uic1msr) { /* look for EMAC errors */
- emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
- if ((hw_p->emac_ier & emac_isr) != 0) {
- emac_err (dev, emac_isr);
- serviced = 1;
- rc = 0;
- }
- }
- if ((hw_p->emac_ier & emac_isr)
- || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
- mtdcr (uic0sr, UIC_MRE); /* Clear */
- mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
- return (rc); /* we had errors so get out */
- }
-
- /* handle MAL RX EOB interupt from a receive */
- /* check for EOB on valid channels */
- if (my_uic0msr & UIC_MRE) {
- mal_rx_eob = mfdcr (malrxeobisr);
- if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel 0 */
- /* clear EOB
- mtdcr(malrxeobisr, mal_rx_eob); */
- enet_rcv (dev, emac_isr);
- /* indicate that we serviced an interrupt */
- serviced = 1;
- rc = 0;
- }
- }
- mtdcr (uic0sr, UIC_MRE); /* Clear */
- mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
- } while (serviced);
-
- return (rc);
-}
-
-#else /* CONFIG_440 */
-
-int enetInt (struct eth_device *dev)
-{
- int serviced;
- int rc = -1; /* default to not us */
- unsigned long mal_isr;
- unsigned long emac_isr = 0;
- unsigned long mal_rx_eob;
- unsigned long my_uicmsr;
-
- EMAC_405_HW_PST hw_p;
-
- /*
- * Because the mal is generic, we need to get the current
- * eth device
- */
-#if defined(CONFIG_NET_MULTI)
- dev = eth_get_dev();
-#else
- dev = emac0_dev;
-#endif
-
- hw_p = dev->priv;
-
- /* enter loop that stays in interrupt code until nothing to service */
- do {
- serviced = 0;
-
- my_uicmsr = mfdcr (uicmsr);
-
- if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */
- return (rc);
- }
- /* get and clear controller status interrupts */
- /* look at Mal and EMAC interrupts */
- if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */
- mal_isr = mfdcr (malesr);
- /* look for mal error */
- if ((my_uicmsr & MAL_UIC_ERR) != 0) {
- mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR);
- serviced = 1;
- rc = 0;
- }
- }
-
- /* port by port dispatch of emac interrupts */
-
- if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */
- emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
- if ((hw_p->emac_ier & emac_isr) != 0) {
- emac_err (dev, emac_isr);
- serviced = 1;
- rc = 0;
- }
- }
- if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) {
- mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */
- return (rc); /* we had errors so get out */
- }
-
- /* handle MAX TX EOB interrupt from a tx */
- if (my_uicmsr & UIC_MAL_TXEOB) {
- mal_rx_eob = mfdcr (maltxeobisr);
- mtdcr (maltxeobisr, mal_rx_eob);
- mtdcr (uicsr, UIC_MAL_TXEOB);
- }
- /* handle MAL RX EOB interupt from a receive */
- /* check for EOB on valid channels */
- if (my_uicmsr & UIC_MAL_RXEOB)
- {
- mal_rx_eob = mfdcr (malrxeobisr);
- if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
- /* clear EOB
- mtdcr(malrxeobisr, mal_rx_eob); */
- enet_rcv (dev, emac_isr);
- /* indicate that we serviced an interrupt */
- serviced = 1;
- rc = 0;
- }
- }
- mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */
- }
- while (serviced);
-
- return (rc);
-}
-#endif
-/*-----------------------------------------------------------------------------+
- * MAL Error Routine
- *-----------------------------------------------------------------------------*/
-static void mal_err (struct eth_device *dev, unsigned long isr,
- unsigned long uic, unsigned long maldef,
- unsigned long mal_errr)
-{
- EMAC_405_HW_PST hw_p = dev->priv;
-
- mtdcr (malesr, isr); /* clear interrupt */
-
- /* clear DE interrupt */
- mtdcr (maltxdeir, 0xC0000000);
- mtdcr (malrxdeir, 0x80000000);
-
-#ifdef INFO_405_ENET
- printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
-#endif
-
- eth_init (hw_p->bis); /* start again... */
-}
-
-/*-----------------------------------------------------------------------------+
- * EMAC Error Routine
- *-----------------------------------------------------------------------------*/
-static void emac_err (struct eth_device *dev, unsigned long isr)
-{
- EMAC_405_HW_PST hw_p = dev->priv;
-
- printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
- out32 (EMAC_ISR + hw_p->hw_addr, isr);
-}
-
-/*-----------------------------------------------------------------------------+
- * enet_rcv() handles the ethernet receive data
- *-----------------------------------------------------------------------------*/
-static void enet_rcv (struct eth_device *dev, unsigned long malisr)
-{
- struct enet_frame *ef_ptr;
- unsigned long data_len;
- unsigned long rx_eob_isr;
- EMAC_405_HW_PST hw_p = dev->priv;
-
- int handled = 0;
- int i;
- int loop_count = 0;
-
- rx_eob_isr = mfdcr (malrxeobisr);
- if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) {
- /* clear EOB */
- mtdcr (malrxeobisr, rx_eob_isr);
-
- /* EMAC RX done */
- while (1) { /* do all */
- i = hw_p->rx_slot;
-
- if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
- || (loop_count >= NUM_RX_BUFF))
- break;
- loop_count++;
- hw_p->rx_slot++;
- if (NUM_RX_BUFF == hw_p->rx_slot)
- hw_p->rx_slot = 0;
- handled++;
- data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */
- if (data_len) {
- if (data_len > ENET_MAX_MTU) /* Check len */
- data_len = 0;
- else {
- if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
- data_len = 0;
- hw_p->stats.rx_err_log[hw_p->
- rx_err_index]
- = hw_p->rx[i].ctrl;
- hw_p->rx_err_index++;
- if (hw_p->rx_err_index ==
- MAX_ERR_LOG)
- hw_p->rx_err_index =
- 0;
- } /* emac_erros */
- } /* data_len < max mtu */
- } /* if data_len */
- if (!data_len) { /* no data */
- hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
-
- hw_p->stats.data_len_err++; /* Error at Rx */
- }
-
- /* !data_len */
- /* AS.HARNOIS */
- /* Check if user has already eaten buffer */
- /* if not => ERROR */
- else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
- if (hw_p->is_receiving)
- printf ("ERROR : Receive buffers are full!\n");
- break;
- } else {
- hw_p->stats.rx_frames++;
- hw_p->stats.rx += data_len;
- ef_ptr = (struct enet_frame *) hw_p->rx[i].
- data_ptr;
-#ifdef INFO_405_ENET
- hw_p->stats.pkts_rx++;
-#endif
- /* AS.HARNOIS
- * use ring buffer
- */
- hw_p->rx_ready[hw_p->rx_i_index] = i;
- hw_p->rx_i_index++;
- if (NUM_RX_BUFF == hw_p->rx_i_index)
- hw_p->rx_i_index = 0;
-
- /* printf("X"); /|* test-only *|/ */
-
- /* AS.HARNOIS
- * free receive buffer only when
- * buffer has been handled (eth_rx)
- rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
- */
- } /* if data_len */
- } /* while */
- } /* if EMACK_RXCHL */
-}
-
-
-static int ppc_4xx_eth_rx (struct eth_device *dev)
-{
- int length;
- int user_index;
- unsigned long msr;
- EMAC_405_HW_PST hw_p = dev->priv;
-
- hw_p->is_receiving = 1; /* tell driver */
-
- for (;;) {
- /* AS.HARNOIS
- * use ring buffer and
- * get index from rx buffer desciptor queue
- */
- user_index = hw_p->rx_ready[hw_p->rx_u_index];
- if (user_index == -1) {
- length = -1;
- break; /* nothing received - leave for() loop */
- }
-
- msr = mfmsr ();
- mtmsr (msr & ~(MSR_EE));
-
- length = hw_p->rx[user_index].data_len;
-
- /* Pass the packet up to the protocol layers. */
- /* NetReceive(NetRxPackets[rxIdx], length - 4); */
- /* NetReceive(NetRxPackets[i], length); */
- NetReceive (NetRxPackets[user_index], length - 4);
- /* Free Recv Buffer */
- hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
- /* Free rx buffer descriptor queue */
- hw_p->rx_ready[hw_p->rx_u_index] = -1;
- hw_p->rx_u_index++;
- if (NUM_RX_BUFF == hw_p->rx_u_index)
- hw_p->rx_u_index = 0;
-
-#ifdef INFO_405_ENET
- hw_p->stats.pkts_handled++;
-#endif
-
- mtmsr (msr); /* Enable IRQ's */
- }
-
- hw_p->is_receiving = 0; /* tell driver */
-
- return length;
-}
-
-static int virgin = 0;
-int ppc_4xx_eth_initialize (bd_t * bis)
-{
- struct eth_device *dev;
- int eth_num = 0;
-
- EMAC_405_HW_PST hw = NULL;
-
- for (eth_num = 0; eth_num < EMAC_NUM_DEV; eth_num++) {
-
- /* Allocate device structure */
- dev = (struct eth_device *) malloc (sizeof (*dev));
- if (dev == NULL) {
- printf ("ppc_405x_eth_initialize: "
- "Cannot allocate eth_device %d\n", eth_num);
- return (-1);
- }
- memset(dev, 0, sizeof(*dev));
- /* Allocate our private use data */
- hw = (EMAC_405_HW_PST) malloc (sizeof (*hw));
- if (hw == NULL) {
- printf ("ppc_405x_eth_initialize: "
- "Cannot allocate private hw data for eth_device %d",
- eth_num);
- free (dev);
- return (-1);
- }
- memset(hw, 0, sizeof(*hw));
-
- switch (eth_num) {
- case 0:
- hw->hw_addr = 0;
- memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
- break;
-#if defined(CONFIG_NET_MULTI)
- case 1:
- hw->hw_addr = 0x100;
- memcpy (dev->enetaddr, bis->bi_enet1addr, 6);
- break;
-#endif
- default:
- hw->hw_addr = 0;
- memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
- break;
- }
-
- hw->devnum = eth_num;
- hw->print_speed = 1;
-
- sprintf (dev->name, "ppc_405x_eth%d", eth_num);
- dev->priv = (void *) hw;
- dev->init = ppc_4xx_eth_init;
- dev->halt = ppc_4xx_eth_halt;
- dev->send = ppc_4xx_eth_send;
- dev->recv = ppc_4xx_eth_rx;
-
- if (0 == virgin) {
- /* set the MAL IER ??? names may change with new spec ??? */
- mal_ier =
- MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
- MAL_IER_OPBE | MAL_IER_PLBE;
- mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
- mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
- mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
- mtdcr (malier, mal_ier);
-
- /* install MAL interrupt handler */
- irq_install_handler (VECNUM_MS,
- (interrupt_handler_t *) enetInt,
- dev);
- irq_install_handler (VECNUM_MTE,
- (interrupt_handler_t *) enetInt,
- dev);
- irq_install_handler (VECNUM_MRE,
- (interrupt_handler_t *) enetInt,
- dev);
- irq_install_handler (VECNUM_TXDE,
- (interrupt_handler_t *) enetInt,
- dev);
- irq_install_handler (VECNUM_RXDE,
- (interrupt_handler_t *) enetInt,
- dev);
- virgin = 1;
- }
-
-#if defined(CONFIG_NET_MULTI)
- eth_register (dev);
-#else
- emac0_dev = dev;
-#endif
-
- } /* end for each supported device */
-
- return (1);
-}
-
-#if !defined(CONFIG_NET_MULTI)
-void eth_halt (void) {
- if (emac0_dev) {
- ppc_4xx_eth_halt(emac0_dev);
- free(emac0_dev);
- emac0_dev = NULL;
- }
-}
-
-int eth_init (bd_t *bis)
-{
- ppc_4xx_eth_initialize(bis);
- return(ppc_4xx_eth_init(emac0_dev, bis));
-}
-
-int eth_send(volatile void *packet, int length)
-{
-
- return (ppc_4xx_eth_send(emac0_dev, packet, length));
-}
-
-int eth_rx(void)
-{
- return (ppc_4xx_eth_rx(emac0_dev));
-}
-#endif
-
-#endif /* CONFIG_405 */
#ifdef CONFIG_PCI
+#if defined(CONFIG_PMC405)
+ushort pmc405_pci_subsys_deviceid(void);
+#endif
+
/*#define DEBUG*/
/*-----------------------------------------------------------------------------+
unsigned short temp_short;
unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI};
#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
- unsigned long ptmla[2] = {bd->bi_memstart, bd->bi_flashstart};
- unsigned long ptmms[2] = {~(bd->bi_memsize - 1) | 1, ~(bd->bi_flashsize - 1) | 1};
char *ptmla_str, *ptmms_str;
-#else
+#endif
unsigned long ptmla[2] = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA};
unsigned long ptmms[2] = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS};
-#endif
#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0};
unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0};
void pci_440_init (struct pci_controller *hose)
{
int reg_num = 0;
- unsigned long strap;
+#ifndef CONFIG_DISABLE_PISE_TEST
/*--------------------------------------------------------------------------+
* The PCI initialization sequence enable bit must be set ... if not abort
* pci setup since updating the bit requires chip reset.
*--------------------------------------------------------------------------*/
-#if defined (CONFIG_440GX) || defined (CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
+ unsigned long strap;
+
mfsdr(sdr_sdstp1,strap);
- if ( (strap & 0x00010000) == 0 ){
+ if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
printf("PCI: SDR0_STRP1[PISE] not set.\n");
printf("PCI: Configuration aborted.\n");
return;
}
-#else
+#elif defined(CONFIG_440GP)
+ unsigned long strap;
+
strap = mfdcr(cpc0_strp1);
- if( (strap & 0x00040000) == 0 ){
+ if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
printf("PCI: CPC0_STRP1[PISE] not set.\n");
printf("PCI: Configuration aborted.\n");
return;
}
#endif
+#endif /* CONFIG_DISABLE_PISE_TEST */
+
/*--------------------------------------------------------------------------+
* PCI controller init
*--------------------------------------------------------------------------*/
pci_set_region(hose->regions + reg_num++,
0x00000000,
- PCIX0_IOBASE,
- 0x10000,
- PCI_REGION_IO);
+ PCIX0_IOBASE,
+ 0x10000,
+ PCI_REGION_IO);
pci_set_region(hose->regions + reg_num++,
CFG_PCI_TARGBASE,
- CFG_PCI_MEMBASE,
- 0x10000000,
- PCI_REGION_MEM );
+ CFG_PCI_MEMBASE,
+ 0x10000000,
+ PCI_REGION_MEM );
hose->region_count = reg_num;
pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA);
#if defined(CFG_PCI_PRE_INIT)
- /* Let board change/modify hose & do initial checks */
- if( pci_pre_init (hose) == 0 ){
- printf("PCI: Board-specific initialization failed.\n");
- printf("PCI: Configuration aborted.\n");
- return;
- }
+ /* Let board change/modify hose & do initial checks */
+ if (pci_pre_init (hose) == 0) {
+ printf("PCI: Board-specific initialization failed.\n");
+ printf("PCI: Configuration aborted.\n");
+ return;
+ }
#endif
pci_register_hose( hose );
#if defined(CFG_PCI_TARGET_INIT)
pci_target_init(hose); /* Let board setup pci target */
#else
- out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
- out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID );
- out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
+ out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
+ out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID );
+ out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
#endif
#if defined(CONFIG_440GX)
out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE );
out32r( PCIX0_POM0PCIAH, 0x00000000 );
out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
- out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
+ out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
#endif
/*--------------------------------------------------------------------------+
* PCI host configuration -- we don't make any assumptions here ... the
- * _board_must_indicate_ what to do -- there's just too many runtime
- * scenarios in environments like cPCI, PPMC, etc. to make a determination
- * based on hard-coded values or state of arbiter enable.
+ * _board_must_indicate_ what to do -- there's just too many runtime
+ * scenarios in environments like cPCI, PPMC, etc. to make a determination
+ * based on hard-coded values or state of arbiter enable.
*--------------------------------------------------------------------------*/
- if( is_pci_host(hose) ){
+ if (is_pci_host(hose)) {
#ifdef CONFIG_PCI_SCAN_SHOW
- printf("PCI: Bus Dev VenId DevId Class Int\n");
+ printf("PCI: Bus Dev VenId DevId Class Int\n");
#endif
#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
- out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
+ out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
#endif
- hose->last_busno = pci_hose_scan(hose);
- }
+ hose->last_busno = pci_hose_scan(hose);
+ }
}
/*-----------------------------------------------------------------------------+
*
- * This source code has been made available to you by IBM on an AS-IS
- * basis. Anyone receiving this source is licensed under IBM
- * copyrights to use it in any way he or she deems fit, including
- * copying it, modifying it, compiling it, and redistributing it either
- * with or without modifications. No license under IBM patents or
- * patent applications is to be implied by the copyright license.
+ * This source code has been made available to you by IBM on an AS-IS
+ * basis. Anyone receiving this source is licensed under IBM
+ * copyrights to use it in any way he or she deems fit, including
+ * copying it, modifying it, compiling it, and redistributing it either
+ * with or without modifications. No license under IBM patents or
+ * patent applications is to be implied by the copyright license.
*
- * Any user of this software should understand that IBM cannot provide
- * technical support for this software and will not be responsible for
- * any consequences resulting from the use of this software.
+ * Any user of this software should understand that IBM cannot provide
+ * technical support for this software and will not be responsible for
+ * any consequences resulting from the use of this software.
*
- * Any person who transfers this source code or any derivative work
- * must include the IBM copyright notice, this paragraph, and the
- * preceding two paragraphs in the transferred software.
+ * Any person who transfers this source code or any derivative work
+ * must include the IBM copyright notice, this paragraph, and the
+ * preceding two paragraphs in the transferred software.
*
- * COPYRIGHT I B M CORPORATION 1995
- * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
+ * COPYRIGHT I B M CORPORATION 1995
+ * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
*-----------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------+
*
- * File Name: enetemac.c
+ * File Name: enetemac.c
*
- * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
+ * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
*
- * Author: Mark Wisner
+ * Author: Mark Wisner
*
* Change Activity-
*
- * Date Description of Change BY
- * --------- --------------------- ---
- * 05-May-99 Created MKW
- * 27-Jun-99 Clean up JWB
- * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
- * 29-Jul-99 Added Full duplex support MKW
- * 06-Aug-99 Changed names for Mal CR reg MKW
- * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
- * 24-Aug-99 Marked descriptor empty after call_xlc MKW
- * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
- * to avoid chaining maximum sized packets. Push starting
- * RX descriptor address up to the next cache line boundary.
- * 16-Jan-00 Added support for booting with IP of 0x0 MKW
- * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
- * EMAC_RXM register. JWB
- * 12-Mar-01 anne-sophie.harnois@nextream.fr
- * - Variables are compatible with those already defined in
- * include/net.h
- * - Receive buffer descriptor ring is used to send buffers
- * to the user
- * - Info print about send/received/handled packet number if
- * INFO_405_ENET is set
- * 17-Apr-01 stefan.roese@esd-electronics.com
- * - MAL reset in "eth_halt" included
- * - Enet speed and duplex output now in one line
- * 08-May-01 stefan.roese@esd-electronics.com
- * - MAL error handling added (eth_init called again)
- * 13-Nov-01 stefan.roese@esd-electronics.com
- * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
- * 04-Jan-02 stefan.roese@esd-electronics.com
- * - Wait for PHY auto negotiation to complete added
- * 06-Feb-02 stefan.roese@esd-electronics.com
- * - Bug fixed in waiting for auto negotiation to complete
- * 26-Feb-02 stefan.roese@esd-electronics.com
- * - rx and tx buffer descriptors now allocated (no fixed address
- * used anymore)
- * 17-Jun-02 stefan.roese@esd-electronics.com
- * - MAL error debug printf 'M' removed (rx de interrupt may
- * occur upon many incoming packets with only 4 rx buffers).
+ * Date Description of Change BY
+ * --------- --------------------- ---
+ * 05-May-99 Created MKW
+ * 27-Jun-99 Clean up JWB
+ * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
+ * 29-Jul-99 Added Full duplex support MKW
+ * 06-Aug-99 Changed names for Mal CR reg MKW
+ * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
+ * 24-Aug-99 Marked descriptor empty after call_xlc MKW
+ * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
+ * to avoid chaining maximum sized packets. Push starting
+ * RX descriptor address up to the next cache line boundary.
+ * 16-Jan-00 Added support for booting with IP of 0x0 MKW
+ * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
+ * EMAC_RXM register. JWB
+ * 12-Mar-01 anne-sophie.harnois@nextream.fr
+ * - Variables are compatible with those already defined in
+ * include/net.h
+ * - Receive buffer descriptor ring is used to send buffers
+ * to the user
+ * - Info print about send/received/handled packet number if
+ * INFO_405_ENET is set
+ * 17-Apr-01 stefan.roese@esd-electronics.com
+ * - MAL reset in "eth_halt" included
+ * - Enet speed and duplex output now in one line
+ * 08-May-01 stefan.roese@esd-electronics.com
+ * - MAL error handling added (eth_init called again)
+ * 13-Nov-01 stefan.roese@esd-electronics.com
+ * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
+ * 04-Jan-02 stefan.roese@esd-electronics.com
+ * - Wait for PHY auto negotiation to complete added
+ * 06-Feb-02 stefan.roese@esd-electronics.com
+ * - Bug fixed in waiting for auto negotiation to complete
+ * 26-Feb-02 stefan.roese@esd-electronics.com
+ * - rx and tx buffer descriptors now allocated (no fixed address
+ * used anymore)
+ * 17-Jun-02 stefan.roese@esd-electronics.com
+ * - MAL error debug printf 'M' removed (rx de interrupt may
+ * occur upon many incoming packets with only 4 rx buffers).
*-----------------------------------------------------------------------------*
- * 17-Nov-03 travis.sawyer@sandburst.com
- * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
- * in the 440GX. This port should work with the 440GP
- * (2 EMACs) also
+ * 17-Nov-03 travis.sawyer@sandburst.com
+ * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
+ * in the 440GX. This port should work with the 440GP
+ * (2 EMACs) also
+ * 15-Aug-05 sr@denx.de
+ * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
+ now handling all 4xx cpu's.
*-----------------------------------------------------------------------------*/
#include <config.h>
-#if defined(CONFIG_440) && defined(CONFIG_NET_MULTI)
-
#include <common.h>
#include <net.h>
#include <asm/processor.h>
-#include <ppc440.h>
#include <commproc.h>
-#include <440gx_enet.h>
+#include <ppc4xx.h>
+#include <ppc4xx_enet.h>
#include <405_mal.h>
#include <miiphy.h>
#include <malloc.h>
#include "vecnum.h"
+/*
+ * Only compile for platform with AMCC EMAC ethernet controller and
+ * network support enabled.
+ * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller!
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480)
-#define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
-#define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
+#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
+#error "CONFIG_MII has to be defined!"
+#endif
+
+#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI)
+#error "CONFIG_NET_MULTI has to be defined for NetConsole"
+#endif
+#define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
+#define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
/* Ethernet Transmit and Receive Buffers */
/* AS.HARNOIS
* In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
* PKTSIZE and PKTSIZE_ALIGN (include/net.h)
*/
-#define ENET_MAX_MTU PKTSIZE
+#define ENET_MAX_MTU PKTSIZE
#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
-
-/* define the number of channels implemented */
-#define EMAC_RXCHL EMAC_NUM_DEV
-#define EMAC_TXCHL EMAC_NUM_DEV
-
/*-----------------------------------------------------------------------------+
* Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
* Interrupt Controller).
#define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
#define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
#define EMAC_UIC_DEF UIC_ENET
+#define EMAC_UIC_DEF1 UIC_ENET1
+#define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET )
-#undef INFO_440_ENET
+#undef INFO_4XX_ENET
-#define BI_PHYMODE_NONE 0
-#define BI_PHYMODE_ZMII 1
+#define BI_PHYMODE_NONE 0
+#define BI_PHYMODE_ZMII 1
#define BI_PHYMODE_RGMII 2
+
/*-----------------------------------------------------------------------------+
* Global variables. TX and RX descriptors and buffers.
*-----------------------------------------------------------------------------*/
/* IER globals */
static uint32_t mal_ier;
+#if !defined(CONFIG_NET_MULTI)
+struct eth_device *emac0_dev = NULL;
+#endif
+
+/*
+ * Get count of EMAC devices (doesn't have to be the max. possible number
+ * supported by the cpu)
+ */
+#if defined(CONFIG_HAS_ETH3)
+#define LAST_EMAC_NUM 4
+#elif defined(CONFIG_HAS_ETH2)
+#define LAST_EMAC_NUM 3
+#elif defined(CONFIG_HAS_ETH1)
+#define LAST_EMAC_NUM 2
+#else
+#define LAST_EMAC_NUM 1
+#endif
+
/*-----------------------------------------------------------------------------+
* Prototypes and externals.
*-----------------------------------------------------------------------------*/
unsigned long mal_errr);
static void emac_err (struct eth_device *dev, unsigned long isr);
+extern int phy_setup_aneg (char *devname, unsigned char addr);
+extern int emac4xx_miiphy_read (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value);
+extern int emac4xx_miiphy_write (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value);
+
/*-----------------------------------------------------------------------------+
-| ppc_440x_eth_halt
+| ppc_4xx_eth_halt
| Disable MAL channel, and EMACn
-|
-|
+-----------------------------------------------------------------------------*/
-static void ppc_440x_eth_halt (struct eth_device *dev)
+static void ppc_4xx_eth_halt (struct eth_device *dev)
{
- EMAC_440GX_HW_PST hw_p = dev->priv;
+ EMAC_4XX_HW_PST hw_p = dev->priv;
uint32_t failsafe = 10000;
out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
/* 1st reset MAL channel */
/* Note: writing a 0 to a channel has no effect */
+#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+ mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
+#else
mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum));
+#endif
mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
/* wait for reset */
- while (mfdcr (maltxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
+ while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
udelay (1000); /* Delay 1 MS so as not to hammer the register */
failsafe--;
if (failsafe == 0)
break;
-
}
/* EMAC RESET */
out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
+#ifndef CONFIG_NETCONSOLE
hw_p->print_speed = 1; /* print speed message again next time */
+#endif
return;
}
-extern int phy_setup_aneg (unsigned char addr);
-extern int miiphy_reset (unsigned char addr);
-
#if defined (CONFIG_440GX)
-int ppc_440x_eth_setup_bridge(int devnum, bd_t * bis)
+int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
{
unsigned long pfc1;
unsigned long zmiifer;
}
#endif
-static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
+static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
{
int i, j;
- unsigned long reg;
+ unsigned long reg = 0;
unsigned long msr;
unsigned long speed;
unsigned long duplex;
unsigned mode_reg;
unsigned short devnum;
unsigned short reg_short;
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
sys_info_t sysinfo;
#if defined(CONFIG_440GX)
- int ethgroup;
+ int ethgroup = -1;
+#endif
#endif
- EMAC_440GX_HW_PST hw_p = dev->priv;
+ EMAC_4XX_HW_PST hw_p = dev->priv;
/* before doing anything, figure out if we have a MAC address */
/* if not, bail */
- if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0)
+ if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) {
+ printf("ERROR: ethaddr not set!\n");
return -1;
+ }
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
/* Need to get the OPB frequency so we can access the PHY */
get_sys_info (&sysinfo);
+#endif
msr = mfmsr ();
mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
devnum = hw_p->devnum;
-#ifdef INFO_440_ENET
+#ifdef INFO_4XX_ENET
/* AS.HARNOIS
* We should have :
- * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
+ * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
* In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
* is possible that new packets (without relationship with
* current transfer) have got the time to arrived before
hw_p->stats.pkts_handled = 0;
#endif
- /* MAL Channel RESET */
- /* 1st reset MAL channel */
- /* Note: writing a 0 to a channel has no effect */
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
- mtdcr (maltxcarr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
-#else
- mtdcr (maltxcarr, (MAL_TXRX_CASR >> hw_p->devnum));
-#endif
-
- mtdcr (malrxcarr, (MAL_TXRX_CASR >> hw_p->devnum));
-
- /* wait for reset */
- /* TBS: should have udelay and failsafe here */
- failsafe = 10000;
- /* wait for reset */
- while (mfdcr (maltxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
- udelay (1000); /* Delay 1 MS so as not to hammer the register */
- failsafe--;
- if (failsafe == 0)
- break;
-
- }
-
- hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
- hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
+ hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
+ hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
hw_p->rx_slot = 0; /* MAL Receive Slot */
hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
hw_p->tx_u_index = 0; /* Transmit User Queue Index */
+#if defined(CONFIG_440) && !defined(CONFIG_440SP)
/* set RMII mode */
/* NOTE: 440GX spec states that mode is mutually exclusive */
/* NOTE: Therefore, disable all other EMACS, since we handle */
udelay (100);
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
- out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
+ out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
#elif defined(CONFIG_440GX)
- ethgroup = ppc_440x_eth_setup_bridge(devnum, bis);
+ ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
+#elif defined(CONFIG_440GP)
+ /* set RMII mode */
+ out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
#else
if ((devnum == 0) || (devnum == 1)) {
out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
#endif
out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
+#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
+
__asm__ volatile ("eieio");
/* reset emac so we have access to the phy */
failsafe--;
}
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
/* Whack the M1 register */
mode_reg = 0x0;
mode_reg &= ~0x00000038;
mode_reg |= EMAC_M1_OBCI_GT100;
out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
-#endif /* defined(CONFIG_440GX) */
+#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
/* wait for PHY to complete auto negotiation */
reg_short = 0;
case 0:
reg = CONFIG_PHY_ADDR;
break;
+#if defined (CONFIG_PHY1_ADDR)
case 1:
reg = CONFIG_PHY1_ADDR;
break;
+#endif
#if defined (CONFIG_440GX)
case 2:
reg = CONFIG_PHY2_ADDR;
bis->bi_phynum[devnum] = reg;
-#ifndef CONFIG_NO_PHY_RESET
+#if defined(CONFIG_PHY_RESET)
/*
* Reset the phy, only if its the first time through
* otherwise, just check the speeds & feeds
*/
if (hw_p->first_init == 0) {
- miiphy_reset (reg);
+ miiphy_reset (dev->name, reg);
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
#if defined(CONFIG_CIS8201_PHY)
/*
* Cicada 8201 PHY needs to have an extended register whacked
*/
if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) {
#if defined(CONFIG_CIS8201_SHORT_ETCH)
- miiphy_write (reg, 23, 0x1300);
+ miiphy_write (dev->name, reg, 23, 0x1300);
#else
- miiphy_write (reg, 23, 0x1000);
+ miiphy_write (dev->name, reg, 23, 0x1000);
#endif
/*
* Vitesse VSC8201/Cicada CIS8201 errata:
* This work around (provided by Vitesse) changes
* the default timer convergence from 8ms to 12ms
*/
- miiphy_write (reg, 0x1f, 0x2a30);
- miiphy_write (reg, 0x08, 0x0200);
- miiphy_write (reg, 0x1f, 0x52b5);
- miiphy_write (reg, 0x02, 0x0004);
- miiphy_write (reg, 0x01, 0x0671);
- miiphy_write (reg, 0x00, 0x8fae);
- miiphy_write (reg, 0x1f, 0x2a30);
- miiphy_write (reg, 0x08, 0x0000);
- miiphy_write (reg, 0x1f, 0x0000);
+ miiphy_write (dev->name, reg, 0x1f, 0x2a30);
+ miiphy_write (dev->name, reg, 0x08, 0x0200);
+ miiphy_write (dev->name, reg, 0x1f, 0x52b5);
+ miiphy_write (dev->name, reg, 0x02, 0x0004);
+ miiphy_write (dev->name, reg, 0x01, 0x0671);
+ miiphy_write (dev->name, reg, 0x00, 0x8fae);
+ miiphy_write (dev->name, reg, 0x1f, 0x2a30);
+ miiphy_write (dev->name, reg, 0x08, 0x0000);
+ miiphy_write (dev->name, reg, 0x1f, 0x0000);
/* end Vitesse/Cicada errata */
}
#endif
#endif
/* Start/Restart autonegotiation */
- phy_setup_aneg (reg);
+ phy_setup_aneg (dev->name, reg);
udelay (1000);
}
-#endif /* CONFIG_NO_PHY_RESET */
+#endif /* defined(CONFIG_PHY_RESET) */
- miiphy_read (reg, PHY_BMSR, ®_short);
+ miiphy_read (dev->name, reg, PHY_BMSR, ®_short);
/*
* Wait if PHY is capable of autonegotiation and autonegotiation is not complete
putc ('.');
}
udelay (1000); /* 1 ms */
- miiphy_read (reg, PHY_BMSR, ®_short);
+ miiphy_read (dev->name, reg, PHY_BMSR, ®_short);
}
puts (" done\n");
udelay (500000); /* another 500 ms (results in faster booting) */
}
-#endif
- speed = miiphy_speed (reg);
- duplex = miiphy_duplex (reg);
+#endif /* #ifndef CONFIG_CS8952_PHY */
+
+ speed = miiphy_speed (dev->name, reg);
+ duplex = miiphy_duplex (dev->name, reg);
if (hw_p->print_speed) {
hw_p->print_speed = 0;
(int) speed, (duplex == HALF) ? "HALF" : "FULL");
}
+#if defined(CONFIG_440) && !defined(CONFIG_440SP)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
mfsdr(sdr_mfr, reg);
if (speed == 100) {
out32 (RGMII_SSR, reg);
}
+#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
/* set the Mal configuration reg */
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
#else
for (i = 0; i < NUM_RX_BUFF; i++) {
hw_p->rx[i].ctrl = 0;
hw_p->rx[i].data_len = 0;
- /* rx[i].data_ptr = (char *) &rx_buff[i]; */
+ /* rx[i].data_ptr = (char *) &rx_buff[i]; */
hw_p->rx[i].data_ptr = (char *) NetRxPackets[i];
if ((NUM_RX_BUFF - 1) == i)
hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
switch (devnum) {
case 1:
/* setup MAL tx & rx channel pointers */
-#if defined (CONFIG_440EP) || defined (CONFIG_440GR)
+#if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
mtdcr (maltxctp2r, hw_p->tx);
#else
mtdcr (maltxctp1r, hw_p->tx);
#endif
+#if defined(CONFIG_440)
mtdcr (maltxbattr, 0x0);
mtdcr (malrxbattr, 0x0);
+#endif
mtdcr (malrxctp1r, hw_p->rx);
/* set RX buffer size */
mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
case 2:
/* setup MAL tx & rx channel pointers */
mtdcr (maltxbattr, 0x0);
- mtdcr (maltxctp2r, hw_p->tx);
mtdcr (malrxbattr, 0x0);
+ mtdcr (maltxctp2r, hw_p->tx);
mtdcr (malrxctp2r, hw_p->rx);
/* set RX buffer size */
mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
case 0:
default:
/* setup MAL tx & rx channel pointers */
+#if defined(CONFIG_440)
mtdcr (maltxbattr, 0x0);
- mtdcr (maltxctp0r, hw_p->tx);
mtdcr (malrxbattr, 0x0);
+#endif
+ mtdcr (maltxctp0r, hw_p->tx);
mtdcr (malrxctp0r, hw_p->rx);
/* set RX buffer size */
mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
}
/* Enable MAL transmit and receive channels */
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
#else
mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
/* set speed */
- if (speed == _1000BASET)
+ if (speed == _1000BASET) {
+#if defined(CONFIG_440SP)
+#define SDR0_PFC1_EM_1000 0x00200000
+ unsigned long pfc1;
+ mfsdr (sdr_pfc1, pfc1);
+ pfc1 |= SDR0_PFC1_EM_1000;
+ mtsdr (sdr_pfc1, pfc1);
+#endif
mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
- else if (speed == _100BASET)
+ } else if (speed == _100BASET)
mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
else
mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
/* set transmit request threshold register */
out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
- /* set receive low/high water mark register */
+ /* set receive low/high water mark register */
+#if defined(CONFIG_440)
/* 440GP has a 64 byte burst length */
out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
+#else
+ /* 405s have a 16 byte burst length */
+ out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
+#endif /* defined(CONFIG_440) */
out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
/* Set fifo limit entry in tx mode 0 */
out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
/* Set EMAC IER */
- hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS |
- EMAC_ISR_PTLE | EMAC_ISR_ORE | EMAC_ISR_IRE;
+ hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
if (speed == _100BASET)
hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
/*
* Connect interrupt service routines
*/
- irq_install_handler (VECNUM_EWU0 + (hw_p->devnum * 2),
- (interrupt_handler_t *) enetInt, dev);
irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2),
(interrupt_handler_t *) enetInt, dev);
}
}
-static int ppc_440x_eth_send (struct eth_device *dev, volatile void *ptr,
+static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
int len)
{
struct enet_frame *ef_ptr;
ulong time_start, time_now;
unsigned long temp_txm0;
- EMAC_440GX_HW_PST hw_p = dev->priv;
+ EMAC_4XX_HW_PST hw_p = dev->priv;
ef_ptr = (struct enet_frame *) ptr;
out32 (EMAC_TXM0 + hw_p->hw_addr,
in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
-#ifdef INFO_440_ENET
+#ifdef INFO_4XX_ENET
hw_p->stats.pkts_tx++;
#endif
}
+#if defined (CONFIG_440)
+
+#if defined(CONFIG_440SP)
+/*
+ * Hack: On 440SP all enet irq sources are located on UIC1
+ * Needs some cleanup. --sr
+ */
+#define UIC0MSR uic1msr
+#define UIC0SR uic1sr
+#else
+#define UIC0MSR uic0msr
+#define UIC0SR uic0sr
+#endif
+
int enetInt (struct eth_device *dev)
{
int serviced;
#if defined(CONFIG_440GX)
unsigned long my_uic2msr;
#endif
- EMAC_440GX_HW_PST hw_p;
+ EMAC_4XX_HW_PST hw_p;
/*
* Because the mal is generic, we need to get the current
* eth device
*/
- dev = eth_get_dev ();
+#if defined(CONFIG_NET_MULTI)
+ dev = eth_get_dev();
+#else
+ dev = emac0_dev;
+#endif
hw_p = dev->priv;
-
/* enter loop that stays in interrupt code until nothing to service */
do {
serviced = 0;
- my_uic0msr = mfdcr (uic0msr);
+ my_uic0msr = mfdcr (UIC0MSR);
my_uic1msr = mfdcr (uic1msr);
#if defined(CONFIG_440GX)
my_uic2msr = mfdcr (uic2msr);
#endif
if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
- && !(my_uic1msr &
- (UIC_ETH0 | UIC_ETH1 | UIC_MS | UIC_MTDE |
- UIC_MRDE))) {
+ && !(my_uic1msr & (UIC_ETH0 | UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE))) {
/* not for us */
return (rc);
}
}
if ((hw_p->emac_ier & emac_isr)
|| (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
- mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
+ mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
return (rc); /* we had errors so get out */
}
}
+#if !defined(CONFIG_440SP)
if (hw_p->devnum == 1) {
if (UIC_ETH1 & my_uic1msr) { /* look for EMAC errors */
emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
}
if ((hw_p->emac_ier & emac_isr)
|| (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
- mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
+ mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
mtdcr (uic1sr, UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
return (rc); /* we had errors so get out */
}
}
if ((hw_p->emac_ier & emac_isr)
|| (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
- mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
+ mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
mtdcr (uic2sr, UIC_ETH2);
return (rc); /* we had errors so get out */
}
if ((hw_p->emac_ier & emac_isr)
|| (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
- mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
+ mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
mtdcr (uic2sr, UIC_ETH3);
return (rc); /* we had errors so get out */
}
}
#endif /* CONFIG_440GX */
+#endif /* !CONFIG_440SP */
+
/* handle MAX TX EOB interrupt from a tx */
if (my_uic0msr & UIC_MTE) {
mal_rx_eob = mfdcr (maltxeobisr);
mtdcr (maltxeobisr, mal_rx_eob);
- mtdcr (uic0sr, UIC_MTE);
+ mtdcr (UIC0SR, UIC_MTE);
}
/* handle MAL RX EOB interupt from a receive */
/* check for EOB on valid channels */
if (my_uic0msr & UIC_MRE) {
mal_rx_eob = mfdcr (malrxeobisr);
- if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
+ if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
/* clear EOB
mtdcr(malrxeobisr, mal_rx_eob); */
enet_rcv (dev, emac_isr);
rc = 0;
}
}
- mtdcr (uic0sr, UIC_MRE); /* Clear */
+
+ mtdcr (UIC0SR, UIC_MRE); /* Clear */
mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
switch (hw_p->devnum) {
case 0:
return (rc);
}
+#else /* CONFIG_440 */
+
+int enetInt (struct eth_device *dev)
+{
+ int serviced;
+ int rc = -1; /* default to not us */
+ unsigned long mal_isr;
+ unsigned long emac_isr = 0;
+ unsigned long mal_rx_eob;
+ unsigned long my_uicmsr;
+
+ EMAC_4XX_HW_PST hw_p;
+
+ /*
+ * Because the mal is generic, we need to get the current
+ * eth device
+ */
+#if defined(CONFIG_NET_MULTI)
+ dev = eth_get_dev();
+#else
+ dev = emac0_dev;
+#endif
+
+ hw_p = dev->priv;
+
+ /* enter loop that stays in interrupt code until nothing to service */
+ do {
+ serviced = 0;
+
+ my_uicmsr = mfdcr (uicmsr);
+
+ if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */
+ return (rc);
+ }
+ /* get and clear controller status interrupts */
+ /* look at Mal and EMAC interrupts */
+ if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */
+ mal_isr = mfdcr (malesr);
+ /* look for mal error */
+ if ((my_uicmsr & MAL_UIC_ERR) != 0) {
+ mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR);
+ serviced = 1;
+ rc = 0;
+ }
+ }
+
+ /* port by port dispatch of emac interrupts */
+
+ if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */
+ emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
+ if ((hw_p->emac_ier & emac_isr) != 0) {
+ emac_err (dev, emac_isr);
+ serviced = 1;
+ rc = 0;
+ }
+ }
+ if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) {
+ mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */
+ return (rc); /* we had errors so get out */
+ }
+
+ /* handle MAX TX EOB interrupt from a tx */
+ if (my_uicmsr & UIC_MAL_TXEOB) {
+ mal_rx_eob = mfdcr (maltxeobisr);
+ mtdcr (maltxeobisr, mal_rx_eob);
+ mtdcr (uicsr, UIC_MAL_TXEOB);
+ }
+ /* handle MAL RX EOB interupt from a receive */
+ /* check for EOB on valid channels */
+ if (my_uicmsr & UIC_MAL_RXEOB)
+ {
+ mal_rx_eob = mfdcr (malrxeobisr);
+ if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
+ /* clear EOB
+ mtdcr(malrxeobisr, mal_rx_eob); */
+ enet_rcv (dev, emac_isr);
+ /* indicate that we serviced an interrupt */
+ serviced = 1;
+ rc = 0;
+ }
+ }
+ mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */
+ }
+ while (serviced);
+
+ return (rc);
+}
+
+#endif /* CONFIG_440 */
+
/*-----------------------------------------------------------------------------+
* MAL Error Routine
*-----------------------------------------------------------------------------*/
unsigned long uic, unsigned long maldef,
unsigned long mal_errr)
{
- EMAC_440GX_HW_PST hw_p = dev->priv;
+ EMAC_4XX_HW_PST hw_p = dev->priv;
mtdcr (malesr, isr); /* clear interrupt */
mtdcr (maltxdeir, 0xC0000000);
mtdcr (malrxdeir, 0x80000000);
-#ifdef INFO_440_ENET
- printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
+#ifdef INFO_4XX_ENET
+ printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
#endif
eth_init (hw_p->bis); /* start again... */
*-----------------------------------------------------------------------------*/
static void emac_err (struct eth_device *dev, unsigned long isr)
{
- EMAC_440GX_HW_PST hw_p = dev->priv;
+ EMAC_4XX_HW_PST hw_p = dev->priv;
printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
out32 (EMAC_ISR + hw_p->hw_addr, isr);
struct enet_frame *ef_ptr;
unsigned long data_len;
unsigned long rx_eob_isr;
- EMAC_440GX_HW_PST hw_p = dev->priv;
+ EMAC_4XX_HW_PST hw_p = dev->priv;
int handled = 0;
int i;
hw_p->stats.rx += data_len;
ef_ptr = (struct enet_frame *) hw_p->rx[i].
data_ptr;
-#ifdef INFO_440_ENET
+#ifdef INFO_4XX_ENET
hw_p->stats.pkts_rx++;
#endif
/* AS.HARNOIS
if (NUM_RX_BUFF == hw_p->rx_i_index)
hw_p->rx_i_index = 0;
- /* printf("X"); /|* test-only *|/ */
-
/* AS.HARNOIS
* free receive buffer only when
* buffer has been handled (eth_rx)
}
-static int ppc_440x_eth_rx (struct eth_device *dev)
+static int ppc_4xx_eth_rx (struct eth_device *dev)
{
int length;
int user_index;
unsigned long msr;
- EMAC_440GX_HW_PST hw_p = dev->priv;
+ EMAC_4XX_HW_PST hw_p = dev->priv;
- hw_p->is_receiving = 1; /* tell driver */
+ hw_p->is_receiving = 1; /* tell driver */
for (;;) {
/* AS.HARNOIS
length = hw_p->rx[user_index].data_len;
/* Pass the packet up to the protocol layers. */
- /* NetReceive(NetRxPackets[rxIdx], length - 4); */
- /* NetReceive(NetRxPackets[i], length); */
+ /* NetReceive(NetRxPackets[rxIdx], length - 4); */
+ /* NetReceive(NetRxPackets[i], length); */
NetReceive (NetRxPackets[user_index], length - 4);
/* Free Recv Buffer */
hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
if (NUM_RX_BUFF == hw_p->rx_u_index)
hw_p->rx_u_index = 0;
-#ifdef INFO_440_ENET
+#ifdef INFO_4XX_ENET
hw_p->stats.pkts_handled++;
#endif
mtmsr (msr); /* Enable IRQ's */
}
- hw_p->is_receiving = 0; /* tell driver */
+ hw_p->is_receiving = 0; /* tell driver */
return length;
}
-int ppc_440x_eth_initialize (bd_t * bis)
+int ppc_4xx_eth_initialize (bd_t * bis)
{
static int virgin = 0;
struct eth_device *dev;
int eth_num = 0;
- EMAC_440GX_HW_PST hw = NULL;
+ EMAC_4XX_HW_PST hw = NULL;
#if defined(CONFIG_440GX)
unsigned long pfc1;
bis->bi_phymode[3] = 2;
#if defined (CONFIG_440GX)
- ppc_440x_eth_setup_bridge(0, bis);
+ ppc_4xx_eth_setup_bridge(0, bis);
#endif
#endif
- for (eth_num = 0; eth_num < EMAC_NUM_DEV; eth_num++) {
+ for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
/* See if we can actually bring up the interface, otherwise, skip it */
switch (eth_num) {
/* Allocate device structure */
dev = (struct eth_device *) malloc (sizeof (*dev));
if (dev == NULL) {
- printf ("ppc_440x_eth_initialize: "
+ printf ("ppc_4xx_eth_initialize: "
"Cannot allocate eth_device %d\n", eth_num);
return (-1);
}
memset(dev, 0, sizeof(*dev));
/* Allocate our private use data */
- hw = (EMAC_440GX_HW_PST) malloc (sizeof (*hw));
+ hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
if (hw == NULL) {
- printf ("ppc_440x_eth_initialize: "
+ printf ("ppc_4xx_eth_initialize: "
"Cannot allocate private hw data for eth_device %d",
eth_num);
free (dev);
hw->devnum = eth_num;
hw->print_speed = 1;
- sprintf (dev->name, "ppc_440x_eth%d", eth_num);
+ sprintf (dev->name, "ppc_4xx_eth%d", eth_num);
dev->priv = (void *) hw;
- dev->init = ppc_440x_eth_init;
- dev->halt = ppc_440x_eth_halt;
- dev->send = ppc_440x_eth_send;
- dev->recv = ppc_440x_eth_rx;
+ dev->init = ppc_4xx_eth_init;
+ dev->halt = ppc_4xx_eth_halt;
+ dev->send = ppc_4xx_eth_send;
+ dev->recv = ppc_4xx_eth_rx;
if (0 == virgin) {
/* set the MAL IER ??? names may change with new spec ??? */
virgin = 1;
}
+#if defined(CONFIG_NET_MULTI)
eth_register (dev);
+#else
+ emac0_dev = dev;
+#endif
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+ miiphy_register (dev->name,
+ emac4xx_miiphy_read, emac4xx_miiphy_write);
+#endif
} /* end for each supported device */
return (1);
}
-#endif /* CONFIG_440 && CONFIG_NET_MULTI */
+
+
+#if !defined(CONFIG_NET_MULTI)
+void eth_halt (void) {
+ if (emac0_dev) {
+ ppc_4xx_eth_halt(emac0_dev);
+ free(emac0_dev);
+ emac0_dev = NULL;
+ }
+}
+
+int eth_init (bd_t *bis)
+{
+ ppc_4xx_eth_initialize(bis);
+ if (emac0_dev) {
+ return ppc_4xx_eth_init(emac0_dev, bis);
+ } else {
+ printf("ERROR: ethaddr not set!\n");
+ return -1;
+ }
+}
+
+int eth_send(volatile void *packet, int length)
+{
+ return (ppc_4xx_eth_send(emac0_dev, packet, length));
+}
+
+int eth_rx(void)
+{
+ return (ppc_4xx_eth_rx(emac0_dev));
+}
+
+int emac4xx_miiphy_initialize (bd_t * bis)
+{
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+ miiphy_register ("ppc_4xx_eth0",
+ emac4xx_miiphy_read, emac4xx_miiphy_write);
+#endif
+
+ return 0;
+}
+#endif /* !defined(CONFIG_NET_MULTI) */
+
+#endif /* #if (CONFIG_COMMANDS & CFG_CMD_NET) */
START = start.o resetvec.o kgdb.o
AOBJS = dcr.o
-COBJS = 405gp_enet.o 405gp_pci.o 440gx_enet.o \
+COBJS = 405gp_pci.o 4xx_enet.o \
bedbug_405.o commproc.o \
cpu.o cpu_init.o i2c.o interrupts.o \
- miiphy.o miiphy_440.o sdram.o serial.o \
+ miiphy.o sdram.o serial.o \
spd_sdram.o speed.o traps.o usb_ohci.o usbdev.o
OBJS = $(AOBJS) $(COBJS)
\f
/* ======================================================================
- * Initialize the global bug_ctx structure for the IBM PPC405. Clear all
+ * Initialize the global bug_ctx structure for the AMCC PPC405. Clear all
* of the breakpoints.
* ====================================================================== */
#if defined(CONFIG_440)
-static int do_chip_reset( unsigned long sys0, unsigned long sys1 );
+#define FREQ_EBC (sys_info.freqEPB)
+#else
+#define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv)
#endif
-/* ------------------------------------------------------------------------- */
+#if defined(CONFIG_405GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
-int checkcpu (void)
+#define PCI_ASYNC
+
+int pci_async_enabled(void)
{
-#if defined(CONFIG_405GP) || \
- defined(CONFIG_405CR) || \
- defined(CONFIG_405EP) || \
- defined(CONFIG_440) || \
- defined(CONFIG_IOP480)
- uint pvr = get_pvr();
+#if defined(CONFIG_405GP)
+ return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
#endif
-#if defined(CONFIG_405GP) || \
- defined(CONFIG_405CR) || \
- defined(CONFIG_405EP) || \
- defined(CONFIG_IOP480)
- DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+ unsigned long val;
+
+ mfsdr(sdr_sdstp1, val);
+ return (val & SDR0_SDSTP1_PAME_MASK);
+#endif
+}
+#endif
+
+#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && !defined(CONFIG_405)
+int pci_arbiter_enabled(void)
+{
+#if defined(CONFIG_405GP)
+ return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
+#endif
+
+#if defined(CONFIG_405EP)
+ return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
+#endif
+
+#if defined(CONFIG_440GP)
+ return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
+#endif
+
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+ unsigned long val;
+
+ mfsdr(sdr_sdstp1, val);
+ return (val & SDR0_SDSTP1_PAE_MASK);
+#endif
+}
+#endif
+
+#if defined(CONFIG_405EP)|| defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440GX) || defined(CONFIG_440SP)
+
+#define I2C_BOOTROM
+
+int i2c_bootrom_enabled(void)
+{
+#if defined(CONFIG_405EP)
+ return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
+#endif
+
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+ unsigned long val;
+
+ mfsdr(sdr_sdcs, val);
+ return (val & SDR0_SDCS_SDD);
+#endif
+}
+#endif
+
+
+#if defined(CONFIG_440)
+static int do_chip_reset(unsigned long sys0, unsigned long sys1);
+#endif
+
+
+int checkcpu (void)
+{
+#if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
+ DECLARE_GLOBAL_DATA_PTR;
+ uint pvr = get_pvr();
ulong clock = gd->cpu_clk;
char buf[32];
-#endif
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP)
- PPC405_SYS_INFO sys_info;
+#if !defined(CONFIG_IOP480)
+ sys_info_t sys_info;
puts ("CPU: ");
get_sys_info(&sys_info);
-#ifdef CONFIG_405GP
- puts ("AMCC PowerPC 405GP");
- if (pvr == PVR_405GPR_RB) {
- putc('r');
- }
- puts (" Rev. ");
-#endif
-#ifdef CONFIG_405CR
- puts ("AMCC PowerPC 405CR Rev. ");
+ puts("AMCC PowerPC 4");
+
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP)
+ puts("05");
#endif
-#ifdef CONFIG_405EP
- puts ("AMCC PowerPC 405EP Rev. ");
+#if defined(CONFIG_440)
+ puts("40");
#endif
+
switch (pvr) {
case PVR_405GP_RB:
- case PVR_405GPR_RB:
- putc('B');
+ puts("GP Rev. B");
break;
+
case PVR_405GP_RC:
-#ifdef CONFIG_405CR
- case PVR_405CR_RC:
-#endif
- putc('C');
+ puts("GP Rev. C");
break;
+
case PVR_405GP_RD:
- putc('D');
+ puts("GP Rev. D");
break;
+
#ifdef CONFIG_405GP
- case PVR_405GP_RE:
- putc('E');
+ case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
+ puts("GP Rev. E");
break;
#endif
+
case PVR_405CR_RA:
- putc('A');
+ puts("CR Rev. A");
break;
+
case PVR_405CR_RB:
- case PVR_405EP_RB:
- putc('B');
+ puts("CR Rev. B");
break;
- default:
- printf ("? (PVR=%08x)", pvr);
- break;
- }
- printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
- sys_info.freqPLB / 1000000,
- sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
- sys_info.freqPLB / sys_info.pllExtBusDiv / 1000000);
-
-#if defined(CONFIG_405GP)
- if (mfdcr(strap) & PSR_PCI_ASYNC_EN) {
- printf (" PCI async ext clock used, ");
- } else {
- printf (" PCI sync clock at %lu MHz, ",
- sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
- }
- printf ("%sternal PCI arbiter enabled\n",
- (mfdcr(strap) & PSR_PCI_ARBIT_EN) ? "in" : "ex");
-#elif defined(CONFIG_405EP)
- printf (" IIC Boot EEPROM %sabled\n",
- (mfdcr(cpc0_boot) & CPC0_BOOT_SEP) ? "en" : "dis");
- printf (" PCI async ext clock used, ");
- printf ("%sternal PCI arbiter enabled\n",
- (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN) ? "in" : "ex");
+#ifdef CONFIG_405CR
+ case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
+ puts("CR Rev. C");
+ break;
#endif
-#if defined(CONFIG_405EP)
- printf (" 16 kB I-Cache 16 kB D-Cache");
-#else
- printf (" 16 kB I-Cache %d kB D-Cache",
- ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
-#endif
-#endif /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */
+ case PVR_405GPR_RB:
+ puts("GPr Rev. B");
+ break;
-#ifdef CONFIG_IOP480
- printf ("PLX IOP480 (PVR=%08x)", pvr);
- printf (" at %s MHz:", strmhz(buf, clock));
- printf (" %u kB I-Cache", 4);
- printf (" %u kB D-Cache", 2);
-#endif
+ case PVR_405EP_RB:
+ puts("EP Rev. B");
+ break;
#if defined(CONFIG_440)
- puts ("AMCC PowerPC 440");
- switch(pvr) {
case PVR_440GP_RB:
puts("GP Rev. B");
/* See errata 1.12: CHIP_4 */
mfdcr(cpc0_strp1) );
}
break;
+
case PVR_440GP_RC:
puts("GP Rev. C");
break;
+
case PVR_440GX_RA:
puts("GX Rev. A");
break;
+
case PVR_440GX_RB:
puts("GX Rev. B");
break;
+
case PVR_440GX_RC:
puts("GX Rev. C");
break;
-#if defined(CONFIG_440GR)
- case PVR_440EP_RA:
- puts("GR Rev. A");
- break;
- case PVR_440EP_RB:
- puts("GR Rev. B");
+
+ case PVR_440GX_RF:
+ puts("GX Rev. F");
break;
-#else
+
case PVR_440EP_RA:
puts("EP Rev. A");
break;
- case PVR_440EP_RB:
+
+#ifdef CONFIG_440EP
+ case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
puts("EP Rev. B");
break;
-#endif
+#endif /* CONFIG_440EP */
+
+#ifdef CONFIG_440GR
+ case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
+ puts("GR Rev. A");
+ break;
+#endif /* CONFIG_440GR */
+#endif /* CONFIG_440 */
+
+ case PVR_440SP_RA:
+ puts("SP Rev. A");
+ break;
+
+ case PVR_440SP_RB:
+ puts("SP Rev. B");
+ break;
default:
printf (" UNKNOWN (PVR=%08x)", pvr);
break;
}
+
+ printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
+ sys_info.freqPLB / 1000000,
+ sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
+ FREQ_EBC / 1000000);
+
+#if defined(I2C_BOOTROM)
+ printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
+#endif
+
+#if defined(CONFIG_PCI)
+ printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
+#endif
+
+#if defined(PCI_ASYNC)
+ if (pci_async_enabled()) {
+ printf (", PCI async ext clock used");
+ } else {
+ printf (", PCI sync clock at %lu MHz",
+ sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
+ }
+#endif
+
+#if defined(CONFIG_PCI)
+ putc('\n');
#endif
- puts ("\n");
+
+#if defined(CONFIG_405EP)
+ printf (" 16 kB I-Cache 16 kB D-Cache");
+#elif defined(CONFIG_440)
+ printf (" 32 kB I-Cache 32 kB D-Cache");
+#else
+ printf (" 16 kB I-Cache %d kB D-Cache",
+ ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
+#endif
+#endif /* !defined(CONFIG_IOP480) */
+
+#if defined(CONFIG_IOP480)
+ printf ("PLX IOP480 (PVR=%08x)", pvr);
+ printf (" at %s MHz:", strmhz(buf, clock));
+ printf (" %u kB I-Cache", 4);
+ printf (" %u kB D-Cache", 2);
+#endif
+
+#endif /* !defined(CONFIG_405) */
+
+ putc ('\n');
return 0;
}
}
#if defined(CONFIG_440)
-static
-int do_chip_reset (unsigned long sys0, unsigned long sys1)
+static int do_chip_reset (unsigned long sys0, unsigned long sys1)
{
/* Changes to cpc0_sys0 and cpc0_sys1 require chip
* reset.
*/
unsigned long get_tbclk (void)
{
-#if defined(CONFIG_440)
-
+#if !defined(CONFIG_IOP480)
sys_info_t sys_info;
get_sys_info(&sys_info);
return (sys_info.freqProcessor);
-
-#elif defined(CONFIG_405GP) || \
- defined(CONFIG_405CR) || \
- defined(CONFIG_405) || \
- defined(CONFIG_405EP)
-
- PPC405_SYS_INFO sys_info;
-
- get_sys_info(&sys_info);
- return (sys_info.freqProcessor);
-
-#elif defined(CONFIG_IOP480)
-
- return (66000000);
-
#else
-
-# error get_tbclk() not implemented
-
+ return (66000000);
#endif
}
#include <common.h>
#include <watchdog.h>
-#include <405gp_enet.h>
+#include <ppc4xx_enet.h>
#include <asm/processor.h>
#include <ppc4xx.h>
*/
uchar i2c_reg_read(uchar i2c_addr, uchar reg)
{
- char buf;
+ uchar buf;
i2c_read(i2c_addr, reg, 1, &buf, 1);
/*-----------------------------------------------------------------------------+
|
- | This source code has been made available to you by IBM on an AS-IS
- | basis. Anyone receiving this source is licensed under IBM
- | copyrights to use it in any way he or she deems fit, including
- | copying it, modifying it, compiling it, and redistributing it either
- | with or without modifications. No license under IBM patents or
- | patent applications is to be implied by the copyright license.
+ | This source code has been made available to you by IBM on an AS-IS
+ | basis. Anyone receiving this source is licensed under IBM
+ | copyrights to use it in any way he or she deems fit, including
+ | copying it, modifying it, compiling it, and redistributing it either
+ | with or without modifications. No license under IBM patents or
+ | patent applications is to be implied by the copyright license.
|
- | Any user of this software should understand that IBM cannot provide
- | technical support for this software and will not be responsible for
- | any consequences resulting from the use of this software.
+ | Any user of this software should understand that IBM cannot provide
+ | technical support for this software and will not be responsible for
+ | any consequences resulting from the use of this software.
|
- | Any person who transfers this source code or any derivative work
- | must include the IBM copyright notice, this paragraph, and the
- | preceding two paragraphs in the transferred software.
+ | Any person who transfers this source code or any derivative work
+ | must include the IBM copyright notice, this paragraph, and the
+ | preceding two paragraphs in the transferred software.
|
- | COPYRIGHT I B M CORPORATION 1995
- | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
+ | COPYRIGHT I B M CORPORATION 1995
+ | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
+-----------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------+
|
- | File Name: miiphy.c
+ | File Name: miiphy.c
|
- | Function: This module has utilities for accessing the MII PHY through
+ | Function: This module has utilities for accessing the MII PHY through
| the EMAC3 macro.
|
- | Author: Mark Wisner
+ | Author: Mark Wisner
|
| Change Activity-
|
- | Date Description of Change BY
- | --------- --------------------- ---
- | 05-May-99 Created MKW
- | 01-Jul-99 Changed clock setting of sta_reg from 66Mhz to 50Mhz to
- | better match OPB speed. Also modified delay times. JWB
- | 29-Jul-99 Added Full duplex support MKW
- | 24-Aug-99 Removed printf from dp83843_duplex() JWB
- | 19-Jul-00 Ported to esd cpci405 sr
+ | Date Description of Change BY
+ | --------- --------------------- ---
+ | 05-May-99 Created MKW
+ | 01-Jul-99 Changed clock setting of sta_reg from 66Mhz to 50Mhz to
+ | better match OPB speed. Also modified delay times. JWB
+ | 29-Jul-99 Added Full duplex support MKW
+ | 24-Aug-99 Removed printf from dp83843_duplex() JWB
+ | 19-Jul-00 Ported to esd cpci405 sr
+ | 23-Dec-03 Ported from miiphy.c to 440GX Travis Sawyer TBS
+ | <travis.sawyer@sandburst.com>
|
+-----------------------------------------------------------------------------*/
#include <asm/processor.h>
#include <ppc_asm.tmpl>
#include <commproc.h>
-#include <405gp_enet.h>
+#include <ppc4xx_enet.h>
#include <405_mal.h>
#include <miiphy.h>
-#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
- (defined(CONFIG_440) && !defined(CONFIG_NET_MULTI))
/***********************************************************/
-/* Dump out to the screen PHY regs */
+/* Dump out to the screen PHY regs */
/***********************************************************/
-void miiphy_dump (unsigned char addr)
+void miiphy_dump (char *devname, unsigned char addr)
{
unsigned long i;
unsigned short data;
for (i = 0; i < 0x1A; i++) {
- if (miiphy_read (addr, i, &data)) {
+ if (miiphy_read (devname, addr, i, &data)) {
printf ("read error for reg %lx\n", i);
return;
}
if (i == 0x07)
i = 0x0f;
- } /* end for loop */
-} /* end dump */
+ } /* end for loop */
+} /* end dump */
/***********************************************************/
-/* read a phy reg and return the value with a rc */
-/* Note: We are referencing to EMAC_STACR register */
-/* @(EMAC_BASE + 92) because of: */
-/* - 405EP has only STACR for EMAC0 pinned out */
-/* - 405GP has onle one EMAC0 */
-/* - For 440 this module gets compiled only for */
-/* !CONFIG_NET_MULTI, i.e. only EMAC0 is supported. */
+/* (Re)start autonegotiation */
/***********************************************************/
+int phy_setup_aneg (char *devname, unsigned char addr)
+{
+ unsigned short ctl, adv;
+
+ /* Setup standard advertise */
+ miiphy_read (devname, addr, PHY_ANAR, &adv);
+ adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 |
+ PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
+ PHY_ANLPAR_10);
+ miiphy_write (devname, addr, PHY_ANAR, adv);
-int miiphy_read (unsigned char addr, unsigned char reg,
- unsigned short *value)
+ /* Start/Restart aneg */
+ miiphy_read (devname, addr, PHY_BMCR, &ctl);
+ ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+ miiphy_write (devname, addr, PHY_BMCR, ctl);
+
+ return 0;
+}
+
+
+/***********************************************************/
+/* read a phy reg and return the value with a rc */
+/***********************************************************/
+unsigned int miiphy_getemac_offset (void)
{
- unsigned long sta_reg; /* STA scratch area */
+#if (defined(CONFIG_440) && !defined(CONFIG_440SP)) && defined(CONFIG_NET_MULTI)
+ unsigned long zmii;
+ unsigned long eoffset;
+
+ /* Need to find out which mdi port we're using */
+ zmii = in32 (ZMII_FER);
+
+ if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) {
+ /* using port 0 */
+ eoffset = 0;
+ } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1))) {
+ /* using port 1 */
+ eoffset = 0x100;
+ } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2))) {
+ /* using port 2 */
+ eoffset = 0x400;
+ } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3))) {
+ /* using port 3 */
+ eoffset = 0x600;
+ } else {
+ /* None of the mdi ports are enabled! */
+ /* enable port 0 */
+ zmii |= ZMII_FER_MDI << ZMII_FER_V (0);
+ out32 (ZMII_FER, zmii);
+ eoffset = 0;
+ /* need to soft reset port 0 */
+ zmii = in32 (EMAC_M0);
+ zmii |= EMAC_M0_SRST;
+ out32 (EMAC_M0, zmii);
+ }
+
+ return (eoffset);
+#else
+ return 0;
+#endif
+}
+
+
+int emac4xx_miiphy_read (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value)
+{
+ unsigned long sta_reg; /* STA scratch area */
unsigned long i;
+ unsigned long emac_reg;
+
+ emac_reg = miiphy_getemac_offset ();
/* see if it is ready for 1000 nsec */
i = 0;
/* see if it is ready for sec */
- while ((in32 (EMAC_STACR) & EMAC_STACR_OC) == 0) {
+ while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) {
udelay (7);
if (i > 5) {
-#if 0 /* test-only */
+#if 0
printf ("read err 1\n");
#endif
return -1;
}
i++;
}
- sta_reg = reg; /* reg address */
+ sta_reg = reg; /* reg address */
/* set clock (50Mhz) and read flags */
+#if defined(CONFIG_440GX)
+ sta_reg |= EMAC_STACR_READ;
+#else
sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
-#ifdef CONFIG_PHY_CLK_FREQ
+#endif
+
+#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX)
sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
#endif
sta_reg = sta_reg | (addr << 5); /* Phy address */
- out32 (EMAC_STACR, sta_reg);
-#if 0 /* test-only */
+ out32 (EMAC_STACR + emac_reg, sta_reg);
+#if 0 /* test-only */
printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
#endif
-#ifdef CONFIG_PHY_CMD_DELAY
- udelay (CONFIG_PHY_CMD_DELAY); /* Intel LXT971A needs this */
-#endif
- sta_reg = in32 (EMAC_STACR);
+ sta_reg = in32 (EMAC_STACR + emac_reg);
i = 0;
while ((sta_reg & EMAC_STACR_OC) == 0) {
udelay (7);
if (i > 5) {
-#if 0 /* test-only */
- printf ("read err 2\n");
-#endif
return -1;
}
i++;
- sta_reg = in32 (EMAC_STACR);
+ sta_reg = in32 (EMAC_STACR + emac_reg);
}
if ((sta_reg & EMAC_STACR_PHYE) != 0) {
-#if 0 /* test-only */
- printf ("read err 3\n");
- printf ("a2: read: EMAC_STACR=0x%0lx, i=%d\n",
- sta_reg, (int) i); /* test-only */
-#endif
return -1;
}
return 0;
-} /* phy_read */
+} /* phy_read */
/***********************************************************/
-/* write a phy reg and return the value with a rc */
+/* write a phy reg and return the value with a rc */
/***********************************************************/
-int miiphy_write (unsigned char addr, unsigned char reg,
- unsigned short value)
+int emac4xx_miiphy_write (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value)
{
- unsigned long sta_reg; /* STA scratch area */
+ unsigned long sta_reg; /* STA scratch area */
unsigned long i;
+ unsigned long emac_reg;
+ emac_reg = miiphy_getemac_offset ();
/* see if it is ready for 1000 nsec */
i = 0;
- while ((in32 (EMAC_STACR) & EMAC_STACR_OC) == 0) {
+ while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) {
if (i > 5)
return -1;
udelay (7);
i++;
}
sta_reg = 0;
- sta_reg = reg; /* reg address */
+ sta_reg = reg; /* reg address */
/* set clock (50Mhz) and read flags */
+#if defined(CONFIG_440GX)
+ sta_reg |= EMAC_STACR_WRITE;
+#else
sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
-#ifdef CONFIG_PHY_CLK_FREQ
- sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */
+#endif
+
+#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX)
+ sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */
#endif
sta_reg = sta_reg | ((unsigned long) addr << 5); /* Phy address */
memcpy (&sta_reg, &value, 2); /* put in data */
- out32 (EMAC_STACR, sta_reg);
+ out32 (EMAC_STACR + emac_reg, sta_reg);
-#ifdef CONFIG_PHY_CMD_DELAY
- udelay (CONFIG_PHY_CMD_DELAY); /* Intel LXT971A needs this */
-#endif
/* wait for completion */
i = 0;
- sta_reg = in32 (EMAC_STACR);
+ sta_reg = in32 (EMAC_STACR + emac_reg);
while ((sta_reg & EMAC_STACR_OC) == 0) {
udelay (7);
if (i > 5)
return -1;
i++;
- sta_reg = in32 (EMAC_STACR);
+ sta_reg = in32 (EMAC_STACR + emac_reg);
}
if ((sta_reg & EMAC_STACR_PHYE) != 0)
return -1;
return 0;
-} /* phy_read */
-
-#endif /* CONFIG_405GP */
+} /* phy_write */
+++ /dev/null
-/*-----------------------------------------------------------------------------+
- |
- | This source code has been made available to you by IBM on an AS-IS
- | basis. Anyone receiving this source is licensed under IBM
- | copyrights to use it in any way he or she deems fit, including
- | copying it, modifying it, compiling it, and redistributing it either
- | with or without modifications. No license under IBM patents or
- | patent applications is to be implied by the copyright license.
- |
- | Any user of this software should understand that IBM cannot provide
- | technical support for this software and will not be responsible for
- | any consequences resulting from the use of this software.
- |
- | Any person who transfers this source code or any derivative work
- | must include the IBM copyright notice, this paragraph, and the
- | preceding two paragraphs in the transferred software.
- |
- | COPYRIGHT I B M CORPORATION 1995
- | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
- +-----------------------------------------------------------------------------*/
-/*-----------------------------------------------------------------------------+
- |
- | File Name: miiphy.c
- |
- | Function: This module has utilities for accessing the MII PHY through
- | the EMAC3 macro.
- |
- | Author: Mark Wisner
- |
- | Change Activity-
- |
- | Date Description of Change BY
- | --------- --------------------- ---
- | 05-May-99 Created MKW
- | 01-Jul-99 Changed clock setting of sta_reg from 66Mhz to 50Mhz to
- | better match OPB speed. Also modified delay times. JWB
- | 29-Jul-99 Added Full duplex support MKW
- | 24-Aug-99 Removed printf from dp83843_duplex() JWB
- | 19-Jul-00 Ported to esd cpci405 sr
- | 23-Dec-03 Ported from miiphy.c to 440GX Travis Sawyer TBS
- | <travis.sawyer@sandburst.com>
- |
- +-----------------------------------------------------------------------------*/
-
-#include <common.h>
-#include <asm/processor.h>
-#include <ppc_asm.tmpl>
-#include <commproc.h>
-#include <440gx_enet.h>
-#include <405_mal.h>
-#include <miiphy.h>
-
-#if defined(CONFIG_440) && defined(CONFIG_NET_MULTI)
-
-
-/***********************************************************/
-/* Dump out to the screen PHY regs */
-/***********************************************************/
-
-void miiphy_dump (unsigned char addr)
-{
- unsigned long i;
- unsigned short data;
-
-
- for (i = 0; i < 0x1A; i++) {
- if (miiphy_read (addr, i, &data)) {
- printf ("read error for reg %lx\n", i);
- return;
- }
- printf ("Phy reg %lx ==> %4x\n", i, data);
-
- /* jump to the next set of regs */
- if (i == 0x07)
- i = 0x0f;
-
- } /* end for loop */
-} /* end dump */
-
-
-/***********************************************************/
-/* (Re)start autonegotiation */
-/***********************************************************/
-int phy_setup_aneg (unsigned char addr)
-{
- unsigned short ctl, adv;
-
- /* Setup standard advertise */
- miiphy_read (addr, PHY_ANAR, &adv);
- adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 |
- PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
- PHY_ANLPAR_10);
- miiphy_write (addr, PHY_ANAR, adv);
-
- /* Start/Restart aneg */
- miiphy_read (addr, PHY_BMCR, &ctl);
- ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
- miiphy_write (addr, PHY_BMCR, ctl);
-
- return 0;
-}
-
-
-/***********************************************************/
-/* read a phy reg and return the value with a rc */
-/***********************************************************/
-unsigned int miiphy_getemac_offset (void)
-{
- unsigned long zmii;
- unsigned long eoffset;
-
- /* Need to find out which mdi port we're using */
- zmii = in32 (ZMII_FER);
-
- if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) {
- /* using port 0 */
- eoffset = 0;
- } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1))) {
- /* using port 1 */
- eoffset = 0x100;
- } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2))) {
- /* using port 2 */
- eoffset = 0x400;
- } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3))) {
- /* using port 3 */
- eoffset = 0x600;
- } else {
- /* None of the mdi ports are enabled! */
- /* enable port 0 */
- zmii |= ZMII_FER_MDI << ZMII_FER_V (0);
- out32 (ZMII_FER, zmii);
- eoffset = 0;
- /* need to soft reset port 0 */
- zmii = in32 (EMAC_M0);
- zmii |= EMAC_M0_SRST;
- out32 (EMAC_M0, zmii);
- }
-
- return (eoffset);
-
-}
-
-
-int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
-{
- unsigned long sta_reg; /* STA scratch area */
- unsigned long i;
- unsigned long emac_reg;
-
-
- emac_reg = miiphy_getemac_offset ();
- /* see if it is ready for 1000 nsec */
- i = 0;
-
- /* see if it is ready for sec */
- while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) {
- udelay (7);
- if (i > 5) {
-#if 0
- printf ("read err 1\n");
-#endif
- return -1;
- }
- i++;
- }
- sta_reg = reg; /* reg address */
- /* set clock (50Mhz) and read flags */
-#if defined(CONFIG_440GX)
- sta_reg |= EMAC_STACR_READ;
-#else
- sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
-#endif
-
-#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX)
- sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
-#endif
- sta_reg = sta_reg | (addr << 5); /* Phy address */
-
- out32 (EMAC_STACR + emac_reg, sta_reg);
-#if 0 /* test-only */
- printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
-#endif
-
- sta_reg = in32 (EMAC_STACR + emac_reg);
- i = 0;
- while ((sta_reg & EMAC_STACR_OC) == 0) {
- udelay (7);
- if (i > 5) {
- return -1;
- }
- i++;
- sta_reg = in32 (EMAC_STACR + emac_reg);
- }
- if ((sta_reg & EMAC_STACR_PHYE) != 0) {
- return -1;
- }
-
- *value = *(short *) (&sta_reg);
- return 0;
-
-
-} /* phy_read */
-
-
-/***********************************************************/
-/* write a phy reg and return the value with a rc */
-/***********************************************************/
-
-int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
-{
- unsigned long sta_reg; /* STA scratch area */
- unsigned long i;
- unsigned long emac_reg;
-
- emac_reg = miiphy_getemac_offset ();
- /* see if it is ready for 1000 nsec */
- i = 0;
-
- while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) {
- if (i > 5)
- return -1;
- udelay (7);
- i++;
- }
- sta_reg = 0;
- sta_reg = reg; /* reg address */
- /* set clock (50Mhz) and read flags */
-#if defined(CONFIG_440GX)
- sta_reg |= EMAC_STACR_WRITE;
-#else
- sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
-#endif
-
-#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX)
- sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */
-#endif
- sta_reg = sta_reg | ((unsigned long) addr << 5); /* Phy address */
- memcpy (&sta_reg, &value, 2); /* put in data */
-
- out32 (EMAC_STACR + emac_reg, sta_reg);
-
- /* wait for completion */
- i = 0;
- sta_reg = in32 (EMAC_STACR + emac_reg);
- while ((sta_reg & EMAC_STACR_OC) == 0) {
- udelay (7);
- if (i > 5)
- return -1;
- i++;
- sta_reg = in32 (EMAC_STACR + emac_reg);
- }
-
- if ((sta_reg & EMAC_STACR_PHYE) != 0)
- return -1;
- return 0;
-
-} /* phy_write */
-
-#endif /* CONFIG_405GP */
/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
* (C) Copyright 2002-2004
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
typedef struct sdram_conf_s sdram_conf_t;
+#ifndef CFG_SDRAM_TABLE
sdram_conf_t mb0cf[] = {
{(128 << 20), 0x000A4001}, /* (0-128MB) Address Mode 3, 13x10(4) */
{(64 << 20), 0x00084001}, /* (0-64MB) Address Mode 3, 13x9(4) */
{(16 << 20), 0x00046001}, /* (0-16MB) Address Mode 4, 12x8(4) */
{(4 << 20), 0x00008001}, /* (0-4MB) Address Mode 5, 11x8(2) */
};
+#else
+sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE;
+#endif
+
#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
+#ifndef CONFIG_440
+
+/*
+ * Autodetect onboard SDRAM on 405 platforms
+ */
void sdram_init(void)
{
ulong sdtr1;
}
}
+#else /* CONFIG_440 */
+
+/*
+ * Autodetect onboard DDR SDRAM on 440 platforms
+ *
+ * NOTE: Some of the hardcoded values are hardware dependant,
+ * so this should be extended for other future boards
+ * using this routine!
+ */
+long int initdram(int board_type)
+{
+ int i;
+
+ for (i=0; i<N_MB0CF; i++) {
+ /*
+ * Disable memory controller.
+ */
+ mtsdram(mem_cfg0, 0x00000000);
+
+ /*
+ * Setup some default
+ */
+ mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
+ mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
+ mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
+ mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
+ mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
+
+ /*
+ * Following for CAS Latency = 2.5 @ 133 MHz PLB
+ */
+ mtsdram(mem_b0cr, mb0cf[i].reg);
+ mtsdram(mem_tr0, 0x41094012);
+ mtsdram(mem_tr1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
+ mtsdram(mem_rtr, 0x7e000000); /* Interval 15.20µs @ 133MHz PLB*/
+ mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/
+ udelay(400); /* Delay 200 usecs (min) */
+
+ /*
+ * Enable the controller, then wait for DCEN to complete
+ */
+ mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
+ udelay(10000);
+
+ if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
+ /*
+ * OK, size detected -> all done
+ */
+ return mb0cf[i].size;
+ }
+ }
+
+ return 0; /* nothing found ! */
+}
+
+#endif /* CONFIG_440 */
+
#endif /* CONFIG_SDRAM_BANK0 */
#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
#endif
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+
+#if defined(CONFIG_440SP)
+#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600
+#endif
+
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
#define CR0_MASK 0xdfffffff
#define CR0_EXTCLK_ENA 0x00800000
#define CR0_UDIV_POS 0
#if defined(CONFIG_UART1_CONSOLE)
#define ACTING_UART0_BASE UART1_BASE
#define ACTING_UART1_BASE UART0_BASE
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
#define UART0_SDR sdr_uart1
#define UART1_SDR sdr_uart0
#endif /* CONFIG_440GX */
#else
#define ACTING_UART0_BASE UART0_BASE
#define ACTING_UART1_BASE UART1_BASE
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
#define UART0_SDR sdr_uart0
#define UART1_SDR sdr_uart1
#endif /* CONFIG_440GX */
#endif
#if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
-#error "External serial clock not supported on IBM PPC405EP!"
+#error "External serial clock not supported on AMCC PPC405EP!"
#endif
#define UART_RBR 0x00
unsigned long tmp;
#endif
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
#if defined(CONFIG_SERIAL_MULTI)
if (UART0_BASE == dev_base) {
mfsdr(UART0_SDR,reg);
serial_divs (gd->baudrate, &udiv, &bdiv);
#endif
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */
#if defined(CONFIG_SERIAL_MULTI)
if (UART0_BASE == dev_base) {
*
* (C) Copyright 2002
* Jun Gu, Artesyn Technology, jung@artesyncp.com
- * Support for IBM 440 based on OpenBIOS draminit.c from IBM.
+ * Support for AMCC 440 based on OpenBIOS draminit.c from IBM.
*
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
/*
* Set default values
*/
-#ifndef CFG_I2C_SPEED
-#define CFG_I2C_SPEED 50000
+#ifndef CFG_I2C_SPEED
+#define CFG_I2C_SPEED 50000
#endif
-#ifndef CFG_I2C_SLAVE
-#define CFG_I2C_SLAVE 0xFE
+#ifndef CFG_I2C_SLAVE
+#define CFG_I2C_SLAVE 0xFE
#endif
-#define ONE_BILLION 1000000000
+#define ONE_BILLION 1000000000
-#ifndef CONFIG_440 /* for 405 WALNUT/SYCAMORE/BUBINGA boards */
+#ifndef CONFIG_440 /* for 405 WALNUT/SYCAMORE/BUBINGA boards */
-#define SDRAM0_CFG_DCE 0x80000000
-#define SDRAM0_CFG_SRE 0x40000000
-#define SDRAM0_CFG_PME 0x20000000
-#define SDRAM0_CFG_MEMCHK 0x10000000
-#define SDRAM0_CFG_REGEN 0x08000000
-#define SDRAM0_CFG_ECCDD 0x00400000
-#define SDRAM0_CFG_EMDULR 0x00200000
-#define SDRAM0_CFG_DRW_SHIFT (31-6)
-#define SDRAM0_CFG_BRPF_SHIFT (31-8)
+#define SDRAM0_CFG_DCE 0x80000000
+#define SDRAM0_CFG_SRE 0x40000000
+#define SDRAM0_CFG_PME 0x20000000
+#define SDRAM0_CFG_MEMCHK 0x10000000
+#define SDRAM0_CFG_REGEN 0x08000000
+#define SDRAM0_CFG_ECCDD 0x00400000
+#define SDRAM0_CFG_EMDULR 0x00200000
+#define SDRAM0_CFG_DRW_SHIFT (31-6)
+#define SDRAM0_CFG_BRPF_SHIFT (31-8)
-#define SDRAM0_TR_CASL_SHIFT (31-8)
-#define SDRAM0_TR_PTA_SHIFT (31-13)
-#define SDRAM0_TR_CTP_SHIFT (31-15)
-#define SDRAM0_TR_LDF_SHIFT (31-17)
-#define SDRAM0_TR_RFTA_SHIFT (31-29)
-#define SDRAM0_TR_RCD_SHIFT (31-31)
+#define SDRAM0_TR_CASL_SHIFT (31-8)
+#define SDRAM0_TR_PTA_SHIFT (31-13)
+#define SDRAM0_TR_CTP_SHIFT (31-15)
+#define SDRAM0_TR_LDF_SHIFT (31-17)
+#define SDRAM0_TR_RFTA_SHIFT (31-29)
+#define SDRAM0_TR_RCD_SHIFT (31-31)
-#define SDRAM0_RTR_SHIFT (31-15)
-#define SDRAM0_ECCCFG_SHIFT (31-11)
+#define SDRAM0_RTR_SHIFT (31-15)
+#define SDRAM0_ECCCFG_SHIFT (31-11)
/* SDRAM0_CFG enable macro */
#define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT )
-#define SDRAM0_BXCR_SZ_MASK 0x000e0000
-#define SDRAM0_BXCR_AM_MASK 0x0000e000
+#define SDRAM0_BXCR_SZ_MASK 0x000e0000
+#define SDRAM0_BXCR_AM_MASK 0x0000e000
-#define SDRAM0_BXCR_SZ_SHIFT (31-14)
-#define SDRAM0_BXCR_AM_SHIFT (31-18)
+#define SDRAM0_BXCR_SZ_SHIFT (31-14)
+#define SDRAM0_BXCR_AM_SHIFT (31-18)
-#define SDRAM0_BXCR_SZ(x) ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) )
-#define SDRAM0_BXCR_AM(x) ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) )
+#define SDRAM0_BXCR_SZ(x) ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) )
+#define SDRAM0_BXCR_AM(x) ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) )
#ifdef CONFIG_SPDDRAM_SILENT
# define SPD_ERR(x) do { return 0; } while (0)
* This function is reading data from the DIMM module EEPROM over the SPD bus
* and uses that to program the sdram controller.
*
- * This works on boards that has the same schematics that the IBM walnut has.
+ * This works on boards that has the same schematics that the AMCC walnut has.
*
* Input: null for default I2C spd functions or a pointer to a custom function
* returning spd_data.
* data from DIMM:
* 27 IN Row Precharge Time ( t RP)
* 29 MIN RAS to CAS Delay ( t RCD)
- * 127 Component and Clock Detail ,clk0-clk3, junction temp, CAS
+ * 127 Component and Clock Detail ,clk0-clk3, junction temp, CAS
* -------------------------------------------------------------------*/
/*
*/
tmp = read_spd(127) & 0x6;
- if (tmp == 0x02){ /* only cas = 2 supported */
+ if (tmp == 0x02) { /* only cas = 2 supported */
min_cas = 2;
-/* t_ck = read_spd(9); */
-/* t_ac = read_spd(10); */
- } else if (tmp == 0x04) { /* only cas = 3 supported */
+/* t_ck = read_spd(9); */
+/* t_ac = read_spd(10); */
+ } else if (tmp == 0x04) { /* only cas = 3 supported */
min_cas = 3;
-/* t_ck = read_spd(9); */
-/* t_ac = read_spd(10); */
- } else if (tmp == 0x06) { /* 2,3 supported, so use 2 */
+/* t_ck = read_spd(9); */
+/* t_ac = read_spd(10); */
+ } else if (tmp == 0x06) { /* 2,3 supported, so use 2 */
min_cas = 2;
-/* t_ck = read_spd(23); */
-/* t_ac = read_spd(24); */
+/* t_ck = read_spd(23); */
+/* t_ac = read_spd(24); */
} else {
SPD_ERR("SDRAM - unsupported CAS latency \n");
}
}
/* convert from nsec to bus cycles */
tmp = (tmp * 10) / bus_period_x_10;
- sdram0_rtr = (tmp & 0x3ff8) << SDRAM0_RTR_SHIFT;
+ sdram0_rtr = (tmp & 0x3ff8) << SDRAM0_RTR_SHIFT;
/*------------------------------------------------------------------
* determine the number of banks used
else if (tmp==4)
bank_cnt *= 4;
else
- bank_cnt = 8; /* 8 is an error code */
+ bank_cnt = 8; /* 8 is an error code */
if (bank_cnt > 4) /* we only have 4 banks to work with */
SPD_ERR("SDRAM - unsupported module rows for this width\n");
total_size *= read_spd(5); /* mult by module rows (dimm sides) */
/*------------------------------------------------------------------
- * map rows * cols * banks to a mode
+ * map rows * cols * banks to a mode
* -------------------------------------------------------------------*/
switch (row) {
bank_size = total_size / bank_cnt;
/* convert bank size to bank size code for ppc4xx
by takeing log2(bank_size) - 22 */
- tmp = bank_size; /* start with tmp = bank_size */
+ tmp = bank_size; /* start with tmp = bank_size */
bank_code = 0; /* and bank_code = 0 */
- while (tmp > 1) { /* this takes log2 of tmp */
+ while (tmp > 1) { /* this takes log2 of tmp */
bank_code++; /* and stores result in bank_code */
tmp = tmp >> 1;
} /* bank_code is now log2(bank_size) */
#endif
mtsdram0( mem_sdtr1 , sdram0_tr );
- /* SDRAM have a power on delay, 500 micro should do */
+ /* SDRAM have a power on delay, 500 micro should do */
udelay(500);
sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
if (ecc_on)
int spd_read(uint addr)
{
- char data[2];
+ uchar data[2];
if (i2c_read(SPD_EEPROM_ADDRESS, addr, 1, data, 1) == 0)
return (int)data[0];
return 0;
}
-#else /* CONFIG_440 */
+#else /* CONFIG_440 */
/*-----------------------------------------------------------------------------
| Memory Controller Options 0
+-----------------------------------------------------------------------------*/
-#define SDRAM_CFG0_DCEN 0x80000000 /* SDRAM Controller Enable */
-#define SDRAM_CFG0_MCHK_MASK 0x30000000 /* Memory data errchecking mask */
-#define SDRAM_CFG0_MCHK_NON 0x00000000 /* No ECC generation */
-#define SDRAM_CFG0_MCHK_GEN 0x20000000 /* ECC generation */
-#define SDRAM_CFG0_MCHK_CHK 0x30000000 /* ECC generation and checking */
-#define SDRAM_CFG0_RDEN 0x08000000 /* Registered DIMM enable */
-#define SDRAM_CFG0_PMUD 0x04000000 /* Page management unit */
-#define SDRAM_CFG0_DMWD_MASK 0x02000000 /* DRAM width mask */
-#define SDRAM_CFG0_DMWD_32 0x00000000 /* 32 bits */
-#define SDRAM_CFG0_DMWD_64 0x02000000 /* 64 bits */
-#define SDRAM_CFG0_UIOS_MASK 0x00C00000 /* Unused IO State */
-#define SDRAM_CFG0_PDP 0x00200000 /* Page deallocation policy */
+#define SDRAM_CFG0_DCEN 0x80000000 /* SDRAM Controller Enable */
+#define SDRAM_CFG0_MCHK_MASK 0x30000000 /* Memory data errchecking mask */
+#define SDRAM_CFG0_MCHK_NON 0x00000000 /* No ECC generation */
+#define SDRAM_CFG0_MCHK_GEN 0x20000000 /* ECC generation */
+#define SDRAM_CFG0_MCHK_CHK 0x30000000 /* ECC generation and checking */
+#define SDRAM_CFG0_RDEN 0x08000000 /* Registered DIMM enable */
+#define SDRAM_CFG0_PMUD 0x04000000 /* Page management unit */
+#define SDRAM_CFG0_DMWD_MASK 0x02000000 /* DRAM width mask */
+#define SDRAM_CFG0_DMWD_32 0x00000000 /* 32 bits */
+#define SDRAM_CFG0_DMWD_64 0x02000000 /* 64 bits */
+#define SDRAM_CFG0_UIOS_MASK 0x00C00000 /* Unused IO State */
+#define SDRAM_CFG0_PDP 0x00200000 /* Page deallocation policy */
/*-----------------------------------------------------------------------------
| Memory Controller Options 1
+-----------------------------------------------------------------------------*/
-#define SDRAM_CFG1_SRE 0x80000000 /* Self-Refresh Entry */
-#define SDRAM_CFG1_PMEN 0x40000000 /* Power Management Enable */
+#define SDRAM_CFG1_SRE 0x80000000 /* Self-Refresh Entry */
+#define SDRAM_CFG1_PMEN 0x40000000 /* Power Management Enable */
/*-----------------------------------------------------------------------------+
| SDRAM DEVPOT Options
+-----------------------------------------------------------------------------*/
-#define SDRAM_DEVOPT_DLL 0x80000000
-#define SDRAM_DEVOPT_DS 0x40000000
+#define SDRAM_DEVOPT_DLL 0x80000000
+#define SDRAM_DEVOPT_DS 0x40000000
/*-----------------------------------------------------------------------------+
| SDRAM MCSTS Options
+-----------------------------------------------------------------------------*/
-#define SDRAM_MCSTS_MRSC 0x80000000
-#define SDRAM_MCSTS_SRMS 0x40000000
-#define SDRAM_MCSTS_CIS 0x20000000
+#define SDRAM_MCSTS_MRSC 0x80000000
+#define SDRAM_MCSTS_SRMS 0x40000000
+#define SDRAM_MCSTS_CIS 0x20000000
/*-----------------------------------------------------------------------------
| SDRAM Refresh Timer Register
+-----------------------------------------------------------------------------*/
-#define SDRAM_RTR_RINT_MASK 0xFFFF0000
+#define SDRAM_RTR_RINT_MASK 0xFFFF0000
#define SDRAM_RTR_RINT_ENCODE(n) (((n) << 16) & SDRAM_RTR_RINT_MASK)
-#define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
+#define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
/*-----------------------------------------------------------------------------+
| SDRAM UABus Base Address Reg
+-----------------------------------------------------------------------------*/
-#define SDRAM_UABBA_UBBA_MASK 0x0000000F
+#define SDRAM_UABBA_UBBA_MASK 0x0000000F
/*-----------------------------------------------------------------------------+
| Memory Bank 0-7 configuration
+-----------------------------------------------------------------------------*/
-#define SDRAM_BXCR_SDBA_MASK 0xff800000 /* Base address */
-#define SDRAM_BXCR_SDSZ_MASK 0x000e0000 /* Size */
-#define SDRAM_BXCR_SDSZ_8 0x00020000 /* 8M */
-#define SDRAM_BXCR_SDSZ_16 0x00040000 /* 16M */
-#define SDRAM_BXCR_SDSZ_32 0x00060000 /* 32M */
-#define SDRAM_BXCR_SDSZ_64 0x00080000 /* 64M */
-#define SDRAM_BXCR_SDSZ_128 0x000a0000 /* 128M */
-#define SDRAM_BXCR_SDSZ_256 0x000c0000 /* 256M */
-#define SDRAM_BXCR_SDSZ_512 0x000e0000 /* 512M */
-#define SDRAM_BXCR_SDAM_MASK 0x0000e000 /* Addressing mode */
-#define SDRAM_BXCR_SDAM_1 0x00000000 /* Mode 1 */
-#define SDRAM_BXCR_SDAM_2 0x00002000 /* Mode 2 */
-#define SDRAM_BXCR_SDAM_3 0x00004000 /* Mode 3 */
-#define SDRAM_BXCR_SDAM_4 0x00006000 /* Mode 4 */
-#define SDRAM_BXCR_SDBE 0x00000001 /* Memory Bank Enable */
+#define SDRAM_BXCR_SDBA_MASK 0xff800000 /* Base address */
+#define SDRAM_BXCR_SDSZ_MASK 0x000e0000 /* Size */
+#define SDRAM_BXCR_SDSZ_8 0x00020000 /* 8M */
+#define SDRAM_BXCR_SDSZ_16 0x00040000 /* 16M */
+#define SDRAM_BXCR_SDSZ_32 0x00060000 /* 32M */
+#define SDRAM_BXCR_SDSZ_64 0x00080000 /* 64M */
+#define SDRAM_BXCR_SDSZ_128 0x000a0000 /* 128M */
+#define SDRAM_BXCR_SDSZ_256 0x000c0000 /* 256M */
+#define SDRAM_BXCR_SDSZ_512 0x000e0000 /* 512M */
+#define SDRAM_BXCR_SDAM_MASK 0x0000e000 /* Addressing mode */
+#define SDRAM_BXCR_SDAM_1 0x00000000 /* Mode 1 */
+#define SDRAM_BXCR_SDAM_2 0x00002000 /* Mode 2 */
+#define SDRAM_BXCR_SDAM_3 0x00004000 /* Mode 3 */
+#define SDRAM_BXCR_SDAM_4 0x00006000 /* Mode 4 */
+#define SDRAM_BXCR_SDBE 0x00000001 /* Memory Bank Enable */
/*-----------------------------------------------------------------------------+
| SDRAM TR0 Options
+-----------------------------------------------------------------------------*/
-#define SDRAM_TR0_SDWR_MASK 0x80000000
-#define SDRAM_TR0_SDWR_2_CLK 0x00000000
-#define SDRAM_TR0_SDWR_3_CLK 0x80000000
-#define SDRAM_TR0_SDWD_MASK 0x40000000
-#define SDRAM_TR0_SDWD_0_CLK 0x00000000
-#define SDRAM_TR0_SDWD_1_CLK 0x40000000
-#define SDRAM_TR0_SDCL_MASK 0x01800000
-#define SDRAM_TR0_SDCL_2_0_CLK 0x00800000
-#define SDRAM_TR0_SDCL_2_5_CLK 0x01000000
-#define SDRAM_TR0_SDCL_3_0_CLK 0x01800000
-#define SDRAM_TR0_SDPA_MASK 0x000C0000
-#define SDRAM_TR0_SDPA_2_CLK 0x00040000
-#define SDRAM_TR0_SDPA_3_CLK 0x00080000
-#define SDRAM_TR0_SDPA_4_CLK 0x000C0000
-#define SDRAM_TR0_SDCP_MASK 0x00030000
-#define SDRAM_TR0_SDCP_2_CLK 0x00000000
-#define SDRAM_TR0_SDCP_3_CLK 0x00010000
-#define SDRAM_TR0_SDCP_4_CLK 0x00020000
-#define SDRAM_TR0_SDCP_5_CLK 0x00030000
-#define SDRAM_TR0_SDLD_MASK 0x0000C000
-#define SDRAM_TR0_SDLD_1_CLK 0x00000000
-#define SDRAM_TR0_SDLD_2_CLK 0x00004000
-#define SDRAM_TR0_SDRA_MASK 0x0000001C
-#define SDRAM_TR0_SDRA_6_CLK 0x00000000
-#define SDRAM_TR0_SDRA_7_CLK 0x00000004
-#define SDRAM_TR0_SDRA_8_CLK 0x00000008
-#define SDRAM_TR0_SDRA_9_CLK 0x0000000C
-#define SDRAM_TR0_SDRA_10_CLK 0x00000010
-#define SDRAM_TR0_SDRA_11_CLK 0x00000014
-#define SDRAM_TR0_SDRA_12_CLK 0x00000018
-#define SDRAM_TR0_SDRA_13_CLK 0x0000001C
-#define SDRAM_TR0_SDRD_MASK 0x00000003
-#define SDRAM_TR0_SDRD_2_CLK 0x00000001
-#define SDRAM_TR0_SDRD_3_CLK 0x00000002
-#define SDRAM_TR0_SDRD_4_CLK 0x00000003
+#define SDRAM_TR0_SDWR_MASK 0x80000000
+#define SDRAM_TR0_SDWR_2_CLK 0x00000000
+#define SDRAM_TR0_SDWR_3_CLK 0x80000000
+#define SDRAM_TR0_SDWD_MASK 0x40000000
+#define SDRAM_TR0_SDWD_0_CLK 0x00000000
+#define SDRAM_TR0_SDWD_1_CLK 0x40000000
+#define SDRAM_TR0_SDCL_MASK 0x01800000
+#define SDRAM_TR0_SDCL_2_0_CLK 0x00800000
+#define SDRAM_TR0_SDCL_2_5_CLK 0x01000000
+#define SDRAM_TR0_SDCL_3_0_CLK 0x01800000
+#define SDRAM_TR0_SDPA_MASK 0x000C0000
+#define SDRAM_TR0_SDPA_2_CLK 0x00040000
+#define SDRAM_TR0_SDPA_3_CLK 0x00080000
+#define SDRAM_TR0_SDPA_4_CLK 0x000C0000
+#define SDRAM_TR0_SDCP_MASK 0x00030000
+#define SDRAM_TR0_SDCP_2_CLK 0x00000000
+#define SDRAM_TR0_SDCP_3_CLK 0x00010000
+#define SDRAM_TR0_SDCP_4_CLK 0x00020000
+#define SDRAM_TR0_SDCP_5_CLK 0x00030000
+#define SDRAM_TR0_SDLD_MASK 0x0000C000
+#define SDRAM_TR0_SDLD_1_CLK 0x00000000
+#define SDRAM_TR0_SDLD_2_CLK 0x00004000
+#define SDRAM_TR0_SDRA_MASK 0x0000001C
+#define SDRAM_TR0_SDRA_6_CLK 0x00000000
+#define SDRAM_TR0_SDRA_7_CLK 0x00000004
+#define SDRAM_TR0_SDRA_8_CLK 0x00000008
+#define SDRAM_TR0_SDRA_9_CLK 0x0000000C
+#define SDRAM_TR0_SDRA_10_CLK 0x00000010
+#define SDRAM_TR0_SDRA_11_CLK 0x00000014
+#define SDRAM_TR0_SDRA_12_CLK 0x00000018
+#define SDRAM_TR0_SDRA_13_CLK 0x0000001C
+#define SDRAM_TR0_SDRD_MASK 0x00000003
+#define SDRAM_TR0_SDRD_2_CLK 0x00000001
+#define SDRAM_TR0_SDRD_3_CLK 0x00000002
+#define SDRAM_TR0_SDRD_4_CLK 0x00000003
/*-----------------------------------------------------------------------------+
| SDRAM TR1 Options
+-----------------------------------------------------------------------------*/
-#define SDRAM_TR1_RDSS_MASK 0xC0000000
-#define SDRAM_TR1_RDSS_TR0 0x00000000
-#define SDRAM_TR1_RDSS_TR1 0x40000000
-#define SDRAM_TR1_RDSS_TR2 0x80000000
-#define SDRAM_TR1_RDSS_TR3 0xC0000000
-#define SDRAM_TR1_RDSL_MASK 0x00C00000
-#define SDRAM_TR1_RDSL_STAGE1 0x00000000
-#define SDRAM_TR1_RDSL_STAGE2 0x00400000
-#define SDRAM_TR1_RDSL_STAGE3 0x00800000
-#define SDRAM_TR1_RDCD_MASK 0x00000800
-#define SDRAM_TR1_RDCD_RCD_0_0 0x00000000
-#define SDRAM_TR1_RDCD_RCD_1_2 0x00000800
-#define SDRAM_TR1_RDCT_MASK 0x000001FF
-#define SDRAM_TR1_RDCT_ENCODE(x) (((x) << 0) & SDRAM_TR1_RDCT_MASK)
-#define SDRAM_TR1_RDCT_DECODE(x) (((x) & SDRAM_TR1_RDCT_MASK) >> 0)
-#define SDRAM_TR1_RDCT_MIN 0x00000000
-#define SDRAM_TR1_RDCT_MAX 0x000001FF
+#define SDRAM_TR1_RDSS_MASK 0xC0000000
+#define SDRAM_TR1_RDSS_TR0 0x00000000
+#define SDRAM_TR1_RDSS_TR1 0x40000000
+#define SDRAM_TR1_RDSS_TR2 0x80000000
+#define SDRAM_TR1_RDSS_TR3 0xC0000000
+#define SDRAM_TR1_RDSL_MASK 0x00C00000
+#define SDRAM_TR1_RDSL_STAGE1 0x00000000
+#define SDRAM_TR1_RDSL_STAGE2 0x00400000
+#define SDRAM_TR1_RDSL_STAGE3 0x00800000
+#define SDRAM_TR1_RDCD_MASK 0x00000800
+#define SDRAM_TR1_RDCD_RCD_0_0 0x00000000
+#define SDRAM_TR1_RDCD_RCD_1_2 0x00000800
+#define SDRAM_TR1_RDCT_MASK 0x000001FF
+#define SDRAM_TR1_RDCT_ENCODE(x) (((x) << 0) & SDRAM_TR1_RDCT_MASK)
+#define SDRAM_TR1_RDCT_DECODE(x) (((x) & SDRAM_TR1_RDCT_MASK) >> 0)
+#define SDRAM_TR1_RDCT_MIN 0x00000000
+#define SDRAM_TR1_RDCT_MAX 0x000001FF
/*-----------------------------------------------------------------------------+
| SDRAM WDDCTR Options
+-----------------------------------------------------------------------------*/
-#define SDRAM_WDDCTR_WRCP_MASK 0xC0000000
-#define SDRAM_WDDCTR_WRCP_0DEG 0x00000000
-#define SDRAM_WDDCTR_WRCP_90DEG 0x40000000
-#define SDRAM_WDDCTR_WRCP_180DEG 0x80000000
-#define SDRAM_WDDCTR_DCD_MASK 0x000001FF
+#define SDRAM_WDDCTR_WRCP_MASK 0xC0000000
+#define SDRAM_WDDCTR_WRCP_0DEG 0x00000000
+#define SDRAM_WDDCTR_WRCP_90DEG 0x40000000
+#define SDRAM_WDDCTR_WRCP_180DEG 0x80000000
+#define SDRAM_WDDCTR_DCD_MASK 0x000001FF
/*-----------------------------------------------------------------------------+
| SDRAM CLKTR Options
+-----------------------------------------------------------------------------*/
-#define SDRAM_CLKTR_CLKP_MASK 0xC0000000
-#define SDRAM_CLKTR_CLKP_0DEG 0x00000000
-#define SDRAM_CLKTR_CLKP_90DEG 0x40000000
-#define SDRAM_CLKTR_CLKP_180DEG 0x80000000
-#define SDRAM_CLKTR_DCDT_MASK 0x000001FF
+#define SDRAM_CLKTR_CLKP_MASK 0xC0000000
+#define SDRAM_CLKTR_CLKP_0DEG 0x00000000
+#define SDRAM_CLKTR_CLKP_90DEG 0x40000000
+#define SDRAM_CLKTR_CLKP_180DEG 0x80000000
+#define SDRAM_CLKTR_DCDT_MASK 0x000001FF
/*-----------------------------------------------------------------------------+
| SDRAM DLYCAL Options
+-----------------------------------------------------------------------------*/
-#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
-#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
-#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
+#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
+#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
+#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
/*-----------------------------------------------------------------------------+
| General Definition
+-----------------------------------------------------------------------------*/
-#define DEFAULT_SPD_ADDR1 0x53
-#define DEFAULT_SPD_ADDR2 0x52
-#define MAXBANKS 4 /* at most 4 dimm banks */
-#define MAX_SPD_BYTES 256
-#define NUMHALFCYCLES 4
-#define NUMMEMTESTS 8
-#define NUMMEMWORDS 8
-#define MAXBXCR 4
-#define TRUE 1
-#define FALSE 0
+#define DEFAULT_SPD_ADDR1 0x53
+#define DEFAULT_SPD_ADDR2 0x52
+#define MAXBANKS 4 /* at most 4 dimm banks */
+#define MAX_SPD_BYTES 256
+#define NUMHALFCYCLES 4
+#define NUMMEMTESTS 8
+#define NUMMEMWORDS 8
+#define MAXBXCR 4
+#define TRUE 1
+#define FALSE 0
const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
{0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xAA55AA55, 0xAA55AA55}
};
+/* bank_parms is used to sort the bank sizes by descending order */
+struct bank_param {
+ unsigned long cr;
+ unsigned long bank_size_bytes;
+};
+
+typedef struct bank_param BANKPARMS;
+
+#ifdef CFG_SIMULATE_SPD_EEPROM
+extern unsigned char cfg_simulate_spd_eeprom[128];
+#endif
unsigned char spd_read(uchar chip, uint addr);
void get_spd_info(unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks);
+ unsigned long num_dimm_banks);
void check_mem_type
(unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks);
+ unsigned long num_dimm_banks);
void check_volt_type
(unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks);
+ unsigned long num_dimm_banks);
void program_cfg0(unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks);
+ unsigned long num_dimm_banks);
void program_cfg1(unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks);
+ unsigned long num_dimm_banks);
void program_rtr (unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks);
+ unsigned long num_dimm_banks);
void program_tr0 (unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks);
+ unsigned long num_dimm_banks);
void program_tr1 (void);
-void program_ecc (unsigned long num_bytes);
+void program_ecc (unsigned long num_bytes);
unsigned
long program_bxcr(unsigned long* dimm_populated,
* This function is reading data from the DIMM module EEPROM over the SPD bus
* and uses that to program the sdram controller.
*
- * This works on boards that has the same schematics that the IBM walnut has.
+ * This works on boards that has the same schematics that the AMCC walnut has.
*
* BUG: Don't handle ECC memory
* BUG: A few values in the TR register is currently hardcoded
unsigned long total_size;
unsigned long cfg0;
unsigned long mcsts;
- unsigned long num_dimm_banks; /* on board dimm banks */
+ unsigned long num_dimm_banks; /* on board dimm banks */
num_dimm_banks = sizeof(iic0_dimm_addr);
return total_size;
}
-unsigned char spd_read(uchar chip, uint addr) {
+unsigned char spd_read(uchar chip, uint addr)
+{
unsigned char data[2];
+#ifdef CFG_SIMULATE_SPD_EEPROM
+ if (chip == CFG_SIMULATE_SPD_EEPROM) {
+ /*
+ * Onboard spd eeprom requested -> simulate values
+ */
+ return cfg_simulate_spd_eeprom[addr];
+ }
+#endif /* CFG_SIMULATE_SPD_EEPROM */
+
if (i2c_probe(chip) == 0) {
if (i2c_read(chip, addr, 1, data, 1) == 0) {
return data[0];
void get_spd_info(unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks)
+ unsigned long num_dimm_banks)
{
unsigned long dimm_num;
unsigned long dimm_found;
void program_cfg0(unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks)
+ unsigned long num_dimm_banks)
{
unsigned long dimm_num;
unsigned long cfg0;
void program_cfg1(unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks)
+ unsigned long num_dimm_banks)
{
unsigned long cfg1;
mfsdram(mem_cfg1, cfg1);
void program_rtr (unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks)
+ unsigned long num_dimm_banks)
{
unsigned long dimm_num;
unsigned long bus_period_x_10;
void program_tr0 (unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks)
+ unsigned long num_dimm_banks)
{
unsigned long dimm_num;
unsigned long tr0;
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
if (dimm_populated[dimm_num] == TRUE) {
wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
- t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
+ t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30);
cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
/*
* Program SD_WR and SD_WCSBC fields
*/
- tr0 |= SDRAM_TR0_SDWR_2_CLK; /* Write Recovery: 2 CLK */
+ tr0 |= SDRAM_TR0_SDWR_2_CLK; /* Write Recovery: 2 CLK */
switch (wcsbc) {
case 0:
tr0 |= SDRAM_TR0_SDWD_0_CLK;
{
unsigned long dimm_num;
unsigned long bank_base_addr;
- unsigned long bank_size_bytes;
unsigned long cr;
unsigned long i;
+ unsigned long j;
unsigned long temp;
unsigned char num_row_addr;
unsigned char num_col_addr;
unsigned char num_banks;
unsigned char bank_size_id;
-
-#ifndef CONFIG_BAMBOO
- unsigned long bxcr_num;
+ unsigned long ctrl_bank_num[MAXBANKS];
+ unsigned long bx_cr_num;
+ unsigned long largest_size_index;
+ unsigned long largest_size;
+ unsigned long current_size_index;
+ BANKPARMS bank_parms[MAXBXCR];
+ unsigned long sorted_bank_num[MAXBXCR]; /* DDR Controller bank number table (sorted by size) */
+ unsigned long sorted_bank_size[MAXBXCR]; /* DDR Controller bank size table (sorted by size)*/
/*
* Set the BxCR regs. First, wipe out the bank config registers.
*/
- for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
- mtdcr(memcfga, mem_b0cr + (bxcr_num << 2));
+ for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
+ mtdcr(memcfga, mem_b0cr + (bx_cr_num << 2));
mtdcr(memcfgd, 0x00000000);
+ bank_parms[bx_cr_num].bank_size_bytes = 0;
}
+
+#ifdef CONFIG_BAMBOO
+ /*
+ * This next section is hardware dependent and must be programmed
+ * to match the hardware. For bammboo, the following holds...
+ * 1. SDRAM0_B0CR: Bank 0 of dimm 0 ctrl_bank_num : 0
+ * 2. SDRAM0_B1CR: Bank 0 of dimm 1 ctrl_bank_num : 1
+ * 3. SDRAM0_B2CR: Bank 1 of dimm 1 ctrl_bank_num : 1
+ * 4. SDRAM0_B3CR: Bank 0 of dimm 2 ctrl_bank_num : 3
+ * ctrl_bank_num corresponds to the first usable DDR controller bank number by DIMM
+ */
+ ctrl_bank_num[0] = 0;
+ ctrl_bank_num[1] = 1;
+ ctrl_bank_num[2] = 3;
+#else
+ ctrl_bank_num[0] = 0;
+ ctrl_bank_num[1] = 1;
+ ctrl_bank_num[2] = 2;
+ ctrl_bank_num[3] = 3;
#endif
/*
* reset the bank_base address
*/
-#ifndef CONFIG_BAMBOO
bank_base_addr = CFG_SDRAM_BASE;
-#else
- bank_base_addr = CFG_SDRAM_ONBOARD_SIZE;
-#endif
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
if (dimm_populated[dimm_num] == TRUE) {
* Set the SDRAM0_BxCR regs
*/
cr = 0;
- bank_size_bytes = 4 * 1024 * 1024 * bank_size_id;
switch (bank_size_id) {
case 0x02:
cr |= SDRAM_BXCR_SDSZ_8;
*/
cr |= SDRAM_BXCR_SDBE;
- /*------------------------------------------------------------------
- | This next section is hardware dependent and must be programmed
- | to match the hardware.
- +-----------------------------------------------------------------*/
- if (dimm_num == 0) {
- for (i = 0; i < num_banks; i++) {
-#ifndef CONFIG_BAMBOO
- mtdcr(memcfga, mem_b0cr + (i << 2));
-#else
- mtdcr(memcfga, mem_b1cr + (i << 2));
-#endif
- temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
- SDRAM_BXCR_SDSZ_MASK |
- SDRAM_BXCR_SDAM_MASK |
- SDRAM_BXCR_SDBE);
- cr |= temp;
- cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
- mtdcr(memcfgd, cr);
- bank_base_addr += bank_size_bytes;
- }
- } else {
- for (i = 0; i < num_banks; i++) {
-#ifndef CONFIG_BAMBOO
- mtdcr(memcfga, mem_b2cr + (i << 2));
-#else
- mtdcr(memcfga, mem_b3cr + (i << 2));
-#endif
- temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
- SDRAM_BXCR_SDSZ_MASK |
- SDRAM_BXCR_SDAM_MASK |
- SDRAM_BXCR_SDBE);
- cr |= temp;
- cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
- mtdcr(memcfgd, cr);
- bank_base_addr += bank_size_bytes;
- }
+ for (i = 0; i < num_banks; i++) {
+ bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes =
+ (4 * 1024 * 1024) * bank_size_id;
+ bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr;
}
}
}
+ /* Initialize sort tables */
+ for (i = 0; i < MAXBXCR; i++) {
+ sorted_bank_num[i] = i;
+ sorted_bank_size[i] = bank_parms[i].bank_size_bytes;
+ }
+
+ for (i = 0; i < MAXBXCR-1; i++) {
+ largest_size = sorted_bank_size[i];
+ largest_size_index = 255;
+
+ /* Find the largest remaining value */
+ for (j = i + 1; j < MAXBXCR; j++) {
+ if (sorted_bank_size[j] > largest_size) {
+ /* Save largest remaining value and its index */
+ largest_size = sorted_bank_size[j];
+ largest_size_index = j;
+ }
+ }
+
+ if (largest_size_index != 255) {
+ /* Swap the current and largest values */
+ current_size_index = sorted_bank_num[largest_size_index];
+ sorted_bank_size[largest_size_index] = sorted_bank_size[i];
+ sorted_bank_size[i] = largest_size;
+ sorted_bank_num[largest_size_index] = sorted_bank_num[i];
+ sorted_bank_num[i] = current_size_index;
+ }
+ }
+
+ /* Set the SDRAM0_BxCR regs thanks to sort tables */
+ for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
+ if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) {
+ mtdcr(memcfga, mem_b0cr + (sorted_bank_num[bx_cr_num] << 2));
+ temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK |
+ SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE);
+ temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) |
+ bank_parms[sorted_bank_num[bx_cr_num]].cr;
+ mtdcr(memcfgd, temp);
+ bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes;
+ }
+ }
+
return(bank_base_addr);
}
-void program_ecc (unsigned long num_bytes)
+void program_ecc (unsigned long num_bytes)
{
unsigned long bank_base_addr;
unsigned long current_address;
return sys_info.freqPCI;
}
-#elif !defined(CONFIG_440GX)
+#elif !defined(CONFIG_440GX) && !defined(CONFIG_440SP)
void get_sys_info (sys_info_t * sysInfo)
{
unsigned long strp0;
extern void get_sys_info (sys_info_t * sysInfo);
extern ulong get_PCI_freq (void);
+#elif defined(CONFIG_AP1000)
+void get_sys_info (sys_info_t * sysInfo) {
+ sysInfo->freqProcessor = 240 * 1000 * 1000;
+ sysInfo->freqPLB = 80 * 1000 * 1000;
+ sysInfo->freqPCI = 33 * 1000 * 1000;
+}
+
#elif defined(CONFIG_405)
void get_sys_info (sys_info_t * sysInfo) {
/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */
/*------------------------------------------------------------------------------- */
-/* U-Boot - Startup Code for IBM 4xx PowerPC based Embedded Boards
+/* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
*
*
* The processor starts at 0xfffffffc and the code is executed
mtspr srr1,r0
mtspr csrr0,r0
mtspr csrr1,r0
-#if defined (CONFIG_440GX) /* NOTE: 440GX adds machine check status regs */
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP) /* NOTE: 440GX adds machine check status regs */
mtspr mcsrr0,r0
mtspr mcsrr1,r0
mfspr r1, mcsr
addi r3,r3,32
bdnz ..d_ag
#else
-#if defined (CONFIG_440GX)
+#if defined (CONFIG_440GX) || defined(CONFIG_440SP)
mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
#endif
mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
mtdcr isram0_pmeg,r1
lis r1,0x8000 /* BAS = 8000_0000 */
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
ori r1,r1,0x0980 /* first 64k */
mtdcr isram0_sb0cr,r1
lis r1,0x8001
/*----------------------------------------------------------------*/
lis r1,CFG_INIT_RAM_ADDR@h
ori r1,r1,CFG_INIT_SP_OFFSET@l
-
li r0,0
stwu r0,-4(r1)
stwu r0,-4(r1) /* Terminate call chain */
stw r0,+12(r1) /* Save return addr (underflow vect) */
GET_GOT
+
+ bl cpu_init_f /* run low-level CPU init code (from Flash) */
bl board_init_f
#endif /* CONFIG_440 */
invalidate_dcache:
addi r6,0,0x0000 /* clear GPR 6 */
/* Do loop for # of dcache congruence classes. */
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */
ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
-#else
- addi r7,r0, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
-#endif
/* NOTE: dccci invalidates both */
mtctr r7 /* ways in the D cache */
..dcloop:
mtdccr r10
/* do loop for # of congruence classes. */
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
lis r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS: for large cache sizes */
ori r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
lis r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */
ori r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */
-#else
- addi r10,r0,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
- addi r11,r0,(CFG_DCACHE_SIZE / 2) /* D cache set size - 2 way sets */
-#endif
mtctr r10
addi r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */
add r11,r10,r11 /* add to get to other side of cache line */
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
dccci 0,0 /* Invalidate data cache, now no longer our stack */
sync
- addi r1,r0,0x0000 /* Tlb entry #0 */
+ addi r1,r0,0x0000 /* TLB entry #0 */
tlbre r0,r1,0x0002 /* Read contents */
- ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
+ ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
tlbwe r0,r1,0x0002 /* Save it out */
isync
#endif
#ifndef _VECNUMS_H_
#define _VECNUMS_H_
-#if defined(CONFIG_440)
+#if defined(CONFIG_440SP)
+
+/* UIC 0 */
+#define VECNUM_U0 0 /* UART0 */
+#define VECNUM_U1 1 /* UART1 */
+#define VECNUM_IIC0 2 /* IIC0 */
+#define VECNUM_IIC1 3 /* IIC1 */
+#define VECNUM_PIM 4 /* PCI inbound message */
+#define VECNUM_PCRW 5 /* PCI command reg write */
+#define VECNUM_PPM 6 /* PCI power management */
+#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
+#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
+
+/* UIC 1 */
+#define VECNUM_EIR0 (32 + 0) /* External interrupt 0 */
+#define VECNUM_MS (32 + 1) /* MAL SERR */
+#define VECNUM_TXDE (32 + 2) /* MAL TXDE */
+#define VECNUM_RXDE (32 + 3) /* MAL RXDE */
+#define VECNUM_MTE (32 + 6) /* MAL Tx EOB */
+#define VECNUM_MRE (32 + 7) /* MAL Rx EOB */
+#define VECNUM_CT0 (32 + 12) /* GPT compare timer 0 */
+#define VECNUM_CT1 (32 + 13) /* GPT compare timer 1 */
+#define VECNUM_CT2 (32 + 14) /* GPT compare timer 2 */
+#define VECNUM_CT3 (32 + 15) /* GPT compare timer 3 */
+#define VECNUM_CT4 (32 + 16) /* GPT compare timer 4 */
+#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */
+#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */
+
+#elif defined(CONFIG_440)
/* UIC 0 */
#define VECNUM_U0 0 /* UART0 */
#
PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
- -mshort-load-bytes -msoft-float
+ -msoft-float
#PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100
-PLATFORM_CPPFLAGS += -mapcs-32 -march=armv5 -mtune=xscale
+PLATFORM_CPPFLAGS += -march=armv5 -mtune=xscale
+# =========================================================================
+#
+# Supply options according to compiler version
+#
+# ========================================================================
+PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
+PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
#
PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
- -mshort-load-bytes -msoft-float
+ -msoft-float
-PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=arm7tdmi -msoft-float
+PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi -msoft-float
+# =========================================================================
+#
+# Supply options according to compiler version
+#
+# ========================================================================
+PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
+PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
#
PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
- -mshort-load-bytes -msoft-float
+ -msoft-float
-PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100
+PLATFORM_CPPFLAGS += -march=armv4 -mtune=strongarm1100
+# =========================================================================
+#
+# Supply options according to compiler version
+#
+# ========================================================================
+PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
+PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
(buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) ) {
return (-1);
} /* no DOS Signature at all */
- if(strncmp(&buffer[DOS_PBR_FSTYPE_OFFSET],"FAT",3)==0)
+ if(strncmp((char *)&buffer[DOS_PBR_FSTYPE_OFFSET],"FAT",3)==0)
return DOS_PBR; /* is PBR */
return DOS_MBR; /* Is MBR */
}
switch(dev_desc->if_type) {
case IF_TYPE_IDE:
case IF_TYPE_ATAPI:
- sprintf (info->name, "hd%c%d\n", 'a' + dev_desc->dev, part_num);
+ sprintf ((char *)info->name, "hd%c%d\n", 'a' + dev_desc->dev, part_num);
break;
case IF_TYPE_SCSI:
- sprintf (info->name, "sd%c%d\n", 'a' + dev_desc->dev, part_num);
+ sprintf ((char *)info->name, "sd%c%d\n", 'a' + dev_desc->dev, part_num);
break;
case IF_TYPE_USB:
- sprintf (info->name, "usbd%c%d\n", 'a' + dev_desc->dev, part_num);
+ sprintf ((char *)info->name, "usbd%c%d\n", 'a' + dev_desc->dev, part_num);
break;
case IF_TYPE_DOC:
- sprintf (info->name, "docd%c%d\n", 'a' + dev_desc->dev, part_num);
+ sprintf ((char *)info->name, "docd%c%d\n", 'a' + dev_desc->dev, part_num);
break;
default:
- sprintf (info->name, "xx%c%d\n", 'a' + dev_desc->dev, part_num);
+ sprintf ((char *)info->name, "xx%c%d\n", 'a' + dev_desc->dev, part_num);
break;
}
/* sprintf(info->type, "%d, pt->sys_ind); */
- sprintf (info->type, "U-Boot");
+ sprintf ((char *)info->type, "U-Boot");
return 0;
}
dev_desc->dev, part_num);
return (-1);
}
- if(strncmp(ppr->stand_ident,"CD001",5)!=0) {
+ if(strncmp((char *)ppr->stand_ident,"CD001",5)!=0) {
if(verb)
printf ("** Wrong ISO Ident: %s on %d:%d **\n",
ppr->stand_ident,dev_desc->dev, part_num);
/* the validation entry seems to be ok, now search the "partition" */
entry_num=0;
offset=0x20;
- sprintf (info->type, "U-Boot");
+ sprintf ((char *)info->type, "U-Boot");
switch(dev_desc->if_type) {
case IF_TYPE_IDE:
case IF_TYPE_ATAPI:
- sprintf (info->name, "hd%c%d\n", 'a' + dev_desc->dev, part_num);
+ sprintf ((char *)info->name, "hd%c%d\n", 'a' + dev_desc->dev, part_num);
break;
case IF_TYPE_SCSI:
- sprintf (info->name, "sd%c%d\n", 'a' + dev_desc->dev, part_num);
+ sprintf ((char *)info->name, "sd%c%d\n", 'a' + dev_desc->dev, part_num);
break;
case IF_TYPE_USB:
- sprintf (info->name, "usbd%c%d\n", 'a' + dev_desc->dev, part_num);
+ sprintf ((char *)info->name, "usbd%c%d\n", 'a' + dev_desc->dev, part_num);
break;
case IF_TYPE_DOC:
- sprintf (info->name, "docd%c%d\n", 'a' + dev_desc->dev, part_num);
+ sprintf ((char *)info->name, "docd%c%d\n", 'a' + dev_desc->dev, part_num);
break;
default:
- sprintf (info->name, "xx%c%d\n", 'a' + dev_desc->dev, part_num);
+ sprintf ((char *)info->name, "xx%c%d\n", 'a' + dev_desc->dev, part_num);
break;
}
/* the bootcatalog (including validation Entry) is limited to 2048Bytes
Notes
-----
-!!!THIS IS AN UNDOCUMENTED I2C BUS BUG, NOT A IBM 4xx BUG!!!
+!!!THIS IS AN UNDOCUMENTED I2C BUS BUG, NOT A AMCC 4xx BUG!!!
This reset edge condition could possibly be present in every I2C
controller and device available. For boards where a I2C bus reset
--- /dev/null
+
+ U-Boot for ARM Integrator Development Platforms
+
+ Peter Pearse, ARM Ltd.
+ peter.pearse@arm.com
+ www.arm.com
+
+Manuals available from :-
+http://www.arm.com/products/DevTools/Hardware_Platforms.html
+
+Overview :
+--------
+There are two Integrator variants - Integrator/AP and Integrator/CP.
+Each may be fitted with a variety of core modules (CMs).
+Each CM consists of a ARM processor core and associated hardware e.g
+ FPGA implementing various controllers and/or register
+ SSRAM
+ SDRAM
+ RAM controllers
+ clock generators etc.
+CMs may be fitted with varying amounts of SDRAM using a DIMM socket.
+
+Boot Methods :
+------------
+Integrator platforms can be configured to use U-Boot in at least three ways :-
+a) Run ARM boot monitor, manually run U-Boot image from flash
+b) Run ARM boot monitor, automatically run U-Boot image from flash
+c) Run U-Boot image direct from flash.
+
+In cases a) and b) the ARM boot monitor will have configured the CM and mapped
+writeable memory to 0x00000000 in the Integrator address space.
+U-Boot has to carry out minimal configration before standard code is run.
+
+In case c) it may be necessary for U-Boot to perform CM dependent initialization.
+
+Configuring U-Boot :
+------------------
+ The makefile contains targets for Integrator platforms of both types
+fitted with all current variants of CM. If these targets are to be used with
+boot process c) above then CONFIG_INIT_CRITICAL may need to be defined to ensure
+that the CM is correctly configured.
+
+ There are also targets independent of CM. These may not be suitable for
+boot process c) above. They have been preserved for backward compatibility with
+existing build processes.
+
+Code Hierarchy Applied :
+----------------------
+Code specific to initialization of a particular ARM processor has been placed in
+cpu/arm<>/start.S so that it may be used by other boards.
+
+However, to avoid duplicating code through all processor files, a generic core
+for ARM Integrator CMs has been added
+
+ cpu/arm_intcm
+
+Otherwise. for example, the standard CM reset via the CM control register would
+need placing in each CM processor file......
+
+Code specific to the initialization of the CM, rather than the cpu, and initialization
+of the Integrator board itself, has been placed in
+
+ board/integrator<>/platform.S
+ board/integrator<>/integrator<>.c
+
+Targets
+=======
+The U-Boot make targets map to the available core modules as below.
+
+Integrator/AP is no longer available from ARM.
+Core modules marked ** are also no longer available.
+
+ap720t_config ** CM720T
+ap920t_config ** CM920T
+ap926ejs_config Integrator Core Module for ARM926EJ-STM
+ap946es_config Integrator Core Module for ARM946E-STM
+cp920t_config ** CM920T
+cp926ejs_config Integrator Core Module for ARM926EJ-STM
+cp946es_config Integrator Core Module for ARM946E-STM
+cp1136_config Integrator Core Module ARM1136JF-S TM
+
+The final groups of targets are for core modules where no explicit cpu
+code has yet been added to U-Boot i.e. they all use the same U-Boot binary
+using the generic "arm_intcm" core:
+
+ap966_config Integrator Core Module for ARM966E-S TM
+ap922_config Integrator Core Module for ARM922T TM with ETM
+ap922_XA10_config Integrator Core Module for ARM922T using Altera Excalibur
+ap7_config ** CM7TDMI
+integratorap_config
+ap_config
+
+
+cp966_config Integrator Core Module for ARM966E-S TM
+cp922_config Integrator Core Module for ARM922T TM with ETM
+cp922_XA10_config Integrator Core Module for ARM922T using Altera Excalibur
+cp1026_config Integrator Core Module ARM1026EJ-S TM
+integratorcp_config
+cp_config
+
+The Makefile targets call board/integrator<>/split_by_variant.sh
+to configure various defines in include/configs/integrator<>.h
+to indicate the core module & core configuration and ensure that
+board/integrator<>/u-boot.lds loads the cpu object first in the U-Boot image.
+
+*********************************
+Because of this mechanism
+> make clean
+must be run before each change in configuration
+*********************************
--- /dev/null
+Open Firmware Flat Tree and usage.
+----------------------------------
+
+As part of the ongoing cleanup of the Linux PPC trees, the preferred
+way to pass bootloader and board setup information is the open
+firmware flat tree.
+
+Please take a look at the following email discussion for some
+background.
+
+ http://ozlabs.org/pipermail/linuxppc-dev/2005-August/019408.html
+ http://ozlabs.org/pipermail/linuxppc-dev/2005-August/019362.html
+
+The generated tree is part static and part dynamic.
+
+There is a static part which is compiled in with DTC and a dynamic
+part which is programmatically appended.
+
+You'll need a fairly recent DTC tool, which is available by git at
+
+ rsync://ozlabs.org/dtc/dtc.git
+
+The xxd binary dumper is needed too which I got from
+
+ ftp://ftp.uni-erlangen.de/pub/utilities/etc/xxd-1.10.tar.gz
+
+
+Pantelis Antoniou, 13 Oct 2005
hostname=sp1
ethaddr=00:03:47:97:E4:6B
load=tftp 100000 u-boot.bin
-update=protect off all;era FFF00000 FFF3FFFF;cp.b 100000 FFF00000 $(filesize);saveenv
+update=protect off all;era FFF00000 FFF3FFFF;cp.b 100000 FFF00000 ${filesize};saveenv
filesize=1f304
gatewayip=145.17.228.1
netmask=255.255.255.0
You can put these commands into some environment variables;
=> setenv load tftp 100000 u-boot.bin
-=> setenv update protect off all\;era FFF00000 FFF3FFFF\;cp.b 100000 FFF00000 \$(filesize)\;saveenv
+=> setenv update protect off all\;era FFF00000 FFF3FFFF\;cp.b 100000 FFF00000 \${filesize}\;saveenv
=> saveenv
Then you just have to type "run load" then "run update"
--------------------------
These changes implement the bedbug (emBEDded deBUGger) debugger in U-Boot.
-A specific implementation is made for the IBM405 processor but other flavors
+A specific implementation is made for the AMCC 405 processor but other flavors
can be easily implemented.
#####################
routines are common to all PowerPC processors.
./cpu/ppc4xx/bedbug_405.c
- IBM PPC405 specific debugger routines.
+ AMCC PPC405 specific debugger routines.
Bedbug support for the MPC860
at the Altera Standard 32 to SRAM:
- ==> cp.b 800000 40000 $(filesize)
+ ==> cp.b 800000 40000 ${filesize}
at the Microtronix LDK 2.0 to SDRAM:
- ==> cp.b 1010000 8000000 $(filesize)
+ ==> cp.b 1010000 8000000 ${filesize}
U-Boot will now automatically start when the board is powered on or
reset using the Standard-32 configuration. To start U-Boot with the
- IBM Ebony Board
+ AMCC Ebony Board
Last Update: September 12, 2002
=======================================================================
-This file contains some handy info regarding U-Boot and the IBM
+This file contains some handy info regarding U-Boot and the AMCC
Ebony evalutation board. See the README.ppc440 for additional
information.
---------------
The Xilinx ML300 board is based on the Virtex-II Pro FPGA with
-integrated IBM PowerPC 405 core. The board is normally booted from
+integrated AMCC PowerPC 405 core. The board is normally booted from
System ACE CF. U-Boot is then run out of main memory.
An FPGA is a configurable and thus very flexible device. To
include/configs/MPC8540ADS.h
include/configs/MPC8560ADS.h
- CONFIG_BOOKE BOOKE(e.g. Motorola MPC85xx, IBM 440, etc)
+ CONFIG_BOOKE BOOKE(e.g. Motorola MPC85xx, AMCC 440, etc)
CONFIG_E500 BOOKE e500 family(Motorola)
CONFIG_MPC85xx MPC8540,MPC8560 and their derivatives
CONFIG_MPC8540 MPC8540 specific
- IBM Ocotea Board
+ AMCC Ocotea Board
Last Update: March 2, 2004
=======================================================================
-This file contains some handy info regarding U-Boot and the IBM
+This file contains some handy info regarding U-Boot and the AMCC
Ocotea 440gx evalutation board. See the README.ppc440 for additional
information.
This has been done in the 440gx_enet.c file with a #ifdef/endif
pair.
-IBM does not store the EMAC ethernet addresses within their PIBS bootloader.
+AMCC does not store the EMAC ethernet addresses within their PIBS bootloader.
The addresses contained in the config header file are from my particular
board and you _*should*_ change them to reflect your board either in the
config file and/or in your environment variables. I found the addresses on
U-Boot 1.1.3 (Apr 5 2005 - 22:59:57)
-IBM PowerPC 440 GX Rev. C
-Board: IBM 440GX Evaluation Board
+AMCC PowerPC 440 GX Rev. C
+Board: AMCC 440GX Evaluation Board
VCO: 1066 MHz
CPU: 533 MHz
PLB: 152 MHz
405gp code. A sample board support implementation is contained
in the board/ebony directory.
-All testing was performed using the IBM Ebony board using both
+All testing was performed using the AMCC Ebony board using both
Rev B and Rev C silicon. However, since the Rev B. silicon has
extensive errata, support for Rev B. is minimal (it boots, and
features such as i2c, pci, tftpboot, etc. seem to work ok).
i8042.o i82365.o inca-ip_sw.o keyboard.o \
lan91c96.o \
natsemi.o ne2000.o netarm_eth.o netconsole.o \
- ns16550.o ns8382x.o ns87308.o omap1510_i2c.o \
+ ns16550.o ns8382x.o ns87308.o ns7520_eth.o omap1510_i2c.o \
omap24xx_i2c.o pci.o pci_auto.o pci_indirect.o \
pcnet.o plb2800_eth.o \
ps2ser.o ps2mult.o pc_keyb.o \
#endif
/*****************************************************************************/
+/* Defines for the SED13806 driver */
+/*****************************************************************************/
+#ifdef CONFIG_VIDEO_SM501
+
+#ifdef CONFIG_HH405
+#define VIDEO_FB_LITTLE_ENDIAN
+#endif
+#endif
+
+/*****************************************************************************/
/* Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc */
/*****************************************************************************/
#include <video_fb.h>
{ 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff } };
+int gunzip(void *, int, unsigned char *, unsigned long *);
+
/******************************************************************************/
static void video_drawchars (int xx, int yy, unsigned char *s, int count)
static inline void video_drawstring (int xx, int yy, unsigned char *s)
{
- video_drawchars (xx, yy, s, strlen (s));
+ video_drawchars (xx, yy, s, strlen ((char *)s));
}
/*****************************************************************************/
sprintf (info, " %02d:%02d:%02d ", tm.tm_hour, tm.tm_min,
tm.tm_sec);
video_drawstring (VIDEO_VISIBLE_COLS - 10 * VIDEO_FONT_WIDTH,
- VIDEO_INFO_Y, info);
+ VIDEO_INFO_Y, (uchar *)info);
sprintf (info, "%02d.%02d.%04d", tm.tm_mday, tm.tm_mon,
tm.tm_year);
video_drawstring (VIDEO_VISIBLE_COLS - 10 * VIDEO_FONT_WIDTH,
- VIDEO_INFO_Y + 1 * VIDEO_FONT_HEIGHT, info);
+ VIDEO_INFO_Y + 1 * VIDEO_FONT_HEIGHT, (uchar *)info);
}
#endif
unsigned colors;
unsigned long compression;
bmp_color_table_entry_t cte;
+#ifdef CONFIG_VIDEO_BMP_GZIP
+ unsigned char *dst = NULL;
+ ulong len;
+#endif
WATCHDOG_RESET ();
if (!((bmp->header.signature[0] == 'B') &&
(bmp->header.signature[1] == 'M'))) {
+
+#ifdef CONFIG_VIDEO_BMP_GZIP
+ /*
+ * Could be a gzipped bmp image, try to decrompress...
+ */
+ len = CFG_VIDEO_LOGO_MAX_SIZE;
+ dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE);
+ if (dst == NULL) {
+ printf("Error: malloc in gunzip failed!\n");
+ return(1);
+ }
+ if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)bmp_image, &len) != 0) {
+ printf ("Error: no valid bmp or bmp.gz image at %lx\n", bmp_image);
+ free(dst);
+ return 1;
+ }
+ if (len == CFG_VIDEO_LOGO_MAX_SIZE) {
+ printf("Image could be truncated (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n");
+ }
+
+ /*
+ * Set addr to decompressed image
+ */
+ bmp = (bmp_image_t *)dst;
+
+ if (!((bmp->header.signature[0] == 'B') &&
+ (bmp->header.signature[1] == 'M'))) {
+ printf ("Error: no valid bmp.gz image at %lx\n", bmp_image);
+ return 1;
+ }
+#else
printf ("Error: no valid bmp image at %lx\n", bmp_image);
return 1;
+#endif /* CONFIG_VIDEO_BMP_GZIP */
}
width = le32_to_cpu (bmp->header.width);
le16_to_cpu (bmp->header.bit_count));
break;
}
+
+#ifdef CONFIG_VIDEO_BMP_GZIP
+ if (dst) {
+ free(dst);
+ }
+#endif
+
return (0);
}
#endif /* (CONFIG_COMMANDS & CFG_CMD_BMP) || CONFIG_SPLASH_SCREEN */
}
#endif /* CONFIG_SPLASH_SCREEN */
-
logo_plot (video_fb_address, VIDEO_COLS, 0, 0);
sprintf (info, " %s", &version_string);
- video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y, info);
+ video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y, (uchar *)info);
#ifdef CONFIG_CONSOLE_EXTRA_INFO
{
if (*info)
video_drawstring (VIDEO_INFO_X,
VIDEO_INFO_Y + i * VIDEO_FONT_HEIGHT,
- info);
+ (uchar *)info);
}
}
#endif
#include <common.h>
#include <asm/processor.h>
#include <asm/byteorder.h>
-#include <linux/byteorder/swab.h>
#include <environment.h>
#ifdef CFG_FLASH_CFI_DRIVER
#define NUM_ERASE_REGIONS 4
+/* use CFG_MAX_FLASH_BANKS_DETECT if defined */
+#ifdef CFG_MAX_FLASH_BANKS_DETECT
+static ulong bank_base[CFG_MAX_FLASH_BANKS_DETECT] = CFG_FLASH_BANKS_LIST;
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS_DETECT]; /* FLASH chips info */
+#else
static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* FLASH chips info */
+#endif
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
static int flash_detect_cfi (flash_info_t * info);
-static ulong flash_get_size (ulong base, int banknum);
+ulong flash_get_size (ulong base, int banknum);
static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword);
static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
ulong tout, char *prompt);
+#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
static flash_info_t *flash_get_info(ulong base);
+#endif
#ifdef CFG_FLASH_USE_BUFFER_WRITE
static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int len);
#endif
cfiptr_t cptr;
int x, y;
- for (x = 0; x < 0x40; x += 16 / info->portwidth) {
+ for (x = 0; x < 0x40; x += 16U / info->portwidth) {
cptr.cp =
flash_make_addr (info, sect,
x + FLASH_OFFSET_CFI_RESP);
flash_info[i].flash_id = FLASH_UNKNOWN;
size += flash_info[i].size = flash_get_size (bank_base[i], i);
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+#ifndef CFG_FLASH_QUIET_TEST
printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
i, flash_info[i].size, flash_info[i].size << 20);
+#endif /* CFG_FLASH_QUIET_TEST */
}
}
/*-----------------------------------------------------------------------
*/
+#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
static flash_info_t *flash_get_info(ulong base)
{
int i;
- flash_info_t * info;
+ flash_info_t * info = 0;
for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
info = & flash_info[i];
return i == CFG_MAX_FLASH_BANKS ? 0 : info;
}
+#endif
/*-----------------------------------------------------------------------
*/
info->start[i],
erased ? " E" : " ",
info->protect[i] ? "RO " : " ");
-#else
+#else /* ! CFG_FLASH_EMPTY_INFO */
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
- info->start[i], info->protect[i] ? " (RO) " : " ");
+ info->start[i], info->protect[i] ? " (RO)" : " ");
#endif
}
putc ('\n');
src = flash_make_addr (info, 0, FLASH_OFFSET_USER_PROTECTION);
flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
memcpy (dst, src + offset, len);
- flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
+ flash_write_cmd (info, 0, 0, info->cmd_reset);
}
/*
src = flash_make_addr (info, 0, FLASH_OFFSET_INTEL_PROTECTION);
flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
memcpy (buffer, src + offset, len);
- flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
+ flash_write_cmd (info, 0, 0, info->cmd_reset);
}
#endif /* CFG_FLASH_PROTECTION */
if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS))
puts ("Vpp Low Error.\n");
}
- flash_write_cmd (info, sector, 0, FLASH_CMD_RESET);
+ flash_write_cmd (info, sector, 0, info->cmd_reset);
break;
default:
break;
static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf)
{
int i;
-
-#if defined(__LITTLE_ENDIAN)
- ushort stmpw;
- uint stmpi;
-#endif
uchar *cp = (uchar *) cmdbuf;
- for (i = 0; i < info->portwidth; i++)
- *cp++ = ((i + 1) & (info->chipwidth - 1)) ? '\0' : cmd;
#if defined(__LITTLE_ENDIAN)
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- break;
- case FLASH_CFI_16BIT:
- stmpw = *(ushort *) cmdbuf;
- *(ushort *) cmdbuf = __swab16 (stmpw);
- break;
- case FLASH_CFI_32BIT:
- stmpi = *(uint *) cmdbuf;
- *(uint *) cmdbuf = __swab32 (stmpi);
- break;
- default:
- puts ("WARNING: flash_make_cmd: unsuppported LittleEndian mode\n");
- break;
- }
+ for (i = info->portwidth; i > 0; i--)
+#else
+ for (i = 1; i <= info->portwidth; i++)
#endif
+ *cp++ = (i & (info->chipwidth - 1)) ? '\0' : cmd;
}
/*
for (info->chipwidth = FLASH_CFI_BY8;
info->chipwidth <= info->portwidth;
info->chipwidth <<= 1) {
- flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
+ flash_write_cmd (info, 0, 0, info->cmd_reset);
flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
&& flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R')
* The following code cannot be run from FLASH!
*
*/
-static ulong flash_get_size (ulong base, int banknum)
+ulong flash_get_size (ulong base, int banknum)
{
flash_info_t *info = &flash_info[banknum];
int i, j;
}
}
- flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
+ flash_write_cmd (info, 0, 0, info->cmd_reset);
return (info->size);
}
static const struct ctfb_chips_properties chips[] = {
{PCI_DEVICE_ID_CT_69000, 0x200000, 1, 4, -2, 3, 257, 100, 220},
+#ifdef CONFIG_USE_CPCIDVI
+ {PCI_DEVICE_ID_CT_69030, 0x400000, 1, 4, -2, 3, 257, 100, 220},
+#endif
{PCI_DEVICE_ID_CT_65555, 0x100000, 16, 4, 0, 1, 255, 48, 220}, /* NOT TESTED */
{0, 0, 0, 0, 0, 0, 0, 0, 0} /* Terminator */
};
*/
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69000},
+#ifdef CONFIG_USE_CPCIDVI
+ {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030},
+#endif
{}
};
pGD->cprBase = pci_mem_base; /* Dummy */
/* set up Hardware */
+#ifdef CONFIG_USE_CPCIDVI
+ if (device_id == PCI_DEVICE_ID_CT_69030) {
+ ctWrite (CT_MSR_W_O, 0x0b);
+ ctWrite (0x3cd, 0x13);
+ ctWrite_i (CT_FP_O, 0x02, 0x00);
+ ctWrite_i (CT_FP_O, 0x05, 0x00);
+ ctWrite_i (CT_FP_O, 0x06, 0x00);
+ ctWrite (0x3c2, 0x0b);
+ ctWrite_i (CT_FP_O, 0x02, 0x10);
+ ctWrite_i (CT_FP_O, 0x01, 0x09);
+ } else {
+ ctWrite (CT_MSR_W_O, 0x01);
+ }
+#else
ctWrite (CT_MSR_W_O, 0x01);
+#endif
/* set the extended Registers */
ctLoadRegs (CT_XR_O, xreg);
{
int idx=0;
int card_number = 0;
- int cfrv;
+ unsigned int cfrv;
unsigned char timer;
pci_dev_t devbusfn;
unsigned int iobase;
#ifndef CONFIG_TULIP_FIX_DAVICOM
static void read_hw_addr(struct eth_device *dev, bd_t *bis)
{
- u_short tmp, *p = (short *)(&dev->enetaddr[0]);
+ u_short tmp, *p = (u_short *)(&dev->enetaddr[0]);
int i, j = 0;
for (i = 0; i < (ETH_ALEN >> 1); i++) {
readl((a)->hw_addr + E1000_##reg + ((offset) << 2)))
#define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);}
+#ifndef CONFIG_AP1000 /* remove for warnings */
/******************************************************************************
* Raises the EEPROM's clock input.
*
return -E1000_ERR_EEPROM;
}
}
+#endif /* #ifndef CONFIG_AP1000 */
/******************************************************************************
* Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
static int
e1000_read_mac_addr(struct eth_device *nic)
{
+#ifndef CONFIG_AP1000
struct e1000_hw *hw = nic->priv;
uint16_t offset;
uint16_t eeprom_data;
/* Invert the last bit if this is the second device */
nic->enetaddr[5] += 1;
}
+#else
+ /*
+ * The AP1000's e1000 has no eeprom; the MAC address is stored in the
+ * environment variables. Currently this does not support the addition
+ * of a PMC e1000 card, which is certainly a possibility, so this should
+ * be updated to properly use the env variable only for the onboard e1000
+ */
+
+ int ii;
+ char *s, *e;
+
+ DEBUGFUNC();
+
+ s = getenv ("ethaddr");
+ if (s == NULL){
+ return -E1000_ERR_EEPROM;
+ }
+ else{
+ for(ii = 0; ii < 6; ii++) {
+ nic->enetaddr[ii] = s ? simple_strtoul (s, &e, 16) : 0;
+ if (s){
+ s = (*e) ? e + 1 : e;
+ }
+ }
+ }
+#endif
return 0;
}
DEBUGFUNC();
+#ifndef CONFIG_AP1000
/* Read and store word 0x0F of the EEPROM. This word contains bits
* that determine the hardware's default PAUSE (flow control) mode,
* a bit that determines whether the HW defaults to enabling or
DEBUGOUT("EEPROM Read Error\n");
return -E1000_ERR_EEPROM;
}
+#else
+ /* we have to hardcode the proper value for our hardware. */
+ /* this value is for the 82540EM pci card used for prototyping, and it works. */
+ eeprom_data = 0xb220;
+#endif
if (hw->fc == e1000_fc_default) {
if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD)
return 0;
/*DEBUGOUT("recv: packet len=%d \n", rd->length); */
- NetReceive(packet, le32_to_cpu(rd->length));
+ NetReceive((uchar *)packet, le32_to_cpu(rd->length));
fill_rx(hw);
return 1;
}
free(nic);
return 0;
}
+#ifndef CONFIG_AP1000
if (e1000_validate_eeprom_checksum(nic) < 0) {
printf("The EEPROM Checksum Is Not Valid\n");
free(hw);
free(nic);
return 0;
}
+#endif
e1000_read_mac_addr(nic);
E1000_WRITE_REG(hw, PBA, E1000_DEFAULT_PBA);
#include <net.h>
#include <asm/io.h>
#include <pci.h>
+#include <miiphy.h>
#undef DEBUG
/* Ethernet chip registers.
*/
-#define SCBStatus 0 /* Rx/Command Unit Status *Word* */
-#define SCBIntAckByte 1 /* Rx/Command Unit STAT/ACK byte */
-#define SCBCmd 2 /* Rx/Command Unit Command *Word* */
-#define SCBIntrCtlByte 3 /* Rx/Command Unit Intr.Control Byte */
-#define SCBPointer 4 /* General purpose pointer. */
-#define SCBPort 8 /* Misc. commands and operands. */
-#define SCBflash 12 /* Flash memory control. */
-#define SCBeeprom 14 /* EEPROM memory control. */
-#define SCBCtrlMDI 16 /* MDI interface control. */
-#define SCBEarlyRx 20 /* Early receive byte count. */
-#define SCBGenControl 28 /* 82559 General Control Register */
-#define SCBGenStatus 29 /* 82559 General Status register */
+#define SCBStatus 0 /* Rx/Command Unit Status *Word* */
+#define SCBIntAckByte 1 /* Rx/Command Unit STAT/ACK byte */
+#define SCBCmd 2 /* Rx/Command Unit Command *Word* */
+#define SCBIntrCtlByte 3 /* Rx/Command Unit Intr.Control Byte */
+#define SCBPointer 4 /* General purpose pointer. */
+#define SCBPort 8 /* Misc. commands and operands. */
+#define SCBflash 12 /* Flash memory control. */
+#define SCBeeprom 14 /* EEPROM memory control. */
+#define SCBCtrlMDI 16 /* MDI interface control. */
+#define SCBEarlyRx 20 /* Early receive byte count. */
+#define SCBGenControl 28 /* 82559 General Control Register */
+#define SCBGenStatus 29 /* 82559 General Status register */
/* 82559 SCB status word defnitions
*/
-#define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */
-#define SCB_STATUS_FR 0x4000 /* frame received */
-#define SCB_STATUS_CNA 0x2000 /* CU left active state */
-#define SCB_STATUS_RNR 0x1000 /* receiver left ready state */
-#define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */
-#define SCB_STATUS_SWI 0x0400 /* software generated interrupt */
-#define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */
+#define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */
+#define SCB_STATUS_FR 0x4000 /* frame received */
+#define SCB_STATUS_CNA 0x2000 /* CU left active state */
+#define SCB_STATUS_RNR 0x1000 /* receiver left ready state */
+#define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */
+#define SCB_STATUS_SWI 0x0400 /* software generated interrupt */
+#define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */
-#define SCB_INTACK_MASK 0xFD00 /* all the above */
+#define SCB_INTACK_MASK 0xFD00 /* all the above */
-#define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA)
-#define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR)
+#define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA)
+#define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR)
/* System control block commands
*/
/* CU Commands */
-#define CU_NOP 0x0000
-#define CU_START 0x0010
-#define CU_RESUME 0x0020
-#define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */
-#define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */
-#define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */
-#define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */
+#define CU_NOP 0x0000
+#define CU_START 0x0010
+#define CU_RESUME 0x0020
+#define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */
+#define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */
+#define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */
+#define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */
/* RUC Commands */
-#define RUC_NOP 0x0000
-#define RUC_START 0x0001
-#define RUC_RESUME 0x0002
-#define RUC_ABORT 0x0004
-#define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */
-#define RUC_RESUMENR 0x0007
-
-#define CU_CMD_MASK 0x00f0
-#define RU_CMD_MASK 0x0007
-
-#define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */
-#define SCB_SWI 0x0200 /* 1 - cause device to interrupt */
-
-#define CU_STATUS_MASK 0x00C0
-#define RU_STATUS_MASK 0x003C
-
-#define RU_STATUS_IDLE (0<<2)
-#define RU_STATUS_SUS (1<<2)
-#define RU_STATUS_NORES (2<<2)
-#define RU_STATUS_READY (4<<2)
-#define RU_STATUS_NO_RBDS_SUS ((1<<2)|(8<<2))
+#define RUC_NOP 0x0000
+#define RUC_START 0x0001
+#define RUC_RESUME 0x0002
+#define RUC_ABORT 0x0004
+#define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */
+#define RUC_RESUMENR 0x0007
+
+#define CU_CMD_MASK 0x00f0
+#define RU_CMD_MASK 0x0007
+
+#define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */
+#define SCB_SWI 0x0200 /* 1 - cause device to interrupt */
+
+#define CU_STATUS_MASK 0x00C0
+#define RU_STATUS_MASK 0x003C
+
+#define RU_STATUS_IDLE (0<<2)
+#define RU_STATUS_SUS (1<<2)
+#define RU_STATUS_NORES (2<<2)
+#define RU_STATUS_READY (4<<2)
+#define RU_STATUS_NO_RBDS_SUS ((1<<2)|(8<<2))
#define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2))
#define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2))
};
#define RFD_STATUS_C 0x8000 /* completion of received frame */
-#define RFD_STATUS_OK 0x2000 /* frame received with no errors */
-
-#define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */
-#define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */
-#define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */
-#define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */
-
-#define RFD_COUNT_MASK 0x3fff
-#define RFD_COUNT_F 0x4000
-#define RFD_COUNT_EOF 0x8000
-
-#define RFD_RX_CRC 0x0800 /* crc error */
-#define RFD_RX_ALIGNMENT 0x0400 /* alignment error */
-#define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */
-#define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */
-#define RFD_RX_SHORT 0x0080 /* short frame error */
-#define RFD_RX_LENGTH 0x0020
-#define RFD_RX_ERROR 0x0010 /* receive error */
-#define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */
-#define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */
-#define RFD_RX_TCO 0x0001 /* TCO indication */
+#define RFD_STATUS_OK 0x2000 /* frame received with no errors */
+
+#define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */
+#define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */
+#define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */
+#define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */
+
+#define RFD_COUNT_MASK 0x3fff
+#define RFD_COUNT_F 0x4000
+#define RFD_COUNT_EOF 0x8000
+
+#define RFD_RX_CRC 0x0800 /* crc error */
+#define RFD_RX_ALIGNMENT 0x0400 /* alignment error */
+#define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */
+#define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */
+#define RFD_RX_SHORT 0x0080 /* short frame error */
+#define RFD_RX_LENGTH 0x0020
+#define RFD_RX_ERROR 0x0010 /* receive error */
+#define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */
+#define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */
+#define RFD_RX_TCO 0x0001 /* TCO indication */
/* Transmit frame descriptors
*/
};
#define TxCB_CMD_TRANSMIT 0x0004 /* transmit command */
-#define TxCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */
-#define TxCB_CMD_NC 0x0010 /* 0=CRC insert by controller */
-#define TxCB_CMD_I 0x2000 /* generate interrupt on completion */
-#define TxCB_CMD_S 0x4000 /* suspend on completion */
-#define TxCB_CMD_EL 0x8000 /* last command block in CBL */
+#define TxCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */
+#define TxCB_CMD_NC 0x0010 /* 0=CRC insert by controller */
+#define TxCB_CMD_I 0x2000 /* generate interrupt on completion */
+#define TxCB_CMD_S 0x4000 /* suspend on completion */
+#define TxCB_CMD_EL 0x8000 /* last command block in CBL */
-#define TxCB_COUNT_MASK 0x3fff
-#define TxCB_COUNT_EOF 0x8000
+#define TxCB_COUNT_MASK 0x3fff
+#define TxCB_COUNT_EOF 0x8000
/* The Speedo3 Rx and Tx frame/buffer descriptors.
*/
struct descriptor { /* A generic descriptor. */
volatile u16 status;
volatile u16 command;
- volatile u32 link; /* struct descriptor * */
+ volatile u32 link; /* struct descriptor * */
unsigned char params[0];
};
-#define CFG_CMD_EL 0x8000
-#define CFG_CMD_SUSPEND 0x4000
-#define CFG_CMD_INT 0x2000
-#define CFG_CMD_IAS 0x0001 /* individual address setup */
-#define CFG_CMD_CONFIGURE 0x0002 /* configure */
+#define CFG_CMD_EL 0x8000
+#define CFG_CMD_SUSPEND 0x4000
+#define CFG_CMD_INT 0x2000
+#define CFG_CMD_IAS 0x0001 /* individual address setup */
+#define CFG_CMD_CONFIGURE 0x0002 /* configure */
-#define CFG_STATUS_C 0x8000
-#define CFG_STATUS_OK 0x2000
+#define CFG_STATUS_C 0x8000
+#define CFG_STATUS_OK 0x2000
/* Misc.
*/
-#define NUM_RX_DESC PKTBUFSRX
-#define NUM_TX_DESC 1 /* Number of TX descriptors */
+#define NUM_RX_DESC PKTBUFSRX
+#define NUM_TX_DESC 1 /* Number of TX descriptors */
#define TOUT_LOOP 1000000
#define ETH_ALEN 6
-static struct RxFD rx_ring[NUM_RX_DESC]; /* RX descriptor ring */
-static struct TxFD tx_ring[NUM_TX_DESC]; /* TX descriptor ring */
+static struct RxFD rx_ring[NUM_RX_DESC]; /* RX descriptor ring */
+static struct TxFD tx_ring[NUM_TX_DESC]; /* TX descriptor ring */
static int rx_next; /* RX descriptor ring pointer */
static int tx_next; /* TX descriptor ring pointer */
static int tx_threshold;
*(volatile u32 *) ((addr + dev->iobase)) = cpu_to_le32 (command);
}
- /* Wait for the chip get the command.
- */
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+static inline int INL (struct eth_device *dev, u_long addr)
+{
+ return le32_to_cpu (*(volatile u32 *) (addr + dev->iobase));
+}
+
+static int get_phyreg (struct eth_device *dev, unsigned char addr,
+ unsigned char reg, unsigned short *value)
+{
+ int cmd;
+ int timeout = 50;
+
+ /* read requested data */
+ cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
+ OUTL (dev, cmd, SCBCtrlMDI);
+
+ do {
+ udelay(1000);
+ cmd = INL (dev, SCBCtrlMDI);
+ } while (!(cmd & (1 << 28)) && (--timeout));
+
+ if (timeout == 0)
+ return -1;
+
+ *value = (unsigned short) (cmd & 0xffff);
+
+ return 0;
+}
+
+static int set_phyreg (struct eth_device *dev, unsigned char addr,
+ unsigned char reg, unsigned short value)
+{
+ int cmd;
+ int timeout = 50;
+
+ /* write requested data */
+ cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
+ OUTL (dev, cmd | value, SCBCtrlMDI);
+
+ while (!(INL (dev, SCBCtrlMDI) & (1 << 28)) && (--timeout))
+ udelay(1000);
+
+ if (timeout == 0)
+ return -1;
+
+ return 0;
+}
+
+/* Check if given phyaddr is valid, i.e. there is a PHY connected.
+ * Do this by checking model value field from ID2 register.
+ */
+static struct eth_device* verify_phyaddr (char *devname, unsigned char addr)
+{
+ struct eth_device *dev;
+ unsigned short value;
+ unsigned char model;
+
+ dev = eth_get_dev_by_name(devname);
+ if (dev == NULL) {
+ printf("%s: no such device\n", devname);
+ return NULL;
+ }
+
+ /* read id2 register */
+ if (get_phyreg(dev, addr, PHY_PHYIDR2, &value) != 0) {
+ printf("%s: mii read timeout!\n", devname);
+ return NULL;
+ }
+
+ /* get model */
+ model = (unsigned char)((value >> 4) & 0x003f);
+
+ if (model == 0) {
+ printf("%s: no PHY at address %d\n", devname, addr);
+ return NULL;
+ }
+
+ return dev;
+}
+
+static int eepro100_miiphy_read (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value)
+{
+ struct eth_device *dev;
+
+ dev = verify_phyaddr(devname, addr);
+ if (dev == NULL)
+ return -1;
+
+ if (get_phyreg(dev, addr, reg, value) != 0) {
+ printf("%s: mii read timeout!\n", devname);
+ return -1;
+ }
+
+ return 0;
+}
+
+static int eepro100_miiphy_write (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value)
+{
+ struct eth_device *dev;
+
+ dev = verify_phyaddr(devname, addr);
+ if (dev == NULL)
+ return -1;
+
+ if (set_phyreg(dev, addr, reg, value) != 0) {
+ printf("%s: mii write timeout!\n", devname);
+ return -1;
+ }
+
+ return 0;
+}
+
+#endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) */
+
+/* Wait for the chip get the command.
+*/
static int wait_for_eepro100 (struct eth_device *dev)
{
int i;
eth_register (dev);
+#if defined (CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+ /* register mii command access routines */
+ miiphy_register(dev->name,
+ eepro100_miiphy_read, eepro100_miiphy_write);
+#endif
+
card_number++;
/* Set the latency timer for value.
OUTW(dev, EE_ENB | dataval, SCBeeprom);
udelay(1);
- datalong = datalong << 1; /* Adjust significant data bit*/
+ datalong = datalong << 1; /* Adjust significant data bit*/
}
/* Finish up command (toggle CS) */
OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
- udelay(1); /* delay for more than 250 ns */
+ udelay(1); /* delay for more than 250 ns */
OUTW(dev, EE_ENB, SCBeeprom);
/* Wait for programming ready (D0 = 1) */
#ifdef CONFIG_I8042_KBD
+#ifdef CONFIG_USE_CPCIDVI
+extern u8 gt_cpcidvi_in8(u32 offset);
+extern void gt_cpcidvi_out8(u32 offset, u8 data);
+
+#define in8(a) gt_cpcidvi_in8(a)
+#define out8(a, b) gt_cpcidvi_out8(a,b)
+#endif
+
#include <i8042.h>
/* defines */
int keymap, try;
char *penv;
+#ifdef CONFIG_USE_CPCIDVI
+ if ((penv = getenv ("console")) != NULL) {
+ if (strncmp (penv, "serial", 7) == 0) {
+ return -1;
+ }
+ }
+#endif
/* Init keyboard device (default US layout) */
keymap = KBD_US;
if ((penv = getenv ("keymap")) != NULL)
if (kbd_input_empty() == 0)
return -1;
+#ifdef CONFIG_USE_CPCIDVI
+ out8 (I8042_COMMAND_REG, 0x60);
+#else
out8 (I8042_DATA_REG, 0x60);
+#endif
if (kbd_input_empty() == 0)
return -1;
#ifdef CONFIG_PXA250
-#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+( r * 4 ))))
-#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+( r * 4 ))))
-#define SMC_inb(p) ({ \
- unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p * 4)); \
- unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \
+#ifdef CONFIG_LUBBOCK
+#define SMC_IO_SHIFT 2
+#undef USE_32_BIT
+
+#else
+#define SMC_IO_SHIFT 0
+#endif
+
+#define SMCREG(r) (SMC_BASE_ADDRESS+((r)<<SMC_IO_SHIFT))
+
+#define SMC_inl(r) (*((volatile dword *)SMCREG(r)))
+#define SMC_inw(r) (*((volatile word *)SMCREG(r)))
+#define SMC_inb(p) ({ \
+ unsigned int __p = p; \
+ unsigned int __v = SMC_inw(__p & ~1); \
if (__p & 1) __v >>= 8; \
else __v &= 0xff; \
__v; })
-#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r * 4))) = d)
-#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r * 4))) = d)
+#define SMC_outl(d,r) (*((volatile dword *)SMCREG(r)) = d)
+#define SMC_outw(d,r) (*((volatile word *)SMCREG(r)) = d)
#define SMC_outb(d,r) ({ word __d = (byte)(d); \
word __w = SMC_inw((r)&~1); \
__w &= ((r)&1) ? 0x00FF : 0xFF00; \
* $Id: diskonchip.c,v 1.45 2005/01/05 18:05:14 dwmw2 Exp $
*/
+#include <common.h>
+#ifdef CONFIG_NEW_NAND_CODE
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/sched.h>
MODULE_LICENSE("GPL");
MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
MODULE_DESCRIPTION("M-Systems DiskOnChip 2000, Millennium and Millennium Plus device driver\n");
+#endif /* CONFIG_NEW_NAND_CODE */
#include <common.h>
+#ifdef CONFIG_NEW_NAND_CODE
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <nand.h>
{
mtd->priv = nand;
- nand->IO_ADDR_R = nand->IO_ADDR_W = base_addr;
+ nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;
board_nand_init(nand);
if (nand_scan(mtd, 1) == 0) {
if (!mtd->name)
- mtd->name = default_nand_name;
+ mtd->name = (char *)default_nand_name;
} else
mtd->name = NULL;
void nand_init(void)
{
int i;
-
+ unsigned int size = 0;
for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) {
nand_init_chip(&nand_info[i], &nand_chip[i], base_address[i]);
+ size += nand_info[i].size;
if (nand_curr_device == -1)
nand_curr_device = i;
- }
+}
+ printf("%lu MiB\n", size / (1024 * 1024));
}
#endif
+#endif /* CONFIG_NEW_NAND_CODE */
+
#endif
#include <common.h>
+#ifdef CONFIG_NEW_NAND_CODE
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
else
this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
- reset_timer_masked();
+ reset_timer();
while (1) {
- if (get_timer_masked() > timeo)
+ if (get_timer(0) > timeo) {
+ printf("Timeout!");
return 0;
+ }
if (this->dev_ready) {
if (this->dev_ready(mtd))
}
}
+ /* XXX nand device 1 on dave (PPChameleonEVB) needs more time */
+ reset_timer();
+ while (get_timer(0) < 10);
+
return this->read_byte(mtd);
}
#endif
if (nand_manuf_ids[j].id == nand_maf_id)
break;
}
- printk (KERN_INFO "NAND device: Manufacturer ID:"
- " 0x%02x, Chip ID: 0x%02x (%s %s)\n", nand_maf_id, nand_dev_id,
- nand_manuf_ids[j].name , nand_flash_ids[i].name);
break;
}
}
#endif
+#endif /* CONFIG_NEW_NAND_CODE */
+
#include <common.h>
+#ifdef CONFIG_NEW_NAND_CODE
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <malloc.h>
loff_t from;
size_t readlen, ooblen;
- printk (KERN_INFO "Scanning device for bad blocks\n");
-
if (bd->options & NAND_BBT_SCANALLPAGES)
len = 1 << (this->bbt_erase_shift - this->page_shift);
else {
for (j = 0; j < len; j++) {
if (check_pattern (&buf[j * scanlen], scanlen, mtd->oobblock, bd)) {
this->bbt[i >> 3] |= 0x03 << (i & 0x6);
- printk (KERN_WARNING "Bad eraseblock %d at 0x%08x\n",
- i >> 1, (unsigned int) from);
break;
}
}
}
#endif
+#endif /* CONFIG_NEW_NAND_CODE */
+
#include <common.h>
+#ifdef CONFIG_NEW_NAND_CODE
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#include<linux/mtd/mtd.h>
/*
* Pre-calculated 256-way 1 byte column parity
*/
}
#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */
+#endif /* CONFIG_NEW_NAND_CODE */
+
* published by the Free Software Foundation.
*
*/
+
#include <common.h>
+#ifdef CONFIG_NEW_NAND_CODE
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
{0x0, "Unknown"}
};
#endif
+#endif /* CONFIG_NEW_NAND_CODE */
+
{
u32 i, status = 0;
u32 tx_status = 0;
+ vu_long *res = (vu_long *)&tx_status;
/* Stop the transmitter */
OUTL(dev, TxOff, ChipCmd);
OUTL(dev, TxOn, ChipCmd);
for (i = 0;
- ((vu_long)tx_status = le32_to_cpu(txd.cmdsts)) & DescOwn;
+ (*res = le32_to_cpu(txd.cmdsts)) & DescOwn;
i++) {
if (i >= TOUT_LOOP) {
printf
#include <devices.h>
#include <net.h>
-#ifndef CONFIG_NET_MULTI
-#error define CONFIG_NET_MULTI to use netconsole
-#endif
-
static char input_buffer[512];
static int input_size = 0; /* char count in input buffer */
static int input_offset = 0; /* offset to valid chars in input buffer */
--- /dev/null
+/***********************************************************************
+ *
+ * Copyright (C) 2005 by Videon Central, Inc.
+ *
+ * $Id$
+ * @Author: Arthur Shipkowski
+ * @Descr: Ethernet driver for the NS7520. Uses polled Ethernet, like
+ * the older netarmeth driver. Note that attempting to filter
+ * broadcast and multicast out in the SAFR register will cause
+ * bad things due to released errata.
+ * @References: [1] NS7520 Hardware Reference, December 2003
+ * [2] Intel LXT971 Datasheet #249414 Rev. 02
+ *
+ ***********************************************************************/
+
+#include <common.h>
+
+#if defined(CONFIG_DRIVER_NS7520_ETHERNET)
+
+#include <net.h> /* NetSendPacket */
+#include <asm/arch/netarm_registers.h>
+#include <asm/arch/netarm_dma_module.h>
+
+#include "ns7520_eth.h" /* for Ethernet and PHY */
+
+/**
+ * Send an error message to the terminal.
+ */
+#define ERROR(x) \
+do { \
+ char *__foo = strrchr(__FILE__, '/'); \
+ \
+ printf("%s: %d: %s(): ", (__foo == NULL ? __FILE__ : (__foo + 1)), \
+ __LINE__, __FUNCTION__); \
+ printf x; printf("\n"); \
+} while (0);
+
+/* some definition to make transistion to linux easier */
+
+#define NS7520_DRIVER_NAME "eth"
+#define KERN_WARNING "Warning:"
+#define KERN_ERR "Error:"
+#define KERN_INFO "Info:"
+
+#if 1
+# define DEBUG
+#endif
+
+#ifdef DEBUG
+# define printk printf
+
+# define DEBUG_INIT 0x0001
+# define DEBUG_MINOR 0x0002
+# define DEBUG_RX 0x0004
+# define DEBUG_TX 0x0008
+# define DEBUG_INT 0x0010
+# define DEBUG_POLL 0x0020
+# define DEBUG_LINK 0x0040
+# define DEBUG_MII 0x0100
+# define DEBUG_MII_LOW 0x0200
+# define DEBUG_MEM 0x0400
+# define DEBUG_ERROR 0x4000
+# define DEBUG_ERROR_CRIT 0x8000
+
+static int nDebugLvl = DEBUG_ERROR_CRIT;
+
+# define DEBUG_ARGS0( FLG, a0 ) if( ( nDebugLvl & (FLG) ) == (FLG) ) \
+ printf("%s: " a0, __FUNCTION__, 0, 0, 0, 0, 0, 0 )
+# define DEBUG_ARGS1( FLG, a0, a1 ) if( ( nDebugLvl & (FLG) ) == (FLG)) \
+ printf("%s: " a0, __FUNCTION__, (int)(a1), 0, 0, 0, 0, 0 )
+# define DEBUG_ARGS2( FLG, a0, a1, a2 ) if( (nDebugLvl & (FLG)) ==(FLG))\
+ printf("%s: " a0, __FUNCTION__, (int)(a1), (int)(a2), 0, 0,0,0 )
+# define DEBUG_ARGS3( FLG, a0, a1, a2, a3 ) if((nDebugLvl &(FLG))==(FLG))\
+ printf("%s: "a0,__FUNCTION__,(int)(a1),(int)(a2),(int)(a3),0,0,0)
+# define DEBUG_FN( FLG ) if( (nDebugLvl & (FLG)) == (FLG) ) \
+ printf("\r%s:line %d\n", (int)__FUNCTION__, __LINE__, 0,0,0,0);
+# define ASSERT( expr, func ) if( !( expr ) ) { \
+ printf( "Assertion failed! %s:line %d %s\n", \
+ (int)__FUNCTION__,__LINE__,(int)(#expr),0,0,0); \
+ func }
+#else /* DEBUG */
+# define printk(...)
+# define DEBUG_ARGS0( FLG, a0 )
+# define DEBUG_ARGS1( FLG, a0, a1 )
+# define DEBUG_ARGS2( FLG, a0, a1, a2 )
+# define DEBUG_ARGS3( FLG, a0, a1, a2, a3 )
+# define DEBUG_FN( n )
+# define ASSERT(expr, func)
+#endif /* DEBUG */
+
+#define NS7520_MII_NEG_DELAY (5*CFG_HZ) /* in s */
+#define TX_TIMEOUT (5*CFG_HZ) /* in s */
+#define RX_STALL_WORKAROUND_CNT 100
+
+static int ns7520_eth_reset(void);
+
+static void ns7520_link_auto_negotiate(void);
+static void ns7520_link_update_egcr(void);
+static void ns7520_link_print_changed(void);
+
+/* the PHY stuff */
+
+static char ns7520_mii_identify_phy(void);
+static unsigned short ns7520_mii_read(unsigned short uiRegister);
+static void ns7520_mii_write(unsigned short uiRegister,
+ unsigned short uiData);
+static unsigned int ns7520_mii_get_clock_divisor(unsigned int
+ unMaxMDIOClk);
+static unsigned int ns7520_mii_poll_busy(void);
+
+static unsigned int nPhyMaxMdioClock = PHY_MDIO_MAX_CLK;
+static unsigned int uiLastLinkStatus;
+static PhyType phyDetected = PHY_NONE;
+
+/***********************************************************************
+ * @Function: eth_init
+ * @Return: -1 on failure otherwise 0
+ * @Descr: Initializes the ethernet engine and uses either FS Forth's default
+ * MAC addr or the one in environment
+ ***********************************************************************/
+
+int eth_init(bd_t * pbis)
+{
+ unsigned char aucMACAddr[6];
+ char *pcTmp = getenv("ethaddr");
+ char *pcEnd;
+ int i;
+
+ DEBUG_FN(DEBUG_INIT);
+
+ /* no need to check for hardware */
+
+ if (!ns7520_eth_reset())
+ return -1;
+
+ if (NULL == pcTmp)
+ return -1;
+
+ for (i = 0; i < 6; i++) {
+ aucMACAddr[i] =
+ pcTmp ? simple_strtoul(pcTmp, &pcEnd, 16) : 0;
+ pcTmp = (*pcTmp) ? pcEnd + 1 : pcEnd;
+ }
+
+ /* configure ethernet address */
+
+ *get_eth_reg_addr(NS7520_ETH_SA1) =
+ aucMACAddr[5] << 8 | aucMACAddr[4];
+ *get_eth_reg_addr(NS7520_ETH_SA2) =
+ aucMACAddr[3] << 8 | aucMACAddr[2];
+ *get_eth_reg_addr(NS7520_ETH_SA3) =
+ aucMACAddr[1] << 8 | aucMACAddr[0];
+
+ /* enable hardware */
+
+ *get_eth_reg_addr(NS7520_ETH_MAC1) = NS7520_ETH_MAC1_RXEN;
+ *get_eth_reg_addr(NS7520_ETH_SUPP) = NS7520_ETH_SUPP_JABBER;
+ *get_eth_reg_addr(NS7520_ETH_MAC1) = NS7520_ETH_MAC1_RXEN;
+
+ /* the linux kernel may give packets < 60 bytes, for example arp */
+ *get_eth_reg_addr(NS7520_ETH_MAC2) = NS7520_ETH_MAC2_CRCEN |
+ NS7520_ETH_MAC2_PADEN | NS7520_ETH_MAC2_HUGE;
+
+ /* Broadcast/multicast allowed; if you don't set this even unicast chokes */
+ /* Based on NS7520 errata documentation */
+ *get_eth_reg_addr(NS7520_ETH_SAFR) =
+ NS7520_ETH_SAFR_BROAD | NS7520_ETH_SAFR_PRM;
+
+ /* enable receive and transmit FIFO, use 10/100 Mbps MII */
+ *get_eth_reg_addr(NS7520_ETH_EGCR) |=
+ NS7520_ETH_EGCR_ETXWM_75 |
+ NS7520_ETH_EGCR_ERX |
+ NS7520_ETH_EGCR_ERXREG |
+ NS7520_ETH_EGCR_ERXBR | NS7520_ETH_EGCR_ETX;
+
+ return 0;
+}
+
+/***********************************************************************
+ * @Function: eth_send
+ * @Return: -1 on timeout otherwise 1
+ * @Descr: sends one frame by DMA
+ ***********************************************************************/
+
+int eth_send(volatile void *pPacket, int nLen)
+{
+ int i, length32, retval = 1;
+ char *pa;
+ unsigned int *pa32, lastp = 0, rest;
+ unsigned int status;
+
+ pa = (char *) pPacket;
+ pa32 = (unsigned int *) pPacket;
+ length32 = nLen / 4;
+ rest = nLen % 4;
+
+ /* make sure there's no garbage in the last word */
+ switch (rest) {
+ case 0:
+ lastp = pa32[length32 - 1];
+ length32--;
+ break;
+ case 1:
+ lastp = pa32[length32] & 0x000000ff;
+ break;
+ case 2:
+ lastp = pa32[length32] & 0x0000ffff;
+ break;
+ case 3:
+ lastp = pa32[length32] & 0x00ffffff;
+ break;
+ }
+
+ while (((*get_eth_reg_addr(NS7520_ETH_EGSR)) &
+ NS7520_ETH_EGSR_TXREGE)
+ == 0) {
+ }
+
+ /* write to the fifo */
+ for (i = 0; i < length32; i++)
+ *get_eth_reg_addr(NS7520_ETH_FIFO) = pa32[i];
+
+ /* the last word is written to an extra register, this
+ starts the transmission */
+ *get_eth_reg_addr(NS7520_ETH_FIFOL) = lastp;
+
+ /* Wait for it to be done */
+ while ((*get_eth_reg_addr(NS7520_ETH_EGSR) & NS7520_ETH_EGSR_TXBC)
+ == 0) {
+ }
+ status = (*get_eth_reg_addr(NS7520_ETH_ETSR));
+ *get_eth_reg_addr(NS7520_ETH_EGSR) = NS7520_ETH_EGSR_TXBC; /* Clear it now */
+
+ if (status & NS7520_ETH_ETSR_TXOK) {
+ retval = 0; /* We're OK! */
+ } else if (status & NS7520_ETH_ETSR_TXDEF) {
+ printf("Deferred, we'll see.\n");
+ retval = 0;
+ } else if (status & NS7520_ETH_ETSR_TXAL) {
+ printf("Late collision error, %d collisions.\n",
+ (*get_eth_reg_addr(NS7520_ETH_ETSR)) &
+ NS7520_ETH_ETSR_TXCOLC);
+ } else if (status & NS7520_ETH_ETSR_TXAEC) {
+ printf("Excessive collisions: %d\n",
+ (*get_eth_reg_addr(NS7520_ETH_ETSR)) &
+ NS7520_ETH_ETSR_TXCOLC);
+ } else if (status & NS7520_ETH_ETSR_TXAED) {
+ printf("Excessive deferral on xmit.\n");
+ } else if (status & NS7520_ETH_ETSR_TXAUR) {
+ printf("Packet underrun.\n");
+ } else if (status & NS7520_ETH_ETSR_TXAJ) {
+ printf("Jumbo packet error.\n");
+ } else {
+ printf("Error: Should never get here.\n");
+ }
+
+ return (retval);
+}
+
+/***********************************************************************
+ * @Function: eth_rx
+ * @Return: size of last frame in bytes or 0 if no frame available
+ * @Descr: gives one frame to U-Boot which has been copied by DMA engine already
+ * to NetRxPackets[ 0 ].
+ ***********************************************************************/
+
+int eth_rx(void)
+{
+ int i;
+ unsigned short rxlen;
+ unsigned short totrxlen = 0;
+ unsigned int *addr;
+ unsigned int rxstatus, lastrxlen;
+ char *pa;
+
+ /* If RXBR is 1, data block was received */
+ while (((*get_eth_reg_addr(NS7520_ETH_EGSR)) &
+ NS7520_ETH_EGSR_RXBR) == NS7520_ETH_EGSR_RXBR) {
+
+ /* get status register and the length of received block */
+ rxstatus = *get_eth_reg_addr(NS7520_ETH_ERSR);
+ rxlen = (rxstatus & NS7520_ETH_ERSR_RXSIZE) >> 16;
+
+ /* clear RXBR to make fifo available */
+ *get_eth_reg_addr(NS7520_ETH_EGSR) = NS7520_ETH_EGSR_RXBR;
+
+ if (rxstatus & NS7520_ETH_ERSR_ROVER) {
+ printf("Receive overrun, resetting FIFO.\n");
+ *get_eth_reg_addr(NS7520_ETH_EGCR) &=
+ ~NS7520_ETH_EGCR_ERX;
+ udelay(20);
+ *get_eth_reg_addr(NS7520_ETH_EGCR) |=
+ NS7520_ETH_EGCR_ERX;
+ }
+ if (rxlen == 0) {
+ printf("Nothing.\n");
+ return 0;
+ }
+
+ addr = (unsigned int *) NetRxPackets[0];
+ pa = (char *) NetRxPackets[0];
+
+ /* read the fifo */
+ for (i = 0; i < rxlen / 4; i++) {
+ *addr = *get_eth_reg_addr(NS7520_ETH_FIFO);
+ addr++;
+ }
+
+ if ((*get_eth_reg_addr(NS7520_ETH_EGSR)) &
+ NS7520_ETH_EGSR_RXREGR) {
+ /* RXFDB indicates wether the last word is 1,2,3 or 4 bytes long */
+ lastrxlen =
+ ((*get_eth_reg_addr(NS7520_ETH_EGSR)) &
+ NS7520_ETH_EGSR_RXFDB_MA) >> 28;
+ *addr = *get_eth_reg_addr(NS7520_ETH_FIFO);
+ switch (lastrxlen) {
+ case 1:
+ *addr &= 0xff000000;
+ break;
+ case 2:
+ *addr &= 0xffff0000;
+ break;
+ case 3:
+ *addr &= 0xffffff00;
+ break;
+ }
+ }
+
+ /* Pass the packet up to the protocol layers. */
+ NetReceive(NetRxPackets[0], rxlen - 4);
+ totrxlen += rxlen - 4;
+ }
+
+ return totrxlen;
+}
+
+/***********************************************************************
+ * @Function: eth_halt
+ * @Return: n/a
+ * @Descr: stops the ethernet engine
+ ***********************************************************************/
+
+void eth_halt(void)
+{
+ DEBUG_FN(DEBUG_INIT);
+
+ *get_eth_reg_addr(NS7520_ETH_MAC1) &= ~NS7520_ETH_MAC1_RXEN;
+ *get_eth_reg_addr(NS7520_ETH_EGCR) &= ~(NS7520_ETH_EGCR_ERX |
+ NS7520_ETH_EGCR_ERXDMA |
+ NS7520_ETH_EGCR_ERXREG |
+ NS7520_ETH_EGCR_ERXBR |
+ NS7520_ETH_EGCR_ETX |
+ NS7520_ETH_EGCR_ETXDMA);
+}
+
+/***********************************************************************
+ * @Function: ns7520_eth_reset
+ * @Return: 0 on failure otherwise 1
+ * @Descr: resets the ethernet interface and the PHY,
+ * performs auto negotiation or fixed modes
+ ***********************************************************************/
+
+static int ns7520_eth_reset(void)
+{
+ DEBUG_FN(DEBUG_MINOR);
+
+ /* Reset important registers */
+ *get_eth_reg_addr(NS7520_ETH_EGCR) = 0; /* Null it out! */
+ *get_eth_reg_addr(NS7520_ETH_MAC1) &= NS7520_ETH_MAC1_SRST;
+ *get_eth_reg_addr(NS7520_ETH_MAC2) = 0;
+ /* Reset MAC */
+ *get_eth_reg_addr(NS7520_ETH_EGCR) |= NS7520_ETH_EGCR_MAC_RES;
+ udelay(5);
+ *get_eth_reg_addr(NS7520_ETH_EGCR) &= ~NS7520_ETH_EGCR_MAC_RES;
+
+ /* reset and initialize PHY */
+
+ *get_eth_reg_addr(NS7520_ETH_MAC1) &= ~NS7520_ETH_MAC1_SRST;
+
+ /* we don't support hot plugging of PHY, therefore we don't reset
+ phyDetected and nPhyMaxMdioClock here. The risk is if the setting is
+ incorrect the first open
+ may detect the PHY correctly but succeding will fail
+ For reseting the PHY and identifying we have to use the standard
+ MDIO CLOCK value 2.5 MHz only after hardware reset
+ After having identified the PHY we will do faster */
+
+ *get_eth_reg_addr(NS7520_ETH_MCFG) =
+ ns7520_mii_get_clock_divisor(nPhyMaxMdioClock);
+
+ /* reset PHY */
+ ns7520_mii_write(PHY_COMMON_CTRL, PHY_COMMON_CTRL_RESET);
+ ns7520_mii_write(PHY_COMMON_CTRL, 0);
+
+ udelay(3000); /* [2] p.70 says at least 300us reset recovery time. */
+
+ /* MII clock has been setup to default, ns7520_mii_identify_phy should
+ work for all */
+
+ if (!ns7520_mii_identify_phy()) {
+ printk(KERN_ERR NS7520_DRIVER_NAME
+ ": Unsupported PHY, aborting\n");
+ return 0;
+ }
+
+ /* now take the highest MDIO clock possible after detection */
+ *get_eth_reg_addr(NS7520_ETH_MCFG) =
+ ns7520_mii_get_clock_divisor(nPhyMaxMdioClock);
+
+ /* PHY has been detected, so there can be no abort reason and we can
+ finish initializing ethernet */
+
+ uiLastLinkStatus = 0xff; /* undefined */
+
+ ns7520_link_auto_negotiate();
+
+ if (phyDetected == PHY_LXT971A)
+ /* set LED2 to link mode */
+ ns7520_mii_write(PHY_LXT971_LED_CFG,
+ (PHY_LXT971_LED_CFG_LINK_ACT <<
+ PHY_LXT971_LED_CFG_SHIFT_LED2) |
+ (PHY_LXT971_LED_CFG_TRANSMIT <<
+ PHY_LXT971_LED_CFG_SHIFT_LED1));
+
+ return 1;
+}
+
+/***********************************************************************
+ * @Function: ns7520_link_auto_negotiate
+ * @Return: void
+ * @Descr: performs auto-negotation of link.
+ ***********************************************************************/
+
+static void ns7520_link_auto_negotiate(void)
+{
+ unsigned long ulStartJiffies;
+ unsigned short uiStatus;
+
+ DEBUG_FN(DEBUG_LINK);
+
+ /* run auto-negotation */
+ /* define what we are capable of */
+ ns7520_mii_write(PHY_COMMON_AUTO_ADV,
+ PHY_COMMON_AUTO_ADV_100BTXFD |
+ PHY_COMMON_AUTO_ADV_100BTX |
+ PHY_COMMON_AUTO_ADV_10BTFD |
+ PHY_COMMON_AUTO_ADV_10BT |
+ PHY_COMMON_AUTO_ADV_802_3);
+ /* start auto-negotiation */
+ ns7520_mii_write(PHY_COMMON_CTRL,
+ PHY_COMMON_CTRL_AUTO_NEG |
+ PHY_COMMON_CTRL_RES_AUTO);
+
+ /* wait for completion */
+
+ ulStartJiffies = get_timer(0);
+ while (get_timer(0) < ulStartJiffies + NS7520_MII_NEG_DELAY) {
+ uiStatus = ns7520_mii_read(PHY_COMMON_STAT);
+ if ((uiStatus &
+ (PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT))
+ ==
+ (PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT)) {
+ /* lucky we are, auto-negotiation succeeded */
+ ns7520_link_print_changed();
+ ns7520_link_update_egcr();
+ return;
+ }
+ }
+
+ DEBUG_ARGS0(DEBUG_LINK, "auto-negotiation timed out\n");
+ /* ignore invalid link settings */
+}
+
+/***********************************************************************
+ * @Function: ns7520_link_update_egcr
+ * @Return: void
+ * @Descr: updates the EGCR and MAC2 link status after mode change or
+ * auto-negotation
+ ***********************************************************************/
+
+static void ns7520_link_update_egcr(void)
+{
+ unsigned int unEGCR;
+ unsigned int unMAC2;
+ unsigned int unIPGT;
+
+ DEBUG_FN(DEBUG_LINK);
+
+ unEGCR = *get_eth_reg_addr(NS7520_ETH_EGCR);
+ unMAC2 = *get_eth_reg_addr(NS7520_ETH_MAC2);
+ unIPGT =
+ *get_eth_reg_addr(NS7520_ETH_IPGT) & ~NS7520_ETH_IPGT_IPGT;
+
+ unEGCR &= ~NS7520_ETH_EGCR_EFULLD;
+ unMAC2 &= ~NS7520_ETH_MAC2_FULLD;
+ if ((uiLastLinkStatus & PHY_LXT971_STAT2_DUPLEX_MODE)
+ == PHY_LXT971_STAT2_DUPLEX_MODE) {
+ unEGCR |= NS7520_ETH_EGCR_EFULLD;
+ unMAC2 |= NS7520_ETH_MAC2_FULLD;
+ unIPGT |= 0x15; /* see [1] p. 167 */
+ } else
+ unIPGT |= 0x12; /* see [1] p. 167 */
+
+ *get_eth_reg_addr(NS7520_ETH_MAC2) = unMAC2;
+ *get_eth_reg_addr(NS7520_ETH_EGCR) = unEGCR;
+ *get_eth_reg_addr(NS7520_ETH_IPGT) = unIPGT;
+}
+
+/***********************************************************************
+ * @Function: ns7520_link_print_changed
+ * @Return: void
+ * @Descr: checks whether the link status has changed and if so prints
+ * the new mode
+ ***********************************************************************/
+
+static void ns7520_link_print_changed(void)
+{
+ unsigned short uiStatus;
+ unsigned short uiControl;
+
+ DEBUG_FN(DEBUG_LINK);
+
+ uiControl = ns7520_mii_read(PHY_COMMON_CTRL);
+
+ if ((uiControl & PHY_COMMON_CTRL_AUTO_NEG) ==
+ PHY_COMMON_CTRL_AUTO_NEG) {
+ /* PHY_COMMON_STAT_LNK_STAT is only set on autonegotiation */
+ uiStatus = ns7520_mii_read(PHY_COMMON_STAT);
+
+ if (!(uiStatus & PHY_COMMON_STAT_LNK_STAT)) {
+ printk(KERN_WARNING NS7520_DRIVER_NAME
+ ": link down\n");
+ /* @TODO Linux: carrier_off */
+ } else {
+ /* @TODO Linux: carrier_on */
+ if (phyDetected == PHY_LXT971A) {
+ uiStatus =
+ ns7520_mii_read(PHY_LXT971_STAT2);
+ uiStatus &=
+ (PHY_LXT971_STAT2_100BTX |
+ PHY_LXT971_STAT2_DUPLEX_MODE |
+ PHY_LXT971_STAT2_AUTO_NEG);
+
+ /* mask out all uninteresting parts */
+ }
+ /* other PHYs must store there link information in
+ uiStatus as PHY_LXT971 */
+ }
+ } else {
+ /* mode has been forced, so uiStatus should be the same as the
+ last link status, enforce printing */
+ uiStatus = uiLastLinkStatus;
+ uiLastLinkStatus = 0xff;
+ }
+
+ if (uiStatus != uiLastLinkStatus) {
+ /* save current link status */
+ uiLastLinkStatus = uiStatus;
+
+ /* print new link status */
+
+ printk(KERN_INFO NS7520_DRIVER_NAME
+ ": link mode %i Mbps %s duplex %s\n",
+ (uiStatus & PHY_LXT971_STAT2_100BTX) ? 100 : 10,
+ (uiStatus & PHY_LXT971_STAT2_DUPLEX_MODE) ? "full" :
+ "half",
+ (uiStatus & PHY_LXT971_STAT2_AUTO_NEG) ? "(auto)" :
+ "");
+ }
+}
+
+/***********************************************************************
+ * the MII low level stuff
+ ***********************************************************************/
+
+/***********************************************************************
+ * @Function: ns7520_mii_identify_phy
+ * @Return: 1 if supported PHY has been detected otherwise 0
+ * @Descr: checks for supported PHY and prints the IDs.
+ ***********************************************************************/
+
+static char ns7520_mii_identify_phy(void)
+{
+ unsigned short uiID1;
+ unsigned short uiID2;
+ unsigned char *szName;
+ char cRes = 0;
+
+ DEBUG_FN(DEBUG_MII);
+
+ phyDetected = (PhyType) uiID1 = ns7520_mii_read(PHY_COMMON_ID1);
+
+ switch (phyDetected) {
+ case PHY_LXT971A:
+ szName = "LXT971A";
+ uiID2 = ns7520_mii_read(PHY_COMMON_ID2);
+ nPhyMaxMdioClock = PHY_LXT971_MDIO_MAX_CLK;
+ cRes = 1;
+ break;
+ case PHY_NONE:
+ default:
+ /* in case uiID1 == 0 && uiID2 == 0 we may have the wrong
+ address or reset sets the wrong NS7520_ETH_MCFG_CLKS */
+
+ uiID2 = 0;
+ szName = "unknown";
+ nPhyMaxMdioClock = PHY_MDIO_MAX_CLK;
+ phyDetected = PHY_NONE;
+ }
+
+ printk(KERN_INFO NS7520_DRIVER_NAME
+ ": PHY (0x%x, 0x%x) = %s detected\n", uiID1, uiID2, szName);
+
+ return cRes;
+}
+
+/***********************************************************************
+ * @Function: ns7520_mii_read
+ * @Return: the data read from PHY register uiRegister
+ * @Descr: the data read may be invalid if timed out. If so, a message
+ * is printed but the invalid data is returned.
+ * The fixed device address is being used.
+ ***********************************************************************/
+
+static unsigned short ns7520_mii_read(unsigned short uiRegister)
+{
+ DEBUG_FN(DEBUG_MII_LOW);
+
+ /* write MII register to be read */
+ *get_eth_reg_addr(NS7520_ETH_MADR) =
+ CONFIG_PHY_ADDR << 8 | uiRegister;
+
+ *get_eth_reg_addr(NS7520_ETH_MCMD) = NS7520_ETH_MCMD_READ;
+
+ if (!ns7520_mii_poll_busy())
+ printk(KERN_WARNING NS7520_DRIVER_NAME
+ ": MII still busy in read\n");
+ /* continue to read */
+
+ *get_eth_reg_addr(NS7520_ETH_MCMD) = 0;
+
+ return (unsigned short) (*get_eth_reg_addr(NS7520_ETH_MRDD));
+}
+
+/***********************************************************************
+ * @Function: ns7520_mii_write
+ * @Return: nothing
+ * @Descr: writes the data to the PHY register. In case of a timeout,
+ * no special handling is performed but a message printed
+ * The fixed device address is being used.
+ ***********************************************************************/
+
+static void ns7520_mii_write(unsigned short uiRegister,
+ unsigned short uiData)
+{
+ DEBUG_FN(DEBUG_MII_LOW);
+
+ /* write MII register to be written */
+ *get_eth_reg_addr(NS7520_ETH_MADR) =
+ CONFIG_PHY_ADDR << 8 | uiRegister;
+
+ *get_eth_reg_addr(NS7520_ETH_MWTD) = uiData;
+
+ if (!ns7520_mii_poll_busy()) {
+ printf(KERN_WARNING NS7520_DRIVER_NAME
+ ": MII still busy in write\n");
+ }
+}
+
+/***********************************************************************
+ * @Function: ns7520_mii_get_clock_divisor
+ * @Return: the clock divisor that should be used in NS7520_ETH_MCFG_CLKS
+ * @Descr: if no clock divisor can be calculated for the
+ * current SYSCLK and the maximum MDIO Clock, a warning is printed
+ * and the greatest divisor is taken
+ ***********************************************************************/
+
+static unsigned int ns7520_mii_get_clock_divisor(unsigned int unMaxMDIOClk)
+{
+ struct {
+ unsigned int unSysClkDivisor;
+ unsigned int unClks; /* field for NS7520_ETH_MCFG_CLKS */
+ } PHYClockDivisors[] = {
+ {
+ 4, NS7520_ETH_MCFG_CLKS_4}, {
+ 6, NS7520_ETH_MCFG_CLKS_6}, {
+ 8, NS7520_ETH_MCFG_CLKS_8}, {
+ 10, NS7520_ETH_MCFG_CLKS_10}, {
+ 14, NS7520_ETH_MCFG_CLKS_14}, {
+ 20, NS7520_ETH_MCFG_CLKS_20}, {
+ 28, NS7520_ETH_MCFG_CLKS_28}
+ };
+
+ int nIndexSysClkDiv;
+ int nArraySize =
+ sizeof(PHYClockDivisors) / sizeof(PHYClockDivisors[0]);
+ unsigned int unClks = NS7520_ETH_MCFG_CLKS_28; /* defaults to
+ greatest div */
+
+ DEBUG_FN(DEBUG_INIT);
+
+ for (nIndexSysClkDiv = 0; nIndexSysClkDiv < nArraySize;
+ nIndexSysClkDiv++) {
+ /* find first sysclock divisor that isn't higher than 2.5 MHz
+ clock */
+ if (NETARM_XTAL_FREQ /
+ PHYClockDivisors[nIndexSysClkDiv].unSysClkDivisor <=
+ unMaxMDIOClk) {
+ unClks = PHYClockDivisors[nIndexSysClkDiv].unClks;
+ break;
+ }
+ }
+
+ DEBUG_ARGS2(DEBUG_INIT,
+ "Taking MDIO Clock bit mask 0x%0x for max clock %i\n",
+ unClks, unMaxMDIOClk);
+
+ /* return greatest divisor */
+ return unClks;
+}
+
+/***********************************************************************
+ * @Function: ns7520_mii_poll_busy
+ * @Return: 0 if timed out otherwise the remaing timeout
+ * @Descr: waits until the MII has completed a command or it times out
+ * code may be interrupted by hard interrupts.
+ * It is not checked what happens on multiple actions when
+ * the first is still being busy and we timeout.
+ ***********************************************************************/
+
+static unsigned int ns7520_mii_poll_busy(void)
+{
+ unsigned int unTimeout = 1000;
+
+ DEBUG_FN(DEBUG_MII_LOW);
+
+ while (((*get_eth_reg_addr(NS7520_ETH_MIND) & NS7520_ETH_MIND_BUSY)
+ == NS7520_ETH_MIND_BUSY) && unTimeout)
+ unTimeout--;
+
+ return unTimeout;
+}
+
+/* ----------------------------------------------------------------------------
+ * Net+ARM ethernet MII functionality.
+ */
+#if defined(CONFIG_MII)
+
+/**
+ * Maximum MII address we support
+ */
+#define MII_ADDRESS_MAX (31)
+
+/**
+ * Maximum MII register address we support
+ */
+#define MII_REGISTER_MAX (31)
+
+/**
+ * Ethernet MII interface return values for public functions.
+ */
+enum mii_status {
+ MII_STATUS_SUCCESS = 0,
+ MII_STATUS_FAILURE = 1,
+};
+
+/**
+ * Read a 16-bit value from an MII register.
+ */
+extern int ns7520_miiphy_read(char *devname, unsigned char const addr,
+ unsigned char const reg, unsigned short *const value)
+{
+ int ret = MII_STATUS_FAILURE;
+
+ /* Parameter checks */
+ if (addr > MII_ADDRESS_MAX) {
+ ERROR(("invalid addr, 0x%02X", addr));
+ goto miiphy_read_failed_0;
+ }
+
+ if (reg > MII_REGISTER_MAX) {
+ ERROR(("invalid reg, 0x%02X", reg));
+ goto miiphy_read_failed_0;
+ }
+
+ if (value == NULL) {
+ ERROR(("NULL value"));
+ goto miiphy_read_failed_0;
+ }
+
+ DEBUG_FN(DEBUG_MII_LOW);
+
+ /* write MII register to be read */
+ *get_eth_reg_addr(NS7520_ETH_MADR) = (addr << 8) | reg;
+
+ *get_eth_reg_addr(NS7520_ETH_MCMD) = NS7520_ETH_MCMD_READ;
+
+ if (!ns7520_mii_poll_busy())
+ printk(KERN_WARNING NS7520_DRIVER_NAME
+ ": MII still busy in read\n");
+ /* continue to read */
+
+ *get_eth_reg_addr(NS7520_ETH_MCMD) = 0;
+
+ *value = (*get_eth_reg_addr(NS7520_ETH_MRDD));
+ ret = MII_STATUS_SUCCESS;
+ /* Fall through */
+
+ miiphy_read_failed_0:
+ return (ret);
+}
+
+/**
+ * Write a 16-bit value to an MII register.
+ */
+extern int ns7520_miiphy_write(char *devname, unsigned char const addr,
+ unsigned char const reg, unsigned short const value)
+{
+ int ret = MII_STATUS_FAILURE;
+
+ /* Parameter checks */
+ if (addr > MII_ADDRESS_MAX) {
+ ERROR(("invalid addr, 0x%02X", addr));
+ goto miiphy_write_failed_0;
+ }
+
+ if (reg > MII_REGISTER_MAX) {
+ ERROR(("invalid reg, 0x%02X", reg));
+ goto miiphy_write_failed_0;
+ }
+
+ /* write MII register to be written */
+ *get_eth_reg_addr(NS7520_ETH_MADR) = (addr << 8) | reg;
+
+ *get_eth_reg_addr(NS7520_ETH_MWTD) = value;
+
+ if (!ns7520_mii_poll_busy()) {
+ printf(KERN_WARNING NS7520_DRIVER_NAME
+ ": MII still busy in write\n");
+ }
+
+ ret = MII_STATUS_SUCCESS;
+ /* Fall through */
+
+ miiphy_write_failed_0:
+ return (ret);
+}
+#endif /* defined(CONFIG_MII) */
+#endif /* CONFIG_DRIVER_NS7520_ETHERNET */
+
+int ns7520_miiphy_initialize(bd_t *bis)
+{
+#if defined(CONFIG_DRIVER_NS7520_ETHERNET)
+#if defined(CONFIG_MII)
+ miiphy_register("ns7520phy", ns7520_miiphy_read, ns7520_miiphy_write);
+#endif
+#endif
+ return 0;
+}
/* get MAC address */
for (i = 0; i < 3; i++) {
u32 data;
- char *mac = &dev->enetaddr[i * 2];
+ char *mac = (char *)&dev->enetaddr[i * 2];
OUTL(dev, i * 2, RxFilterAddr);
data = INL(dev, RxFilterData);
ns8382x_send(struct eth_device *dev, volatile void *packet, int length)
{
u32 i, status = 0;
- u32 tx_stat = 0;
+ vu_long tx_stat = 0;
/* Stop the transmitter */
OUTL(dev, TxOff, ChipCmd);
/* restart the transmitter */
OUTL(dev, TxOn, ChipCmd);
- for (i = 0; ((vu_long)tx_stat = le32_to_cpu(txd.cmdsts)) & DescOwn; i++) {
+ for (i = 0; (tx_stat = le32_to_cpu(txd.cmdsts)) & DescOwn; i++) {
if (i >= TOUT_LOOP) {
printf ("%s: tx error buffer not ready: txd.cmdsts %#X\n",
dev->name, tx_stat);
static void wait_for_bb (void);
static u16 wait_for_pin (void);
-void flush_fifo(void);
+static void flush_fifo(void);
void i2c_init (int speed, int slaveadd)
{
u16 scl;
+ outw(0x2, I2C_SYSC); /* for ES2 after soft reset */
+ udelay(1000);
+ outw(0x0, I2C_SYSC); /* will probably self clear but */
+
if (inw (I2C_CON) & I2C_CON_EN) {
outw (0, I2C_CON);
udelay (50000);
/* own address */
outw (slaveadd, I2C_OA);
outw (I2C_CON_EN, I2C_CON);
- outw (0, I2C_CNT);
+
/* have to enable intrrupts or OMAP i2c module doesn't work */
outw (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE);
udelay (1000);
+ flush_fifo();
+ outw (0xFFFF, I2C_STAT);
+ outw (0, I2C_CNT);
}
static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
}
if (!i2c_error) {
+ int eout = 200;
+
outw (I2C_CON_EN, I2C_CON);
while ((stat = inw (I2C_STAT)) || (inw (I2C_CON) & I2C_CON_MST)) {
udelay (1000);
/* have to read to clear intrrupt */
outw (0xFFFF, I2C_STAT);
+ if(--eout == 0) /* better leave with error than hang */
+ break;
}
}
flush_fifo();
return i2c_error;
}
-void flush_fifo(void)
+static void flush_fifo(void)
{ u16 stat;
/* note: if you try and read data when its not there or ready
| KBD_MODE_DISABLE_MOUSE
| KBD_MODE_KCC);
- /* ibm powerpc portables need this to use scan-code set 1 -- Cort */
+ /* AMCC powerpc portables need this to use scan-code set 1 -- Cort */
kbd_write_command_w(KBD_CCMD_READ_MODE);
if (!(kbd_wait_for_input() & KBD_MODE_KCC)) {
/*
if (bus >= hose->first_busno && bus <= hose->last_busno)
return hose;
- debug ("pci_bus_to_hose() failed\n");
+ printf("pci_bus_to_hose() failed\n");
return NULL;
}
PCI_DEV(dev));
break;
#endif
-
+#ifdef CONFIG_MPC834X
+ case PCI_CLASS_BRIDGE_OTHER:
+ /*
+ * The host/PCI bridge 1 seems broken in 8349 - it presents
+ * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
+ * device claiming resources io/mem/irq.. we only allow for
+ * the PIMMR window to be allocated (BAR0 - 1MB size)
+ */
+ DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n");
+ pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_io);
+ break;
+#endif
default:
pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
break;
#include <common.h>
#ifdef CONFIG_PCI
-#ifndef __I386__
+#if (!defined(__I386__) && !defined(CONFIG_IXDP425))
#include <asm/processor.h>
#include <asm/io.h>
hose->cfg_data = (unsigned char *) cfg_data;
}
-#endif
-#endif
+#endif /* !__I386__ && !CONFIG_IXDP425 */
+#endif /* CONFIG_PCI */
/*
* Setup the PCI device.
*/
- pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &dev->iobase);
+ pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (unsigned int *)&dev->iobase);
dev->iobase &= ~0xf;
PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ",
};
static char SMI_EXT_CRT[] = {
0x31, 0x00, 0x32, 0x00, 0x33, 0x00, 0x34, 0x00, 0x35, 0x00,
- 0x36, 0x00, 0x3b, 0x00, 0x3c, 0x00, 0x3d, 0x00, 0x3e, 0x00, 0x3f, 0x00
+ 0x36, 0x00, 0x3b, 0x00, 0x3c, 0x00, 0x3d, 0x00, 0x3e, 0x00, 0x3f, 0x00,
};
static char SMI_ATTR [] = {
0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04, 0x05, 0x05,
};
static char SMI_GCR[18] = {
0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x03, 0x00, 0x04, 0x00, 0x05, 0x40,
- 0x06, 0x05, 0x07, 0x0f, 0x08, 0xff
+ 0x06, 0x05, 0x07, 0x0f, 0x08, 0xff,
};
static char SMI_SEQR[] = {
- 0x00, 0x00, 0x01, 0x01, 0x02, 0x0f, 0x03, 0x03, 0x04, 0x0e, 0x00, 0x03
+ 0x00, 0x00, 0x01, 0x01, 0x02, 0x0f, 0x03, 0x03, 0x04, 0x0e, 0x00, 0x03,
};
static char SMI_PCR [] = {
- 0x20, 0x04, 0x21, 0x30, 0x22, 0x00, 0x23, 0x00, 0x24, 0x00
+ 0x20, 0x04, 0x21, 0x30, 0x22, 0x00, 0x23, 0x00, 0x24, 0x00,
};
static char SMI_MCR[] = {
0x60, 0x01, 0x61, 0x00,
+#ifdef CONFIG_HMI1001
+ 0x62, 0x74, /* Memory type is not configured by pins on HMI1001 */
+#endif
};
static char SMI_HCR[] = {
0x80, 0xff, 0x81, 0x07, 0x82, 0x00, 0x83, 0xff, 0x84, 0xff, 0x88, 0x00,
- 0x89, 0x02, 0x8a, 0x80, 0x8b, 0x01, 0x8c, 0xff, 0x8d, 0x00
+ 0x89, 0x02, 0x8a, 0x80, 0x8b, 0x01, 0x8c, 0xff, 0x8d, 0x00,
};
/*****************************************************************************/
static void smiLoadCcr (struct ctfb_res_modes *var, unsigned short device_id)
{
- unsigned int p, q;
+ unsigned int p = 0;
+ unsigned int q = 0;
long long freq;
register GraphicDevice *pGD = (GraphicDevice *)&smi;
#if defined(CONFIG_TSEC_ENET)
#include "tsec.h"
+#include "miiphy.h"
-#define TX_BUF_CNT 2
+#define TX_BUF_CNT 2
static uint rxIdx; /* index of the current RX buffer */
static uint txIdx; /* index of the current TX buffer */
void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
static void adjust_link(struct eth_device *dev);
static void relocate_cmds(void);
+static int tsec_miiphy_write(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value);
+static int tsec_miiphy_read(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value);
/* Initialize device structure. Returns success if PHY
* initialization succeeded (i.e. if it recognizes the PHY)
priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \
+ && !defined(BITBANGMII)
+ miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
+#endif
+
/* Try to initialize PHY here, and return */
return init_phy(dev);
}
for(i=0;i<MAC_ADDR_LEN;i++) {
tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
}
- (uint)(regs->macstnaddr1) = *((uint *)(tmpbuf));
+ regs->macstnaddr1 = *((uint *)(tmpbuf));
tempval = *((uint *)(tmpbuf +4));
- (uint)(regs->macstnaddr2) = tempval;
+ regs->macstnaddr2 = tempval;
/* reset the indices to zero */
rxIdx = 0;
* auto-negotiation */
uint mii_parse_sr(uint mii_reg, struct tsec_private *priv)
{
- uint timeout = TSEC_TIMEOUT;
-
- if(mii_reg & MIIM_STATUS_LINK)
- priv->link = 1;
- else
- priv->link = 0;
+ /*
+ * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
+ */
+ mii_reg = read_phy_reg(priv, MIIM_STATUS);
+ if ((mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
+ int i = 0;
+
+ puts ("Waiting for PHY auto negotiation to complete");
+ while (!((mii_reg & PHY_BMSR_AUTN_COMP) && (mii_reg & MIIM_STATUS_LINK))) {
+ /*
+ * Timeout reached ?
+ */
+ if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
+ puts (" TIMEOUT !\n");
+ priv->link = 0;
+ break;
+ }
- if(priv->link) {
- while((!(mii_reg & MIIM_STATUS_AN_DONE)) && timeout--)
+ if ((i++ % 1000) == 0) {
+ putc ('.');
+ }
+ udelay (1000); /* 1 ms */
mii_reg = read_phy_reg(priv, MIIM_STATUS);
+ }
+ puts (" done\n");
+ priv->link = 1;
+ udelay (500000); /* another 500 ms (results in faster booting) */
+ } else {
+ priv->link = 1;
}
return 0;
{
uint speed;
+ mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
+
+ if (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
+ (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
+ int i = 0;
+
+ puts ("Waiting for PHY realtime link");
+ while (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
+ (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
+ /*
+ * Timeout reached ?
+ */
+ if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
+ puts (" TIMEOUT !\n");
+ priv->link = 0;
+ break;
+ }
+
+ if ((i++ % 1000) == 0) {
+ putc ('.');
+ }
+ udelay (1000); /* 1 ms */
+ mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
+ }
+ puts (" done\n");
+ udelay (500000); /* another 500 ms (results in faster booting) */
+ }
+
if(mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
priv->duplexity = 1;
else
printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID);
return NULL;
} else {
- printf("%s: PHY is %s (%x)\n", dev->name, theInfo->name,
- phy_ID);
+ debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
}
return theInfo;
}
-#ifndef CONFIG_BITBANGMII
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \
+ && !defined(BITBANGMII)
struct tsec_private * get_priv_for_phy(unsigned char phyaddr)
{
* Returns:
* 0 on success
*/
-int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value)
+static int tsec_miiphy_read(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value)
{
unsigned short ret;
struct tsec_private *priv = get_priv_for_phy(addr);
* Returns:
* 0 on success
*/
-int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
+static int tsec_miiphy_write(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value)
{
struct tsec_private *priv = get_priv_for_phy(addr);
return 0;
}
-#endif /* CONFIG_BITBANGMII */
+#endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+ && !defined(BITBANGMII) */
#endif /* CONFIG_TSEC_ENET */
#define TSEC_TIMEOUT 1000
#define TOUT_LOOP 1000000
+#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */
+
/* MAC register bits */
#define MACCFG1_SOFT_RESET 0x80000000
#define MACCFG1_RESET_RX_MC 0x00080000
#define MIIM_CONTROL 0x00
#define MIIM_CONTROL_RESET 0x00009140
#define MIIM_CONTROL_INIT 0x00001140
+#define MIIM_CONTROL_RESTART 0x00001340
#define MIIM_ANEN 0x00001000
#define MIIM_CR 0x00
#define MIIM_STATUS 0x1
#define MIIM_STATUS_AN_DONE 0x00000020
#define MIIM_STATUS_LINK 0x0004
+#define PHY_BMSR_AUTN_ABLE 0x0008
+#define PHY_BMSR_AUTN_COMP 0x0020
#define MIIM_PHYIR1 0x2
#define MIIM_PHYIR2 0x3
static inline void *memcpy(void *dst, const void *src, unsigned int len)
{
- void * ret = dst;
- while (len-- > 0) *((char *)dst)++ = *((char *)src)++;
- return ret;
+ char *ret = dst;
+ while (len-- > 0) {
+ *ret++ = *((char *)src);
+ src++;
+ }
+ return (void *)ret;
}
/* The EEPROM commands include the alway-set leading bit. */
/* CMD TABLE - uboot command sections
*/
+ . = .;
__uboot_cmd_start = .;
.u_boot_cmd :
{
current_tid = id;
PDEBUG ("thread_start: to be stack=0%08x",
(unsigned)lthreads[id].stack);
- setctxsp (<hreads[id].stack[STK_SIZE]);
+ setctxsp ((vu_char *)<hreads[id].stack[STK_SIZE]);
thread_launcher ();
}
/* CPU address space offset calculation macro, struct part_info offset is
* device address space offset, so we need to shift it by a device start address. */
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+extern flash_info_t flash_info[];
#define PART_OFFSET(x) (x->offset + flash_info[x->dev->id->num].start[0])
static int cramfs_read_super (struct part_info *info)
int blockcnt;
int log2blocksize = LOG2_EXT2_BLOCK_SIZE (node->data);
int blocksize = 1 << (log2blocksize + DISK_SECTOR_BITS);
- unsigned int filesize = node->inode.size;
+ unsigned int filesize = __le32_to_cpu(node->inode.size);
/* Adjust len so it we can't read past the end of the file. */
if (len > filesize) {
/* no signature found */
return -1;
}
- if(!strncmp(&buffer[DOS_FS_TYPE_OFFSET],"FAT",3)) {
+ if(!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET],"FAT",3)) {
/* ok, we assume we are on a PBR only */
cur_part = 1;
part_offset=0;
void rubin_do_decompress(unsigned char *bits, unsigned char *in,
unsigned char *page_out, __u32 destlen)
{
- register char *curr = page_out;
- char *end = page_out + destlen;
+ register char *curr = (char *)page_out;
+ char *end = (char *)(page_out + destlen);
register unsigned long temp;
register unsigned long result;
register unsigned long p;
rec_q <<= 1;
rec_q |= (temp >> (bit++ ^ 7)) & 1;
if (bit > 31) {
+ u32 *p = (u32 *)in;
bit = 0;
- temp = *(++((u32 *) in));
+ temp = *(++p);
+ in = (unsigned char *)p;
}
}
i0 = (bits[i] * p) >> 8;
u32 addr = off;
struct mtdids *id = current_part->dev->id;
- extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+ extern flash_info_t flash_info[];
flash_info_t *flash = &flash_info[id->num];
addr += flash->start[0];
/* length is also the same, so use ascending sort by name
*/
- cmp = strncmp(jNew->name, jOld->name, jNew->nsize);
+ cmp = strncmp((char *)jNew->name, (char *)jOld->name, jNew->nsize);
if (cmp != 0)
return cmp > 0;
struct jffs2_raw_inode *jNode;
u32 totalSize = 0;
u32 latestVersion = 0;
- char *lDest;
- char *src;
+ uchar *lDest;
+ uchar *src;
long ret;
int i;
u32 counter = 0;
#endif
if(dest) {
- src = ((char *) jNode) + sizeof(struct jffs2_raw_inode);
+ src = ((uchar *) jNode) + sizeof(struct jffs2_raw_inode);
/* ignore data behind latest known EOF */
if (jNode->offset > totalSize) {
put_fl_mem(jNode);
continue;
}
- lDest = (char *) (dest + jNode->offset);
+ lDest = (uchar *) (dest + jNode->offset);
#if 0
putLabeledWord("read_inode: src = ", src);
putLabeledWord("read_inode: dest = ", lDest);
jDir = (struct jffs2_raw_dirent *) get_node_mem(b->offset);
if ((pino == jDir->pino) && (len == jDir->nsize) &&
(jDir->ino) && /* 0 for unlink */
- (!strncmp(jDir->name, name, len))) { /* a match */
+ (!strncmp((char *)jDir->name, name, len))) { /* a match */
if (jDir->version < version) {
put_fl_mem(jDir);
continue;
if (st->st_mtime == (time_t)(-1)) /* some ctimes really hate -1 */
st->st_mtime = 1;
- ctime_r(&st->st_mtime, s/*,64*/); /* newlib ctime doesn't have buflen */
+ ctime_r((time_t *)&st->st_mtime, s/*,64*/); /* newlib ctime doesn't have buflen */
if ((p = strchr(s,'\n')) != NULL) *p = '\0';
if ((p = strchr(s,'\r')) != NULL) *p = '\0';
if(!d || !i) return -1;
- strncpy(fname, d->name, d->nsize);
+ strncpy(fname, (char *)d->name, d->nsize);
fname[d->nsize] = '\0';
memset(&st,0,sizeof(st));
putnstr(src, jNode->dsize);
putstr("\r\n");
#endif
- strncpy(tmp, src, jNode->dsize);
+ strncpy(tmp, (char *)src, jNode->dsize);
tmp[jNode->dsize] = '\0';
put_fl_mem(jNode);
break;
+++ /dev/null
-/*----------------------------------------------------------------------------+
-|
-| This source code has been made available to you by IBM on an AS-IS
-| basis. Anyone receiving this source is licensed under IBM
-| copyrights to use it in any way he or she deems fit, including
-| copying it, modifying it, compiling it, and redistributing it either
-| with or without modifications. No license under IBM patents or
-| patent applications is to be implied by the copyright license.
-|
-| Any user of this software should understand that IBM cannot provide
-| technical support for this software and will not be responsible for
-| any consequences resulting from the use of this software.
-|
-| Any person who transfers this source code or any derivative work
-| must include the IBM copyright notice, this paragraph, and the
-| preceding two paragraphs in the transferred software.
-|
-| COPYRIGHT I B M CORPORATION 1999
-| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
-+----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------+
-|
-| File Name: enetemac.h
-|
-| Function: Header file for the EMAC3 macro on the 405GP.
-|
-| Author: Mark Wisner
-|
-| Change Activity-
-|
-| Date Description of Change BY
-| --------- --------------------- ---
-| 29-Apr-99 Created MKW
-|
-+----------------------------------------------------------------------------*/
-#ifndef _enetemac_h_
-#define _enetemac_h_
-#include <net.h>
-#include <405_mal.h>
-
-/*-----------------------------------------------------------------------------+
-| General enternet defines. 802 frames are not supported.
-+-----------------------------------------------------------------------------*/
-#define ENET_ADDR_LENGTH 6
-#define ENET_ARPTYPE 0x806
-#define ARP_REQUEST 1
-#define ARP_REPLY 2
-#define ENET_IPTYPE 0x800
-#define ARP_CACHE_SIZE 5
-
-
-struct enet_frame {
- unsigned char dest_addr[ENET_ADDR_LENGTH];
- unsigned char source_addr[ENET_ADDR_LENGTH];
- unsigned short type;
- unsigned char enet_data[1];
-};
-
-struct arp_entry {
- unsigned long inet_address;
- unsigned char mac_address[ENET_ADDR_LENGTH];
- unsigned long valid;
- unsigned long sec;
- unsigned long nsec;
-};
-
-
- /*Register addresses */
-#if defined(CONFIG_440)
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
-#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00)
-#else
-#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780)
-#endif
-#define ZMII_FER (ZMII_BASE)
-#define ZMII_SSR (ZMII_BASE + 4)
-#define ZMII_SMIISR (ZMII_BASE + 8)
-
-#define ZMII_RMII 0x22000000
-#define ZMII_MDI0 0x80000000
-#endif /* CONFIG_440 */
-
-#if defined(CONFIG_440)
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
-#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00)
-#else
-#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)
-#endif
-#else
-#define EMAC_BASE 0xEF600800
-#endif
-
-#define EMAC_M0 (EMAC_BASE)
-#define EMAC_M1 (EMAC_BASE + 4)
-#define EMAC_TXM0 (EMAC_BASE + 8)
-#define EMAC_TXM1 (EMAC_BASE + 12)
-#define EMAC_RXM (EMAC_BASE + 16)
-#define EMAC_ISR (EMAC_BASE + 20)
-#define EMAC_IER (EMAC_BASE + 24)
-#define EMAC_IAH (EMAC_BASE + 28)
-#define EMAC_IAL (EMAC_BASE + 32)
-#define EMAC_VLAN_TPID_REG (EMAC_BASE + 36)
-#define EMAC_VLAN_TCI_REG (EMAC_BASE + 40)
-#define EMAC_PAUSE_TIME_REG (EMAC_BASE + 44)
-#define EMAC_IND_HASH_1 (EMAC_BASE + 48)
-#define EMAC_IND_HASH_2 (EMAC_BASE + 52)
-#define EMAC_IND_HASH_3 (EMAC_BASE + 56)
-#define EMAC_IND_HASH_4 (EMAC_BASE + 60)
-#define EMAC_GRP_HASH_1 (EMAC_BASE + 64)
-#define EMAC_GRP_HASH_2 (EMAC_BASE + 68)
-#define EMAC_GRP_HASH_3 (EMAC_BASE + 72)
-#define EMAC_GRP_HASH_4 (EMAC_BASE + 76)
-#define EMAC_LST_SRC_LOW (EMAC_BASE + 80)
-#define EMAC_LST_SRC_HI (EMAC_BASE + 84)
-#define EMAC_I_FRAME_GAP_REG (EMAC_BASE + 88)
-#define EMAC_STACR (EMAC_BASE + 92)
-#define EMAC_TRTR (EMAC_BASE + 96)
-#define EMAC_RX_HI_LO_WMARK (EMAC_BASE + 100)
-
-/* bit definitions */
-/* MODE REG 0 */
-#define EMAC_M0_RXI 0x80000000
-#define EMAC_M0_TXI 0x40000000
-#define EMAC_M0_SRST 0x20000000
-#define EMAC_M0_TXE 0x10000000
-#define EMAC_M0_RXE 0x08000000
-#define EMAC_M0_WKE 0x04000000
-
-/* MODE Reg 1 */
-#define EMAC_M1_FDE 0x80000000
-#define EMAC_M1_ILE 0x40000000
-#define EMAC_M1_VLE 0x20000000
-#define EMAC_M1_EIFC 0x10000000
-#define EMAC_M1_APP 0x08000000
-#define EMAC_M1_AEMI 0x02000000
-#define EMAC_M1_IST 0x01000000
-#define EMAC_M1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */
-#define EMAC_M1_MF_100MBPS 0x00400000
-#define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */
-#define EMAC_M1_RFS_2K 0x00200000
-#define EMAC_M1_RFS_1K 0x00100000
-#define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */
-#define EMAC_M1_TX_FIFO_1K 0x00040000
-#define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */
-#define EMAC_M1_TR0_MULTI 0x00008000
-#define EMAC_M1_TR1_DEPEND 0x00004000
-#define EMAC_M1_TR1_MULTI 0x00002000
-#define EMAC_M1_JUMBO_ENABLE 0x00001000
-
-/* Transmit Mode Register 0 */
-#define EMAC_TXM0_GNP0 0x80000000
-#define EMAC_TXM0_GNP1 0x40000000
-#define EMAC_TXM0_GNPD 0x20000000
-#define EMAC_TXM0_FC 0x10000000
-
-/* Receive Mode Register */
-#define EMAC_RMR_SP 0x80000000
-#define EMAC_RMR_SFCS 0x40000000
-#define EMAC_RMR_ARRP 0x20000000
-#define EMAC_RMR_ARP 0x10000000
-#define EMAC_RMR_AROP 0x08000000
-#define EMAC_RMR_ARPI 0x04000000
-#define EMAC_RMR_PPP 0x02000000
-#define EMAC_RMR_PME 0x01000000
-#define EMAC_RMR_PMME 0x00800000
-#define EMAC_RMR_IAE 0x00400000
-#define EMAC_RMR_MIAE 0x00200000
-#define EMAC_RMR_BAE 0x00100000
-#define EMAC_RMR_MAE 0x00080000
-
-/* Interrupt Status & enable Regs */
-#define EMAC_ISR_OVR 0x02000000
-#define EMAC_ISR_PP 0x01000000
-#define EMAC_ISR_BP 0x00800000
-#define EMAC_ISR_RP 0x00400000
-#define EMAC_ISR_SE 0x00200000
-#define EMAC_ISR_SYE 0x00100000
-#define EMAC_ISR_BFCS 0x00080000
-#define EMAC_ISR_PTLE 0x00040000
-#define EMAC_ISR_ORE 0x00020000
-#define EMAC_ISR_IRE 0x00010000
-#define EMAC_ISR_DBDM 0x00000200
-#define EMAC_ISR_DB0 0x00000100
-#define EMAC_ISR_SE0 0x00000080
-#define EMAC_ISR_TE0 0x00000040
-#define EMAC_ISR_DB1 0x00000020
-#define EMAC_ISR_SE1 0x00000010
-#define EMAC_ISR_TE1 0x00000008
-#define EMAC_ISR_MOS 0x00000002
-#define EMAC_ISR_MOF 0x00000001
-
-
-/* STA CONTROL REG */
-#define EMAC_STACR_OC 0x00008000
-#define EMAC_STACR_PHYE 0x00004000
-#define EMAC_STACR_WRITE 0x00002000
-#define EMAC_STACR_READ 0x00001000
-#define EMAC_STACR_CLK_83MHZ 0x00000800 /* 0's for 50Mhz */
-#define EMAC_STACR_CLK_66MHZ 0x00000400
-#define EMAC_STACR_CLK_100MHZ 0x00000C00
-
-/* Transmit Request Threshold Register */
-#define EMAC_TRTR_256 0x18000000 /* 0's for 64 Bytes */
-#define EMAC_TRTR_192 0x10000000
-#define EMAC_TRTR_128 0x01000000
-
-/* the follwing defines are for the MadMAL status and control registers. */
-/* For bits 0..5 look at the mal.h file */
-#define EMAC_TX_CTRL_GFCS 0x0200
-#define EMAC_TX_CTRL_GP 0x0100
-#define EMAC_TX_CTRL_ISA 0x0080
-#define EMAC_TX_CTRL_RSA 0x0040
-#define EMAC_TX_CTRL_IVT 0x0020
-#define EMAC_TX_CTRL_RVT 0x0010
-
-#define EMAC_TX_CTRL_DEFAULT (EMAC_TX_CTRL_GFCS |EMAC_TX_CTRL_GP)
-
-#define EMAC_TX_ST_BFCS 0x0200
-#define EMAC_TX_ST_BPP 0x0100
-#define EMAC_TX_ST_LCS 0x0080
-#define EMAC_TX_ST_ED 0x0040
-#define EMAC_TX_ST_EC 0x0020
-#define EMAC_TX_ST_LC 0x0010
-#define EMAC_TX_ST_MC 0x0008
-#define EMAC_TX_ST_SC 0x0004
-#define EMAC_TX_ST_UR 0x0002
-#define EMAC_TX_ST_SQE 0x0001
-
-#define EMAC_TX_ST_DEFAULT 0x03F3
-
-
-/* madmal receive status / Control bits */
-
-#define EMAC_RX_ST_OE 0x0200
-#define EMAC_RX_ST_PP 0x0100
-#define EMAC_RX_ST_BP 0x0080
-#define EMAC_RX_ST_RP 0x0040
-#define EMAC_RX_ST_SE 0x0020
-#define EMAC_RX_ST_AE 0x0010
-#define EMAC_RX_ST_BFCS 0x0008
-#define EMAC_RX_ST_PTL 0x0004
-#define EMAC_RX_ST_ORE 0x0002
-#define EMAC_RX_ST_IRE 0x0001
-/* all the errors we care about */
-#define EMAC_RX_ERRORS 0x03FF
-
-#define NUM_RX_BUFF PKTBUFSRX
-#define NUM_TX_BUFF 1
-
-#define MAX_ERR_LOG 10
-typedef struct emac_stats_st{ /* Statistic Block */
- int data_len_err;
- int rx_frames;
- int rx;
- int rx_prot_err;
- int int_err;
- int pkts_tx;
- int pkts_rx;
- int pkts_handled;
- short tx_err_log[MAX_ERR_LOG];
- short rx_err_log[MAX_ERR_LOG];
-} EMAC_STATS_ST, *EMAC_STATS_PST;
-
-/* Structure containing variables used by the shared code (440gx_enet.c) */
-typedef struct emac_440gx_hw_st {
- uint32_t hw_addr; /* EMAC offset */
- uint32_t tah_addr; /* TAH offset */
- uint32_t phy_id;
- uint32_t phy_addr;
- uint32_t original_fc;
- uint32_t txcw;
- uint32_t autoneg_failed;
- uint32_t emac_ier;
- volatile mal_desc_t *tx;
- volatile mal_desc_t *rx;
- bd_t *bis; /* for eth_init upon mal error */
- mal_desc_t *alloc_tx_buf;
- mal_desc_t *alloc_rx_buf;
- char *txbuf_ptr;
- uint16_t devnum;
- int get_link_status;
- int tbi_compatibility_en;
- int tbi_compatibility_on;
- int fc_send_xon;
- int report_tx_early;
- int first_init;
- int tx_err_index;
- int rx_err_index;
- int rx_slot; /* MAL Receive Slot */
- int rx_i_index; /* Receive Interrupt Queue Index */
- int rx_u_index; /* Receive User Queue Index */
- int tx_slot; /* MAL Transmit Slot */
- int tx_i_index; /* Transmit Interrupt Queue Index */
- int tx_u_index; /* Transmit User Queue Index */
- int rx_ready[NUM_RX_BUFF]; /* Receive Ready Queue */
- int tx_run[NUM_TX_BUFF]; /* Transmit Running Queue */
- int is_receiving; /* sync with eth interrupt */
- int print_speed; /* print speed message upon start */
- EMAC_STATS_ST stats;
-} EMAC_405_HW_ST, *EMAC_405_HW_PST;
-
-/*-----------------------------------------------------------------------------+
-| Function prototypes for device table.
-+-----------------------------------------------------------------------------*/
-#endif /* _enetLib_h_ */
--- /dev/null
+/************************************************
+ * NAME arm946es.h *
+ * $Version$ *
+ ************************************************/
+/* Currently empty */
+#ifndef __ARM946ES_H__
+#define __ARM946ES_H__
+#endif /*__ARM946ES_H__*/
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * ARM Ltd.
+ * Peter Pearse, <Peter.Pearse@arm.com>
+ * Configuration for ARM Core Modules.
+ * No standalonw port yet available
+ * - this file is included by both integratorap.h & integratorcp.h
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ARMCOREMODULE_H
+#define __ARMCOREMODULE_H
+
+#define CM_BASE 0x10000000
+
+/* CM registers common to all CMs */
+/* Note that observed values after reboot into the ARM Boot Monitor
+ have been used as defaults, rather than the POR values */
+#define OS_CTRL 0x0000000C
+#define CMMASK_REMAP 0x00000005 /* set remap & led */
+#define CMMASK_RESET 0x00000008
+#define OS_LOCK 0x00000014
+#define CMVAL_LOCK1 0x0000A000 /* locking value */
+#define CMVAL_LOCK2 0x0000005F /* locking value */
+#define CMVAL_UNLOCK 0x00000000 /* any value != CM_LOCKVAL */
+#define OS_SDRAM 0x00000020
+#define OS_INIT 0x00000024
+#define CMMASK_MAP_SIMPLE 0xFFFDFFFF /* simple mapping */
+#define CMMASK_TCRAM_DISABLE 0xFFFEFFFF /* TCRAM disabled */
+#define CMMASK_LOWVEC 0x00000000 /* vectors @ 0x00000000 */
+#define CMMASK_LE 0xFFFFFFF7 /* little endian */
+#define CMMASK_CMxx6_COMMON 0x00000013 /* Common value for CMxx6 */
+ /* - observed reset value of */
+ /* CM926EJ-S */
+ /* CM1136-EJ-S */
+
+#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
+#define CMMASK_INIT_102 0x00000300 /* see CM102xx ref manual */
+ /* - PLL test clock bypassed */
+ /* - bus clock ratio 2 */
+ /* - little endian */
+ /* - vectors at zero */
+#endif /* CM1022xx */
+
+/* Determine CM characteristics */
+
+#undef CONFIG_CM_MULTIPLE_SSRAM
+#undef CONFIG_CM_SPD_DETECT
+#undef CONFIG_CM_REMAP
+#undef CONFIG_CM_INIT
+#undef CONFIG_CM_TCRAM
+
+#if defined (CONFIG_CM946E_S) || defined (CONFIG_CM966E_S)
+#define CONFIG_CM_MULTIPLE_SSRAM /* CM has multiple SSRAM mapping */
+#endif
+
+/* Excalibur core module has reduced functionality */
+#ifndef CONFIG_CM922T_XA10
+#define CONFIG_CM_SPD_DETECT /* CM supports SPD query */
+#define OS_SPD 0x00000100 /* Address of SPD data */
+#define CONFIG_CM_REMAP /* CM supports remapping */
+#define CONFIG_CM_INIT /* CM has initialization reg */
+#endif /* NOT EXCALIBUR */
+
+#if defined(CONFIG_CM926EJ_S) || defined (CONFIG_CM946E_S) || \
+ defined(CONFIG_CM966E_S) || defined (CONFIG_CM1026EJ_S) || \
+ defined(CONFIG_CM1136JF_S)
+#define CONFIG_CM_TCRAM /* CM has TCRAM */
+#endif
+
+#ifdef CONFIG_CM_SPD_DETECT
+#define OS_SPD 0x00000100 /* The SDRAM SPD data is copied here */
+#endif
+
+#endif /* __ARMCOREMODULE_H */
#define II_MPU_DIV 0x2 /* mpu = core/2 */
#define II_DSP_DIV 0x343 /* dsp & iva divider */
#define II_GFX_DIV 0x2
-#define II_BUS_DIV 0x04600C26
-#define II_BUS_DIV_ES1 0x04601026
+#define II_BUS_DIV 0x04601026
#define II_DPLL_300 0x01832100
/****************************************************************************;
#define III_MPU_DIV 0x2 /* mpu = core/2 */
#define III_DSP_DIV 0x23C3 /* dsp & iva divider sych enabled*/
#define III_GFX_DIV 0x2
-#define III_BUS_DIV 0x08300c44
-#define III_BUS_DIV_ES1 0x08301044
+#define III_BUS_DIV 0x08301044
#define III_DPLL_266 0x01885500
/* set defaults for boot up */
# define DSP_DIV II_DSP_DIV
# define GFX_DIV II_GFX_DIV
# define BUS_DIV II_BUS_DIV
-# define BUS_DIV_ES1 II_BUS_DIV_ES1
# define DPLL_VAL II_DPLL_300
#elif PRCM_CONFIG_III
# define DPLL_OUT III_DPLL_OUT_X2
# define DSP_DIV III_DSP_DIV
# define GFX_DIV III_GFX_DIV
# define BUS_DIV III_BUS_DIV
-# define BUS_DIV_ES1 III_BUS_DIV_ES1
# define DPLL_VAL III_DPLL_266
#endif
#define I2C_BUF (I2C_BASE + 0x14)
#define I2C_CNT (I2C_BASE + 0x18)
#define I2C_DATA (I2C_BASE + 0x1c)
+#define I2C_SYSC (I2C_BASE + 0x20)
#define I2C_CON (I2C_BASE + 0x24)
#define I2C_OA (I2C_BASE + 0x28)
#define I2C_SA (I2C_BASE + 0x2c)
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
#ifndef _OMAP24XX_MEM_H_
#define _OMAP24XX_MEM_H_
-#define SDRC_CS0_OSET 0x0
-#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */
+#define SDRC_CS0_OSET 0x0
+#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */
#ifndef __ASSEMBLY__
/* struct's for holding data tables for current boards, they are getting used
u32 sdrc_rfr_ctrl;
u32 sdrc_mr_0_ddr;
u32 sdrc_mr_0_sdr;
- u32 sdrc_dlla_ctrl;
- u32 sdrc_dllb_ctrl;
+ u32 sdrc_dllab_ctrl;
} /*__attribute__ ((packed))*/;
typedef struct sdrc_data_s sdrc_data_t;
STACKED = 0,
IP_DDR = 1,
COMBO_DDR = 2,
- IP_SDR = 3,
+ IP_SDR = 3,
} mem_t;
#endif
/* Slower full frequency range default timings for x32 operation*/
-#define H4_2420_SDRC_SHARING 0x00000100
+#define H4_2420_SDRC_SHARING 0x00000100
#define H4_2420_SDRC_MDCFG_0_SDR 0x00D04010 /* discrete sdr module */
#define H4_2420_SDRC_MR_0_SDR 0x00000031
#define H4_2420_SDRC_MDCFG_0_DDR 0x01702011 /* descrite ddr module */
#define H4_2420_COMBO_MDCFG_0_DDR 0x00801011 /* combo module */
#define H4_2420_SDRC_MR_0_DDR 0x00000032
-#ifndef CONFIG_OPTIMIZE_DDR
-# define H4_2420_SDRC_ACTIM_CTRLA_0 0x9bead909
-# define H4_2420_SDRC_ACTIM_CTRLB_0 0x00000014
-# define H4_2420_SDRC_RFR_CTRL_ES1 0x00002401
-# define H4_2420_SDRC_RFR_CTRL 0x0002da01
-#endif
-#define H4_2420_SDRC_DLLA_CTRL 0x00007307 /* load value at 100Mhz */
-#define H4_2420_SDRC_DLLB_CTRL 0x00007307
-
#define H4_2422_SDRC_SHARING 0x00004b00
#define H4_2422_SDRC_MDCFG_0_DDR 0x00801011 /* stacked ddr on 2422 */
-#ifndef CONFIG_OPTIMIZE_DDR
-# define H4_2422_SDRC_ACTIM_CTRLA_0 0x9BEAD909
-# define H4_2422_SDRC_ACTIM_CTRLB_0 0x00000020
-# define H4_2422_SDRC_RFR_CTRL_ES1 0x00002401
-# define H4_2422_SDRC_RFR_CTRL 0x0002da01
-#endif
#define H4_2422_SDRC_MR_0_DDR 0x00000032
-#define H4_2422_SDRC_DLLA_CTRL 0x00007307
-#define H4_2422_SDRC_DLLB_CTRL 0x00007307
-/* optimized timings */
+/* ES1 work around timings */
+#define H4_242x_SDRC_ACTIM_CTRLA_0_ES1 0x9bead909 /* 165Mhz for use with 100/133 */
+#define H4_242x_SDRC_ACTIM_CTRLB_0_ES1 0x00000020
+#define H4_242x_SDRC_RFR_CTRL_ES1 0x00002401 /* use over refresh for ES1 */
+
+/* optimized timings good for current shipping parts */
#define H4_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x5A59B485
#define H4_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000e
-#define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz 0x8BA6E6C8 /* temp warn 0 settigs */
-#define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz 0x00000010 /* temp warn 0 settings */
-#define H4_242X_SDRC_RFR_CTRL_100MHz 0x0002da01 /* this is not optimal yet */
-#define H4_242X_SDRC_RFR_CTRL_133MHz 0x0003de01
-
-#ifdef CONFIG_OPTIMIZE_DDR
-# ifdef PRCM_CONFIG_II
-# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
-# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
-# define H4_2420_SDRC_RFR_CTRL_ES1 H4_242X_SDRC_RFR_CTRL_100MHz
-# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz
-# elif PRCM_CONFIG_III
-# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz
-# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz
-# define H4_2420_SDRC_RFR_CTRL_ES1 H4_242X_SDRC_RFR_CTRL_133MHz
-# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz
-# endif
-# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_2420_SDRC_ACTIM_CTRLA_0
-# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_2420_SDRC_ACTIM_CTRLB_0
-# define H4_2422_SDRC_RFR_CTRL_ES1 H4_2420_SDRC_RFR_CTRL_ES1
-# define H4_2422_SDRC_RFR_CTRL H4_2420_SDRC_RFR_CTRL
+#define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz 0x8BA6E6C8 /* temp warn 0 settings */
+#define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz 0x00000010 /* temp warn 0 settings */
+#define H4_242X_SDRC_RFR_CTRL_100MHz 0x0002da01
+#define H4_242X_SDRC_RFR_CTRL_133MHz 0x0003de01
+#define H4_242x_SDRC_DLLAB_CTRL_100MHz 0x0000980E /* 72deg, allow DPLLout*1 to work (combo)*/
+#define H4_242x_SDRC_DLLAB_CTRL_133MHz 0x0000690E /* 72deg, for ES2 */
+
+#ifdef PRCM_CONFIG_II
+# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
+# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
+# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz
+# define H4_2420_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz
+# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
+# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
+# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz
+# define H4_2422_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz
+#elif PRCM_CONFIG_III
+# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz
+# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz
+# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz
+# define H4_2420_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_133MHz
+# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
+# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
+# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz
+# define H4_2422_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz
#endif
/* GPMC settings */
-#ifdef PRCM_CONFIG_II /* L3 at 100MHz */
-#ifdef CFG_NAND_BOOT
-#define H4_24XX_GPMC_CONFIG1_0 0x0
-#define H4_24XX_GPMC_CONFIG2_0 0x00141400
-#define H4_24XX_GPMC_CONFIG3_0 0x00141400
-#define H4_24XX_GPMC_CONFIG4_0 0x0F010F01
-#define H4_24XX_GPMC_CONFIG5_0 0x010C1414
-#define H4_24XX_GPMC_CONFIG6_0 0x00000A80
-#else
-#define H4_24XX_GPMC_CONFIG1_0 0x3
-#define H4_24XX_GPMC_CONFIG2_0 0x000f0f01
-#define H4_24XX_GPMC_CONFIG3_0 0x00050502
-#define H4_24XX_GPMC_CONFIG4_0 0x0C060C06
-#define H4_24XX_GPMC_CONFIG5_0 0x01131F1F
-#endif
-#define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24))
-
-#define H4_24XX_GPMC_CONFIG1_1 0x00011000
-#define H4_24XX_GPMC_CONFIG2_1 0x001F1F00
-#define H4_24XX_GPMC_CONFIG3_1 0x00080802
-#define H4_24XX_GPMC_CONFIG4_1 0x1C091C09
-#define H4_24XX_GPMC_CONFIG5_1 0x031A1F1F
-#define H4_24XX_GPMC_CONFIG6_1 0x000003C2
-#define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24))
-#endif
-
-#ifdef PRCM_CONFIG_III /* L3 at 133MHz */
-#ifdef CFG_NAND_BOOT
-#define H4_24XX_GPMC_CONFIG1_0 0x0
-#define H4_24XX_GPMC_CONFIG2_0 0x00141400
-#define H4_24XX_GPMC_CONFIG3_0 0x00141400
-#define H4_24XX_GPMC_CONFIG4_0 0x0F010F01
-#define H4_24XX_GPMC_CONFIG5_0 0x010C1414
-#define H4_24XX_GPMC_CONFIG6_0 0x00000A80
-#else
-#define H4_24XX_GPMC_CONFIG1_0 0x3
-#define H4_24XX_GPMC_CONFIG2_0 0x00151501
-#define H4_24XX_GPMC_CONFIG3_0 0x00060602
-#define H4_24XX_GPMC_CONFIG4_0 0x10081008
-#define H4_24XX_GPMC_CONFIG5_0 0x01131F1F
-#define H4_24XX_GPMC_CONFIG6_0 0x000004c4
-#endif
-#define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24))
-
-#define H4_24XX_GPMC_CONFIG1_1 0x00011000
-#define H4_24XX_GPMC_CONFIG2_1 0x001f1f01
-#define H4_24XX_GPMC_CONFIG3_1 0x00080803
-#define H4_24XX_GPMC_CONFIG4_1 0x1C091C09
-#define H4_24XX_GPMC_CONFIG5_1 0x041f1F1F
-#define H4_24XX_GPMC_CONFIG6_1 0x000004C4
-#define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24))
-#endif
-
-#ifdef CONFIG_APTIX /* SDRC-SDR for Aptix x16 */
-#define VAL_H4_SDRC_SHARING_16 0x00002400 /* No-Tristate, 16bit on D31-D16, CS1=dont care */
-#define VAL_H4_SDRC_SHARING 0x00000100
-#define VAL_H4_SDRC_MCFG_0_16 0x00901000 /* SDR-SDRAM,External,x16 bit */
-#define VAL_H4_SDRC_MCFG_0 0x01702011
-#define VAL_H4_SDRC_MR_0 0x00000029 /* Burst=2, Serial Mode, CAS 3*/
-#define VAL_H4_SDRC_RFR_CTRL_0 0x00001703 /* refresh time */
-#define VAL_H4_SDRC_DCDL2_CTRL 0x5A59B485
-#endif
-
-#endif
+#ifdef PRCM_CONFIG_II /* L3 at 100MHz */
+# ifdef CFG_NAND_BOOT
+# define H4_24XX_GPMC_CONFIG1_0 0x0
+# define H4_24XX_GPMC_CONFIG2_0 0x00141400
+# define H4_24XX_GPMC_CONFIG3_0 0x00141400
+# define H4_24XX_GPMC_CONFIG4_0 0x0F010F01
+# define H4_24XX_GPMC_CONFIG5_0 0x010C1414
+# define H4_24XX_GPMC_CONFIG6_0 0x00000A80
+# else /* else NOR */
+# define H4_24XX_GPMC_CONFIG1_0 0x3
+# define H4_24XX_GPMC_CONFIG2_0 0x000f0f01
+# define H4_24XX_GPMC_CONFIG3_0 0x00050502
+# define H4_24XX_GPMC_CONFIG4_0 0x0C060C06
+# define H4_24XX_GPMC_CONFIG5_0 0x01131F1F
+# endif /* endif CFG_NAND_BOOT */
+# define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24))
+# define H4_24XX_GPMC_CONFIG1_1 0x00011000
+# define H4_24XX_GPMC_CONFIG2_1 0x001F1F00
+# define H4_24XX_GPMC_CONFIG3_1 0x00080802
+# define H4_24XX_GPMC_CONFIG4_1 0x1C091C09
+# define H4_24XX_GPMC_CONFIG5_1 0x031A1F1F
+# define H4_24XX_GPMC_CONFIG6_1 0x000003C2
+# define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24))
+#endif /* endif PRCM_CONFIG_II */
+
+#ifdef PRCM_CONFIG_III /* L3 at 133MHz */
+# ifdef CFG_NAND_BOOT
+# define H4_24XX_GPMC_CONFIG1_0 0x0
+# define H4_24XX_GPMC_CONFIG2_0 0x00141400
+# define H4_24XX_GPMC_CONFIG3_0 0x00141400
+# define H4_24XX_GPMC_CONFIG4_0 0x0F010F01
+# define H4_24XX_GPMC_CONFIG5_0 0x010C1414
+# define H4_24XX_GPMC_CONFIG6_0 0x00000A80
+# else /* NOR boot */
+# define H4_24XX_GPMC_CONFIG1_0 0x3
+# define H4_24XX_GPMC_CONFIG2_0 0x00151501
+# define H4_24XX_GPMC_CONFIG3_0 0x00060602
+# define H4_24XX_GPMC_CONFIG4_0 0x10081008
+# define H4_24XX_GPMC_CONFIG5_0 0x01131F1F
+# define H4_24XX_GPMC_CONFIG6_0 0x000004c4
+# endif /* endif CFG_NAND_BOOT */
+# define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24))
+# define H4_24XX_GPMC_CONFIG1_1 0x00011000
+# define H4_24XX_GPMC_CONFIG2_1 0x001f1f01
+# define H4_24XX_GPMC_CONFIG3_1 0x00080803
+# define H4_24XX_GPMC_CONFIG4_1 0x1C091C09
+# define H4_24XX_GPMC_CONFIG5_1 0x041f1F1F
+# define H4_24XX_GPMC_CONFIG6_1 0x000004C4
+# define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24))
+#endif /* endif CFG_PRCM_III */
+
+#endif /* endif _OMAP24XX_MEM_H_ */
* 2420 specific Section
*/
+/* L3 Firewall */
+#define A_REQINFOPERM0 0x68005048
+#define A_READPERM0 0x68005050
+#define A_WRITEPERM0 0x68005058
+/* #define GP_DEVICE (BIT8|BIT9) FIXME -- commented out to make compile -- FIXME */
+
+/* L3 Firewall */
+#define A_REQINFOPERM0 0x68005048
+#define A_READPERM0 0x68005050
+#define A_WRITEPERM0 0x68005058
+
/* CONTROL */
#define OMAP2420_CTRL_BASE (0x48000000)
#define CONTROL_STATUS (OMAP2420_CTRL_BASE + 0x2F8)
+/* device type */
+#define TST_DEVICE 0x0
+#define EMU_DEVICE 0x1
+#define HS_DEVICE 0x2
+#define GP_DEVICE 0x3
+
/* TAP information */
#define OMAP2420_TAP_BASE (0x48014000)
#define TAP_IDCODE_REG (OMAP2420_TAP_BASE+0x204)
+#define PRODUCTION_ID (OMAP2420_TAP_BASE+0x208)
/* GPMC */
#define OMAP2420_GPMC_BASE (0x6800A000)
#define OMAP2420_SDRC_BASE 0x68009000
#define SDRC_SYSCONFIG (OMAP2420_SDRC_BASE+0x10)
#define SDRC_STATUS (OMAP2420_SDRC_BASE+0x14)
+#define SDRC_CS_CFG (OMAP2420_SDRC_BASE+0x40)
#define SDRC_SHARING (OMAP2420_SDRC_BASE+0x44)
#define SDRC_DLLA_CTRL (OMAP2420_SDRC_BASE+0x60)
#define SDRC_DLLB_CTRL (OMAP2420_SDRC_BASE+0x68)
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _OMAP24XX_REV_H_
-#define _OMAP24XX_REV_H_
-
-typedef struct h4_system_data {
- /* base board info */
- u32 base_b_rev; /* rev from base board i2c */
- /* cpu board info */
- u32 cpu_b_rev; /* rev from cpu board i2c */
- u32 cpu_b_mux; /* mux type on daughter board */
- u32 cpu_b_ddr_type; /* mem type */
- u32 cpu_b_ddr_speed; /* ddr speed rating */
- u32 cpu_b_switches; /* boot ctrl switch settings */
- /* cpu info */
- u32 cpu_type; /* type of cpu; 2420, 2422, 2430,...*/
- u32 cpu_rev; /* rev of given cpu; ES1, ES2,...*/
-} h4_sys_data;
-
-#define CDB_DDR_COMBO /* combo part on cpu daughter card */
-#define CDB_DDR_IPDB /* 2x16 parts on daughter card */
-
-#define DDR_100 100 /* type found on most mem d-boards */
-#define DDR_111 111 /* some combo parts */
-#define DDR_133 133 /* most combo, some mem d-boards */
-#define DDR_165 165 /* future parts */
-
-#define CPU_2420 0x2420
-#define CPU_2422 0x2422
-
-#define CPU_2422_ES1 1
-#define CPU_2422_ES2 2
-#define CPU_2420_ES1 1
-#define CPU_2420_ES2 2
-
-#endif
u32 cpu_rev; /* rev of given cpu; ES1, ES2,...*/
} h4_sys_data;
-#define SDR_DISCRETE 4
+#define XDR_POP 5 /* package on package part */
+#define SDR_DISCRETE 4 /* 128M memory SDR module*/
#define DDR_STACKED 3 /* stacked part on 2422 */
#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */
#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */
#define DDR_165 165 /* future parts */
#define CPU_2420 0x2420
-#define CPU_2422 0x2422
+#define CPU_2422 0x2422 /* 2420 + 64M stacked */
+#define CPU_2423 0x2423 /* 2420 + 96M stacked */
#define CPU_2422_ES1 1
#define CPU_2422_ES2 2
#define CPU_2420_ES1 1
#define CPU_2420_ES2 2
+#define CPU_2420_2422_ES1 1
#define CPU_2420_CHIPID 0x0B5D9000
#define CPU_24XX_ID_MASK 0x0FFFF000
#define CPU_242X_REV_MASK 0xF0000000
+#define CPU_242X_PID_MASK 0x000F0000
#define BOARD_H4_MENELAUS 1
#define BOARD_H4_SDP 2
u32 get_board_type(void);
void display_board_info(u32);
void update_mux(u32,u32);
+u32 get_sdr_cs_size(u32 offset);
u32 running_in_sdram(void);
u32 running_in_sram(void);
u32 running_in_flash(void);
u32 running_from_internal_boot(void);
-
+u32 get_device_type(void);
#endif
/* include IMPA7 specific hardware file if there was one */
#elif defined(CONFIG_EP7312)
/* include EP7312 specific hardware file if there was one */
+#elif defined(CONFIG_ARMADILLO)
+/* include armadillo specific hardware file if there was one */
+#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+/* include IntegratorCP/CM720T specific hardware file if there was one */
#else
#error No hardware file defined for this configuration
#endif
/*
* include/asm-armnommu/arch-netarm/netarm_gen_module.h
*
+ * Copyright (C) 2005
+ * Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
+ *
* Copyright (C) 2000, 2001 NETsilicon, Inc.
* Copyright (C) 2000, 2001 Red Hat, Inc.
*
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* author(s) : Joe deBlaquiere
+ *
+ * Modified to support NS7520 by Art Shipkowski.
*/
#ifndef __NETARM_GEN_MODULE_REGISTERS_H
#define NETARM_GEN_TIMER2_STATUS (0x1c)
#define NETARM_GEN_PORTA (0x20)
+#ifndef CONFIG_NETARM_NS7520
#define NETARM_GEN_PORTB (0x24)
+#endif
#define NETARM_GEN_PORTC (0x28)
#define NETARM_GEN_INTR_ENABLE (0x30)
/* PORT C Register ( 0xFFB0_0028 ) */
+#ifndef CONFIG_NETARM_NS7520
#define NETARM_GEN_PORT_MODE(x) (((x)<<24) + (0xFF00))
#define NETARM_GEN_PORT_DIR(x) (((x)<<16) + (0xFF00))
+#else
+#define NETARM_GEN_PORT_MODE(x) ((x)<<24)
+#define NETARM_GEN_PORT_DIR(x) ((x)<<16)
+#define NETARM_GEN_PORT_CSF(x) ((x)<<8)
+#endif
/* Timer Registers ( 0xFFB0_0010 0xFFB0_0018 ) */
#define NETARM_GEN_TCTL_INIT_COUNT(x) ((x) & 0x1FF)
#define NETARM_GEN_TSTAT_INTPEN (0x40000000)
+#if ~defined(CONFIG_NETARM_NS7520)
#define NETARM_GEN_TSTAT_CTC_MASK (0x000001FF)
+#else
+#define NETARM_GEN_TSTAT_CTC_MASK (0x0FFFFFFF)
+#endif
/* prescale to msecs conversion */
+#if !defined(CONFIG_NETARM_PLL_BYPASS)
#define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 20480 ) * ( 0x1FF - ( (x) & \
NETARM_GEN_TSTAT_CTC_MASK ) + \
1 ) ) / (NETARM_XTAL_FREQ/1000) )
NETARM_GEN_TSTAT_CTC_MASK ) | \
NETARM_GEN_TCTL_USE_PRESCALE )
-#if 0
-/* ifdef CONFIG_NETARM_PLL_BYPASS else */
-#error test
+#else
#define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 4096 ) * ( 0x1FF - ( (x) & \
NETARM_GEN_TSTAT_CTC_MASK ) + \
1 ) ) / (NETARM_XTAL_FREQ/1000) )
/*
* include/asm-armnommu/arch-netarm/netarm_mem_module.h
*
+ * Copyright (C) 2005
+ * Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
+ *
* Copyright (C) 2000, 2001 NETsilicon, Inc.
* Copyright (C) 2000, 2001 Red Hat, Inc.
*
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* author(s) : Joe deBlaquiere
+ *
+ * Modified to support NS7520 by Art Shipkowski.
*/
#ifndef __NETARM_MEM_MODULE_REGISTERS_H
#define NETARM_MEM_OPT_WRITE_ASYNC (0x00000000)
#define NETARM_MEM_OPT_WRITE_SYNC (0x00000001)
+#ifdef CONFIG_NETARM_NS7520
+/* The NS7520 has a second options register for each chip select */
+#define NETARM_MEM_CS0_OPTIONS_B (0x18)
+#define NETARM_MEM_CS1_OPTIONS_B (0x28)
+#define NETARM_MEM_CS2_OPTIONS_B (0x38)
+#define NETARM_MEM_CS3_OPTIONS_B (0x48)
+#define NETARM_MEM_CS4_OPTIONS_B (0x58)
+
+/* Option B Registers (0xFFC0_00x8) */
+#define NETARM_MEM_OPTB_SYNC_1_STAGE (0x00000001)
+#define NETARM_MEM_OPTB_SYNC_2_STAGE (0x00000002)
+#define NETARM_MEM_OPTB_BCYC_PLUS0 (0x00000000)
+#define NETARM_MEM_OPTB_BCYC_PLUS4 (0x00000004)
+#define NETARM_MEM_OPTB_BCYC_PLUS8 (0x00000008)
+#define NETARM_MEM_OPTB_BCYC_PLUS12 (0x0000000C)
+
+#define NETARM_MEM_OPTB_WAIT_PLUS0 (0x00000000)
+#define NETARM_MEM_OPTB_WAIT_PLUS16 (0x00000010)
+#define NETARM_MEM_OPTB_WAIT_PLUS32 (0x00000020)
+#define NETARM_MEM_OPTB_WAIT_PLUS48 (0x00000030)
+#endif
+
#endif
/*
* linux/include/asm-arm/arch-netarm/netarm_registers.h
*
+ * Copyright (C) 2005
+ * Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
+ *
* Copyright (C) 2000, 2001 NETsilicon, Inc.
* Copyright (C) 2000, 2001 WireSpeed Communications Corporation
*
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* author(s) : Joe deBlaquiere
+ *
+ * Modified to support NS7520 by Art Shipkowski.
*/
#ifndef __NET_ARM_REGISTERS_H
/* the input crystal/clock frequency ( in Hz ) */
#define NETARM_XTAL_FREQ_25MHz (18432000)
#define NETARM_XTAL_FREQ_33MHz (23698000)
+#define NETARM_XTAL_FREQ_48MHz (48000000)
+#define NETARM_XTAL_FREQ_55MHz (55000000)
#define NETARM_XTAL_FREQ_EMLIN1 (20000000)
/* the frequency of SYS_CLK */
#define NETARM_PLL_COUNT_VAL 4
#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz
-#else /* CONFIG_NETARM_NET50 */
+#elif defined(CONFIG_NETARM_NET50)
/* NET+50 boards: 40 MHz (with NETARM_XTAL_FREQ_25MHz) */
#define NETARM_PLL_COUNT_VAL 8
#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz
+#else /* CONFIG_NETARM_NS7520 */
+
+#define NETARM_PLL_COUNT_VAL 0
+
+#if defined(CONFIG_BOARD_UNC20)
+#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_48MHz
+#else
+#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_55MHz
+#endif
+
#endif
/* #include "arm_registers.h" */
#ifndef AT91RM9200_H
#define AT91RM9200_H
-typedef volatile unsigned int AT91_REG;/* Hardware register definition */
+typedef volatile unsigned int AT91_REG; /* Hardware register definition */
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_TC {
+/******************************************************************************/
+/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */
+/******************************************************************************/
+typedef struct _AT91S_TC
+{
AT91_REG TC_CCR; /* Channel Control Register */
AT91_REG TC_CMR; /* Channel Mode Register */
AT91_REG Reserved0[2]; /* */
AT91_REG TC_IMR; /* Interrupt Mask Register */
} AT91S_TC, *AT91PS_TC;
-#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */
-#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */
-#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */
-#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */
-#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK */
-#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */
-#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */
-#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */
-#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */
-#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */
-#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */
-#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */
-#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */
-#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */
-
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Usart */
-/* ***************************************************************************** */
-typedef struct _AT91S_USART {
+#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */
+#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */
+#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */
+#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */
+#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK */
+#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */
+#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */
+#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */
+#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */
+#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */
+#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */
+#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */
+#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */
+#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */
+
+/******************************************************************************/
+/* SOFTWARE API DEFINITION FOR Usart */
+/******************************************************************************/
+typedef struct _AT91S_USART
+{
AT91_REG US_CR; /* Control Register */
AT91_REG US_MR; /* Mode Register */
AT91_REG US_IER; /* Interrupt Enable Register */
AT91_REG US_NER; /* Nb Errors Register */
AT91_REG US_XXR; /* XON_XOFF Register */
AT91_REG US_IF; /* IRDA_FILTER Register */
- AT91_REG Reserved1[44]; /* */
+ AT91_REG Reserved1[44]; /* */
AT91_REG US_RPR; /* Receive Pointer Register */
AT91_REG US_RCR; /* Receive Counter Register */
AT91_REG US_TPR; /* Transmit Pointer Register */
AT91_REG US_PTSR; /* PDC Transfer Status Register */
} AT91S_USART, *AT91PS_USART;
-/************************************************************************/
-/* SOFTWARE API DEFINITION FOR Clock Generator Controler */
-/************************************************************************/
-typedef struct _AT91S_CKGR {
+/******************************************************************************/
+/* SOFTWARE API DEFINITION FOR Clock Generator Controler */
+/******************************************************************************/
+typedef struct _AT91S_CKGR
+{
AT91_REG CKGR_MOR; /* Main Oscillator Register */
AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */
AT91_REG CKGR_PLLAR; /* PLL A Register */
} AT91S_CKGR, *AT91PS_CKGR;
/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
-#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) /* (CKGR) Main Oscillator Enable */
-#define AT91C_CKGR_OSCTEST ((unsigned int) 0x1 << 1) /* (CKGR) Oscillator Test */
-#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) /* (CKGR) Main Oscillator Start-up Time */
+#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) /* (CKGR) Main Oscillator Enable */
+#define AT91C_CKGR_OSCTEST ((unsigned int) 0x1 << 1) /* (CKGR) Oscillator Test */
+#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) /* (CKGR) Main Oscillator Start-up Time */
+
/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
-#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) /* (CKGR) Main Clock Frequency */
-#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) /* (CKGR) Main Clock Ready */
+#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) /* (CKGR) Main Clock Frequency */
+#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) /* (CKGR) Main Clock Ready */
+
/* -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- */
-#define AT91C_CKGR_DIVA ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected */
-#define AT91C_CKGR_DIVA_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0 */
-#define AT91C_CKGR_DIVA_BYPASS ((unsigned int) 0x1) /* (CKGR) Divider is bypassed */
-#define AT91C_CKGR_PLLACOUNT ((unsigned int) 0x3F << 8) /* (CKGR) PLL A Counter */
-#define AT91C_CKGR_OUTA ((unsigned int) 0x3 << 14) /* (CKGR) PLL A Output Frequency Range */
-#define AT91C_CKGR_OUTA_0 ((unsigned int) 0x0 << 14) /* (CKGR) Please refer to the PLLA datasheet */
-#define AT91C_CKGR_OUTA_1 ((unsigned int) 0x1 << 14) /* (CKGR) Please refer to the PLLA datasheet */
-#define AT91C_CKGR_OUTA_2 ((unsigned int) 0x2 << 14) /* (CKGR) Please refer to the PLLA datasheet */
-#define AT91C_CKGR_OUTA_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLA datasheet */
-#define AT91C_CKGR_MULA ((unsigned int) 0x7FF << 16) /* (CKGR) PLL A Multiplier */
-#define AT91C_CKGR_SRCA ((unsigned int) 0x1 << 29) /* (CKGR) PLL A Source */
+#define AT91C_CKGR_DIVA ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected */
+#define AT91C_CKGR_DIVA_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0 */
+#define AT91C_CKGR_DIVA_BYPASS ((unsigned int) 0x1) /* (CKGR) Divider is bypassed */
+#define AT91C_CKGR_PLLACOUNT ((unsigned int) 0x3F << 8) /* (CKGR) PLL A Counter */
+#define AT91C_CKGR_OUTA ((unsigned int) 0x3 << 14) /* (CKGR) PLL A Output Frequency Range */
+#define AT91C_CKGR_OUTA_0 ((unsigned int) 0x0 << 14) /* (CKGR) Please refer to the PLLA datasheet */
+#define AT91C_CKGR_OUTA_1 ((unsigned int) 0x1 << 14) /* (CKGR) Please refer to the PLLA datasheet */
+#define AT91C_CKGR_OUTA_2 ((unsigned int) 0x2 << 14) /* (CKGR) Please refer to the PLLA datasheet */
+#define AT91C_CKGR_OUTA_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLA datasheet */
+#define AT91C_CKGR_MULA ((unsigned int) 0x7FF << 16) /* (CKGR) PLL A Multiplier */
+#define AT91C_CKGR_SRCA ((unsigned int) 0x1 << 29) /* (CKGR) PLL A Source */
+
/* -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- */
-#define AT91C_CKGR_DIVB ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected */
-#define AT91C_CKGR_DIVB_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0 */
-#define AT91C_CKGR_DIVB_BYPASS ((unsigned int) 0x1) /* (CKGR) Divider is bypassed */
-#define AT91C_CKGR_PLLBCOUNT ((unsigned int) 0x3F << 8) /* (CKGR) PLL B Counter */
-#define AT91C_CKGR_OUTB ((unsigned int) 0x3 << 14) /* (CKGR) PLL B Output Frequency Range */
-#define AT91C_CKGR_OUTB_0 ((unsigned int) 0x0 << 14) /* (CKGR) Please refer to the PLLB datasheet */
-#define AT91C_CKGR_OUTB_1 ((unsigned int) 0x1 << 14) /* (CKGR) Please refer to the PLLB datasheet */
-#define AT91C_CKGR_OUTB_2 ((unsigned int) 0x2 << 14) /* (CKGR) Please refer to the PLLB datasheet */
-#define AT91C_CKGR_OUTB_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLB datasheet */
-#define AT91C_CKGR_MULB ((unsigned int) 0x7FF << 16) /* (CKGR) PLL B Multiplier */
-#define AT91C_CKGR_USB_96M ((unsigned int) 0x1 << 28) /* (CKGR) Divider for USB Ports */
-#define AT91C_CKGR_USB_PLL ((unsigned int) 0x1 << 29) /* (CKGR) PLL Use */
-
-/* ************************************************************************* */
-/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */
-/* ************************************************************************* */
-typedef struct _AT91S_PIO {
+#define AT91C_CKGR_DIVB ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected */
+#define AT91C_CKGR_DIVB_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0 */
+#define AT91C_CKGR_DIVB_BYPASS ((unsigned int) 0x1) /* (CKGR) Divider is bypassed */
+#define AT91C_CKGR_PLLBCOUNT ((unsigned int) 0x3F << 8) /* (CKGR) PLL B Counter */
+#define AT91C_CKGR_OUTB ((unsigned int) 0x3 << 14) /* (CKGR) PLL B Output Frequency Range */
+#define AT91C_CKGR_OUTB_0 ((unsigned int) 0x0 << 14) /* (CKGR) Please refer to the PLLB datasheet */
+#define AT91C_CKGR_OUTB_1 ((unsigned int) 0x1 << 14) /* (CKGR) Please refer to the PLLB datasheet */
+#define AT91C_CKGR_OUTB_2 ((unsigned int) 0x2 << 14) /* (CKGR) Please refer to the PLLB datasheet */
+#define AT91C_CKGR_OUTB_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLB datasheet */
+#define AT91C_CKGR_MULB ((unsigned int) 0x7FF << 16) /* (CKGR) PLL B Multiplier */
+#define AT91C_CKGR_USB_96M ((unsigned int) 0x1 << 28) /* (CKGR) Divider for USB Ports */
+#define AT91C_CKGR_USB_PLL ((unsigned int) 0x1 << 29) /* (CKGR) PLL Use */
+
+/******************************************************************************/
+/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */
+/******************************************************************************/
+typedef struct _AT91S_PIO
+{
AT91_REG PIO_PER; /* PIO Enable Register */
AT91_REG PIO_PDR; /* PIO Disable Register */
AT91_REG PIO_PSR; /* PIO Status Register */
} AT91S_PIO, *AT91PS_PIO;
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Debug Unit */
-/* ***************************************************************************** */
-typedef struct _AT91S_DBGU {
+/******************************************************************************/
+/* SOFTWARE API DEFINITION FOR Debug Unit */
+/******************************************************************************/
+typedef struct _AT91S_DBGU
+{
AT91_REG DBGU_CR; /* Control Register */
AT91_REG DBGU_MR; /* Mode Register */
AT91_REG DBGU_IER; /* Interrupt Enable Register */
} AT91S_DBGU, *AT91PS_DBGU;
/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
-#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* (DBGU) RXRDY Interrupt */
-#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* (DBGU) TXRDY Interrupt */
-#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) /* (DBGU) End of Receive Transfer Interrupt */
-#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) /* (DBGU) End of Transmit Interrupt */
-#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) /* (DBGU) Overrun Interrupt */
-#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) /* (DBGU) Framing Error Interrupt */
-#define AT91C_US_PARE ((unsigned int) 0x1 << 7) /* (DBGU) Parity Error Interrupt */
-#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) /* (DBGU) TXEMPTY Interrupt */
-#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) /* (DBGU) TXBUFE Interrupt */
-#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) /* (DBGU) RXBUFF Interrupt */
-#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) /* (DBGU) COMM_TX Interrupt */
-#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) /* (DBGU) COMM_RX Interrupt */
+#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* (DBGU) RXRDY Interrupt */
+#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* (DBGU) TXRDY Interrupt */
+#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) /* (DBGU) End of Receive Transfer Interrupt */
+#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) /* (DBGU) End of Transmit Interrupt */
+#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) /* (DBGU) Overrun Interrupt */
+#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) /* (DBGU) Framing Error Interrupt */
+#define AT91C_US_PARE ((unsigned int) 0x1 << 7) /* (DBGU) Parity Error Interrupt */
+#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) /* (DBGU) TXEMPTY Interrupt */
+#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) /* (DBGU) TXBUFE Interrupt */
+#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) /* (DBGU) RXBUFF Interrupt */
+#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) /* (DBGU) COMM_TX Interrupt */
+#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) /* (DBGU) COMM_RX Interrupt */
/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
-#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* (DBGU) Reset Receiver */
-#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* (DBGU) Reset Transmitter */
-#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* (DBGU) Receiver Enable */
-#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* (DBGU) Receiver Disable */
-#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* (DBGU) Transmitter Enable */
-#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* (DBGU) Transmitter Disable */
-
-#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* (USART) Clock */
-#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* (USART) Character Length: 8 bits */
-#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* (DBGU) No Parity */
-#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */
-
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_SMC2 {
+#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* (DBGU) Reset Receiver */
+#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* (DBGU) Reset Transmitter */
+#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* (DBGU) Receiver Enable */
+#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* (DBGU) Receiver Disable */
+#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* (DBGU) Transmitter Enable */
+#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* (DBGU) Transmitter Disable */
+
+#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* (USART) Clock */
+#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* (USART) Character Length: 8 bits */
+#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* (DBGU) No Parity */
+#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */
+
+/******************************************************************************/
+/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */
+/******************************************************************************/
+typedef struct _AT91S_SMC2
+{
AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */
} AT91S_SMC2, *AT91PS_SMC2;
/* -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- */
-#define AT91C_SMC2_NWS ((unsigned int) 0x7F << 0) /* (SMC2) Number of Wait States */
-#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */
-#define AT91C_SMC2_TDF ((unsigned int) 0xF << 8) /* (SMC2) Data Float Time */
-#define AT91C_SMC2_BAT ((unsigned int) 0x1 << 12) /* (SMC2) Byte Access Type */
-#define AT91C_SMC2_DBW ((unsigned int) 0x1 << 13) /* (SMC2) Data Bus Width */
-#define AT91C_SMC2_DBW_16 ((unsigned int) 0x1 << 13) /* (SMC2) 16-bit. */
-#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */
-#define AT91C_SMC2_DRP ((unsigned int) 0x1 << 15) /* (SMC2) Data Read Protocol */
-#define AT91C_SMC2_ACSS ((unsigned int) 0x3 << 16) /* (SMC2) Address to Chip Select Setup */
-#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */
-#define AT91C_SMC2_ACSS_1_CYCLE ((unsigned int) 0x1 << 16) /* (SMC2) One cycle less at the beginning and the end of the access. */
-#define AT91C_SMC2_ACSS_2_CYCLES ((unsigned int) 0x2 << 16) /* (SMC2) Two cycles less at the beginning and the end of the access. */
-#define AT91C_SMC2_ACSS_3_CYCLES ((unsigned int) 0x3 << 16) /* (SMC2) Three cycles less at the beginning and the end of the access. */
-#define AT91C_SMC2_RWSETUP ((unsigned int) 0x7 << 24) /* (SMC2) Read and Write Signal Setup Time */
-#define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */
-
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Power Management Controler */
-/* ******************************************************************************/
-typedef struct _AT91S_PMC {
+#define AT91C_SMC2_NWS ((unsigned int) 0x7F << 0) /* (SMC2) Number of Wait States */
+#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */
+#define AT91C_SMC2_TDF ((unsigned int) 0xF << 8) /* (SMC2) Data Float Time */
+#define AT91C_SMC2_BAT ((unsigned int) 0x1 << 12) /* (SMC2) Byte Access Type */
+#define AT91C_SMC2_DBW ((unsigned int) 0x1 << 13) /* (SMC2) Data Bus Width */
+#define AT91C_SMC2_DBW_16 ((unsigned int) 0x1 << 13) /* (SMC2) 16-bit. */
+#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */
+#define AT91C_SMC2_DRP ((unsigned int) 0x1 << 15) /* (SMC2) Data Read Protocol */
+#define AT91C_SMC2_ACSS ((unsigned int) 0x3 << 16) /* (SMC2) Address to Chip Select Setup */
+#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */
+#define AT91C_SMC2_ACSS_1_CYCLE ((unsigned int) 0x1 << 16) /* (SMC2) One cycle less at the beginning and the end of the access. */
+#define AT91C_SMC2_ACSS_2_CYCLES ((unsigned int) 0x2 << 16) /* (SMC2) Two cycles less at the beginning and the end of the access. */
+#define AT91C_SMC2_ACSS_3_CYCLES ((unsigned int) 0x3 << 16) /* (SMC2) Three cycles less at the beginning and the end of the access. */
+#define AT91C_SMC2_RWSETUP ((unsigned int) 0x7 << 24) /* (SMC2) Read and Write Signal Setup Time */
+#define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */
+
+/******************************************************************************/
+/* SOFTWARE API DEFINITION FOR Power Management Controler */
+/******************************************************************************/
+typedef struct _AT91S_PMC
+{
AT91_REG PMC_SCER; /* System Clock Enable Register */
AT91_REG PMC_SCDR; /* System Clock Disable Register */
AT91_REG PMC_SCSR; /* System Clock Status Register */
AT91_REG PMC_IMR; /* Interrupt Mask Register */
} AT91S_PMC, *AT91PS_PMC;
-
/*------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------*/
-#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) /* (PMC) Processor Clock */
-#define AT91C_PMC_UDP ((unsigned int) 0x1 << 1) /* (PMC) USB Device Port Clock */
-#define AT91C_PMC_MCKUDP ((unsigned int) 0x1 << 2) /* (PMC) USB Device Port Master Clock Automatic Disable on Suspend */
-#define AT91C_PMC_UHP ((unsigned int) 0x1 << 4) /* (PMC) USB Host Port Clock */
-#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK4 ((unsigned int) 0x1 << 12) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK5 ((unsigned int) 0x1 << 13) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK6 ((unsigned int) 0x1 << 14) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK7 ((unsigned int) 0x1 << 15) /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) /* (PMC) Processor Clock */
+#define AT91C_PMC_UDP ((unsigned int) 0x1 << 1) /* (PMC) USB Device Port Clock */
+#define AT91C_PMC_MCKUDP ((unsigned int) 0x1 << 2) /* (PMC) USB Device Port Master Clock Automatic Disable on Suspend */
+#define AT91C_PMC_UHP ((unsigned int) 0x1 << 4) /* (PMC) USB Host Port Clock */
+#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK4 ((unsigned int) 0x1 << 12) /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK5 ((unsigned int) 0x1 << 13) /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK6 ((unsigned int) 0x1 << 14) /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK7 ((unsigned int) 0x1 << 15) /* (PMC) Programmable Clock Output */
/*-------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register ------*/
/*-------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------*/
/*-------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------*/
-#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) /* (PMC) Programmable Clock Selection */
-#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) /* (PMC) Slow Clock is selected */
-#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) /* (PMC) Main Clock is selected */
-#define AT91C_PMC_CSS_PLLA_CLK ((unsigned int) 0x2) /* (PMC) Clock from PLL A is selected */
-#define AT91C_PMC_CSS_PLLB_CLK ((unsigned int) 0x3) /* (PMC) Clock from PLL B is selected */
-#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) /* (PMC) Programmable Clock Prescaler */
-#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) /* (PMC) Selected clock */
-#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) /* (PMC) Selected clock divided by 2 */
-#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) /* (PMC) Selected clock divided by 4 */
-#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) /* (PMC) Selected clock divided by 8 */
-#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) /* (PMC) Selected clock divided by 16 */
-#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) /* (PMC) Selected clock divided by 32 */
-#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) /* (PMC) Selected clock divided by 64 */
-#define AT91C_PMC_MDIV ((unsigned int) 0x3 << 8) /* (PMC) Master Clock Division */
-#define AT91C_PMC_MDIV_1 ((unsigned int) 0x0 << 8) /* (PMC) The master clock and the processor clock are the same */
-#define AT91C_PMC_MDIV_2 ((unsigned int) 0x1 << 8) /* (PMC) The processor clock is twice as fast as the master clock */
-#define AT91C_PMC_MDIV_3 ((unsigned int) 0x2 << 8) /* (PMC) The processor clock is three times faster than the master clock */
-#define AT91C_PMC_MDIV_4 ((unsigned int) 0x3 << 8) /* (PMC) The processor clock is four times faster than the master clock */
+#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) /* (PMC) Programmable Clock Selection */
+#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) /* (PMC) Slow Clock is selected */
+#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) /* (PMC) Main Clock is selected */
+#define AT91C_PMC_CSS_PLLA_CLK ((unsigned int) 0x2) /* (PMC) Clock from PLL A is selected */
+#define AT91C_PMC_CSS_PLLB_CLK ((unsigned int) 0x3) /* (PMC) Clock from PLL B is selected */
+#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) /* (PMC) Programmable Clock Prescaler */
+#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) /* (PMC) Selected clock */
+#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) /* (PMC) Selected clock divided by 2 */
+#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) /* (PMC) Selected clock divided by 4 */
+#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) /* (PMC) Selected clock divided by 8 */
+#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) /* (PMC) Selected clock divided by 16 */
+#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) /* (PMC) Selected clock divided by 32 */
+#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) /* (PMC) Selected clock divided by 64 */
+#define AT91C_PMC_MDIV ((unsigned int) 0x3 << 8) /* (PMC) Master Clock Division */
+#define AT91C_PMC_MDIV_1 ((unsigned int) 0x0 << 8) /* (PMC) The master clock and the processor clock are the same */
+#define AT91C_PMC_MDIV_2 ((unsigned int) 0x1 << 8) /* (PMC) The processor clock is twice as fast as the master clock */
+#define AT91C_PMC_MDIV_3 ((unsigned int) 0x2 << 8) /* (PMC) The processor clock is three times faster than the master clock */
+#define AT91C_PMC_MDIV_4 ((unsigned int) 0x3 << 8) /* (PMC) The processor clock is four times faster than the master clock */
/*------ PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------*/
/*------ PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------*/
-#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) /* (PMC) MOSC Status/Enable/Disable/Mask */
-#define AT91C_PMC_LOCKA ((unsigned int) 0x1 << 1) /* (PMC) PLL A Status/Enable/Disable/Mask */
-#define AT91C_PMC_LOCKB ((unsigned int) 0x1 << 2) /* (PMC) PLL B Status/Enable/Disable/Mask */
-#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK4RDY ((unsigned int) 0x1 << 12) /* (PMC) PCK4_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK5RDY ((unsigned int) 0x1 << 13) /* (PMC) PCK5_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK6RDY ((unsigned int) 0x1 << 14) /* (PMC) PCK6_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK7RDY ((unsigned int) 0x1 << 15) /* (PMC) PCK7_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) /* (PMC) MOSC Status/Enable/Disable/Mask */
+#define AT91C_PMC_LOCKA ((unsigned int) 0x1 << 1) /* (PMC) PLL A Status/Enable/Disable/Mask */
+#define AT91C_PMC_LOCKB ((unsigned int) 0x1 << 2) /* (PMC) PLL B Status/Enable/Disable/Mask */
+#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK4RDY ((unsigned int) 0x1 << 12) /* (PMC) PCK4_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK5RDY ((unsigned int) 0x1 << 13) /* (PMC) PCK5_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK6RDY ((unsigned int) 0x1 << 14) /* (PMC) PCK6_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK7RDY ((unsigned int) 0x1 << 15) /* (PMC) PCK7_RDY Status/Enable/Disable/Mask */
/*---- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------*/
/*-------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------*/
/*-------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------*/
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Ethernet MAC */
-/* ***************************************************************************** */
-typedef struct _AT91S_EMAC {
+/******************************************************************************/
+/* SOFTWARE API DEFINITION FOR Ethernet MAC */
+/******************************************************************************/
+typedef struct _AT91S_EMAC
+{
AT91_REG EMAC_CTL; /* Network Control Register */
AT91_REG EMAC_CFG; /* Network Configuration Register */
AT91_REG EMAC_SR; /* Network Status Register */
} AT91S_EMAC, *AT91PS_EMAC;
/* -------- EMAC_CTL : (EMAC Offset: 0x0) -------- */
-#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */
-#define AT91C_EMAC_LBL ((unsigned int) 0x1 << 1) /* (EMAC) Loopback local. */
-#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) /* (EMAC) Receive enable. */
-#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) /* (EMAC) Transmit enable. */
-#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) /* (EMAC) Management port enable. */
-#define AT91C_EMAC_CSR ((unsigned int) 0x1 << 5) /* (EMAC) Clear statistics registers. */
-#define AT91C_EMAC_ISR ((unsigned int) 0x1 << 6) /* (EMAC) Increment statistics registers. */
-#define AT91C_EMAC_WES ((unsigned int) 0x1 << 7) /* (EMAC) Write enable for statistics registers. */
-#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) /* (EMAC) Back pressure. */
+#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */
+#define AT91C_EMAC_LBL ((unsigned int) 0x1 << 1) /* (EMAC) Loopback local. */
+#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) /* (EMAC) Receive enable. */
+#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) /* (EMAC) Transmit enable. */
+#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) /* (EMAC) Management port enable. */
+#define AT91C_EMAC_CSR ((unsigned int) 0x1 << 5) /* (EMAC) Clear statistics registers. */
+#define AT91C_EMAC_ISR ((unsigned int) 0x1 << 6) /* (EMAC) Increment statistics registers. */
+#define AT91C_EMAC_WES ((unsigned int) 0x1 << 7) /* (EMAC) Write enable for statistics registers. */
+#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) /* (EMAC) Back pressure. */
+
/* -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- */
-#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) /* (EMAC) Speed. */
-#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) /* (EMAC) Full duplex. */
-#define AT91C_EMAC_BR ((unsigned int) 0x1 << 2) /* (EMAC) Bit rate. */
-#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) /* (EMAC) Copy all frames. */
-#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) /* (EMAC) No broadcast. */
-#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) /* (EMAC) Multicast hash enable */
-#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) /* (EMAC) Unicast hash enable. */
-#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) /* (EMAC) Receive 1522 bytes. */
-#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) /* (EMAC) External address match enable. */
-#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) /* (EMAC) */
-#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) /* (EMAC) HCLK divided by 8 */
-#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) /* (EMAC) HCLK divided by 16 */
-#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) /* (EMAC) HCLK divided by 32 */
-#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) /* (EMAC) HCLK divided by 64 */
-#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) /* (EMAC) */
-#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 13) /* (EMAC) */
+#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) /* (EMAC) Speed. */
+#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) /* (EMAC) Full duplex. */
+#define AT91C_EMAC_BR ((unsigned int) 0x1 << 2) /* (EMAC) Bit rate. */
+#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) /* (EMAC) Copy all frames. */
+#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) /* (EMAC) No broadcast. */
+#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) /* (EMAC) Multicast hash enable */
+#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) /* (EMAC) Unicast hash enable. */
+#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) /* (EMAC) Receive 1522 bytes. */
+#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) /* (EMAC) External address match enable. */
+#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) /* (EMAC) */
+#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) /* (EMAC) HCLK divided by 8 */
+#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) /* (EMAC) HCLK divided by 16 */
+#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) /* (EMAC) HCLK divided by 32 */
+#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) /* (EMAC) HCLK divided by 64 */
+#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) /* (EMAC) */
+#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 13) /* (EMAC) */
+
/* -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- */
-#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) /* (EMAC) */
-#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) /* (EMAC) */
+#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) /* (EMAC) */
+#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) /* (EMAC) */
+
/* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- */
-#define AT91C_EMAC_LEN ((unsigned int) 0x7FF << 0) /* (EMAC) */
-#define AT91C_EMAC_NCRC ((unsigned int) 0x1 << 15) /* (EMAC) */
+#define AT91C_EMAC_LEN ((unsigned int) 0x7FF << 0) /* (EMAC) */
+#define AT91C_EMAC_NCRC ((unsigned int) 0x1 << 15) /* (EMAC) */
+
/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- */
-#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 0) /* (EMAC) */
-#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) /* (EMAC) */
-#define AT91C_EMAC_RLE ((unsigned int) 0x1 << 2) /* (EMAC) */
-#define AT91C_EMAC_TXIDLE ((unsigned int) 0x1 << 3) /* (EMAC) */
-#define AT91C_EMAC_BNQ ((unsigned int) 0x1 << 4) /* (EMAC) */
-#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) /* (EMAC) */
-#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) /* (EMAC) */
+#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 0) /* (EMAC) */
+#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) /* (EMAC) */
+#define AT91C_EMAC_RLE ((unsigned int) 0x1 << 2) /* (EMAC) */
+#define AT91C_EMAC_TXIDLE ((unsigned int) 0x1 << 3) /* (EMAC) */
+#define AT91C_EMAC_BNQ ((unsigned int) 0x1 << 4) /* (EMAC) */
+#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) /* (EMAC) */
+#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) /* (EMAC) */
+
/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
-#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) /* (EMAC) */
-#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */
-#define AT91C_EMAC_RSR_OVR ((unsigned int) 0x1 << 2) /* (EMAC) */
+#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) /* (EMAC) */
+#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */
+#define AT91C_EMAC_RSR_OVR ((unsigned int) 0x1 << 2) /* (EMAC) */
+
/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
-#define AT91C_EMAC_DONE ((unsigned int) 0x1 << 0) /* (EMAC) */
-#define AT91C_EMAC_RCOM ((unsigned int) 0x1 << 1) /* (EMAC) */
-#define AT91C_EMAC_RBNA ((unsigned int) 0x1 << 2) /* (EMAC) */
-#define AT91C_EMAC_TOVR ((unsigned int) 0x1 << 3) /* (EMAC) */
-#define AT91C_EMAC_TUND ((unsigned int) 0x1 << 4) /* (EMAC) */
-#define AT91C_EMAC_RTRY ((unsigned int) 0x1 << 5) /* (EMAC) */
-#define AT91C_EMAC_TBRE ((unsigned int) 0x1 << 6) /* (EMAC) */
-#define AT91C_EMAC_TCOM ((unsigned int) 0x1 << 7) /* (EMAC) */
-#define AT91C_EMAC_TIDLE ((unsigned int) 0x1 << 8) /* (EMAC) */
-#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) /* (EMAC) */
-#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) /* (EMAC) */
-#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) /* (EMAC) */
+#define AT91C_EMAC_DONE ((unsigned int) 0x1 << 0) /* (EMAC) */
+#define AT91C_EMAC_RCOM ((unsigned int) 0x1 << 1) /* (EMAC) */
+#define AT91C_EMAC_RBNA ((unsigned int) 0x1 << 2) /* (EMAC) */
+#define AT91C_EMAC_TOVR ((unsigned int) 0x1 << 3) /* (EMAC) */
+#define AT91C_EMAC_TUND ((unsigned int) 0x1 << 4) /* (EMAC) */
+#define AT91C_EMAC_RTRY ((unsigned int) 0x1 << 5) /* (EMAC) */
+#define AT91C_EMAC_TBRE ((unsigned int) 0x1 << 6) /* (EMAC) */
+#define AT91C_EMAC_TCOM ((unsigned int) 0x1 << 7) /* (EMAC) */
+#define AT91C_EMAC_TIDLE ((unsigned int) 0x1 << 8) /* (EMAC) */
+#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) /* (EMAC) */
+#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) /* (EMAC) */
+#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) /* (EMAC) */
+
/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */
/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
-#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) /* (EMAC) */
-#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) /* (EMAC) */
-#define AT91C_EMAC_CODE_802_3 ((unsigned int) 0x2 << 16) /* (EMAC) Write Operation */
-#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) /* (EMAC) */
-#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) /* (EMAC) */
-#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) /* (EMAC) */
-#define AT91C_EMAC_RW_R ((unsigned int) 0x2 << 28) /* (EMAC) Read Operation */
-#define AT91C_EMAC_RW_W ((unsigned int) 0x1 << 28) /* (EMAC) Write Operation */
-#define AT91C_EMAC_HIGH ((unsigned int) 0x1 << 30) /* (EMAC) */
-#define AT91C_EMAC_LOW ((unsigned int) 0x1 << 31) /* (EMAC) */
-
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_SPI {
+#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) /* (EMAC) */
+#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) /* (EMAC) */
+#define AT91C_EMAC_CODE_802_3 ((unsigned int) 0x2 << 16) /* (EMAC) Write Operation */
+#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) /* (EMAC) */
+#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) /* (EMAC) */
+#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) /* (EMAC) */
+#define AT91C_EMAC_RW_R ((unsigned int) 0x2 << 28) /* (EMAC) Read Operation */
+#define AT91C_EMAC_RW_W ((unsigned int) 0x1 << 28) /* (EMAC) Write Operation */
+#define AT91C_EMAC_HIGH ((unsigned int) 0x1 << 30) /* (EMAC) */
+#define AT91C_EMAC_LOW ((unsigned int) 0x1 << 31) /* (EMAC) */
+
+/******************************************************************************/
+/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */
+/******************************************************************************/
+typedef struct _AT91S_SPI
+{
AT91_REG SPI_CR; /* Control Register */
AT91_REG SPI_MR; /* Mode Register */
AT91_REG SPI_RDR; /* Receive Data Register */
} AT91S_SPI, *AT91PS_SPI;
/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
-#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) /* (SPI) SPI Enable */
-#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) /* (SPI) SPI Disable */
-#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) /* (SPI) SPI Software reset */
+#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) /* (SPI) SPI Enable */
+#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) /* (SPI) SPI Disable */
+#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) /* (SPI) SPI Software reset */
+
/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
-#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) /* (SPI) Master/Slave Mode */
-#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) /* (SPI) Peripheral Select */
-#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) /* (SPI) Fixed Peripheral Select */
-#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) /* (SPI) Variable Peripheral Select */
-#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) /* (SPI) Chip Select Decode */
-#define AT91C_SPI_DIV32 ((unsigned int) 0x1 << 3) /* (SPI) Clock Selection */
-#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) /* (SPI) Mode Fault Detection */
-#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) /* (SPI) Clock Selection */
-#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select */
-#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Chip Selects */
+#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) /* (SPI) Master/Slave Mode */
+#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) /* (SPI) Peripheral Select */
+#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) /* (SPI) Fixed Peripheral Select */
+#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) /* (SPI) Variable Peripheral Select */
+#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) /* (SPI) Chip Select Decode */
+#define AT91C_SPI_DIV32 ((unsigned int) 0x1 << 3) /* (SPI) Clock Selection */
+#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) /* (SPI) Mode Fault Detection */
+#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) /* (SPI) Clock Selection */
+#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select */
+#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Chip Selects */
+
/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
-#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) /* (SPI) Receive Data */
-#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */
+#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) /* (SPI) Receive Data */
+#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */
+
/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
-#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) /* (SPI) Transmit Data */
-#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */
+#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) /* (SPI) Transmit Data */
+#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */
+
/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
-#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) /* (SPI) Receive Data Register Full */
-#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) /* (SPI) Transmit Data Register Empty */
-#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) /* (SPI) Mode Fault Error */
-#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) /* (SPI) Overrun Error Status */
-#define AT91C_SPI_SPENDRX ((unsigned int) 0x1 << 4) /* (SPI) End of Receiver Transfer */
-#define AT91C_SPI_SPENDTX ((unsigned int) 0x1 << 5) /* (SPI) End of Receiver Transfer */
-#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) /* (SPI) RXBUFF Interrupt */
-#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) /* (SPI) TXBUFE Interrupt */
-#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) /* (SPI) Enable Status */
+#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) /* (SPI) Receive Data Register Full */
+#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) /* (SPI) Transmit Data Register Empty */
+#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) /* (SPI) Mode Fault Error */
+#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) /* (SPI) Overrun Error Status */
+#define AT91C_SPI_SPENDRX ((unsigned int) 0x1 << 4) /* (SPI) End of Receiver Transfer */
+#define AT91C_SPI_SPENDTX ((unsigned int) 0x1 << 5) /* (SPI) End of Receiver Transfer */
+#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) /* (SPI) RXBUFF Interrupt */
+#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) /* (SPI) TXBUFE Interrupt */
+#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) /* (SPI) Enable Status */
+
/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
-#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) /* (SPI) Clock Polarity */
-#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) /* (SPI) Clock Phase */
-#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) /* (SPI) Bits Per Transfer */
-#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) /* (SPI) 8 Bits Per transfer */
-#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) /* (SPI) 9 Bits Per transfer */
-#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) /* (SPI) 10 Bits Per transfer */
-#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) /* (SPI) 11 Bits Per transfer */
-#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) /* (SPI) 12 Bits Per transfer */
-#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) /* (SPI) 13 Bits Per transfer */
-#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) /* (SPI) 14 Bits Per transfer */
-#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) /* (SPI) 15 Bits Per transfer */
-#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) /* (SPI) 16 Bits Per transfer */
-#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) /* (SPI) Serial Clock Baud Rate */
-#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) /* (SPI) Serial Clock Baud Rate */
-#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Consecutive Transfers */
-
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */
-/* ***************************************************************************** */
-typedef struct _AT91S_PDC {
+#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) /* (SPI) Clock Polarity */
+#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) /* (SPI) Clock Phase */
+#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) /* (SPI) Bits Per Transfer */
+#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) /* (SPI) 8 Bits Per transfer */
+#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) /* (SPI) 9 Bits Per transfer */
+#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) /* (SPI) 10 Bits Per transfer */
+#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) /* (SPI) 11 Bits Per transfer */
+#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) /* (SPI) 12 Bits Per transfer */
+#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) /* (SPI) 13 Bits Per transfer */
+#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) /* (SPI) 14 Bits Per transfer */
+#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) /* (SPI) 15 Bits Per transfer */
+#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) /* (SPI) 16 Bits Per transfer */
+#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) /* (SPI) Serial Clock Baud Rate */
+#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) /* (SPI) Serial Clock Baud Rate */
+#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Consecutive Transfers */
+
+/******************************************************************************/
+/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */
+/******************************************************************************/
+typedef struct _AT91S_PDC
+{
AT91_REG PDC_RPR; /* Receive Pointer Register */
AT91_REG PDC_RCR; /* Receive Counter Register */
AT91_REG PDC_TPR; /* Transmit Pointer Register */
} AT91S_PDC, *AT91PS_PDC;
/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
-#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) /* (PDC) Receiver Transfer Enable */
-#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) /* (PDC) Receiver Transfer Disable */
-#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) /* (PDC) Transmitter Transfer Enable */
-#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) /* (PDC) Transmitter Transfer Disable */
+#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) /* (PDC) Receiver Transfer Enable */
+#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) /* (PDC) Receiver Transfer Disable */
+#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) /* (PDC) Transmitter Transfer Enable */
+#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) /* (PDC) Transmitter Transfer Disable */
/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */
/* ========== Register definition ==================================== */
-#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) /* (SPI) Chip Select Register */
-#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) /* (PMC) Peripheral Clock Enable Register */
-#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) /* (PIOA) PIO Enable Register */
-#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) /* (PIOA) PIO Disable Register */
-#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) /* (PIOA) PIO Status Register */
-#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) /* (PIOA) PIO Output Enable Register */
-#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) /* (PIOA) PIO Output Disable Register */
-#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) /* (PIOA) PIO Output Status Register */
-#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) /* (PIOA) PIO Glitch Input Filter Enable Register */
-#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) /* (PIOA) PIO Glitch Input Filter Disable Register */
-#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) /* (PIOA) PIO Glitch Input Filter Status Register */
-#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) /* (PIOA) PIO Set Output Data Register */
-#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) /* (PIOA) PIO Clear Output Data Register */
-#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) /* (PIOA) PIO Output Data Status Register */
-#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) /* (PIOA) PIO Pin Data Status Register */
-#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) /* (PIOA) PIO Interrupt Enable Register */
-#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) /* (PIOA) PIO Interrupt Disable Register */
-#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) /* (PIOA) PIO Interrupt Mask Register */
-#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) /* (PIOA) PIO Interrupt Status Register */
-#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) /* (PIOA) PIO Multi-drive Enable Register */
-#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) /* (PIOA) PIO Multi-drive Disable Register */
-#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) /* (PIOA) PIO Multi-drive Status Register */
-#define AT91C_PIOA_PUDR ((AT91_REG *) 0xFFFFF460) /* (PIOA) PIO Pull-up Disable Register */
-#define AT91C_PIOA_PUER ((AT91_REG *) 0xFFFFF464) /* (PIOA) PIO Pull-up Enable Register */
-#define AT91C_PIOA_PUSR ((AT91_REG *) 0xFFFFF468) /* (PIOA) PIO Pull-up Status Register */
-#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) /* (PIOA) PIO Peripheral A Select Register */
-#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) /* (PIOA) PIO Peripheral B Select Register */
-#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) /* (PIOA) PIO Peripheral AB Select Register */
-#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) /* (PIOA) PIO Output Write Enable Register */
-#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) /* (PIOA) PIO Output Write Disable Register */
-#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) /* (PIOA) PIO Output Write Status Register */
-#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */
-
-#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) /* Pin Controlled by PA30 */
-#define AT91C_PIO_PC0 ((unsigned int) 1 << 0) /* Pin Controlled by PC0 */
-#define AT91C_PC0_BFCK ((unsigned int) AT91C_PIO_PC0) /* Burst Flash Clock */
-#define AT91C_PA30_DRXD ((unsigned int) AT91C_PIO_PA30) /* DBGU Debug Receive Data */
-#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) /* Pin Controlled by PA31 */
+#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) /* (SPI) Chip Select Register */
+#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) /* (PMC) Peripheral Clock Enable Register */
+#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) /* (PMC) Peripheral Clock Enable Register */
+#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) /* (PMC) Peripheral Clock Enable Register */
+#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) /* (PMC) Peripheral Clock Enable Register */
+#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) /* (PIOA) PIO Enable Register */
+#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) /* (PIOA) PIO Disable Register */
+#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) /* (PIOA) PIO Status Register */
+#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) /* (PIOA) PIO Output Enable Register */
+#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) /* (PIOA) PIO Output Disable Register */
+#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) /* (PIOA) PIO Output Status Register */
+#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) /* (PIOA) PIO Glitch Input Filter Enable Register */
+#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) /* (PIOA) PIO Glitch Input Filter Disable Register */
+#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) /* (PIOA) PIO Glitch Input Filter Status Register */
+#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) /* (PIOA) PIO Set Output Data Register */
+#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) /* (PIOA) PIO Clear Output Data Register */
+#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) /* (PIOA) PIO Output Data Status Register */
+#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) /* (PIOA) PIO Pin Data Status Register */
+#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) /* (PIOA) PIO Interrupt Enable Register */
+#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) /* (PIOA) PIO Interrupt Disable Register */
+#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) /* (PIOA) PIO Interrupt Mask Register */
+#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) /* (PIOA) PIO Interrupt Status Register */
+#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) /* (PIOA) PIO Multi-drive Enable Register */
+#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) /* (PIOA) PIO Multi-drive Disable Register */
+#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) /* (PIOA) PIO Multi-drive Status Register */
+#define AT91C_PIOA_PUDR ((AT91_REG *) 0xFFFFF460) /* (PIOA) PIO Pull-up Disable Register */
+#define AT91C_PIOA_PUER ((AT91_REG *) 0xFFFFF464) /* (PIOA) PIO Pull-up Enable Register */
+#define AT91C_PIOA_PUSR ((AT91_REG *) 0xFFFFF468) /* (PIOA) PIO Pull-up Status Register */
+#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) /* (PIOA) PIO Peripheral A Select Register */
+#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) /* (PIOA) PIO Peripheral B Select Register */
+#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) /* (PIOA) PIO Peripheral AB Select Register */
+#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) /* (PIOA) PIO Output Write Enable Register */
+#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) /* (PIOA) PIO Output Write Disable Register */
+#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) /* (PIOA) PIO Output Write Status Register */
+#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */
+
+#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) /* Pin Controlled by PA30 */
+#define AT91C_PIO_PC0 ((unsigned int) 1 << 0) /* Pin Controlled by PC0 */
+#define AT91C_PC0_BFCK ((unsigned int) AT91C_PIO_PC0) /* Burst Flash Clock */
+#define AT91C_PA30_DRXD ((unsigned int) AT91C_PIO_PA30) /* DBGU Debug Receive Data */
+#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) /* Pin Controlled by PA31 */
#define AT91C_PA25_TWD ((unsigned int) 1 << 25)
#define AT91C_PA26_TWCK ((unsigned int) 1 << 26)
-#define AT91C_PA31_DTXD ((unsigned int) AT91C_PIO_PA31) /* DBGU Debug Transmit Data */
-#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) /* Pin Controlled by PA17 */
-#define AT91C_PA17_TXD0 AT91C_PIO_PA17 /* USART0 Transmit Data */
-#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) /* Pin Controlled by PA18 */
-#define AT91C_PA18_RXD0 AT91C_PIO_PA18 /* USART0 Receive Data */
-#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) /* Pin Controlled by PB20 */
-#define AT91C_PB20_RXD1 AT91C_PIO_PB20 /* USART1 Receive Data */
-#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) /* Pin Controlled by PB21 */
-#define AT91C_PB21_TXD1 AT91C_PIO_PB21 /* USART1 Transmit Data */
-
-#define AT91C_ID_SYS ((unsigned int) 1) /* System Peripheral */
-#define AT91C_ID_PIOA ((unsigned int) 2) /* PIO port A */
-#define AT91C_ID_PIOB ((unsigned int) 3) /* PIO port B */
-#define AT91C_ID_PIOC ((unsigned int) 4) /* PIO port C */
-#define AT91C_ID_USART0 ((unsigned int) 6) /* USART 0 */
-#define AT91C_ID_USART1 ((unsigned int) 7) /* USART 1 */
-#define AT91C_ID_TWI ((unsigned int) 12) /* Two Wire Interface */
-#define AT91C_ID_SPI ((unsigned int) 13) /* Serial Peripheral Interface */
-#define AT91C_ID_TC0 ((unsigned int) 17) /* Timer Counter 0 */
-#define AT91C_ID_EMAC ((unsigned int) 24) /* Ethernet MAC */
-
-#define AT91C_PIO_PC1 ((unsigned int) 1 << 1) /* Pin Controlled by PC1 */
-#define AT91C_PC1_BFRDY_SMOE ((unsigned int) AT91C_PIO_PC1) /* Burst Flash Ready */
-#define AT91C_PIO_PC3 ((unsigned int) 1 << 3) /* Pin Controlled by PC3 */
-#define AT91C_PC3_BFBAA_SMWE ((unsigned int) AT91C_PIO_PC3) /* Burst Flash Address Advance / SmartMedia Write Enable */
-#define AT91C_PIO_PC2 ((unsigned int) 1 << 2) /* Pin Controlled by PC2 */
-#define AT91C_PC2_BFAVD ((unsigned int) AT91C_PIO_PC2) /* Burst Flash Address Valid */
-#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) /* Pin Controlled by PB1 */
-
-#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) /* Pin Controlled by PA23 */
-#define AT91C_PA23_TXD2 ((unsigned int) AT91C_PIO_PA23) /* USART 2 Transmit Data */
-
-#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) /* Pin Controlled by PA0 */
-#define AT91C_PA0_MISO ((unsigned int) AT91C_PIO_PA0) /* SPI Master In Slave */
-#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) /* Pin Controlled by PA1 */
-#define AT91C_PA1_MOSI ((unsigned int) AT91C_PIO_PA1) /* SPI Master Out Slave */
-#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) /* Pin Controlled by PA2 */
-#define AT91C_PA2_SPCK ((unsigned int) AT91C_PIO_PA2) /* SPI Serial Clock */
-#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) /* Pin Controlled by PA3 */
-#define AT91C_PA3_NPCS0 ((unsigned int) AT91C_PIO_PA3) /* SPI Peripheral Chip Select 0 */
-#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) /* Pin Controlled by PA4 */
-#define AT91C_PA4_NPCS1 ((unsigned int) AT91C_PIO_PA4) /* SPI Peripheral Chip Select 1 */
-#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) /* Pin Controlled by PA5 */
-#define AT91C_PA5_NPCS2 ((unsigned int) AT91C_PIO_PA5) /* SPI Peripheral Chip Select 2 */
-#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) /* Pin Controlled by PA6 */
-#define AT91C_PA6_NPCS3 ((unsigned int) AT91C_PIO_PA6) /* SPI Peripheral Chip Select 3 */
-
-
-#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) /* Pin Controlled by PA16 */
-#define AT91C_PA16_EMDIO ((unsigned int) AT91C_PIO_PA16) /* Ethernet MAC Management Data Input/Output */
-#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) /* Pin Controlled by PA15 */
-#define AT91C_PA15_EMDC ((unsigned int) AT91C_PIO_PA15) /* Ethernet MAC Management Data Clock */
-#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) /* Pin Controlled by PA14 */
-#define AT91C_PA14_ERXER ((unsigned int) AT91C_PIO_PA14) /* Ethernet MAC Receive Error */
-#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) /* Pin Controlled by PA13 */
-#define AT91C_PA13_ERX1 ((unsigned int) AT91C_PIO_PA13) /* Ethernet MAC Receive Data 1 */
-#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) /* Pin Controlled by PA12 */
-#define AT91C_PA12_ERX0 ((unsigned int) AT91C_PIO_PA12) /* Ethernet MAC Receive Data 0 */
-#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) /* Pin Controlled by PA11 */
-#define AT91C_PA11_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PA11) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */
-#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) /* Pin Controlled by PA10 */
-#define AT91C_PA10_ETX1 ((unsigned int) AT91C_PIO_PA10) /* Ethernet MAC Transmit Data 1 */
-#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) /* Pin Controlled by PA9 */
-#define AT91C_PA9_ETX0 ((unsigned int) AT91C_PIO_PA9) /* Ethernet MAC Transmit Data 0 */
-#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) /* Pin Controlled by PA8 */
-#define AT91C_PA8_ETXEN ((unsigned int) AT91C_PIO_PA8) /* Ethernet MAC Transmit Enable */
-#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) /* Pin Controlled by PA7 */
-#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) /* Ethernet MAC Transmit Clock/Reference Clock */
-
-#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) /* Pin Controlled by PB7 */
-#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) /* Pin Controlled by PB7 */
-#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) /* Pin Controlled by PB7 */
-#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB7 */
-#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) /* Pin Controlled by PB7 */
-#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */
-#define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */
-#define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) /* Ethernet MAC Force 100 Mbits */
-#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) /* Pin Controlled by PB19 */
-#define AT91C_PB19_DTR1 ((unsigned int) AT91C_PIO_PB19) /* USART 1 Data Terminal ready */
-#define AT91C_PB19_ERXCK ((unsigned int) AT91C_PIO_PB19) /* Ethernet MAC Receive Clock */
-#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) /* Pin Controlled by PB18 */
-#define AT91C_PB18_RI1 ((unsigned int) AT91C_PIO_PB18) /* USART 1 Ring Indicator */
-#define AT91C_PB18_ECOL ((unsigned int) AT91C_PIO_PB18) /* Ethernet MAC Collision Detected */
-#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) /* Pin Controlled by PB17 */
-#define AT91C_PB17_RF2 ((unsigned int) AT91C_PIO_PB17) /* SSC Receive Frame Sync 2 */
-#define AT91C_PB17_ERXDV ((unsigned int) AT91C_PIO_PB17) /* Ethernet MAC Receive Data Valid */
-#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) /* Pin Controlled by PB16 */
-#define AT91C_PB16_RK2 ((unsigned int) AT91C_PIO_PB16) /* SSC Receive Clock 2 */
-#define AT91C_PB16_ERX3 ((unsigned int) AT91C_PIO_PB16) /* Ethernet MAC Receive Data 3 */
-#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) /* Pin Controlled by PB15 */
-#define AT91C_PB15_RD2 ((unsigned int) AT91C_PIO_PB15) /* SSC Receive Data 2 */
-#define AT91C_PB15_ERX2 ((unsigned int) AT91C_PIO_PB15) /* Ethernet MAC Receive Data 2 */
-#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) /* Pin Controlled by PB14 */
-#define AT91C_PB14_TD2 ((unsigned int) AT91C_PIO_PB14) /* SSC Transmit Data 2 */
-#define AT91C_PB14_ETXER ((unsigned int) AT91C_PIO_PB14) /* Ethernet MAC Transmikt Coding Error */
-#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) /* Pin Controlled by PB13 */
-#define AT91C_PB13_TK2 ((unsigned int) AT91C_PIO_PB13) /* SSC Transmit Clock 2 */
-#define AT91C_PB13_ETX3 ((unsigned int) AT91C_PIO_PB13) /* Ethernet MAC Transmit Data 3 */
-#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) /* Pin Controlled by PB12 */
-#define AT91C_PB12_TF2 ((unsigned int) AT91C_PIO_PB12) /* SSC Transmit Frame Sync 2 */
-#define AT91C_PB12_ETX2 ((unsigned int) AT91C_PIO_PB12) /* Ethernet MAC Transmit Data 2 */
-
-#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) /* (PIOB) Select B Register */
-#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */
-
-#define AT91C_EBI_CS3A_SMC_SmartMedia ((unsigned int) 0x1 << 3) /* (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. */
-#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */
-#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */
-#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */
-#define AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) /* (PIOC) Select A Register */
-#define AT91C_PIOC_SODR ((AT91_REG *) 0xFFFFF830) /* (PIOC) Set Output Data Register */
-#define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) /* (PIOC) Clear Output Data Register */
-#define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) /* (PIOC) Pin Data Status Register */
-
-#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) /* (SPI) Base Address */
-#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */
-#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) /* (PMC) Base Address */
-#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) /* (TC0) Base Address */
-#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */
-#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) /* (CKGR) Base Address */
-#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) /* (PIOC) Base Address */
-#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) /* (PIOB) Base Address */
-#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) /* (PIOA) Base Address */
-#define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) /* (EBI) Chip Select Assignment Register */
-#define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) /* (SMC2) Base Address */
-#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) /* (US0) Base Address */
-#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */
-#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) /* (TCB0) TC Block Mode Register */
-#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) /* (TCB0) TC Block Control Register */
-#define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) /* (PIOC) PIO Disable Register */
-#define AT91C_PIOC_PER ((AT91_REG *) 0xFFFFF800) /* (PIOC) PIO Enable Register */
-#define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) /* (PIOC) Output Disable Registerr */
-#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) /* (PIOB) PIO Enable Register */
-#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) /* (PIOB) Output Disable Registerr */
-#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) /* (PIOB) Pin Data Status Register */
+#define AT91C_PA31_DTXD ((unsigned int) AT91C_PIO_PA31) /* DBGU Debug Transmit Data */
+#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) /* Pin Controlled by PA17 */
+#define AT91C_PA17_TXD0 AT91C_PIO_PA17 /* USART0 Transmit Data */
+#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) /* Pin Controlled by PA18 */
+#define AT91C_PA18_RXD0 AT91C_PIO_PA18 /* USART0 Receive Data */
+#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) /* Pin Controlled by PB20 */
+#define AT91C_PB20_RXD1 AT91C_PIO_PB20 /* USART1 Receive Data */
+#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) /* Pin Controlled by PB21 */
+#define AT91C_PB21_TXD1 AT91C_PIO_PB21 /* USART1 Transmit Data */
+
+#define AT91C_ID_SYS ((unsigned int) 1) /* System Peripheral */
+#define AT91C_ID_PIOA ((unsigned int) 2) /* PIO port A */
+#define AT91C_ID_PIOB ((unsigned int) 3) /* PIO port B */
+#define AT91C_ID_PIOC ((unsigned int) 4) /* PIO port C */
+#define AT91C_ID_USART0 ((unsigned int) 6) /* USART 0 */
+#define AT91C_ID_USART1 ((unsigned int) 7) /* USART 1 */
+#define AT91C_ID_TWI ((unsigned int) 12) /* Two Wire Interface */
+#define AT91C_ID_SPI ((unsigned int) 13) /* Serial Peripheral Interface */
+#define AT91C_ID_TC0 ((unsigned int) 17) /* Timer Counter 0 */
+#define AT91C_ID_UHP ((unsigned int) 23) /* OHCI USB Host Port */
+#define AT91C_ID_EMAC ((unsigned int) 24) /* Ethernet MAC */
+
+#define AT91C_PIO_PC1 ((unsigned int) 1 << 1) /* Pin Controlled by PC1 */
+#define AT91C_PC1_BFRDY_SMOE ((unsigned int) AT91C_PIO_PC1) /* Burst Flash Ready */
+#define AT91C_PIO_PC3 ((unsigned int) 1 << 3) /* Pin Controlled by PC3 */
+#define AT91C_PC3_BFBAA_SMWE ((unsigned int) AT91C_PIO_PC3) /* Burst Flash Address Advance / SmartMedia Write Enable */
+#define AT91C_PIO_PC2 ((unsigned int) 1 << 2) /* Pin Controlled by PC2 */
+#define AT91C_PC2_BFAVD ((unsigned int) AT91C_PIO_PC2) /* Burst Flash Address Valid */
+#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) /* Pin Controlled by PB1 */
+
+#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) /* Pin Controlled by PA23 */
+#define AT91C_PA23_TXD2 ((unsigned int) AT91C_PIO_PA23) /* USART 2 Transmit Data */
+
+#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) /* Pin Controlled by PA0 */
+#define AT91C_PA0_MISO ((unsigned int) AT91C_PIO_PA0) /* SPI Master In Slave */
+#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) /* Pin Controlled by PA1 */
+#define AT91C_PA1_MOSI ((unsigned int) AT91C_PIO_PA1) /* SPI Master Out Slave */
+#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) /* Pin Controlled by PA2 */
+#define AT91C_PA2_SPCK ((unsigned int) AT91C_PIO_PA2) /* SPI Serial Clock */
+#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) /* Pin Controlled by PA3 */
+#define AT91C_PA3_NPCS0 ((unsigned int) AT91C_PIO_PA3) /* SPI Peripheral Chip Select 0 */
+#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) /* Pin Controlled by PA4 */
+#define AT91C_PA4_NPCS1 ((unsigned int) AT91C_PIO_PA4) /* SPI Peripheral Chip Select 1 */
+#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) /* Pin Controlled by PA5 */
+#define AT91C_PA5_NPCS2 ((unsigned int) AT91C_PIO_PA5) /* SPI Peripheral Chip Select 2 */
+#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) /* Pin Controlled by PA6 */
+#define AT91C_PA6_NPCS3 ((unsigned int) AT91C_PIO_PA6) /* SPI Peripheral Chip Select 3 */
+
+#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) /* Pin Controlled by PA16 */
+#define AT91C_PA16_EMDIO ((unsigned int) AT91C_PIO_PA16) /* Ethernet MAC Management Data Input/Output */
+#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) /* Pin Controlled by PA15 */
+#define AT91C_PA15_EMDC ((unsigned int) AT91C_PIO_PA15) /* Ethernet MAC Management Data Clock */
+#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) /* Pin Controlled by PA14 */
+#define AT91C_PA14_ERXER ((unsigned int) AT91C_PIO_PA14) /* Ethernet MAC Receive Error */
+#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) /* Pin Controlled by PA13 */
+#define AT91C_PA13_ERX1 ((unsigned int) AT91C_PIO_PA13) /* Ethernet MAC Receive Data 1 */
+#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) /* Pin Controlled by PA12 */
+#define AT91C_PA12_ERX0 ((unsigned int) AT91C_PIO_PA12) /* Ethernet MAC Receive Data 0 */
+#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) /* Pin Controlled by PA11 */
+#define AT91C_PA11_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PA11) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */
+#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) /* Pin Controlled by PA10 */
+#define AT91C_PA10_ETX1 ((unsigned int) AT91C_PIO_PA10) /* Ethernet MAC Transmit Data 1 */
+#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) /* Pin Controlled by PA9 */
+#define AT91C_PA9_ETX0 ((unsigned int) AT91C_PIO_PA9) /* Ethernet MAC Transmit Data 0 */
+#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) /* Pin Controlled by PA8 */
+#define AT91C_PA8_ETXEN ((unsigned int) AT91C_PIO_PA8) /* Ethernet MAC Transmit Enable */
+#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) /* Pin Controlled by PA7 */
+#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) /* Ethernet MAC Transmit Clock/Reference Clock */
+
+#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) /* Pin Controlled by PB3 */
+#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) /* Pin Controlled by PB4 */
+#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) /* Pin Controlled by PB5 */
+#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB6 */
+#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) /* Pin Controlled by PB7 */
+#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */
+#define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */
+#define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) /* Ethernet MAC Force 100 Mbits */
+#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) /* Pin Controlled by PB19 */
+#define AT91C_PB19_DTR1 ((unsigned int) AT91C_PIO_PB19) /* USART 1 Data Terminal ready */
+#define AT91C_PB19_ERXCK ((unsigned int) AT91C_PIO_PB19) /* Ethernet MAC Receive Clock */
+#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) /* Pin Controlled by PB18 */
+#define AT91C_PB18_RI1 ((unsigned int) AT91C_PIO_PB18) /* USART 1 Ring Indicator */
+#define AT91C_PB18_ECOL ((unsigned int) AT91C_PIO_PB18) /* Ethernet MAC Collision Detected */
+#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) /* Pin Controlled by PB17 */
+#define AT91C_PB17_RF2 ((unsigned int) AT91C_PIO_PB17) /* SSC Receive Frame Sync 2 */
+#define AT91C_PB17_ERXDV ((unsigned int) AT91C_PIO_PB17) /* Ethernet MAC Receive Data Valid */
+#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) /* Pin Controlled by PB16 */
+#define AT91C_PB16_RK2 ((unsigned int) AT91C_PIO_PB16) /* SSC Receive Clock 2 */
+#define AT91C_PB16_ERX3 ((unsigned int) AT91C_PIO_PB16) /* Ethernet MAC Receive Data 3 */
+#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) /* Pin Controlled by PB15 */
+#define AT91C_PB15_RD2 ((unsigned int) AT91C_PIO_PB15) /* SSC Receive Data 2 */
+#define AT91C_PB15_ERX2 ((unsigned int) AT91C_PIO_PB15) /* Ethernet MAC Receive Data 2 */
+#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) /* Pin Controlled by PB14 */
+#define AT91C_PB14_TD2 ((unsigned int) AT91C_PIO_PB14) /* SSC Transmit Data 2 */
+#define AT91C_PB14_ETXER ((unsigned int) AT91C_PIO_PB14) /* Ethernet MAC Transmikt Coding Error */
+#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) /* Pin Controlled by PB13 */
+#define AT91C_PB13_TK2 ((unsigned int) AT91C_PIO_PB13) /* SSC Transmit Clock 2 */
+#define AT91C_PB13_ETX3 ((unsigned int) AT91C_PIO_PB13) /* Ethernet MAC Transmit Data 3 */
+#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) /* Pin Controlled by PB12 */
+#define AT91C_PB12_TF2 ((unsigned int) AT91C_PIO_PB12) /* SSC Transmit Frame Sync 2 */
+#define AT91C_PB12_ETX2 ((unsigned int) AT91C_PIO_PB12) /* Ethernet MAC Transmit Data 2 */
+
+#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) /* (PIOB) Select B Register */
+#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */
+
+#define AT91C_EBI_CS3A_SMC_SmartMedia ((unsigned int) 0x1 << 3) /* (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. */
+#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */
+#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */
+#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */
+#define AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) /* (PIOC) Select A Register */
+#define AT91C_PIOC_SODR ((AT91_REG *) 0xFFFFF830) /* (PIOC) Set Output Data Register */
+#define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) /* (PIOC) Clear Output Data Register */
+#define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) /* (PIOC) Pin Data Status Register */
+
+#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) /* (SPI) Base Address */
+#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */
+#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) /* (PMC) Base Address */
+#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) /* (TC0) Base Address */
+#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */
+#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) /* (CKGR) Base Address */
+#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) /* (PIOC) Base Address */
+#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) /* (PIOB) Base Address */
+#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) /* (PIOA) Base Address */
+#define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) /* (EBI) Chip Select Assignment Register */
+#define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) /* (SMC2) Base Address */
+#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) /* (US0) Base Address */
+#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */
+#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) /* (TCB0) TC Block Mode Register */
+#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) /* (TCB0) TC Block Control Register */
+#define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) /* (PIOC) PIO Disable Register */
+#define AT91C_PIOC_PER ((AT91_REG *) 0xFFFFF800) /* (PIOC) PIO Enable Register */
+#define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) /* (PIOC) Output Disable Registerr */
+#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) /* (PIOB) PIO Enable Register */
+#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) /* (PIOB) Output Disable Registerr */
+#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) /* (PIOB) Pin Data Status Register */
#endif
#define AT91_TCB1_BASE 0xFFFA4000 /*16K */
#define AT91_TCB0_BASE 0xFFFA0000 /*16K */
+#define AT91_USB_HOST_BASE 0x00300000
+
/*
* Where in virtual memory the IO devices (timers, system controllers
* and so on)
/*
- * This was automagically generated from mach-types!
+ * This was automagically generated from arch/arm/tools/mach-types!
* Do NOT edit
*/
#define MACH_TYPE_PNP1110 215
#define MACH_TYPE_CSB226 216
#define MACH_TYPE_ARNOLD 217
-#define MACH_TYPE_PSIBOARD 218
+#define MACH_TYPE_VOICEBLUE 218
#define MACH_TYPE_JZ8028 219
#define MACH_TYPE_H5400 220
#define MACH_TYPE_FORTE 221
#define MACH_TYPE_PDB 239
#define MACH_TYPE_BLUE_2G 240
#define MACH_TYPE_BLUEARCH 241
-#define MACH_TYPE_IXDB2400 242
-#define MACH_TYPE_IXDB2800 243
+#define MACH_TYPE_IXDP2400 242
+#define MACH_TYPE_IXDP2800 243
#define MACH_TYPE_EXPLORER 244
#define MACH_TYPE_IXDP425 245
#define MACH_TYPE_CHIMP 246
#define MACH_TYPE_XAENIAX 585
#define MACH_TYPE_SOMN4250 586
#define MACH_TYPE_PLEB2 587
-#define MACH_TYPE_CWL 588
-#define MACH_TYPE_GD 589
+#define MACH_TYPE_CORNWALLIS 588
+#define MACH_TYPE_GURNEY_DRV 589
#define MACH_TYPE_CHAFFEE 590
#define MACH_TYPE_RMS101 591
#define MACH_TYPE_RX3715 592
#define MACH_TYPE_RMS100 611
#define MACH_TYPE_KB9200 612
#define MACH_TYPE_SX1 613
+#define MACH_TYPE_HMS39C7092 614
+#define MACH_TYPE_ARMADILLO 615
+#define MACH_TYPE_IPCU 616
+#define MACH_TYPE_LOOX720 617
+#define MACH_TYPE_IXDP465 618
+#define MACH_TYPE_IXDP2351 619
+#define MACH_TYPE_ADSVIX 620
+#define MACH_TYPE_DM270 621
+#define MACH_TYPE_SOCLTPLUS 622
+#define MACH_TYPE_ECIA 623
+#define MACH_TYPE_CM4008 624
+#define MACH_TYPE_P2001 625
+#define MACH_TYPE_TWISTER 626
+#define MACH_TYPE_MUDSHARK 627
+#define MACH_TYPE_HB2 628
+#define MACH_TYPE_IQ80332 629
+#define MACH_TYPE_SENDT 630
+#define MACH_TYPE_MX2JAZZ 631
+#define MACH_TYPE_MULTIIO 632
+#define MACH_TYPE_HRDISPLAY 633
+#define MACH_TYPE_SCMA11BB 634
+#define MACH_TYPE_TRIZEPS3 635
+#define MACH_TYPE_ZEFEERDZA 636
+#define MACH_TYPE_ZEFEERDZB 637
+#define MACH_TYPE_ZEFEERDZG 638
+#define MACH_TYPE_ZEFEERDZN 639
+#define MACH_TYPE_ZEFEERDZQ 640
+#define MACH_TYPE_GTWX5715 641
+#define MACH_TYPE_ASTRO_JACK 643
+#define MACH_TYPE_TIP03 644
+#define MACH_TYPE_A9200EC 645
+#define MACH_TYPE_PNX0105 646
+#define MACH_TYPE_ADCPOECPU 647
+#define MACH_TYPE_CSB637 648
+#define MACH_TYPE_ML69Q6203 649
+#define MACH_TYPE_MB9200 650
+#define MACH_TYPE_KULUN 651
+#define MACH_TYPE_SNAPPER 652
+#define MACH_TYPE_OPTIMA 653
+#define MACH_TYPE_DLHSBC 654
+#define MACH_TYPE_X30 655
+#define MACH_TYPE_N30 656
+#define MACH_TYPE_MANGA_KS8695 657
+#define MACH_TYPE_AJAX 658
+#define MACH_TYPE_NEC_MP900 659
+#define MACH_TYPE_VVTK1000 661
+#define MACH_TYPE_KAFA 662
+#define MACH_TYPE_VVTK3000 663
+#define MACH_TYPE_PIMX1 664
+#define MACH_TYPE_OLLIE 665
+#define MACH_TYPE_SKYMAX 666
+#define MACH_TYPE_JAZZ 667
+#define MACH_TYPE_TEL_T3 668
+#define MACH_TYPE_AISINO_FCR255 669
+#define MACH_TYPE_BTWEB 670
+#define MACH_TYPE_DBG_LH79520 671
+#define MACH_TYPE_CM41XX 672
+#define MACH_TYPE_TS72XX 673
+#define MACH_TYPE_NGGPXA 674
+#define MACH_TYPE_CSB535 675
+#define MACH_TYPE_CSB536 676
+#define MACH_TYPE_PXA_TRAKPOD 677
+#define MACH_TYPE_PRAXIS 678
+#define MACH_TYPE_LH75411 679
+#define MACH_TYPE_OTOM 680
+#define MACH_TYPE_NEXCODER_2440 681
+#define MACH_TYPE_LOOX410 682
+#define MACH_TYPE_WESTLAKE 683
+#define MACH_TYPE_NSB 684
+#define MACH_TYPE_ESL_SARVA_STN 685
+#define MACH_TYPE_ESL_SARVA_TFT 686
+#define MACH_TYPE_ESL_SARVA_IAD 687
+#define MACH_TYPE_ESL_SARVA_ACC 688
+#define MACH_TYPE_TYPHOON 689
+#define MACH_TYPE_CNAV 690
+#define MACH_TYPE_A730 691
+#define MACH_TYPE_NETSTAR 692
+#define MACH_TYPE_PHASEFALE_SUPERCON 693
+#define MACH_TYPE_SHIVA1100 694
+#define MACH_TYPE_ETEXSC 695
+#define MACH_TYPE_IXDPG465 696
+#define MACH_TYPE_A9M2410 697
+#define MACH_TYPE_A9M2440 698
+#define MACH_TYPE_A9M9750 699
+#define MACH_TYPE_A9M9360 700
+#define MACH_TYPE_UNC90 701
+#define MACH_TYPE_ECO920 702
+#define MACH_TYPE_SATVIEW 703
+#define MACH_TYPE_ROADRUNNER 704
+#define MACH_TYPE_AT91RM9200EK 705
+#define MACH_TYPE_GP32 706
+#define MACH_TYPE_GEM 707
+#define MACH_TYPE_I858 708
+#define MACH_TYPE_HX2750 709
+#define MACH_TYPE_ZEUSEVB 710
+#define MACH_TYPE_P700 711
+#define MACH_TYPE_CPE 712
+#define MACH_TYPE_SPITZ 713
+#define MACH_TYPE_NIMBRA340 714
+#define MACH_TYPE_LPC22XX 715
+#define MACH_TYPE_COMET3 716
+#define MACH_TYPE_COMET4 717
+#define MACH_TYPE_CSB625 718
+#define MACH_TYPE_FORTUNET2 719
+#define MACH_TYPE_S5H2200 720
+#define MACH_TYPE_OPTORM920 721
+#define MACH_TYPE_ADSBITSYXB 722
+#define MACH_TYPE_ADSSPHERE 723
+#define MACH_TYPE_ADSPORTAL 724
+#define MACH_TYPE_LN2410SBC 725
+#define MACH_TYPE_CB3RUFC 726
+#define MACH_TYPE_MP2USB 727
#ifdef CONFIG_ARCH_EBSA110
# ifdef machine_arch_type
# define machine_is_arnold() (0)
#endif
-#ifdef CONFIG_SA1100_PSIBOARD
+#ifdef CONFIG_MACH_VOICEBLUE
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_PSIBOARD
+# define machine_arch_type MACH_TYPE_VOICEBLUE
# endif
-# define machine_is_psiboard() (machine_arch_type == MACH_TYPE_PSIBOARD)
+# define machine_is_voiceblue() (machine_arch_type == MACH_TYPE_VOICEBLUE)
#else
-# define machine_is_psiboard() (0)
+# define machine_is_voiceblue() (0)
#endif
#ifdef CONFIG_ARCH_JZ8028
# define machine_is_bluearch() (0)
#endif
-#ifdef CONFIG_ARCH_IXDB2400
+#ifdef CONFIG_ARCH_IXDP2400
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_IXDB2400
+# define machine_arch_type MACH_TYPE_IXDP2400
# endif
-# define machine_is_ixdp2400() (machine_arch_type == MACH_TYPE_IXDB2400)
+# define machine_is_ixdp2400() (machine_arch_type == MACH_TYPE_IXDP2400)
#else
# define machine_is_ixdp2400() (0)
#endif
-#ifdef CONFIG_ARCH_IXDB2800
+#ifdef CONFIG_ARCH_IXDP2800
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_IXDB2800
+# define machine_arch_type MACH_TYPE_IXDP2800
# endif
-# define machine_is_ixdp2800() (machine_arch_type == MACH_TYPE_IXDB2800)
+# define machine_is_ixdp2800() (machine_arch_type == MACH_TYPE_IXDP2800)
#else
# define machine_is_ixdp2800() (0)
#endif
# else
# define machine_arch_type MACH_TYPE_GUMSTIK
# endif
-# define machine_is_gumstik() (machine_arch_type == MACH_TYPE_GUMSTIK)
+# define machine_is_gumstix() (machine_arch_type == MACH_TYPE_GUMSTIK)
#else
-# define machine_is_gumstik() (0)
+# define machine_is_gumstix() (0)
#endif
#ifdef CONFIG_ARCH_RCUBE
# define machine_is_pleb2() (0)
#endif
-#ifdef CONFIG_MACH_CWL
+#ifdef CONFIG_MACH_CORNWALLIS
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_CWL
+# define machine_arch_type MACH_TYPE_CORNWALLIS
# endif
-# define machine_is_cwl() (machine_arch_type == MACH_TYPE_CWL)
+# define machine_is_cornwallis() (machine_arch_type == MACH_TYPE_CORNWALLIS)
#else
-# define machine_is_cwl() (0)
+# define machine_is_cornwallis() (0)
#endif
-#ifdef CONFIG_MACH_GD
+#ifdef CONFIG_MACH_GURNEY_DRV
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_GD
+# define machine_arch_type MACH_TYPE_GURNEY_DRV
# endif
-# define machine_is_gd() (machine_arch_type == MACH_TYPE_GD)
+# define machine_is_gurney_drv() (machine_arch_type == MACH_TYPE_GURNEY_DRV)
#else
-# define machine_is_gd() (0)
+# define machine_is_gurney_drv() (0)
#endif
#ifdef CONFIG_MACH_CHAFFEE
# define machine_is_sx1() (0)
#endif
+#ifdef CONFIG_MACH_HMS39C7092
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HMS39C7092
+# endif
+# define machine_is_hms39c7092() (machine_arch_type == MACH_TYPE_HMS39C7092)
+#else
+# define machine_is_hms39c7092() (0)
+#endif
+
+#ifdef CONFIG_MACH_ARMADILLO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ARMADILLO
+# endif
+# define machine_is_armadillo() (machine_arch_type == MACH_TYPE_ARMADILLO)
+#else
+# define machine_is_armadillo() (0)
+#endif
+
+#ifdef CONFIG_MACH_IPCU
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_IPCU
+# endif
+# define machine_is_ipcu() (machine_arch_type == MACH_TYPE_IPCU)
+#else
+# define machine_is_ipcu() (0)
+#endif
+
+#ifdef CONFIG_MACH_LOOX720
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LOOX720
+# endif
+# define machine_is_loox720() (machine_arch_type == MACH_TYPE_LOOX720)
+#else
+# define machine_is_loox720() (0)
+#endif
+
+#ifdef CONFIG_MACH_IXDP465
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_IXDP465
+# endif
+# define machine_is_ixdp465() (machine_arch_type == MACH_TYPE_IXDP465)
+#else
+# define machine_is_ixdp465() (0)
+#endif
+
+#ifdef CONFIG_MACH_IXDP2351
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_IXDP2351
+# endif
+# define machine_is_ixdp2351() (machine_arch_type == MACH_TYPE_IXDP2351)
+#else
+# define machine_is_ixdp2351() (0)
+#endif
+
+#ifdef CONFIG_MACH_ADSVIX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ADSVIX
+# endif
+# define machine_is_adsvix() (machine_arch_type == MACH_TYPE_ADSVIX)
+#else
+# define machine_is_adsvix() (0)
+#endif
+
+#ifdef CONFIG_MACH_DM270
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DM270
+# endif
+# define machine_is_dm270() (machine_arch_type == MACH_TYPE_DM270)
+#else
+# define machine_is_dm270() (0)
+#endif
+
+#ifdef CONFIG_MACH_SOCLTPLUS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SOCLTPLUS
+# endif
+# define machine_is_socltplus() (machine_arch_type == MACH_TYPE_SOCLTPLUS)
+#else
+# define machine_is_socltplus() (0)
+#endif
+
+#ifdef CONFIG_MACH_ECIA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ECIA
+# endif
+# define machine_is_ecia() (machine_arch_type == MACH_TYPE_ECIA)
+#else
+# define machine_is_ecia() (0)
+#endif
+
+#ifdef CONFIG_MACH_CM4008
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CM4008
+# endif
+# define machine_is_cm4008() (machine_arch_type == MACH_TYPE_CM4008)
+#else
+# define machine_is_cm4008() (0)
+#endif
+
+#ifdef CONFIG_MACH_P2001
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_P2001
+# endif
+# define machine_is_p2001() (machine_arch_type == MACH_TYPE_P2001)
+#else
+# define machine_is_p2001() (0)
+#endif
+
+#ifdef CONFIG_MACH_TWISTER
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TWISTER
+# endif
+# define machine_is_twister() (machine_arch_type == MACH_TYPE_TWISTER)
+#else
+# define machine_is_twister() (0)
+#endif
+
+#ifdef CONFIG_MACH_MUDSHARK
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MUDSHARK
+# endif
+# define machine_is_mudshark() (machine_arch_type == MACH_TYPE_MUDSHARK)
+#else
+# define machine_is_mudshark() (0)
+#endif
+
+#ifdef CONFIG_MACH_HB2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HB2
+# endif
+# define machine_is_hb2() (machine_arch_type == MACH_TYPE_HB2)
+#else
+# define machine_is_hb2() (0)
+#endif
+
+#ifdef CONFIG_MACH_IQ80332
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_IQ80332
+# endif
+# define machine_is_iq80332() (machine_arch_type == MACH_TYPE_IQ80332)
+#else
+# define machine_is_iq80332() (0)
+#endif
+
+#ifdef CONFIG_MACH_SENDT
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SENDT
+# endif
+# define machine_is_sendt() (machine_arch_type == MACH_TYPE_SENDT)
+#else
+# define machine_is_sendt() (0)
+#endif
+
+#ifdef CONFIG_MACH_MX2JAZZ
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MX2JAZZ
+# endif
+# define machine_is_mx2jazz() (machine_arch_type == MACH_TYPE_MX2JAZZ)
+#else
+# define machine_is_mx2jazz() (0)
+#endif
+
+#ifdef CONFIG_MACH_MULTIIO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MULTIIO
+# endif
+# define machine_is_multiio() (machine_arch_type == MACH_TYPE_MULTIIO)
+#else
+# define machine_is_multiio() (0)
+#endif
+
+#ifdef CONFIG_MACH_HRDISPLAY
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HRDISPLAY
+# endif
+# define machine_is_hrdisplay() (machine_arch_type == MACH_TYPE_HRDISPLAY)
+#else
+# define machine_is_hrdisplay() (0)
+#endif
+
+#ifdef CONFIG_MACH_SCMA11BB
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SCMA11BB
+# endif
+# define machine_is_scma11bb() (machine_arch_type == MACH_TYPE_SCMA11BB)
+#else
+# define machine_is_scma11bb() (0)
+#endif
+
+#ifdef CONFIG_MACH_TRIZEPS3
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TRIZEPS3
+# endif
+# define machine_is_trizeps3() (machine_arch_type == MACH_TYPE_TRIZEPS3)
+#else
+# define machine_is_trizeps3() (0)
+#endif
+
+#ifdef CONFIG_MACH_ZEFEERDZA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ZEFEERDZA
+# endif
+# define machine_is_zefeerdza() (machine_arch_type == MACH_TYPE_ZEFEERDZA)
+#else
+# define machine_is_zefeerdza() (0)
+#endif
+
+#ifdef CONFIG_MACH_ZEFEERDZB
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ZEFEERDZB
+# endif
+# define machine_is_zefeerdzb() (machine_arch_type == MACH_TYPE_ZEFEERDZB)
+#else
+# define machine_is_zefeerdzb() (0)
+#endif
+
+#ifdef CONFIG_MACH_ZEFEERDZG
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ZEFEERDZG
+# endif
+# define machine_is_zefeerdzg() (machine_arch_type == MACH_TYPE_ZEFEERDZG)
+#else
+# define machine_is_zefeerdzg() (0)
+#endif
+
+#ifdef CONFIG_MACH_ZEFEERDZN
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ZEFEERDZN
+# endif
+# define machine_is_zefeerdzn() (machine_arch_type == MACH_TYPE_ZEFEERDZN)
+#else
+# define machine_is_zefeerdzn() (0)
+#endif
+
+#ifdef CONFIG_MACH_ZEFEERDZQ
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ZEFEERDZQ
+# endif
+# define machine_is_zefeerdzq() (machine_arch_type == MACH_TYPE_ZEFEERDZQ)
+#else
+# define machine_is_zefeerdzq() (0)
+#endif
+
+#ifdef CONFIG_MACH_GTWX5715
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_GTWX5715
+# endif
+# define machine_is_gtwx5715() (machine_arch_type == MACH_TYPE_GTWX5715)
+#else
+# define machine_is_gtwx5715() (0)
+#endif
+
+#ifdef CONFIG_MACH_ASTRO_JACK
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ASTRO_JACK
+# endif
+# define machine_is_astro_jack() (machine_arch_type == MACH_TYPE_ASTRO_JACK)
+#else
+# define machine_is_astro_jack() (0)
+#endif
+
+#ifdef CONFIG_MACH_TIP03
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TIP03
+# endif
+# define machine_is_tip03() (machine_arch_type == MACH_TYPE_TIP03)
+#else
+# define machine_is_tip03() (0)
+#endif
+
+#ifdef CONFIG_MACH_A9200EC
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_A9200EC
+# endif
+# define machine_is_a9200ec() (machine_arch_type == MACH_TYPE_A9200EC)
+#else
+# define machine_is_a9200ec() (0)
+#endif
+
+#ifdef CONFIG_MACH_PNX0105
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PNX0105
+# endif
+# define machine_is_pnx0105() (machine_arch_type == MACH_TYPE_PNX0105)
+#else
+# define machine_is_pnx0105() (0)
+#endif
+
+#ifdef CONFIG_MACH_ADCPOECPU
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ADCPOECPU
+# endif
+# define machine_is_adcpoecpu() (machine_arch_type == MACH_TYPE_ADCPOECPU)
+#else
+# define machine_is_adcpoecpu() (0)
+#endif
+
+#ifdef CONFIG_MACH_CSB637
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CSB637
+# endif
+# define machine_is_csb637() (machine_arch_type == MACH_TYPE_CSB637)
+#else
+# define machine_is_csb637() (0)
+#endif
+
+#ifdef CONFIG_MACH_ML69Q6203
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ML69Q6203
+# endif
+# define machine_is_ml69q6203() (machine_arch_type == MACH_TYPE_ML69Q6203)
+#else
+# define machine_is_ml69q6203() (0)
+#endif
+
+#ifdef CONFIG_MACH_MB9200
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MB9200
+# endif
+# define machine_is_mb9200() (machine_arch_type == MACH_TYPE_MB9200)
+#else
+# define machine_is_mb9200() (0)
+#endif
+
+#ifdef CONFIG_MACH_KULUN
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_KULUN
+# endif
+# define machine_is_kulun() (machine_arch_type == MACH_TYPE_KULUN)
+#else
+# define machine_is_kulun() (0)
+#endif
+
+#ifdef CONFIG_MACH_SNAPPER
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SNAPPER
+# endif
+# define machine_is_snapper() (machine_arch_type == MACH_TYPE_SNAPPER)
+#else
+# define machine_is_snapper() (0)
+#endif
+
+#ifdef CONFIG_MACH_OPTIMA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OPTIMA
+# endif
+# define machine_is_optima() (machine_arch_type == MACH_TYPE_OPTIMA)
+#else
+# define machine_is_optima() (0)
+#endif
+
+#ifdef CONFIG_MACH_DLHSBC
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DLHSBC
+# endif
+# define machine_is_dlhsbc() (machine_arch_type == MACH_TYPE_DLHSBC)
+#else
+# define machine_is_dlhsbc() (0)
+#endif
+
+#ifdef CONFIG_MACH_X30
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_X30
+# endif
+# define machine_is_x30() (machine_arch_type == MACH_TYPE_X30)
+#else
+# define machine_is_x30() (0)
+#endif
+
+#ifdef CONFIG_MACH_N30
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_N30
+# endif
+# define machine_is_n30() (machine_arch_type == MACH_TYPE_N30)
+#else
+# define machine_is_n30() (0)
+#endif
+
+#ifdef CONFIG_MACH_MANGA_KS8695
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MANGA_KS8695
+# endif
+# define machine_is_manga_ks8695() (machine_arch_type == MACH_TYPE_MANGA_KS8695)
+#else
+# define machine_is_manga_ks8695() (0)
+#endif
+
+#ifdef CONFIG_MACH_AJAX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AJAX
+# endif
+# define machine_is_ajax() (machine_arch_type == MACH_TYPE_AJAX)
+#else
+# define machine_is_ajax() (0)
+#endif
+
+#ifdef CONFIG_MACH_NEC_MP900
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NEC_MP900
+# endif
+# define machine_is_nec_mp900() (machine_arch_type == MACH_TYPE_NEC_MP900)
+#else
+# define machine_is_nec_mp900() (0)
+#endif
+
+#ifdef CONFIG_MACH_VVTK1000
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VVTK1000
+# endif
+# define machine_is_vvtk1000() (machine_arch_type == MACH_TYPE_VVTK1000)
+#else
+# define machine_is_vvtk1000() (0)
+#endif
+
+#ifdef CONFIG_MACH_KAFA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_KAFA
+# endif
+# define machine_is_kafa() (machine_arch_type == MACH_TYPE_KAFA)
+#else
+# define machine_is_kafa() (0)
+#endif
+
+#ifdef CONFIG_MACH_VVTK3000
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VVTK3000
+# endif
+# define machine_is_vvtk3000() (machine_arch_type == MACH_TYPE_VVTK3000)
+#else
+# define machine_is_vvtk3000() (0)
+#endif
+
+#ifdef CONFIG_MACH_PIMX1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PIMX1
+# endif
+# define machine_is_pimx1() (machine_arch_type == MACH_TYPE_PIMX1)
+#else
+# define machine_is_pimx1() (0)
+#endif
+
+#ifdef CONFIG_MACH_OLLIE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OLLIE
+# endif
+# define machine_is_ollie() (machine_arch_type == MACH_TYPE_OLLIE)
+#else
+# define machine_is_ollie() (0)
+#endif
+
+#ifdef CONFIG_MACH_SKYMAX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SKYMAX
+# endif
+# define machine_is_skymax() (machine_arch_type == MACH_TYPE_SKYMAX)
+#else
+# define machine_is_skymax() (0)
+#endif
+
+#ifdef CONFIG_MACH_JAZZ
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_JAZZ
+# endif
+# define machine_is_jazz() (machine_arch_type == MACH_TYPE_JAZZ)
+#else
+# define machine_is_jazz() (0)
+#endif
+
+#ifdef CONFIG_MACH_TEL_T3
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TEL_T3
+# endif
+# define machine_is_tel_t3() (machine_arch_type == MACH_TYPE_TEL_T3)
+#else
+# define machine_is_tel_t3() (0)
+#endif
+
+#ifdef CONFIG_MACH_AISINO_FCR255
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AISINO_FCR255
+# endif
+# define machine_is_aisino_fcr255() (machine_arch_type == MACH_TYPE_AISINO_FCR255)
+#else
+# define machine_is_aisino_fcr255() (0)
+#endif
+
+#ifdef CONFIG_MACH_BTWEB
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BTWEB
+# endif
+# define machine_is_btweb() (machine_arch_type == MACH_TYPE_BTWEB)
+#else
+# define machine_is_btweb() (0)
+#endif
+
+#ifdef CONFIG_MACH_DBG_LH79520
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DBG_LH79520
+# endif
+# define machine_is_dbg_lh79520() (machine_arch_type == MACH_TYPE_DBG_LH79520)
+#else
+# define machine_is_dbg_lh79520() (0)
+#endif
+
+#ifdef CONFIG_MACH_CM41XX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CM41XX
+# endif
+# define machine_is_cm41xx() (machine_arch_type == MACH_TYPE_CM41XX)
+#else
+# define machine_is_cm41xx() (0)
+#endif
+
+#ifdef CONFIG_MACH_TS72XX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TS72XX
+# endif
+# define machine_is_ts72xx() (machine_arch_type == MACH_TYPE_TS72XX)
+#else
+# define machine_is_ts72xx() (0)
+#endif
+
+#ifdef CONFIG_MACH_NGGPXA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NGGPXA
+# endif
+# define machine_is_nggpxa() (machine_arch_type == MACH_TYPE_NGGPXA)
+#else
+# define machine_is_nggpxa() (0)
+#endif
+
+#ifdef CONFIG_MACH_CSB535
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CSB535
+# endif
+# define machine_is_csb535() (machine_arch_type == MACH_TYPE_CSB535)
+#else
+# define machine_is_csb535() (0)
+#endif
+
+#ifdef CONFIG_MACH_CSB536
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CSB536
+# endif
+# define machine_is_csb536() (machine_arch_type == MACH_TYPE_CSB536)
+#else
+# define machine_is_csb536() (0)
+#endif
+
+#ifdef CONFIG_MACH_PXA_TRAKPOD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PXA_TRAKPOD
+# endif
+# define machine_is_pxa_trakpod() (machine_arch_type == MACH_TYPE_PXA_TRAKPOD)
+#else
+# define machine_is_pxa_trakpod() (0)
+#endif
+
+#ifdef CONFIG_MACH_PRAXIS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PRAXIS
+# endif
+# define machine_is_praxis() (machine_arch_type == MACH_TYPE_PRAXIS)
+#else
+# define machine_is_praxis() (0)
+#endif
+
+#ifdef CONFIG_MACH_LH75411
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LH75411
+# endif
+# define machine_is_lh75411() (machine_arch_type == MACH_TYPE_LH75411)
+#else
+# define machine_is_lh75411() (0)
+#endif
+
+#ifdef CONFIG_MACH_OTOM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OTOM
+# endif
+# define machine_is_otom() (machine_arch_type == MACH_TYPE_OTOM)
+#else
+# define machine_is_otom() (0)
+#endif
+
+#ifdef CONFIG_MACH_NEXCODER_2440
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NEXCODER_2440
+# endif
+# define machine_is_nexcoder_2440() (machine_arch_type == MACH_TYPE_NEXCODER_2440)
+#else
+# define machine_is_nexcoder_2440() (0)
+#endif
+
+#ifdef CONFIG_MACH_LOOX410
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LOOX410
+# endif
+# define machine_is_loox410() (machine_arch_type == MACH_TYPE_LOOX410)
+#else
+# define machine_is_loox410() (0)
+#endif
+
+#ifdef CONFIG_MACH_WESTLAKE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_WESTLAKE
+# endif
+# define machine_is_westlake() (machine_arch_type == MACH_TYPE_WESTLAKE)
+#else
+# define machine_is_westlake() (0)
+#endif
+
+#ifdef CONFIG_MACH_NSB
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NSB
+# endif
+# define machine_is_nsb() (machine_arch_type == MACH_TYPE_NSB)
+#else
+# define machine_is_nsb() (0)
+#endif
+
+#ifdef CONFIG_MACH_ESL_SARVA_STN
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ESL_SARVA_STN
+# endif
+# define machine_is_esl_sarva_stn() (machine_arch_type == MACH_TYPE_ESL_SARVA_STN)
+#else
+# define machine_is_esl_sarva_stn() (0)
+#endif
+
+#ifdef CONFIG_MACH_ESL_SARVA_TFT
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ESL_SARVA_TFT
+# endif
+# define machine_is_esl_sarva_tft() (machine_arch_type == MACH_TYPE_ESL_SARVA_TFT)
+#else
+# define machine_is_esl_sarva_tft() (0)
+#endif
+
+#ifdef CONFIG_MACH_ESL_SARVA_IAD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ESL_SARVA_IAD
+# endif
+# define machine_is_esl_sarva_iad() (machine_arch_type == MACH_TYPE_ESL_SARVA_IAD)
+#else
+# define machine_is_esl_sarva_iad() (0)
+#endif
+
+#ifdef CONFIG_MACH_ESL_SARVA_ACC
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ESL_SARVA_ACC
+# endif
+# define machine_is_esl_sarva_acc() (machine_arch_type == MACH_TYPE_ESL_SARVA_ACC)
+#else
+# define machine_is_esl_sarva_acc() (0)
+#endif
+
+#ifdef CONFIG_MACH_TYPHOON
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TYPHOON
+# endif
+# define machine_is_typhoon() (machine_arch_type == MACH_TYPE_TYPHOON)
+#else
+# define machine_is_typhoon() (0)
+#endif
+
+#ifdef CONFIG_MACH_CNAV
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CNAV
+# endif
+# define machine_is_cnav() (machine_arch_type == MACH_TYPE_CNAV)
+#else
+# define machine_is_cnav() (0)
+#endif
+
+#ifdef CONFIG_MACH_A730
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_A730
+# endif
+# define machine_is_a730() (machine_arch_type == MACH_TYPE_A730)
+#else
+# define machine_is_a730() (0)
+#endif
+
+#ifdef CONFIG_MACH_NETSTAR
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NETSTAR
+# endif
+# define machine_is_netstar() (machine_arch_type == MACH_TYPE_NETSTAR)
+#else
+# define machine_is_netstar() (0)
+#endif
+
+#ifdef CONFIG_MACH_PHASEFALE_SUPERCON
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PHASEFALE_SUPERCON
+# endif
+# define machine_is_supercon() (machine_arch_type == MACH_TYPE_PHASEFALE_SUPERCON)
+#else
+# define machine_is_supercon() (0)
+#endif
+
+#ifdef CONFIG_MACH_SHIVA1100
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SHIVA1100
+# endif
+# define machine_is_shiva1100() (machine_arch_type == MACH_TYPE_SHIVA1100)
+#else
+# define machine_is_shiva1100() (0)
+#endif
+
+#ifdef CONFIG_MACH_ETEXSC
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ETEXSC
+# endif
+# define machine_is_etexsc() (machine_arch_type == MACH_TYPE_ETEXSC)
+#else
+# define machine_is_etexsc() (0)
+#endif
+
+#ifdef CONFIG_MACH_IXDPG465
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_IXDPG465
+# endif
+# define machine_is_ixdpg465() (machine_arch_type == MACH_TYPE_IXDPG465)
+#else
+# define machine_is_ixdpg465() (0)
+#endif
+
+#ifdef CONFIG_MACH_A9M2410
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_A9M2410
+# endif
+# define machine_is_a9m2410() (machine_arch_type == MACH_TYPE_A9M2410)
+#else
+# define machine_is_a9m2410() (0)
+#endif
+
+#ifdef CONFIG_MACH_A9M2440
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_A9M2440
+# endif
+# define machine_is_a9m2440() (machine_arch_type == MACH_TYPE_A9M2440)
+#else
+# define machine_is_a9m2440() (0)
+#endif
+
+#ifdef CONFIG_MACH_A9M9750
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_A9M9750
+# endif
+# define machine_is_a9m9750() (machine_arch_type == MACH_TYPE_A9M9750)
+#else
+# define machine_is_a9m9750() (0)
+#endif
+
+#ifdef CONFIG_MACH_A9M9360
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_A9M9360
+# endif
+# define machine_is_a9m9360() (machine_arch_type == MACH_TYPE_A9M9360)
+#else
+# define machine_is_a9m9360() (0)
+#endif
+
+#ifdef CONFIG_MACH_UNC90
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_UNC90
+# endif
+# define machine_is_unc90() (machine_arch_type == MACH_TYPE_UNC90)
+#else
+# define machine_is_unc90() (0)
+#endif
+
+#ifdef CONFIG_MACH_ECO920
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ECO920
+# endif
+# define machine_is_eco920() (machine_arch_type == MACH_TYPE_ECO920)
+#else
+# define machine_is_eco920() (0)
+#endif
+
+#ifdef CONFIG_MACH_SATVIEW
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SATVIEW
+# endif
+# define machine_is_satview() (machine_arch_type == MACH_TYPE_SATVIEW)
+#else
+# define machine_is_satview() (0)
+#endif
+
+#ifdef CONFIG_MACH_ROADRUNNER
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ROADRUNNER
+# endif
+# define machine_is_roadrunner() (machine_arch_type == MACH_TYPE_ROADRUNNER)
+#else
+# define machine_is_roadrunner() (0)
+#endif
+
+#ifdef CONFIG_MACH_AT91RM9200EK
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT91RM9200EK
+# endif
+# define machine_is_at91rm9200ek() (machine_arch_type == MACH_TYPE_AT91RM9200EK)
+#else
+# define machine_is_at91rm9200ek() (0)
+#endif
+
+#ifdef CONFIG_MACH_GP32
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_GP32
+# endif
+# define machine_is_gp32() (machine_arch_type == MACH_TYPE_GP32)
+#else
+# define machine_is_gp32() (0)
+#endif
+
+#ifdef CONFIG_MACH_GEM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_GEM
+# endif
+# define machine_is_gem() (machine_arch_type == MACH_TYPE_GEM)
+#else
+# define machine_is_gem() (0)
+#endif
+
+#ifdef CONFIG_MACH_I858
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_I858
+# endif
+# define machine_is_i858() (machine_arch_type == MACH_TYPE_I858)
+#else
+# define machine_is_i858() (0)
+#endif
+
+#ifdef CONFIG_MACH_HX2750
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HX2750
+# endif
+# define machine_is_hx2750() (machine_arch_type == MACH_TYPE_HX2750)
+#else
+# define machine_is_hx2750() (0)
+#endif
+
+#ifdef CONFIG_MACH_ZEUSEVB
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ZEUSEVB
+# endif
+# define machine_is_zeusevb() (machine_arch_type == MACH_TYPE_ZEUSEVB)
+#else
+# define machine_is_zeusevb() (0)
+#endif
+
+#ifdef CONFIG_MACH_P700
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_P700
+# endif
+# define machine_is_p700() (machine_arch_type == MACH_TYPE_P700)
+#else
+# define machine_is_p700() (0)
+#endif
+
+#ifdef CONFIG_MACH_CPE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CPE
+# endif
+# define machine_is_cpe() (machine_arch_type == MACH_TYPE_CPE)
+#else
+# define machine_is_cpe() (0)
+#endif
+
+#ifdef CONFIG_MACH_SPITZ
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SPITZ
+# endif
+# define machine_is_spitz() (machine_arch_type == MACH_TYPE_SPITZ)
+#else
+# define machine_is_spitz() (0)
+#endif
+
+#ifdef CONFIG_MACH_NIMBRA340
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NIMBRA340
+# endif
+# define machine_is_nimbra340() (machine_arch_type == MACH_TYPE_NIMBRA340)
+#else
+# define machine_is_nimbra340() (0)
+#endif
+
+#ifdef CONFIG_MACH_LPC22XX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LPC22XX
+# endif
+# define machine_is_lpc22xx() (machine_arch_type == MACH_TYPE_LPC22XX)
+#else
+# define machine_is_lpc22xx() (0)
+#endif
+
+#ifdef CONFIG_MACH_COMET3
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_COMET3
+# endif
+# define machine_is_omap_comet3() (machine_arch_type == MACH_TYPE_COMET3)
+#else
+# define machine_is_omap_comet3() (0)
+#endif
+
+#ifdef CONFIG_MACH_COMET4
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_COMET4
+# endif
+# define machine_is_omap_comet4() (machine_arch_type == MACH_TYPE_COMET4)
+#else
+# define machine_is_omap_comet4() (0)
+#endif
+
+#ifdef CONFIG_MACH_CSB625
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CSB625
+# endif
+# define machine_is_csb625() (machine_arch_type == MACH_TYPE_CSB625)
+#else
+# define machine_is_csb625() (0)
+#endif
+
+#ifdef CONFIG_MACH_FORTUNET2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_FORTUNET2
+# endif
+# define machine_is_fortunet2() (machine_arch_type == MACH_TYPE_FORTUNET2)
+#else
+# define machine_is_fortunet2() (0)
+#endif
+
+#ifdef CONFIG_MACH_S5H2200
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_S5H2200
+# endif
+# define machine_is_s5h2200() (machine_arch_type == MACH_TYPE_S5H2200)
+#else
+# define machine_is_s5h2200() (0)
+#endif
+
+#ifdef CONFIG_MACH_OPTORM920
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OPTORM920
+# endif
+# define machine_is_optorm920() (machine_arch_type == MACH_TYPE_OPTORM920)
+#else
+# define machine_is_optorm920() (0)
+#endif
+
+#ifdef CONFIG_MACH_ADSBITSYXB
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ADSBITSYXB
+# endif
+# define machine_is_adsbitsyxb() (machine_arch_type == MACH_TYPE_ADSBITSYXB)
+#else
+# define machine_is_adsbitsyxb() (0)
+#endif
+
+#ifdef CONFIG_MACH_ADSSPHERE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ADSSPHERE
+# endif
+# define machine_is_adssphere() (machine_arch_type == MACH_TYPE_ADSSPHERE)
+#else
+# define machine_is_adssphere() (0)
+#endif
+
+#ifdef CONFIG_MACH_ADSPORTAL
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ADSPORTAL
+# endif
+# define machine_is_adsportal() (machine_arch_type == MACH_TYPE_ADSPORTAL)
+#else
+# define machine_is_adsportal() (0)
+#endif
+
+#ifdef CONFIG_MACH_LN2410SBC
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LN2410SBC
+# endif
+# define machine_is_ln2410sbc() (machine_arch_type == MACH_TYPE_LN2410SBC)
+#else
+# define machine_is_ln2410sbc() (0)
+#endif
+
+#ifdef CONFIG_MACH_CB3RUFC
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CB3RUFC
+# endif
+# define machine_is_cb3rufc() (machine_arch_type == MACH_TYPE_CB3RUFC)
+#else
+# define machine_is_cb3rufc() (0)
+#endif
+
+#ifdef CONFIG_MACH_MP2USB
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MP2USB
+# endif
+# define machine_is_mp2usb() (machine_arch_type == MACH_TYPE_MP2USB)
+#else
+# define machine_is_mp2usb() (0)
+#endif
+
/*
* These have not yet been registered
*/
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
*/
#ifndef _U_BOOT_H_
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
*/
#ifndef _U_BOOT_H_
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
*/
#ifndef __U_BOOT_H__
*/
#ifndef __ASSEMBLY__
-#include <linux/types.h>
typedef struct bd_info {
unsigned long bi_memstart; /* start of DRAM memory */
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
*/
#ifndef _U_BOOT_H_
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
*/
#ifndef _U_BOOT_H_
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
*/
#ifndef _U_BOOT_H_
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
*/
#ifndef __ASM_NIOS2_U_BOOT_H_
# define __arch_swab16(x) ld_le16(&x)
# define __arch_swab32(x) ld_le32(&x)
#else
-static __inline__ __const__ __u16 ___arch__swab16(__u16 value)
+static __inline__ __attribute__((const)) __u16 ___arch__swab16(__u16 value)
{
__u16 result;
return result;
}
-static __inline__ __const__ __u32 ___arch__swab32(__u32 value)
+static __inline__ __attribute__((const)) __u32 ___arch__swab32(__u32 value)
{
__u32 result;
* downloading RAM microcode.
*/
#define CPM_DATAONLY_BASE ((uint)128)
+#define CPM_DP_NOSPACE ((uint)0x7FFFFFFF)
+#if defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000)
+#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
+#else /* MPC8540, MPC8560 */
+#define CPM_FCC_SPECIAL_BASE ((uint)0x0000B000)
#define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE)
-#define CPM_DP_NOSPACE ((uint)0x7fffffff)
-#define CPM_FCC_SPECIAL_BASE ((uint)0x0000b000)
+#endif
/* The number of pages of host memory we allocate for CPM. This is
* done early in kernel initialization to get physically contiguous
u32 lbiu_clk;
u32 lclk_clk;
u32 ddr_clk;
+ u32 pci_clk;
#endif
#if defined(CONFIG_MPC5xxx)
unsigned long ipb_clk;
#error CFG_I2C_OFFSET is not defined in /include/configs/${BOARD}.h
#endif
-#ifdef CONFIG_MPC8349ADS
+#if defined(CONFIG_MPC8349ADS) || defined(CONFIG_TQM834X)
/*
* MPC8349 have two i2c bus
*/
#define LAWBAR_BAR 0xFFFFF000
#define LAWBAR_RES ~(LAWBAR_BAR)
u32 ar; /* LBIU local access window attribute register */
-/*
- * This Macro were moved into mmu.h
- */
-#if 0
-/* 0 The local bus local access window n is disabled. 1 The local bus
- * local access window n is enabled and other LBLAWAR0 and LBLAWBAR0 fields
- * combine to identify an address range for this window.
- */
-#define LAWAR_EN 0x80000000
-/* Identifies the size of the window from the starting address. Window
- * size is 2^(SIZE+1) bytes. 000000\96001010Reserved. Window is
- * undefined.
- */
-#define LAWAR_SIZE 0x0000003F
-#define LAWAR_SIZE_4K 0x0000000B
-#define LAWAR_SIZE_8K 0x0000000C
-#define LAWAR_SIZE_16K 0x0000000D
-#define LAWAR_SIZE_32K 0x0000000E
-#define LAWAR_SIZE_64K 0x0000000F
-#define LAWAR_SIZE_128K 0x00000010
-#define LAWAR_SIZE_256K 0x00000011
-#define LAWAR_SIZE_512K 0x00000012
-#define LAWAR_SIZE_1M 0x00000013
-#define LAWAR_SIZE_2M 0x00000014
-#define LAWAR_SIZE_4M 0x00000015
-#define LAWAR_SIZE_8M 0x00000016
-#define LAWAR_SIZE_16M 0x00000017
-#define LAWAR_SIZE_32M 0x00000018
-#define LAWAR_SIZE_64M 0x00000019
-#define LAWAR_SIZE_128M 0x0000001A
-#define LAWAR_SIZE_256M 0x0000001B
-#define LAWAR_SIZE_512M 0x0000001C
-#define LAWAR_SIZE_1G 0x0000001D
-#define LAWAR_SIZE_2G 0x0000001E
-#define LAWAR_RES ~(LAWAR_EN|LAWAR_SIZE)
-#endif
-
} law8349_t;
/*
typedef struct ddr_cs_bnds{
u32 csbnds;
#define CSBNDS_SA 0x00FF0000
-#define CSBNDS_SA_SHIFT 16
+#define CSBNDS_SA_SHIFT 8
#define CSBNDS_EA 0x000000FF
-#define CSBNDS_EA_SHIFT 0
+#define CSBNDS_EA_SHIFT 24
u8 res0[4];
} ddr_cs_bnds_t;
#define TIMING_CFG1_ACTTOACT_SHIFT 4
#define TIMING_CFG1_WRTORD 0x00000007
#define TIMING_CFG1_WRTORD_SHIFT 0
+#define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */
+#define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */
u32 timing_cfg_2; /**< SDRAM Timing Configuration 2 */
#define TIMING_CFG2_CPO 0x0F000000
#define TIMING_CFG2_ACSM 0x00080000
#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
+#define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */
u32 sdram_cfg; /**< SDRAM Control Configuration */
#define SDRAM_CFG_MEM_EN 0x80000000
#define SDRAM_CFG_8_BE 0x00040000
#define SDRAM_CFG_NCAP 0x00020000
#define SDRAM_CFG_2T_EN 0x00008000
+#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000
u8 res2[4];
u32 sdram_mode; /**< SDRAM Mode Configuration */
#define SDRAM_MODE_ESD_SHIFT 16
#define SDRAM_MODE_SD 0x0000FFFF
#define SDRAM_MODE_SD_SHIFT 0
+#define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */
+#define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */
+#define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */
+#define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */
+#define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */
+#define DDR_MODE_WEAK 0x0002 /* weak drivers */
+#define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */
+#define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */
+#define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */
+#define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */
+#define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */
+#define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */
+#define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */
+#define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */
+#define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */
+#define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */
+#define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125 µs */
+#define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */
+#define DDR_MODE_MODEREG 0x0000 /* select mode register */
u8 res3[8];
u32 sdram_interval; /**< SDRAM Interval Configuration */
#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0
u8 res9[8];
u32 sdram_clk_cntl;
+#define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000
+
u8 res4[0xCCC];
u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */
u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */
--- /dev/null
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * MPC8xx I/O port pin manipulation functions
+ * Roughly based on iopin_8260.h
+ */
+
+#ifndef _ASM_IOPIN_8XX_H_
+#define _ASM_IOPIN_8XX_H_
+
+#include <linux/types.h>
+#include <asm/8xx_immap.h>
+
+#ifdef __KERNEL__
+
+typedef struct {
+ u_char port:2; /* port number (A=0, B=1, C=2, D=3) */
+ u_char pin:5; /* port pin (0-31) */
+ u_char flag:1; /* for whatever */
+} iopin_t;
+
+#define IOPIN_PORTA 0
+#define IOPIN_PORTB 1
+#define IOPIN_PORTC 2
+#define IOPIN_PORTD 3
+
+extern __inline__ void
+iopin_set_high(iopin_t *iopin)
+{
+ if (iopin->port == IOPIN_PORTA) {
+ volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padat;
+ *datp |= (1 << (15 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTB) {
+ volatile uint *datp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdat;
+ *datp |= (1 << (31 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTC) {
+ volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdat;
+ *datp |= (1 << (15 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTD) {
+ volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddat;
+ *datp |= (1 << (15 - iopin->pin));
+ }
+}
+
+extern __inline__ void
+iopin_set_low(iopin_t *iopin)
+{
+ if (iopin->port == IOPIN_PORTA) {
+ volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padat;
+ *datp &= ~(1 << (15 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTB) {
+ volatile uint *datp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdat;
+ *datp &= ~(1 << (31 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTC) {
+ volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdat;
+ *datp &= ~(1 << (15 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTD) {
+ volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddat;
+ *datp &= ~(1 << (15 - iopin->pin));
+ }
+}
+
+extern __inline__ uint
+iopin_is_high(iopin_t *iopin)
+{
+ if (iopin->port == IOPIN_PORTA) {
+ volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padat;
+ return (*datp >> (15 - iopin->pin)) & 1;
+ } else if (iopin->port == IOPIN_PORTB) {
+ volatile uint *datp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdat;
+ return (*datp >> (31 - iopin->pin)) & 1;
+ } else if (iopin->port == IOPIN_PORTC) {
+ volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdat;
+ return (*datp >> (15 - iopin->pin)) & 1;
+ } else if (iopin->port == IOPIN_PORTD) {
+ volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddat;
+ return (*datp >> (15 - iopin->pin)) & 1;
+ }
+ return 0;
+}
+
+extern __inline__ uint
+iopin_is_low(iopin_t *iopin)
+{
+ if (iopin->port == IOPIN_PORTA) {
+ volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padat;
+ return ((*datp >> (15 - iopin->pin)) & 1) ^ 1;
+ } else if (iopin->port == IOPIN_PORTB) {
+ volatile uint *datp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdat;
+ return ((*datp >> (31 - iopin->pin)) & 1) ^ 1;
+ } else if (iopin->port == IOPIN_PORTC) {
+ volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdat;
+ return ((*datp >> (15 - iopin->pin)) & 1) ^ 1;
+ } else if (iopin->port == IOPIN_PORTD) {
+ volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddat;
+ return ((*datp >> (15 - iopin->pin)) & 1) ^ 1;
+ }
+ return 0;
+}
+
+extern __inline__ void
+iopin_set_out(iopin_t *iopin)
+{
+ if (iopin->port == IOPIN_PORTA) {
+ volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padir;
+ *dirp |= (1 << (15 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTB) {
+ volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdir;
+ *dirp |= (1 << (31 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTC) {
+ volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdir;
+ *dirp |= (1 << (15 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTD) {
+ volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddir;
+ *dirp |= (1 << (15 - iopin->pin));
+ }
+}
+
+extern __inline__ void
+iopin_set_in(iopin_t *iopin)
+{
+ if (iopin->port == IOPIN_PORTA) {
+ volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padir;
+ *dirp &= ~(1 << (15 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTB) {
+ volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdir;
+ *dirp &= ~(1 << (31 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTC) {
+ volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdir;
+ *dirp &= ~(1 << (15 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTD) {
+ volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddir;
+ *dirp &= ~(1 << (15 - iopin->pin));
+ }
+}
+
+extern __inline__ uint
+iopin_is_out(iopin_t *iopin)
+{
+ if (iopin->port == IOPIN_PORTA) {
+ volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padir;
+ return (*dirp >> (15 - iopin->pin)) & 1;
+ } else if (iopin->port == IOPIN_PORTB) {
+ volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdir;
+ return (*dirp >> (31 - iopin->pin)) & 1;
+ } else if (iopin->port == IOPIN_PORTC) {
+ volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdir;
+ return (*dirp >> (15 - iopin->pin)) & 1;
+ } else if (iopin->port == IOPIN_PORTD) {
+ volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddir;
+ return (*dirp >> (15 - iopin->pin)) & 1;
+ }
+ return 0;
+}
+
+extern __inline__ uint
+iopin_is_in(iopin_t *iopin)
+{
+ if (iopin->port == IOPIN_PORTA) {
+ volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padir;
+ return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1;
+ } else if (iopin->port == IOPIN_PORTB) {
+ volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdir;
+ return ((*dirp >> (31 - iopin->pin)) & 1) ^ 1;
+ } else if (iopin->port == IOPIN_PORTC) {
+ volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdir;
+ return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1;
+ } else if (iopin->port == IOPIN_PORTD) {
+ volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddir;
+ return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1;
+ }
+ return 0;
+}
+
+extern __inline__ void
+iopin_set_odr(iopin_t *iopin)
+{
+ if (iopin->port == IOPIN_PORTA) {
+ volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_paodr;
+ *odrp |= (1 << (15 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTB) {
+ volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbodr;
+ *odrp |= (1 << (31 - iopin->pin));
+ }
+}
+
+extern __inline__ void
+iopin_set_act(iopin_t *iopin)
+{
+ if (iopin->port == IOPIN_PORTA) {
+ volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_paodr;
+ *odrp &= ~(1 << (15 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTB) {
+ volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbodr;
+ *odrp &= ~(1 << (31 - iopin->pin));
+ }
+}
+
+extern __inline__ uint
+iopin_is_odr(iopin_t *iopin)
+{
+ if (iopin->port == IOPIN_PORTA) {
+ volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_paodr;
+ return (*odrp >> (15 - iopin->pin)) & 1;
+ } else if (iopin->port == IOPIN_PORTB) {
+ volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbodr;
+ return (*odrp >> (31 - iopin->pin)) & 1;
+ }
+ return 0;
+}
+
+extern __inline__ uint
+iopin_is_act(iopin_t *iopin)
+{
+ if (iopin->port == IOPIN_PORTA) {
+ volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_paodr;
+ return ((*odrp >> (15 - iopin->pin)) & 1) ^ 1;
+ } else if (iopin->port == IOPIN_PORTB) {
+ volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbodr;
+ return ((*odrp >> (31 - iopin->pin)) & 1) ^ 1;
+ }
+ return 0;
+}
+
+extern __inline__ void
+iopin_set_ded(iopin_t *iopin)
+{
+ if (iopin->port == IOPIN_PORTA) {
+ volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_papar;
+ *parp |= (1 << (15 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTB) {
+ volatile uint *parp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbpar;
+ *parp |= (1 << (31 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTC) {
+ volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcpar;
+ *parp |= (1 << (15 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTD) {
+ volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdpar;
+ *parp |= (1 << (15 - iopin->pin));
+ }
+}
+
+extern __inline__ void
+iopin_set_gen(iopin_t *iopin)
+{
+ if (iopin->port == IOPIN_PORTA) {
+ volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_papar;
+ *parp &= ~(1 << (15 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTB) {
+ volatile uint *parp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbpar;
+ *parp &= ~(1 << (31 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTC) {
+ volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcpar;
+ *parp &= ~(1 << (15 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTD) {
+ volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdpar;
+ *parp &= ~(1 << (15 - iopin->pin));
+ }
+}
+
+extern __inline__ uint
+iopin_is_ded(iopin_t *iopin)
+{
+ if (iopin->port == IOPIN_PORTA) {
+ volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_papar;
+ return (*parp >> (15 - iopin->pin)) & 1;
+ } else if (iopin->port == IOPIN_PORTB) {
+ volatile uint *parp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbpar;
+ return (*parp >> (31 - iopin->pin)) & 1;
+ } else if (iopin->port == IOPIN_PORTC) {
+ volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcpar;
+ return (*parp >> (15 - iopin->pin)) & 1;
+ } else if (iopin->port == IOPIN_PORTD) {
+ volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdpar;
+ return (*parp >> (15 - iopin->pin)) & 1;
+ }
+ return 0;
+}
+
+extern __inline__ uint
+iopin_is_gen(iopin_t *iopin)
+{
+ if (iopin->port == IOPIN_PORTA) {
+ volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_papar;
+ return ((*parp >> (15 - iopin->pin)) & 1) ^ 1;
+ } else if (iopin->port == IOPIN_PORTB) {
+ volatile uint *parp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbpar;
+ return ((*parp >> (31 - iopin->pin)) & 1) ^ 1;
+ } else if (iopin->port == IOPIN_PORTC) {
+ volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcpar;
+ return ((*parp >> (15 - iopin->pin)) & 1) ^ 1;
+ } else if (iopin->port == IOPIN_PORTD) {
+ volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdpar;
+ return ((*parp >> (15 - iopin->pin)) & 1) ^ 1;
+ }
+ return 0;
+}
+
+extern __inline__ void
+iopin_set_opt2(iopin_t *iopin)
+{
+ if (iopin->port == IOPIN_PORTC) {
+ volatile ushort *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcso;
+ *sorp |= (1 << (15 - iopin->pin));
+ }
+}
+
+extern __inline__ void
+iopin_set_opt1(iopin_t *iopin)
+{
+ if (iopin->port == IOPIN_PORTC) {
+ volatile ushort *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcso;
+ *sorp &= ~(1 << (15 - iopin->pin));
+ }
+}
+
+extern __inline__ uint
+iopin_is_opt2(iopin_t *iopin)
+{
+ if (iopin->port == IOPIN_PORTC) {
+ volatile ushort *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcso;
+ return (*sorp >> (15 - iopin->pin)) & 1;
+ }
+ return 0;
+}
+
+extern __inline__ uint
+iopin_is_opt1(iopin_t *iopin)
+{
+ if (iopin->port == IOPIN_PORTC) {
+ volatile ushort *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcso;
+ return ((*sorp >> (15 - iopin->pin)) & 1) ^ 1;
+ }
+ return 0;
+}
+
+extern __inline__ void
+iopin_set_falledge(iopin_t *iopin)
+{
+ if (iopin->port == IOPIN_PORTC) {
+ volatile ushort *intp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcint;
+ *intp |= (1 << (15 - iopin->pin));
+ }
+}
+
+extern __inline__ void
+iopin_set_anyedge(iopin_t *iopin)
+{
+ if (iopin->port == IOPIN_PORTC) {
+ volatile ushort *intp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcint;
+ *intp &= ~(1 << (15 - iopin->pin));
+ }
+}
+
+extern __inline__ uint
+iopin_is_falledge(iopin_t *iopin)
+{
+ if (iopin->port == IOPIN_PORTC) {
+ volatile ushort *intp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcint;
+ return (*intp >> (15 - iopin->pin)) & 1;
+ }
+ return 0;
+}
+
+extern __inline__ uint
+iopin_is_anyedge(iopin_t *iopin)
+{
+ if (iopin->port == IOPIN_PORTC) {
+ volatile ushort *intp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcint;
+ return ((*intp >> (15 - iopin->pin)) & 1) ^ 1;
+ }
+ return 0;
+}
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_IOPIN_8XX_H_ */
#define SPRN_TBHU 0x3CC /* Time Base High User-mode */
#define SPRN_TBLO 0x3DD /* Time Base Low */
#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */
-#define SPRN_TBRL 0x10D /* Time Base Read Lower Register */
-#define SPRN_TBRU 0x10C /* Time Base Read Upper Register */
-#define SPRN_TBWL 0x11D /* Time Base Write Lower Register */
-#define SPRN_TBWU 0x11C /* Time Base Write Upper Register */
+#define SPRN_TBRL 0x10C /* Time Base Read Lower Register */
+#define SPRN_TBRU 0x10D /* Time Base Read Upper Register */
+#define SPRN_TBWL 0x11C /* Time Base Write Lower Register */
+#define SPRN_TBWU 0x11D /* Time Base Write Upper Register */
#ifndef CONFIG_BOOKE
#define SPRN_TCR 0x3DA /* Timer Control Register */
#else
#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
/*
- * IBM has further subdivided the standard PowerPC 16-bit version and
+ * AMCC has further subdivided the standard PowerPC 16-bit version and
* revision subfields of the PVR for the PowerPC 403s into the following:
*/
#define PVR_440GP_RB 0x40120440
#define PVR_440GP_RC 0x40120481
#define PVR_440EP_RA 0x42221850
-#define PVR_440EP_RB 0x422218D3
+#define PVR_440EP_RB 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
+#define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
#define PVR_440GX_RA 0x51B21850
#define PVR_440GX_RB 0x51B21851
#define PVR_440GX_RC 0x51B21892
+#define PVR_440GX_RF 0x51B21894
#define PVR_405EP_RB 0x51210950
+#define PVR_440SP_RA 0x53221850
+#define PVR_440SP_RB 0x53221891
#define PVR_601 0x00010000
#define PVR_602 0x00050000
#define PVR_603 0x00030000
#define _MACH_gemini 0x00000200 /* Synergy Microsystems gemini board */
#define _MACH_classic 0x00000400 /* RPCG RPX-Classic 8xx board */
#define _MACH_oak 0x00000800 /* IBM "Oak" 403 eval. board */
-#define _MACH_walnut 0x00001000 /* IBM "Walnut" 405GP eval. board */
+#define _MACH_walnut 0x00001000 /* AMCC "Walnut" 405GP eval. board */
#define _MACH_8260 0x00002000 /* Generic 8260 */
#define _MACH_sandpoint 0x00004000 /* Motorola SPS Processor eval board */
#define _MACH_tqm860 0x00008000 /* TQM860/L */
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
*/
#ifndef __U_BOOT_H__
*/
#ifndef __ASSEMBLY__
-#include <linux/types.h>
typedef struct bd_info {
unsigned long bi_memstart; /* start of DRAM memory */
defined(CONFIG_405EP) || \
defined(CONFIG_440)
unsigned char bi_s_version[4]; /* Version of this structure */
- unsigned char bi_r_version[32]; /* Version of the ROM (IBM) */
+ unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */
unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */
unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */
unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
#if defined(CONFIG_NX823)
unsigned char bi_sernum[8];
#endif
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
- int bi_phynum[2]; /* Determines phy mapping */
- int bi_phymode[2]; /* Determines phy mode */
-#endif
+#if defined(CONFIG_4xx)
#if defined(CONFIG_440GX)
int bi_phynum[4]; /* Determines phy mapping */
int bi_phymode[4]; /* Determines phy mode */
+#elif defined(CONFIG_405EP) || defined(CONFIG_440)
+ int bi_phynum[2]; /* Determines phy mapping */
+ int bi_phymode[2]; /* Determines phy mode */
+#else
+ int bi_phynum[1]; /* Determines phy mapping */
+ int bi_phymode[1]; /* Determines phy mode */
#endif
+#endif /* defined(CONFIG_4xx) */
} bd_t;
#endif /* __ASSEMBLY__ */
void at91rm9200_EmacDisableMDIO(AT91PS_EMAC p_mac);
UCHAR at91rm9200_EmacReadPhy(AT91PS_EMAC p_mac, unsigned char RegisterAddress, unsigned short *pInput);
UCHAR at91rm9200_EmacWritePhy(AT91PS_EMAC p_mac, unsigned char RegisterAddress, unsigned short *pOutput);
-void at91rm92000_GetPhyInterface(AT91PS_PhyOps p_phyops);
+void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops);
#endif /* AT91RM9200_ETHERNET */
--- /dev/null
+/*
+ * Broadcom BCM5221 Ethernet PHY
+ *
+ * (C) Copyright 2005 REA Elektronik GmbH <www.rea.de>
+ * Anders Larsen <alarsen@rea.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define BCM5221_BMCR 0 /* Basic Mode Control Register */
+#define BCM5221_BMSR 1 /* Basic Mode Status Register */
+#define BCM5221_PHYID1 2 /* PHY Identifier Register 1 */
+#define BCM5221_PHYID2 3 /* PHY Identifier Register 2 */
+#define BCM5221_ANAR 4 /* Auto-negotiation Advertisement Register */
+#define BCM5221_ANLPAR 5 /* Auto-negotiation Link Partner Ability Register */
+#define BCM5221_ANER 6 /* Auto-negotiation Expansion Register */
+#define BCM5221_ACSR 24 /* Auxiliary Control/Status Register */
+#define BCM5221_INTR 26 /* Interrupt Register */
+
+/* --Bit definitions: BCM5221_BMCR */
+#define BCM5221_RESET (1 << 15) /* 1= Software Reset; 0=Normal Operation */
+#define BCM5221_LOOPBACK (1 << 14) /* 1=loopback Enabled; 0=Normal Operation */
+#define BCM5221_SPEED_SELECT (1 << 13) /* 1=100Mbps; 0=10Mbps */
+#define BCM5221_AUTONEG (1 << 12)
+#define BCM5221_POWER_DOWN (1 << 11)
+#define BCM5221_ISOLATE (1 << 10)
+#define BCM5221_RESTART_AUTONEG (1 << 9)
+#define BCM5221_DUPLEX_MODE (1 << 8)
+#define BCM5221_COLLISION_TEST (1 << 7)
+
+/*--Bit definitions: BCM5221_BMSR */
+#define BCM5221_100BASE_T4 (1 << 15)
+#define BCM5221_100BASE_TX_FD (1 << 14)
+#define BCM5221_100BASE_TX_HD (1 << 13)
+#define BCM5221_10BASE_T_FD (1 << 12)
+#define BCM5221_10BASE_T_HD (1 << 11)
+#define BCM5221_MF_PREAMB_SUPPR (1 << 6)
+#define BCM5221_AUTONEG_COMP (1 << 5)
+#define BCM5221_REMOTE_FAULT (1 << 4)
+#define BCM5221_AUTONEG_ABILITY (1 << 3)
+#define BCM5221_LINK_STATUS (1 << 2)
+#define BCM5221_JABBER_DETECT (1 << 1)
+#define BCM5221_EXTEND_CAPAB (1 << 0)
+
+/*--definitions: BCM5221_PHYID1 */
+#define BCM5221_PHYID1_OUI 0x1018
+#define BCM5221_LSB_MASK 0x3F
+
+/*--Bit definitions: BCM5221_ANAR, BCM5221_ANLPAR */
+#define BCM5221_NP (1 << 15)
+#define BCM5221_ACK (1 << 14)
+#define BCM5221_RF (1 << 13)
+#define BCM5221_FCS (1 << 10)
+#define BCM5221_T4 (1 << 9)
+#define BCM5221_TX_FDX (1 << 8)
+#define BCM5221_TX_HDX (1 << 7)
+#define BCM5221_10_FDX (1 << 6)
+#define BCM5221_10_HDX (1 << 5)
+#define BCM5221_AN_IEEE_802_3 0x0001
+
+/*--Bit definitions: BCM5221_ANER */
+#define BCM5221_PDF (1 << 4)
+#define BCM5221_LP_NP_ABLE (1 << 3)
+#define BCM5221_NP_ABLE (1 << 2)
+#define BCM5221_PAGE_RX (1 << 1)
+#define BCM5221_LP_AN_ABLE (1 << 0)
+
+/*--Bit definitions: BCM5221_ACSR */
+#define BCM5221_100 (1 << 1)
+#define BCM5221_FDX (1 << 0)
+
+/*--Bit definitions: BCM5221_INTR */
+#define BCM5221_FDX_LED (1 << 15)
+#define BCM5221_INTR_ENABLE (1 << 14)
+#define BCM5221_FDX_MASK (1 << 11)
+#define BCM5221_SPD_MASK (1 << 10)
+#define BCM5221_LINK_MASK (1 << 9)
+#define BCM5221_INTR_MASK (1 << 8)
+#define BCM5221_FDX_CHG (1 << 3)
+#define BCM5221_SPD_CHG (1 << 2)
+#define BCM5221_LINK_CHG (1 << 1)
+#define BCM5221_INTR_STATUS (1 << 0)
+
+/****************** function prototypes **********************/
+unsigned int bcm5221_IsPhyConnected(AT91PS_EMAC p_mac);
+unsigned char bcm5221_GetLinkSpeed(AT91PS_EMAC p_mac);
+unsigned char bcm5221_AutoNegotiate(AT91PS_EMAC p_mac, int *status);
+unsigned char bcm5221_InitPhy(AT91PS_EMAC p_mac);
/* crc, base, loop, mtest */
#define CFG_CMD_NET 0x00000080ULL /* bootp, tftpboot, rarpboot */
#define CFG_CMD_ENV 0x00000100ULL /* saveenv */
-#define CFG_CMD_KGDB 0x00000200ULL /* kgdb */
+#define CFG_CMD_KGDB 0x0000000000000200ULL /* kgdb */
#define CFG_CMD_PCMCIA 0x00000400ULL /* PCMCIA support */
#define CFG_CMD_IDE 0x00000800ULL /* IDE harddisk support */
#define CFG_CMD_PCI 0x00001000ULL /* pciinfo */
#define CFG_CMD_CDP 0x0200000000000000ULL /* Cisco Discovery Protocol */
#define CFG_CMD_XIMG 0x0400000000000000ULL /* Load part of Multi Image */
#define CFG_CMD_UNIVERSE 0x0800000000000000ULL /* Tundra Universe Support */
-#define CFG_CMD_EXT2 0x1000000000000000ULL /* EXT2 Support */
+#define CFG_CMD_EXT2 0x1000000000000000ULL /* EXT2 Support */
#define CFG_CMD_SNTP 0x2000000000000000ULL /* SNTP support */
+#define CFG_CMD_DISPLAY 0x4000000000000000ULL /* Display support */
#define CFG_CMD_ALL 0xFFFFFFFFFFFFFFFFULL /* ALL commands */
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
+ CFG_CMD_DISPLAY | \
CFG_CMD_DOC | \
CFG_CMD_DTT | \
CFG_CMD_ECHO | \
/* common/cmd_nvedit.c */
int env_init (void);
void env_relocate (void);
-char *getenv (uchar *);
-int getenv_r (uchar *name, uchar *buf, unsigned len);
+char *getenv (char *);
+int getenv_r (char *name, char *buf, unsigned len);
int saveenv (void);
#ifdef CONFIG_PPC /* ARM version to be fixed! */
void inline setenv (char *, char *);
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */
-#define CFG_CACHELINE_SIZE 16 /* For IBM 401/403 CPUs */
+#define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
#define CONFIG_BOOTCOMMAND \
"bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"bootm" /* autoboot command */
#undef CONFIG_BOOTARGS
--- /dev/null
+/*
+ * AMIRIX.h: AMIRIX specific config options
+ *
+ * Author : Frank Smith (smith at amirix dot com)
+ *
+ * Derived from : other configuration header files in this tree
+ *
+ * This software may be used and distributed according to the terms of
+ * the GNU General Public License (GPL) version 2, incorporated herein by
+ * reference. Drivers based on or derived from this code fall under the GPL
+ * and must retain the authorship, copyright and this license notice. This
+ * file is not a complete program and may only be used when the entire
+ * program is licensed under the GPL.
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#undef DEBUG
+
+#define CONFIG_405 1 /* This is a PPC405 CPU */
+#define CONFIG_4xx 1 /* ...member of PPC4xx family */
+
+#define CONFIG_AP1000 1 /* ...on an AP1000 board */
+
+#define CONFIG_PCI 1
+
+#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
+#define CFG_PROMPT "0> "
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_COMMAND_EDIT 1
+#define CONFIG_COMMAND_HISTORY 1
+#define CONFIG_COMPLETE_ADDRESSES 1
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_FLASH_USE_BUFFER_WRITE
+
+#ifdef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_FLASH
+#else
+#ifdef CFG_ENV_IS_IN_FLASH
+#undef CFG_ENV_IS_IN_NVRAM
+#endif
+#endif
+
+#define CONFIG_BAUDRATE 57600
+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
+
+#define CONFIG_BOOTCOMMAND "" /* autoboot command */
+
+/* Size (bytes) of interrupt driven serial port buffer.
+ * Set to 0 to use polling instead of interrupts.
+ * Setting to 0 will also disable RTS/CTS handshaking.
+ */
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+
+#define CONFIG_BOOTARGS "console=ttyS0,57600"
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_ELF | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_MVENV | \
+ CFG_CMD_PCI | \
+ CFG_CMD_PING \
+ )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#define CONFIG_SYS_CLK_FREQ 30000000
+
+#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+/* usually: (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) */
+#define CFG_PBSIZE (CFG_CBSIZE+4+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_ALT_MEMTEST 1
+#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x01000000 /* 4 ... 16 MB in DRAM */
+
+/*
+ * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * The Linux BASE_BAUD define should match this configuration.
+ * baseBaud = cpuClock/(uartDivisor*16)
+ * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
+#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
+
+#define CFG_NS16550_CLK 40000000
+#define CFG_DUART_CHAN 0
+#define CFG_NS16550_COM1 (0x4C000000 + 0x1000)
+#define CFG_NS16550_COM2 (0x4C800000 + 0x1000)
+#define CFG_NS16550_REG_SIZE 4
+#define CFG_NS16550 1
+#define CFG_INIT_CHAN1 1
+#define CFG_INIT_CHAN2 0
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+#define CFG_LOAD_ADDR 0x00200000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0x20000000
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI 1
+#define CFG_PROGFLASH_BASE CFG_FLASH_BASE
+#define CFG_CONFFLASH_BASE 0x24000000
+
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_PROTECTION 1 /* use hardware protection */
+
+/* BEG ENVIRONNEMENT FLASH */
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE 0x20000 /* see README - env sector total size */
+#endif
+/* END ENVIRONNEMENT FLASH */
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
+#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
+
+#ifdef CFG_ENV_IS_IN_NVRAM
+#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
+#define CFG_ENV_ADDR \
+ (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
+#endif
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 16384
+#define CFG_CACHELINE_SIZE 32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
+#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
+
+/* Configuration Port location */
+#define CONFIG_PORT_ADDR 0xF0000500
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+
+#define CFG_INIT_RAM_ADDR 0x400000 /* inside of SDRAM */
+#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for Serial Presence Detect EEPROM address
+ * (to get SDRAM settings)
+ */
+#define SPD_EEPROM_ADDRESS 0x50
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/* JFFS2 stuff */
+
+#define CFG_JFFS2_FIRST_BANK 0
+#define CFG_JFFS2_NUM_BANKS 1
+#define CFG_JFFS2_FIRST_SECTOR 1
+
+#define CONFIG_NET_MULTI
+#define CONFIG_E1000
+
+#define CFG_ETH_DEV_FN 0x0800
+#define CFG_ETH_IOBASE 0x31000000
+#define CFG_ETH_MEMBASE 0x32000000
+
+#endif /* __CONFIG_H */
#undef CONFIG_BOOTARGS
#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+ "setenv bootargs root=/dev/ram rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"bootm ffc00000 ffca0000"
#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"bootm ffc00000"
#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
+#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_LCD_MEM CFG_LCD_BIG_MEM
#define CFG_LCD_REG CFG_LCD_BIG_REG
-#define CFG_LCD_LOGO_MAX_SIZE (1024*1024)
+#define CFG_VIDEO_LOGO_MAX_SIZE (1 << 20)
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in data cache)
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
+#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
+#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
CFG_CMD_SNTP )
#define CONFIG_NET_MULTI
+#define CONFIG_MII
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_BOOTCOMMAND \
"bootp 1000000; " \
"setenv bootargs root=ramfs console=ttyS00,9600 " \
- "ip=$(ipaddr):$(serverip):$(rootpath):$(gatewayip):" \
- "$(netmask):$(hostname):eth0:none; " \
+ "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:" \
+ "${netmask}:${hostname}:eth0:none; " \
"bootm"
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
+#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND "setenv bootargs " \
- "mem=$(mem) " \
- "root=/dev/ram rw ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off " \
+ "mem=${mem} " \
+ "root=/dev/ram rw ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
"wt_8xx=timeout:3600; " \
"bootm"
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * CMS700.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP 1 /* This is a PPC405 CPU */
+#define CONFIG_4xx 1 /* ...member of PPC4xx family */
+#define CONFIG_VOM405 1 /* ...on a VOM405 board */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
+#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
+
+#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
+
+#define CONFIG_BAUDRATE 9600
+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
+
+#undef CONFIG_BOOTARGS
+#undef CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT /* enable preboot variable */
+
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_NET_MULTI 1
+#undef CONFIG_HAS_ETH1
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 0 /* PHY address */
+#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
+
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
+ CONFIG_BOOTP_DNS | \
+ CONFIG_BOOTP_DNS2 | \
+ CONFIG_BOOTP_SEND_HOSTNAME )
+
+#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_BSP | \
+ CFG_CMD_PCI | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_ELF | \
+ CFG_CMD_NAND | \
+ CFG_CMD_I2C | \
+ CFG_CMD_DATE | \
+ CFG_CMD_MII | \
+ CFG_CMD_PING | \
+ CFG_CMD_EEPROM )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
+
+#undef CONFIG_PRAM /* no "protected RAM" */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#undef CFG_HUSH_PARSER /* use "hush" command parser */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
+
+#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
+#define CFG_BASE_BAUD 691200
+#define CONFIG_UART1_CONSOLE /* define for uart1 as console */
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE \
+ { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
+ 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * RTC stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_RTC_DS1337
+#define CFG_I2C_RTC_ADDR 0x68
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+
+#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
+#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
+#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
+#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
+#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
+#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
+#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
+
+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+
+#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
+#define PCI_HOST_FORCE 1 /* configure as pci host */
+#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
+
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
+#undef CONFIG_PCI_PNP /* do pci plug-and-play */
+ /* resource configuration */
+
+#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
+#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
+#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
+#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
+#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
+#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
+
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
+#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
+#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
+#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
+#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
+
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+
+#if 0 /* test-only */
+#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0xFFFC0000
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
+
+#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
+# define CFG_RAMBOOT 1
+#else
+# undef CFG_RAMBOOT
+#endif
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
+ /* total size of a CAT24WC16 is 2048 bytes */
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
+#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
+/* mask of address bits that overflow into the "EEPROM chip address" */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
+ /* 16 byte page write mode using*/
+ /* last 4 bits of the address */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+#define CFG_EEPROM_WREN 1
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
+ /* have only 8kB, 16kB is save here */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+#define CFG_PLD_BASE 0xf0000000
+#define CFG_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
+#define CFG_EBC_PB0AP 0x92015480
+#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
+#define CFG_EBC_PB1AP 0x92015480
+#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
+
+/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
+#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
+#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */
+#define CFG_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */
+#define CFG_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */
+#define CFG_FPGA_INIT 0x00010000 /* unused (ppc input) */
+#define CFG_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM 1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR 0xF8000000
+#define CFG_OCM_DATA_SIZE 0x1000
+#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
+#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0] - External Bus Controller BLAST output
+ * GPIO0[1-9] - Instruction trace outputs -> GPIO
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+/* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */
+/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */
+/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */
+/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
+#define CFG_GPIO0_OSRH 0x40000500 /* 0 ... 15 */
+#define CFG_GPIO0_OSRL 0x00000110 /* 16 ... 31 */
+#define CFG_GPIO0_ISR1H 0x00000000 /* 0 ... 15 */
+#define CFG_GPIO0_ISR1L 0x14000045 /* 16 ... 31 */
+#define CFG_GPIO0_TSRH 0x00000000 /* 0 ... 15 */
+#define CFG_GPIO0_TSRL 0x00000000 /* 16 ... 31 */
+#define CFG_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */
+
+#define CFG_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */
+#define CFG_PLD_RESET (0x80000000 >> 12) /* GPIO12 */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+/*
+ * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * This value will be set if iic boot eprom is disabled.
+ */
+#if 0
+#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
+#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
+#endif
+#if 1
+#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
+#endif
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP 1 /* This is a PPC405 CPU */
+#define CONFIG_4xx 1 /* ...member of PPC4xx family */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
+
+#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
+
+#define CONFIG_BAUDRATE 9600
+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
+
+#undef CONFIG_BOOTARGS
+#undef CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT /* enable preboot variable */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 0 /* PHY address */
+
+#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & ~CFG_CMD_NET) | \
+ CFG_CMD_PCI | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_ELF | \
+ CFG_CMD_I2C | \
+ CFG_CMD_BSP | \
+ CFG_CMD_EEPROM )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#undef CFG_HUSH_PARSER /* use "hush" command parser */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
+
+#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
+
+#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
+#define CFG_BASE_BAUD 691200
+#define CONFIG_UART1_CONSOLE /* define for uart1 as console */
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE \
+ { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
+ 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_LOOPW 1 /* enable loopw command */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
+#define PCI_HOST_FORCE 1 /* configure as pci host */
+#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
+
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+ /* resource configuration */
+
+#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
+#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
+#define CFG_PCI_SUBSYS_DEVICEID 0x040b /* PCI Device ID: CPCI-2DP */
+#define CFG_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/
+
+#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
+#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
+#define CFG_PCI_PTM2LA 0xef000000 /* point to internal regs + PB0/1 */
+#define CFG_PCI_PTM2MS 0xff000001 /* 16MB, enable */
+#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0xFFFC0000
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
+#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
+#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
+
+#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
+#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
+#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
+
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+
+#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
+#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
+/* mask of address bits that overflow into the "EEPROM chip address" */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
+ /* 16 byte page write mode using*/
+ /* last 4 bits of the address */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+#define CFG_EEPROM_WREN 1
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
+ /* have only 8kB, 16kB is save here */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
+#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization */
+#define CFG_EBC_PB0AP 0x92015480
+#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (PB0) initialization */
+#define CFG_EBC_PB2AP 0x03004580 /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
+#define CFG_EBC_PB2CR 0xEF018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
+
+/* Memory Bank 3 (PB1) initialization */
+#define CFG_EBC_PB3AP 0x03004580 /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
+#define CFG_EBC_PB3CR 0xEF118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
+
+#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
+#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * GPIO definitions
+ */
+#define CFG_EEPROM_WP (0x80000000 >> 13) /* GPIO13 */
+#define CFG_SELF_RST (0x80000000 >> 14) /* GPIO14 */
+#define CFG_PB_LED (0x80000000 >> 16) /* GPIO16 */
+#define CFG_INTA_FAKE (0x80000000 >> 23) /* GPIO23 */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#endif /* __CONFIG_H */
#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
+#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
+#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
+#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
+#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
+#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
+#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
+#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 32768 /* For IBM 440 CPUs */
+#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#define CONFIG_IDENT_STRING "Marvell 64360 + IBM750FX"
/*#define CFG_HUSH_PARSER*/
-#undef CFG_HUSH_PARSER
+#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
+#define CFG_AUTO_COMPLETE 1
+
/* Define which ETH port will be used for connecting the network */
#define CFG_ETH_PORT ETH_0
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
+#define CONFIG_USE_CPCIDVI
+
+#ifdef CONFIG_USE_CPCIDVI
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_CT69000
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_I8042_KBD
+#define CFG_ISA_IO 0
+#endif
+
/*
* Miscellaneous configurable options
*/
#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE)
#define CFG_PCI1_IO_SPACE_PCI 0x00000000
+#define CFG_ISA_IO_BASE_ADDRESS (CFG_PCI0_IO_BASE)
+
#if defined (CONFIG_750CX)
#define CFG_PCI_IDSEL 0x0
#else
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
/*-----------------------------------------------------------------------
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */
-#define CFG_CACHELINE_SIZE 16 /* For IBM 401/403 CPUs */
+#define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
/* ronen - autoboot using tftp */
#if (CONFIG_BOOTDELAY >= 0)
#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\
- setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \
- ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; "
+ setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \
+ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000; "
#define CONFIG_BOOTARGS "console=ttyS0,115200"
"bootargs_root=root=/dev/nfs rw\0" \
"bootargs_end=:::DB64360:eth0:none \0"\
"ethprime=mv_enet0\0"\
- "standalone=fsload 0x400000 uImage;setenv bootargs $(bootargs) root=/dev/mtdblock/0 rw \
-ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000;\0"
+ "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \
+ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
/* --------------------------------------------------------------------------------------------------------------- */
/* New bootcommands for Marvell DB64360 c 2002 Ingo Assmus */
/* ronen - autoboot using tftp */
#if (CONFIG_BOOTDELAY >= 0)
#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\
- setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \
- ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; "
+ setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \
+ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000; "
#define CONFIG_BOOTARGS "console=ttyS0,115200"
"bootargs_root=root=/dev/nfs rw\0" \
"bootargs_end=:::DB64460:eth0:none \0"\
"ethprime=mv_enet0\0"\
- "standalone=fsload 0x400000 uImage;setenv bootargs $(bootargs) root=/dev/mtdblock/0 rw \
-ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000;\0"
+ "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \
+ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
/* --------------------------------------------------------------------------------------------------------------- */
/* New bootcommands for Marvell DB64460 c 2002 Ingo Assmus */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
+#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#define CONFIG_BOOTCOMMAND \
"bootp 1000000; " \
"setenv bootargs root=ramfs console=ttyS00,9600 " \
- "ip=$(ipaddr):$(serverip):$(rootpath):$(gatewayip):" \
- "$(netmask):$(hostname):eth0:none; " \
+ "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:" \
+ "${netmask}:${hostname}:eth0:none; " \
"bootm"
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
#define CONFIG_EXTRA_ENV_SETTINGS \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "rootargs=setenv rootpath /tftp/$(ipaddr)\0" \
+ "rootargs=setenv rootpath /tftp/${ipaddr}\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):eth0:off panic=1\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:eth0:off panic=1\0" \
"ramboot=tftp 400000 /home/paugaml/pMulti;" \
"run ramargs;bootm\0" \
"nfsboot=tftp 400000 /home/paugaml/uImage;" \
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
"setenv bootargs root=/dev/ram rw ramdisk_size=4690 " \
"U-Boot_version=U-Boot-1.0.x-Date " \
"panic=1 " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_NFSBOOTCOMMAND \
"bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(nfsip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${nfsip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
#define CONFIG_BOOTCOMMAND \
"bootp ;" \
"setenv bootargs console=tty0 console=ttyS0 " \
-"root=/dev/nfs nfsroot=$(serverip):$(rootpath) " \
-"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname):eth0:off ;" \
+"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \
+"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ;" \
"bootm"
#else
#define CONFIG_BOOTDELAY 0 /* autoboot disabled */
#define CONFIG_EXTRA_ENV_SETTINGS \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off\0" \
- "addmisc=setenv bootargs $(bootargs) " \
- "console=ttyS0,$(baudrate) " \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off\0" \
+ "addmisc=setenv bootargs ${bootargs} " \
+ "console=ttyS0,${baudrate} " \
"panic=1\0" \
"flash_nfs=run nfsargs addip addmisc;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addmisc;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};" \
"run nfsargs addip addmisc;bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/g2000/pImage\0" \
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
+#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
/*
#define CONFIG_BOOTCOMMAND \
"bootp; tftp; " \
"setenv bootargs console=tty0 console=ttyS0 " \
-"root=/dev/nfs nfsroot=$(serverip):$(rootpath) " \
-"ip=$(ipaddr):$(serverip):$(gatewayip):$(subnetmask):$(hostname):eth0:off ;" \
+"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \
+"ip=${ipaddr}:${serverip}:${gatewayip}:${subnetmask}:${hostname}:eth0:off ;" \
"bootm "
#else
#define CONFIG_BOOTDELAY 0 /* autoboot disabled */
* (C) Copyright 2001-2004
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
#define CONFIG_PREBOOT "autoupd"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "pciconfighost=1\0" \
+ ""
+
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
+/*
+ * Video console
+ */
+#define CONFIG_VIDEO /* for sm501 video support */
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_SM501
+#if 0
+#define CONFIG_VIDEO_SM501_32BPP
+#else
+#define CONFIG_VIDEO_SM501_16BPP
+#endif
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_SPLASH_SCREEN
+#define CFG_CONSOLE_IS_IN_ENV
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */
+#define CFG_VIDEO_LOGO_MAX_SIZE (2 << 20) /* for decompressed img */
+
+#define ADD_BMP_CMD CFG_CMD_BMP
+#else
+#define ADD_BMP_CMD 0
+#endif /* CONFIG_VIDEO */
+
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_DHCP | \
CFG_CMD_PCI | \
CFG_CMD_IRQ | \
CFG_CMD_IDE | \
CFG_CMD_FAT | \
+ CFG_CMD_EXT2 | \
CFG_CMD_ELF | \
CFG_CMD_NAND | \
CFG_CMD_I2C | \
+ CFG_CMD_DATE | \
CFG_CMD_MII | \
CFG_CMD_PING | \
+ ADD_BMP_CMD | \
CFG_CMD_EEPROM )
#define CONFIG_MAC_PARTITION
#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
-#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
+#undef CFG_CONSOLE_INFO_QUIET /* print console @ startup */
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
/*-----------------------------------------------------------------------
+ * RTC stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_RTC_DS1338
+#define CFG_I2C_RTC_ADDR 0x68
+
+/*-----------------------------------------------------------------------
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CFG_FLASH_BASE 0xFFF80000
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
-#define CFG_MALLOC_LEN (2 * 1024*1024) /* Reserve 2 MB for malloc() */
+#define CFG_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc() */
#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
# define CFG_RAMBOOT 1
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
+#define CFG_EEPROM_WREN 1
+
#if 1 /* test-only */
/* CAT24WC08/16... */
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
+#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */
#define CFG_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */
-#define CFG_LCD_LOGO_MAX_SIZE (1024*1024)
-
/*-----------------------------------------------------------------------
* Universal Interrupt Controller (UIC) Setup
*/
#define CFG_GPIO0_TCR 0xF7FE0017
#define CFG_LCD_ENDIAN (0x80000000 >> 7)
-#define CFG_TOUCH_RST (0x80000000 >> 9)
+#define CFG_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */
+#define CFG_TOUCH_RST (0x80000000 >> 9) /* GPIO9 */
#define CFG_LCD0_RST (0x80000000 >> 30)
#define CFG_LCD1_RST (0x80000000 >> 31)
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/HMI10/uImage\0" \
"kernel_addr=40040000\0" \
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
+#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#undef CONFIG_BOOTARGS
/* #define CONFIG_BOOTCOMMAND \
"bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"bootm"
*/
# undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
# define CONFIG_FEC_ENET 1 /* use FEC ethernet */
+# define CONFIG_MII 1
# define CFG_DISCOVER_PHY 1
# define CONFIG_FEC_UTOPIA 1
# define CONFIG_ETHADDR 08:00:06:26:A2:6D
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"bootm"
#undef CONFIG_WATCHDOG /* watchdog disabled */
#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
+#define CONFIG_MII 1
#if 1
#define CFG_DISCOVER_PHY 1
#else
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw " \
"console=ttyS0,115200\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_82xx\0" \
"bootfile=/tftpboot/IDS8247/uImage\0" \
"kernel_addr=ff800000\0" \
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" \
-"\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 $(filesize)\0"
+"\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 ${filesize}\0"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_XLB_PIPELINING 1
#define CONFIG_NET_MULTI 1
+#define CONFIG_MII 1
#define CONFIG_EEPRO100 1
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
#else /* MPC5100 */
+#define CONFIG_MII 1
#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_82xx\0" \
"bootfile=/tftpboot/MPC5200/uImage\0" \
""
#define CONFIG_PHY_ADDR 1 /* PHY address */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_FLASH | \
- CFG_CMD_NET | \
CFG_CMD_DHCP | \
- CFG_CMD_PING | \
- CFG_CMD_MII | \
CFG_CMD_EEPROM | \
+ CFG_CMD_ELF | \
CFG_CMD_FAT | \
- CFG_CMD_ELF )
+ CFG_CMD_FLASH | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_MII | \
+ CFG_CMD_NET | \
+ CFG_CMD_PCI | \
+ CFG_CMD_PING )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405GPr CPUs */
+#define CFG_DCACHE_SIZE 16384 /* For AMCC 405GPr CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#define CONFIG_HAS_ETH3
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */
#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */
#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */
"run addhw; diskboot 200000 2:1; bootm 200000\0" \
"nfs_boot=dhcp; run nfsargs addip addhw; bootm 200000\0" \
"panic_boot=echo No Bootdevice !!! reset\0" \
-"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0" \
+"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
-"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip)" \
- ":$(netmask):$(hostname):$(netdev):off\0" \
-"addhw=setenv bootargs $(bootargs) hw=$(hw) key1=$(key1) panic=1\0" \
+"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}" \
+ ":${netmask}:${hostname}:${netdev}:off\0" \
+"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0" \
"netdev=eth0\0" \
"contrast=55\0" \
"silent=1\0" \
"load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0" \
-"update=protect off 1:0-7;era 1:0-7;cp.b 100000 40000000 $(filesize);" \
+"update=protect off 1:0-7;era 1:0-7;cp.b 100000 40000000 ${filesize};" \
"cp.b 200000 40050000 14000\0"
#define CONFIG_BOOTCOMMAND \
#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
#define CFG_DISCOVER_PHY
+#define CONFIG_MII
#if 0
#define CONFIG_ETHADDR 00:0B:64:00:00:00 /* our OUI from IEEE */
usb stop; bootm 200000\0" \
"nfs_boot=dhcp;run nfsargs addip addhw;bootm 200000\0" \
"panic_boot=echo No Bootdevice !!! reset\0" \
-"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0" \
+"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
-"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip)" \
- ":$(netmask):$(hostname):$(netdev):off\0" \
-"addhw=setenv bootargs $(bootargs) hw=$(hw) key1=$(key1) panic=1\0" \
+"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}" \
+ ":${netmask}:${hostname}:${netdev}:off\0" \
+"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0" \
"netdev=eth0\0" \
"silent=1\0" \
"load=tftp 200000 bootloader-4x.bitmap;tftp 100000 bootloader-4x.bin\0" \
-"update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 $(filesize);" \
+"update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 ${filesize};" \
"cp.b 200000 40040000 14000\0"
#define CONFIG_BOOTCOMMAND \
#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
#define CFG_DISCOVER_PHY
+#define CONFIG_MII
#if 0
#define CONFIG_ETHADDR 00:0B:64:80:00:00 /* our OUI from IEEE */
#define CONFIG_CMD_FULL (CFG_CMD_ALL & ~CFG_CMD_BEDBUG \
& ~CFG_CMD_BMP \
& ~CFG_CMD_BSP \
+ & ~CFG_CMD_DISPLAY \
& ~CFG_CMD_DOC \
& ~CFG_CMD_DTT \
& ~CFG_CMD_EEPROM \
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#define CONFIG_HAS_ETH3
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */
#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */
#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 0x4000 /* For IBM 405GPr CPUs */
+#define CFG_DCACHE_SIZE 0x4000 /* For AMCC 405GPr CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
* Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
* Ported to MPC8272ADS board.
*
+ * Copyright (c) 2005 MontaVista Software, Inc.
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ * Added support for PCI bridge on MPC8272ADS
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
* Figure out if we are booting low via flash HRCW or high via the BCSR.
*/
#if (TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */
-# define CFG_LOWBOOT 1
+# define CFG_LOWBOOT 1
#endif
-
/* ADS flavours */
#define CFG_8260ADS 1 /* MPC8260ADS */
#define CFG_8266ADS 2 /* MPC8266ADS */
#define CFG_MDIO_PIN 0x00002000 /* PC18 */
#define CFG_MDC_PIN 0x00001000 /* PC19 */
#else
-#define CFG_MDIO_PIN 0x00400000 /* PC9 */
+#define CFG_MDIO_PIN 0x00400000 /* PC9 */
#define CFG_MDC_PIN 0x00200000 /* PC10 */
#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
#define CFG_I2C_SLAVE 0x7F
#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
-#define CONFIG_SPD_ADDR 0x50
+#define CONFIG_SPD_ADDR 0x50
#endif
#endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
+/*PCI*/
+#ifdef CONFIG_MPC8272
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_BOOTDELAY 0
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
#ifndef CONFIG_SDRAM_PBI
-#define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */
+#define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */
#endif
#ifndef CONFIG_8260_CLKIN
#define CONFIG_BAUDRATE 115200
-#define CFG_EXCLUDE CFG_CMD_BEDBUG | \
+#define CFG_EXCLUDE CFG_CMD_BEDBUG | \
CFG_CMD_BMP | \
CFG_CMD_BSP | \
CFG_CMD_DATE | \
+ CFG_CMD_DISPLAY | \
CFG_CMD_DOC | \
CFG_CMD_DTT | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_ELF | \
CFG_CMD_EXT2 | \
- CFG_CMD_FAT | \
+ CFG_CMD_FAT | \
CFG_CMD_FDC | \
CFG_CMD_FDOS | \
CFG_CMD_HWFLOW | \
CFG_CMD_KGDB | \
CFG_CMD_MMC | \
CFG_CMD_NAND | \
- CFG_CMD_PCI | \
- CFG_CMD_PCMCIA | \
+ CFG_CMD_PCMCIA | \
CFG_CMD_REISER | \
CFG_CMD_SCSI | \
CFG_CMD_SPI | \
CFG_CMD_VFD | \
CFG_CMD_XIMG
-#if CONFIG_ADSTYPE >= CFG_PQ2FADS
+#if CONFIG_ADSTYPE == CFG_8272ADS
+#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
+ CFG_CMD_SDRAM | \
+ CFG_CMD_I2C | \
+ CFG_EXCLUDE ) )
+#elif CONFIG_ADSTYPE >= CFG_PQ2FADS
#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
CFG_CMD_SDRAM | \
CFG_CMD_I2C | \
+ CFG_CMD_PCI | \
CFG_EXCLUDE ) )
#else
#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
- CFG_EXCLUDE ) )
+ CMD_CFG_PCI | \
+ CFG_EXCLUDE ) )
#endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#endif
#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
-#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
+#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
/*
* Miscellaneous configurable options
#define CFG_IMMR 0xF0000000
#define CFG_BCSR 0xF4500000
+#if CONFIG_ADSTYPE == CFG_8272ADS
+#define CFG_PCI_INT 0xF8200000
+#endif
#define CFG_SDRAM_BASE 0x00000000
#define CFG_LSDRAM_BASE 0xFD000000
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-
#ifdef CFG_LOWBOOT
/* PQ2FADS flash HRCW = 0x0EB4B645 */
#define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
# define CFG_ENV_SIZE 0x200
#endif /* CFG_RAMBOOT */
-
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
-
#define CFG_HID0_INIT 0
#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
#define CFG_BR1_PRELIM CFG_BCSR | 0x00001801
#define CFG_OR1_PRELIM 0xFFFF8010
+/*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/
+
+#if CONFIG_ADSTYPE == CFG_8272ADS
+#define CFG_BR3_PRELIM (CFG_PCI_INT | 0x1801) /* PCI interrupt controller */
+#define CFG_OR3_PRELIM 0xFFFF8010
+#endif
+
#define CFG_RMR RMR_CSRE
#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
#define CFG_RESET_ADDRESS 0x04400000
+#if CONFIG_ADSTYPE == CFG_8272ADS
+
+/* PCI Memory map (if different from default map */
+#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */
+#define CFG_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
+#define CFG_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
+ PICMR_PREFETCH_EN)
+
+/*
+ * These are the windows that allow the CPU to access PCI address space.
+ * All three PCI master windows, which allow the CPU to access PCI
+ * prefetch, non prefetch, and IO space (see below), must all fit within
+ * these windows.
+ */
+
+/*
+ * Master window that allows the CPU to access PCI Memory (prefetch).
+ * This window will be setup with the second set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CFG_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
+#define CFG_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
+#define CFG_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
+#define CFG_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
+#define CFG_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
+
+/*
+ * Master window that allows the CPU to access PCI Memory (non-prefetch).
+ * This window will be setup with the second set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CFG_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
+#define CFG_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
+#define CFG_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
+#define CFG_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
+#define CFG_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
+
+/*
+ * Master window that allows the CPU to access PCI IO space.
+ * This window will be setup with the first set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CFG_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */
+#define CFG_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
+#define CFG_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
+#define CFG_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */
+#define CFG_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
+
+
+/* PCIBR0 - for PCI IO*/
+#define CFG_PCI_MSTR0_LOCAL CFG_PCI_MSTR_IO_LOCAL /* Local base */
+#define CFG_PCIMSK0_MASK ~(CFG_PCI_MSTR_IO_SIZE - 1U) /* Size of window */
+/* PCIBR1 - prefetch and non-prefetch regions joined together */
+#define CFG_PCI_MSTR1_LOCAL CFG_PCI_MSTR_MEM_LOCAL
+#define CFG_PCIMSK1_MASK ~(CFG_PCI_MSTR_MEM_SIZE + CFG_PCI_MSTR_MEMIO_SIZE - 1U)
+
+#endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/
+
+#if CONFIG_ADSTYPE == CFG_8272ADS
+#define CONFIG_HAS_ETH1
+#endif
+
#endif /* __CONFIG_H */
*/
/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
- !! !!
+ !! !!
!! This configuration requires JP3 to be in position 1-2 to work !!
- !! To make it work for the default, the TEXT_BASE define in !!
+ !! To make it work for the default, the TEXT_BASE define in !!
!! board/mpc8266ads/config.mk must be changed from 0xfe000000 to !!
!! 0xfff00000 !!
!! The CFG_HRCW_MASTER define below must also be changed to match !!
- !! !!
+ !! !!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
*/
* Definitions for Serial Presence Detect EEPROM address
* (to get SDRAM settings)
*/
-#define SPD_EEPROM_ADDRESS 0x50
+#define SPD_EEPROM_ADDRESS 0x50
#define CONFIG_8260_CLKIN 66000000 /* in Hz */
#define CONFIG_BAUDRATE 115200
-#define CONFIG_COMMANDS ( CFG_CMD_ALL & ~( \
- CFG_CMD_BEDBUG | \
+#define CONFIG_COMMANDS ( CFG_CMD_ALL & ~( \
+ CFG_CMD_BEDBUG | \
CFG_CMD_BMP | \
CFG_CMD_BSP | \
CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DISPLAY | \
CFG_CMD_DOC | \
CFG_CMD_DTT | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_ELF | \
CFG_CMD_EXT2 | \
CFG_CMD_FDC | \
CFG_CMD_FDOS | \
CFG_CMD_KGDB | \
CFG_CMD_MMC | \
CFG_CMD_NAND | \
- CFG_CMD_PCMCIA | \
+ CFG_CMD_PCMCIA | \
CFG_CMD_REISER | \
CFG_CMD_SCSI | \
CFG_CMD_SPI | \
/* Define a command string that is automatically executed when no character
* is read on the console interface withing "Boot Delay" after reset.
*/
-#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
-#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
+#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
+#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
#ifdef CONFIG_BOOT_ROOT_INITRD
#define CONFIG_BOOTCOMMAND \
"echo;" \
"bootp;" \
"setenv bootargs root=/dev/ram0 rw " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"bootm"
#endif /* CONFIG_BOOT_ROOT_INITRD */
"version;" \
"echo;" \
"bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"bootm"
#endif /* CONFIG_BOOT_ROOT_NFS */
/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers 2-11
+ * HIDx - Hardware Implementation-dependent Registers 2-11
*-----------------------------------------------------------------------
* HID0 also contains cache control - initially enable both caches and
* invalidate contents, then the final state leaves only the instruction
* 0x80000000-0x9FFFFFFF 512MB outbound prefetchable PCI memory window
* 0xA0000000-0xBFFFFFFF 512MB outbound non-prefetchable PCI memory window
* 0xF0000000-0xF001FFFF 128KB MPC8266 internal memory
- * 0xF4000000-0xF7FFFFFF 64MB outbound PCI I/O window
+ * 0xF4000000-0xF7FFFFFF 64MB outbound PCI I/O window
* 0xF8000000-0xF8007FFF 32KB BCSR
* 0xF8100000-0xF8107FFF 32KB ATM UNI
* 0xF8200000-0xF8207FFF 32KB PCI interrupt controller
* in the bridge.
*/
-#define CFG_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
-#define CFG_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
-#define CFG_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
-#define CFG_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
+#define CFG_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
+#define CFG_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
+#define CFG_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
+#define CFG_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
#define CFG_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
/*
* in the bridge.
*/
-#define CFG_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
-#define CFG_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
-#define CFG_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
-#define CFG_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
-#define CFG_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
+#define CFG_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
+#define CFG_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
+#define CFG_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
+#define CFG_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
+#define CFG_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
/*
* Master window that allows the CPU to access PCI IO space.
* in the bridge.
*/
-#define CFG_PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */
-#define CFG_PCI_MSTR_IO_BUS 0xF4000000 /* PCI base */
-#define CFG_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
-#define CFG_PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */
-#define CFG_POCMR2_MASK_ATTRIB (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO)
+#define CFG_PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */
+#define CFG_PCI_MSTR_IO_BUS 0xF4000000 /* PCI base */
+#define CFG_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
+#define CFG_PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */
+#define CFG_POCMR2_MASK_ATTRIB (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO)
/*
* JFFS2 partitions
#define CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#undef CONFIG_TSEC_ENET /* tsec ethernet support */
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
+#define CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_DLL /* possible DLL fix needed */
#define CFG_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */
#define CFG_BR5_PRELIM (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V)
+#define CONFIG_HAS_ETH1
+
#endif /* __CONFIG_H */
"flashboot=setenv bootargs root=/dev/mtdblock5 ro rootfstype=jffs2;run addcons;bootm ffc00000\0" \
"safeboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=cramfs;run addcons;bootm ffc00000\0" \
"hdboot=setenv bootargs root=/dev/hda1;run addcons;bootm ffc00000\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off\0" \
- "addcons=setenv bootargs $(bootargs) console=ttyS$(console_nr),$(baudrate)N8\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \
+ "addcons=setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8\0" \
"mv_version=" MV_VERSION "\0" \
"bootretry=30\0"
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw"
#define CONFIG_BOOTCOMMAND \
"bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"bootm"
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define SCL 0x1000 /* PA 3 */
#define SDA 0x2000 /* PA 2 */
-#define PAR immr->im_ioport.iop_papar
-#define DIR immr->im_ioport.iop_padir
-#define DAT immr->im_ioport.iop_padat
-
-#define I2C_INIT {PAR &= ~(SCL | SDA); DIR |= SCL;}
-#define I2C_ACTIVE (DIR |= SDA)
-#define I2C_TRISTATE (DIR &= ~SDA)
-#define I2C_READ ((DAT & SDA) != 0)
-#define I2C_SDA(bit) if (bit) DAT |= SDA; \
- else DAT &= ~SDA
-#define I2C_SCL(bit) if (bit) DAT |= SCL; \
- else DAT &= ~SCL
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
+#define __I2C_DIR immr->im_ioport.iop_padir
+#define __I2C_DAT immr->im_ioport.iop_padat
+#define __I2C_PAR immr->im_ioport.iop_papar
+#define I2C_INIT { __I2C_PAR &= ~(SDA|SCL); \
+ __I2C_DIR |= (SDA|SCL); }
+#define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0)
+#define I2C_SDA(x) { if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; }
+#define I2C_SCL(x) { if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; }
+#define I2C_DELAY { udelay(5); }
+#define I2C_ACTIVE { __I2C_DIR |= SDA; }
+#define I2C_TRISTATE { __I2C_DIR &= ~SDA; }
#define CONFIG_RTC_PCF8563
#define CFG_I2C_RTC_ADDR 0x51
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/NSCU/uImage\0" \
"kernel_addr=40080000\0" \
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
"netdev=eth0\0" \
"hostname=p3g4\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
- "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
"flash_nfs=run nfsargs addip addtty;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addtty;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_74xx\0" \
"bootfile=/tftpboot/p3g4/uImage\0" \
"ramdisk_addr=ff010000\0" \
"load=tftp 100000 /tftpboot/p3g4/u-boot.bin\0" \
"update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \
- "cp.b 100000 fff00000 $(filesize);" \
+ "cp.b 100000 fff00000 ${filesize};" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
""
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
+#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_PCI_IO_SIZE 0x01000000
#define CONFIG_NET_MULTI 1
+#define CONFIG_MII 1
#define CONFIG_EEPRO100 1
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#undef CONFIG_NS8382X
"netdev=eth0\0" \
"hostname=pm520\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk30/ppc_82xx\0" \
"bootfile=/tftpboot/PM520/uImage\0" \
""
* Flash configuration (8,16 or 32 MB)
* TEXT base always at 0xFFF00000
* ENV_ADDR always at 0xFFF40000
- * FLASH_BASE at 0xFC000000 for 32 MB
+ * FLASH_BASE at 0xFA000000 for 64 MB
+ * 0xFC000000 for 32 MB
* 0xFD000000 for 16 MB
* 0xFD800000 for 8 MB
*/
-#define CFG_FLASH_BASE 0xfc000000
-#define CFG_FLASH_SIZE 0x02000000
+#define CFG_FLASH_BASE 0xFA000000
+#define CFG_FLASH_SIZE 0x04000000
#define CFG_BOOTROM_BASE 0xFFF00000
#define CFG_BOOTROM_SIZE 0x00080000
#define CFG_ENV_ADDR (0xFDF00000 + 0x40000)
* Flash configuration (8,16 or 32 MB)
* TEXT base always at 0xFFF00000
* ENV_ADDR always at 0xFFF40000
- * FLASH_BASE at 0xFE000000 for 32 MB
+ * FLASH_BASE at 0xFC000000 for 64 MB
+ * 0xFE000000 for 32 MB
* 0xFF000000 for 16 MB
* 0xFF800000 for 8 MB
*/
-#define CFG_FLASH_BASE 0xfe000000
-#define CFG_FLASH_SIZE 0x02000000
+#define CFG_FLASH_BASE 0xFC000000
+#define CFG_FLASH_SIZE 0x04000000
#define CFG_ENV_ADDR (0xFFF00000 + 0x40000)
#endif
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
-#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
+#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
#define CFG_CS0_SIZE CFG_BOOTROM_SIZE
#define CFG_CS1_START CFG_FLASH_BASE
#define CFG_CS1_SIZE CFG_FLASH_SIZE
-#define CFG_CS1_CFG 0x0004fb00
+#define CFG_CS1_CFG 0x0004FF00
#else
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG 0x0004fb00
+#define CFG_BOOTCS_CFG 0x0004FF00
#define CFG_CS0_START CFG_FLASH_BASE
#define CFG_CS0_SIZE CFG_FLASH_SIZE
#define CFG_CS1_START CFG_DOC_BASE
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
/* enable I2C and select the hardware/software driver */
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"bootm"
/* enable I2C and select the hardware/software driver */
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#undef CONFIG_EEPRO100
-#undef CONFIG_TULIP
+#define CONFIG_EEPRO100
+#define CONFIG_E1000
+#undef CONFIG_TULIP
#if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR 0xe0000000
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_EEPROM \
| CFG_CMD_DATE \
+ | CFG_CMD_MII \
| CFG_CMD_PCI \
| CFG_CMD_PING \
| CFG_CMD_I2C)
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_EEPROM \
| CFG_CMD_DATE \
+ | CFG_CMD_MII \
| CFG_CMD_PING \
| CFG_CMD_I2C)
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+#define CONFIG_NET_MULTI 1
+#undef CONFIG_HAS_ETH1
+
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
+
+#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_BSP | \
#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0408 /* PCI Device ID: PMC-405 */
+#define CFG_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID: Non-Monarch */
+#define CFG_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID: Monarch */
+#define CFG_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid()
+
#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
+
+#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
+#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
+#if 1
+#define CFG_PCI_PTM2LA 0xef000000 /* point to internal regs */
+#define CFG_PCI_PTM2MS 0xff000001 /* 16MB, enable */
+#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
+#else /* old mapping */
#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
+#endif
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
-#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#undef CFG_FLASH_PROTECTION /* don't use hardware protection */
-#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_FLASH_BASE 0xFE000000
#define CFG_FLASH_INCREMENT 0x01000000
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CFG_FLASH_PROTECTION 1 /* don't use hardware protection */
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + CFG_FLASH_INCREMENT }
+#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
+
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
/*
/* No command line, one static partition, whole device */
#undef CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_DEV "nor0"
-#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+#define CONFIG_JFFS2_PART_SIZE 0x01b00000
+#define CONFIG_JFFS2_PART_OFFSET 0x00400000
/* mtdparts command line support */
/* Note: fake mtd_id used, no linux mtd map file */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
+#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */
#define CAN_BA 0xF0000000 /* CAN Base Address */
#define RTC_BA 0xF0000500 /* RTC Base Address */
-#define CF_BA 0xF0100000 /* CompactFlash Base Address */
+#define NVRAM_BA 0xF0200000 /* NVRAM Base Address */
/* Memory Bank 0 (Flash Bank 0) initialization */
#define CFG_EBC_PB0AP 0x92015480
#define CFG_EBC_PB2AP 0x03000440 /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
#define CFG_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization */
-#define CFG_EBC_PB3AP 0x010059C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR CF_BA | 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+/* Memory Bank 3 -> unused */
+
+/* Memory Bank 4 (NVRAM) initialization */
+#define CFG_EBC_PB4AP 0x03000440 /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
+#define CFG_EBC_PB4CR NVRAM_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
/*-----------------------------------------------------------------------
* FPGA stuff
#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
/*-----------------------------------------------------------------------
+ * GPIOs
+ */
+#define CFG_NONMONARCH (0x80000000 >> 14) /* GPIO24 */
+#define CFG_XEREADY (0x80000000 >> 15) /* GPIO15 */
+#define CFG_INTA_FAKE (0x80000000 >> 19) /* GPIO19 */
+#define CFG_SELF_RST (0x80000000 >> 21) /* GPIO21 */
+#define CFG_REV1_2 (0x80000000 >> 23) /* GPIO23 */
+
+/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in data cache)
*/
#define CONFIG_BOOTCOMMAND \
"setenv verify y;" \
"setenv bootargs console=ttyS0,19200 mem=31M quiet " \
- "root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip)::$(netmask):pn62:eth0:off;" \
+ "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \
"loadp 100000; bootm"
/* "tftpboot 100000 uImage; bootm" */
#else
"setenv verify n;" \
"setenv bootargs console=ttyS0,19200 mem=31M quiet " \
"root=/dev/ram rw " \
- "ip=$(ipaddr):$(serverip)::$(netmask):pn62:eth0:off;" \
+ "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \
"loadp 200000; bootm"
#endif
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
+
+/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
+#define CONFIG_NEW_NAND_CODE
#define CFG_NAND0_BASE 0xFF400000
#define CFG_NAND1_BASE 0xFF000000
-
-#define CFG_MAX_NAND_DEVICE 2 /* Max number of NAND devices */
+#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, CFG_NAND1_BASE }
+#define NAND_BIG_DELAY_US 25
+#define CFG_MAX_NAND_DEVICE 2 /* Max number of NAND devices */
#define SECTORSIZE 512
#define NAND_NO_RB
#define CFG_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */
#define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
+#ifdef CONFIG_NEW_NAND_CODE
+#define MACRO_NAND_DISABLE_CE(nandptr) do \
+{ \
+ switch((unsigned long)nandptr) \
+ { \
+ case CFG_NAND0_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
+ break; \
+ case CFG_NAND1_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
+ break; \
+ } \
+} while(0)
+
+#define MACRO_NAND_ENABLE_CE(nandptr) do \
+{ \
+ switch((unsigned long)nandptr) \
+ { \
+ case CFG_NAND0_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
+ break; \
+ case CFG_NAND1_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
+ break; \
+ } \
+} while(0)
+
+#define MACRO_NAND_CTL_CLRALE(nandptr) do \
+{ \
+ switch((unsigned long)nandptr) \
+ { \
+ case CFG_NAND0_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
+ break; \
+ case CFG_NAND1_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
+ break; \
+ } \
+} while(0)
+
+#define MACRO_NAND_CTL_SETALE(nandptr) do \
+{ \
+ switch((unsigned long)nandptr) \
+ { \
+ case CFG_NAND0_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
+ break; \
+ case CFG_NAND1_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
+ break; \
+ } \
+} while(0)
+
+#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
+{ \
+ switch((unsigned long)nandptr) \
+ { \
+ case CFG_NAND0_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
+ break; \
+ case CFG_NAND1_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
+ break; \
+ } \
+} while(0)
+
+#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
+ switch((unsigned long)nandptr) { \
+ case CFG_NAND0_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
+ break; \
+ case CFG_NAND1_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
+ break; \
+ } \
+} while(0)
+#else
#define NAND_DISABLE_CE(nand) do \
{ \
switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
break; \
} \
} while(0)
+#endif /* !CONFIG_NEW_NAND_CODE */
#ifdef NAND_NO_RB
/* constant delay (see also tR in the datasheet) */
#define CFG_SDRAM_BASE 0x00000000
/* Reserve 256 kB for Monitor */
+/*
#define CFG_FLASH_BASE 0xFFFC0000
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MONITOR_LEN (256 * 1024)
+*/
/* Reserve 320 kB for Monitor */
-/*
#define CFG_FLASH_BASE 0xFFFB0000
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MONITOR_LEN (320 * 1024)
-*/
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
+#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_QS860T 1 /* ...on a QS860T module */
#define CONFIG_FEC_ENET 1 /* FEC 10/100BaseT ethernet */
+#define CONFIG_MII
#define FEC_INTERRUPT SIU_LEVEL1
#undef CONFIG_SCC1_ENET /* SCC1 10BaseT ethernet */
#define CFG_DISCOVER_PHY
#undef CONFIG_BOOTARGS
/* TODO compare against CADM860 */
#define CONFIG_BOOTCOMMAND "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#undef CONFIG_SCC1_ENET
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_COMMANDS ( CFG_CMD_ALL & \
~CFG_CMD_BSP & \
~CFG_CMD_DATE & \
+ ~CFG_CMD_DISPLAY& \
~CFG_CMD_DTT & \
~CFG_CMD_EXT2 & \
~CFG_CMD_FDC & \
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"tftpboot; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs console=tty0 console=ttyS0,9600 " \
- "root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0" \
+ "root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs console=tty0 root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"gatewayip=172.16.115.254\0" \
"netmask=255.255.255.0\0" \
"kernel_addr=ff040000\0" \
"ramdisk_addr=ff200000\0" \
- "ku=era $(kernel_addr) ff1fffff;cp.b 100000 $(kernel_addr) " \
- "$(filesize);md $(kernel_addr);" \
+ "ku=era ${kernel_addr} ff1fffff;cp.b 100000 ${kernel_addr} " \
+ "${filesize};md ${kernel_addr};" \
"echo kernel updating finished\0" \
"uu=protect off 1:0-4;era 1:0-4;cp.b 100000 ff000000 " \
- "$(filesize);md ff000000;" \
+ "${filesize};md ff000000;" \
"echo u-boot updating finished\0" \
"eu=protect off 1:6;era 1:6;reset\0" \
"lcd=setenv stdout lcd;setenv stdin lcd\0" \
"netdev=eth0\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
- "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip)" \
- ":$(gatewayip):$(netmask):$(hostname):$(netdev):off\0" \
- "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}" \
+ ":${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
"load=tftp 100000 /tftpboot/u-boot.bin\0" \
"update=protect off 1:0-8;era 1:0-8;" \
- "cp.b 100000 40000000 $(filesize);" \
+ "cp.b 100000 40000000 ${filesize};" \
"setenv filesize;saveenv\0" \
"kernel_addr=40040000\0" \
"ramdisk_addr=40100000\0" \
"kernel_img=/tftpboot/uImage\0" \
- "kernel_load=tftp 200000 $(kernel_img)\0" \
+ "kernel_load=tftp 200000 ${kernel_img}\0" \
"net_nfs=run kernel_load nfsargs addip addtty;bootm\0" \
- "flash_nfs=run nfsargs addip addtty;bootm $(kernel_addr)\0" \
+ "flash_nfs=run nfsargs addip addtty;bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addtty;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0"
+ "bootm ${kernel_addr} ${ramdisk_addr}\0"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
/* enable I2C and select the hardware/software driver */
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
# define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
+#define CONFIG_MII 1
#define CFG_DISCOVER_PHY
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
- "net_self=tftp $(kernel_addr) $(bootfile);" \
- "tftp $(ramdisk_addr) $(ramdisk);" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "net_self=tftp ${kernel_addr} ${bootfile};" \
+ "tftp ${ramdisk_addr} ${ramdisk};" \
"run ramargs addip;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp $(kernel_addr) $(bootfile);" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp ${kernel_addr} ${bootfile};" \
"run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_82xx\0" \
"bootfile=/tftpboot/SP8240/uImage\0" \
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_82xx\0" \
"bootfile=/tftpboot/MPC5200/uImage\0" \
""
#if defined (CONFIG_SOFT_I2C)
#define SDA 0x00010
#define SCL 0x00020
-#define DIR immr->im_cpm.cp_pbdir
-#define DAT immr->im_cpm.cp_pbdat
-#define PAR immr->im_cpm.cp_pbpar
-#define ODR immr->im_cpm.cp_pbodr
-#define I2C_INIT {PAR&=~(SDA|SCL);ODR&=~(SDA|SCL);DAT|=(SDA|SCL);DIR|=(SDA|SCL);}
-#define I2C_READ ((DAT&SDA)?1:0)
-#define I2C_SDA(x) {if(x)DAT|=SDA;else DAT&=~SDA;}
-#define I2C_SCL(x) {if(x)DAT|=SCL;else DAT&=~SCL;}
-#define I2C_DELAY {udelay(5);}
-#define I2C_ACTIVE {DIR|=SDA;}
-#define I2C_TRISTATE {DIR&=~SDA;}
+#define __I2C_DIR immr->im_cpm.cp_pbdir
+#define __I2C_DAT immr->im_cpm.cp_pbdat
+#define __I2C_PAR immr->im_cpm.cp_pbpar
+#define __I2C_ODR immr->im_cpm.cp_pbodr
+#define I2C_INIT { __I2C_PAR &= ~(SDA|SCL); \
+ __I2C_ODR &= ~(SDA|SCL); \
+ __I2C_DAT |= (SDA|SCL); \
+ __I2C_DIR|=(SDA|SCL); }
+#define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0)
+#define I2C_SDA(x) { if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; }
+#define I2C_SCL(x) { if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; }
+#define I2C_DELAY { udelay(5); }
+#define I2C_ACTIVE { __I2C_DIR |= SDA; }
+#define I2C_TRISTATE { __I2C_DIR &= ~SDA; }
#endif
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
/*
#define CONFIG_PCI_IO_SIZE 0x01000000
#define CONFIG_NET_MULTI 1
-#define CONFIG_EEPRO100 1
+#define CONFIG_EEPRO100
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
#endif /* CONFIG_STK52XX */
CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
+ CFG_CMD_JFFS2 | \
CFG_CMD_MII | \
CFG_CMD_NFS | \
CFG_CMD_PING | \
CFG_CMD_POST_DIAG | \
CFG_CMD_REGINFO | \
- CFG_CMD_SNTP )
+ CFG_CMD_SNTP | \
+ CFG_CMD_BSP)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
"rootpath=/opt/eldk/ppc_6xx\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
"flash_self=run ramargs addip;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
"flash_nfs=run nfsargs addip;" \
- "bootm $(kernel_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "bootm ${kernel_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"bootfile=/tftpboot/tqm5200/uImage\0" \
- "load=tftp 200000 $(u-boot)\0" \
+ "load=tftp 200000 ${u-boot}\0" \
"u-boot=/tftpboot/tqm5200/u-boot.bin" CONFIG_U_BOOT_SUFFIX \
"update=protect off FC000000 FC05FFFF;" \
"erase FC000000 FC05FFFF;" \
- "cp.b 200000 FC000000 $(filesize);" \
+ "cp.b 200000 FC000000 ${filesize};" \
"protect on FC000000 FC05FFFF\0" \
""
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
+/* Dynamic MTD partition support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=TQM5200-0"
+#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
+ "1408k(kernel)," \
+ "2m(initrd)," \
+ "4m(small-fs)," \
+ "16m(big-fs)," \
+ "8m(misc)"
/*
* Environment settings
#endif
#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
-#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
/*
* RTC configuration
*/
-#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
+#if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100)
+# define CONFIG_RTC_M41T11 1
+# define CFG_I2C_RTC_ADDR 0x68
+#else
+# define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
+#endif
/*
* Miscellaneous configurable options
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM823L/uImage\0" \
"kernel_addr=40040000\0" \
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM823M/uImage\0" \
"kernel_addr=40080000\0" \
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_82xx\0" \
"bootfile=/tftpboot/TQM8260/uImage\0" \
"kernel_addr=40040000\0" \
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * TQM8349 board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define DEBUG
+#undef DEBUG
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1 /* E300 Family */
+#define CONFIG_MPC83XX 1 /* MPC83XX family */
+#define CONFIG_MPC834X 1 /* MPC834X specific */
+#define CONFIG_TQM834X 1 /* TQM834X board specific */
+
+/* IMMR Base Addres Register, use Freescale default: 0xff400000 */
+#define CFG_IMMRBAR 0xff400000
+
+/* System clock. Primary input clock when in PCI host mode */
+#define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */
+
+/*
+ * Local Bus LCRR
+ * LCRR: DLL bypass, Clock divider is 8
+ *
+ * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
+ *
+ * External Local Bus rate is
+ * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
+ */
+#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8)
+
+/* board pre init: do not call, nothing to do */
+#undef CONFIG_BOARD_EARLY_INIT_F
+
+/* detect the number of flash banks */
+#define CONFIG_BOARD_EARLY_INIT_R
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
+#define CFG_SDRAM_BASE CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
+#define DDR_CASLAT_25 /* CASLAT set to 2.5 */
+#undef CONFIG_DDR_ECC /* only for ECC DDR module */
+#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
+
+#undef CFG_DRAM_TEST /* memory test, takes time */
+#define CFG_MEMTEST_START 0x00000000 /* memtest region */
+#define CFG_MEMTEST_END 0x00100000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI /* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_BASE 0x80000000 /* start of FLASH */
+
+/* buffered writes in the AMD chip set is not supported yet */
+#undef CFG_FLASH_USE_BUFFER_WRITE
+
+/*
+ * FLASH bank number detection
+ */
+
+/*
+ * When CFG_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash
+ * banks has to be determined at runtime and stored in a gloabl variable
+ * tqm834x_num_flash_banks. The value of CFG_MAX_FLASH_BANKS_DETECT is only
+ * used instead of CFG_MAX_FLASH_BANKS to allocate the array flash_info, and
+ * should be made sufficiently large to accomodate the number of banks that
+ * might actually be detected. Since most (all?) Flash related functions use
+ * CFG_MAX_FLASH_BANKS as the number of actual banks on the board, it is
+ * defined as tqm834x_num_flash_banks.
+ */
+#define CFG_MAX_FLASH_BANKS_DETECT 2
+#ifndef __ASSEMBLY__
+extern int tqm834x_num_flash_banks;
+#endif
+#define CFG_MAX_FLASH_BANKS (tqm834x_num_flash_banks)
+
+#define CFG_MAX_FLASH_SECT 512 /* max sectors per device */
+
+/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
+#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA) | \
+ BR_MS_GPCM | BR_PS_32 | BR_V)
+
+/* FLASH timing (0x0000_0c54) */
+#define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_0b10 | \
+ OR_GPCM_SCY_5 | OR_GPCM_TRLX)
+
+#define CFG_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */
+
+#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+
+#define CFG_LBLAWAR0_PRELIM 0x8000001D /* 1 GiB window size (2^(size + 1)) */
+
+#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
+
+/* disable remaining mappings */
+#define CFG_BR1_PRELIM 0x00000000
+#define CFG_OR1_PRELIM 0x00000000
+#define CFG_LBLAWBAR1_PRELIM 0x00000000
+#define CFG_LBLAWAR1_PRELIM 0x00000000
+
+#define CFG_BR2_PRELIM 0x00000000
+#define CFG_OR2_PRELIM 0x00000000
+#define CFG_LBLAWBAR2_PRELIM 0x00000000
+#define CFG_LBLAWAR2_PRELIM 0x00000000
+
+#define CFG_BR3_PRELIM 0x00000000
+#define CFG_OR3_PRELIM 0x00000000
+#define CFG_LBLAWBAR3_PRELIM 0x00000000
+#define CFG_LBLAWAR3_PRELIM 0x00000000
+
+#define CFG_BR4_PRELIM 0x00000000
+#define CFG_OR4_PRELIM 0x00000000
+#define CFG_LBLAWBAR4_PRELIM 0x00000000
+#define CFG_LBLAWAR4_PRELIM 0x00000000
+
+#define CFG_BR5_PRELIM 0x00000000
+#define CFG_OR5_PRELIM 0x00000000
+#define CFG_LBLAWBAR5_PRELIM 0x00000000
+#define CFG_LBLAWAR5_PRELIM 0x00000000
+
+#define CFG_BR6_PRELIM 0x00000000
+#define CFG_OR6_PRELIM 0x00000000
+#define CFG_LBLAWBAR6_PRELIM 0x00000000
+#define CFG_LBLAWAR6_PRELIM 0x00000000
+
+#define CFG_BR7_PRELIM 0x00000000
+#define CFG_OR7_PRELIM 0x00000000
+#define CFG_LBLAWBAR7_PRELIM 0x00000000
+#define CFG_LBLAWAR7_PRELIM 0x00000000
+
+/*
+ * Monitor config
+ */
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef CFG_RAMBOOT
+#endif
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
+
+#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1 (CFG_IMMRBAR + 0x4500)
+#define CFG_NS16550_COM2 (CFG_IMMRBAR + 0x4600)
+
+/*
+ * I2C
+ */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed: 400KHz */
+#define CFG_I2C_SLAVE 0x7F /* slave address */
+#define CFG_I2C_OFFSET 0x3000
+
+/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
+#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
+#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes per write */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
+#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
+
+/* I2C RTC */
+#define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
+#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
+
+/* I2C SYSMON (LM75) */
+#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
+#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
+#define CFG_DTT_MAX_TEMP 70
+#define CFG_DTT_LOW_TEMP -30
+#define CFG_DTT_HYSTERESIS 3
+
+/*
+ * TSEC
+ */
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_MII
+
+#define CFG_TSEC1_OFFSET 0x24000
+#define CFG_TSEC1 (CFG_IMMRBAR + CFG_TSEC1_OFFSET)
+#define CFG_TSEC2_OFFSET 0x25000
+#define CFG_TSEC2 (CFG_IMMRBAR + CFG_TSEC2_OFFSET)
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI
+#endif
+
+#define CONFIG_MPC83XX_TSEC1 1
+#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
+#define CONFIG_MPC83XX_TSEC2 1
+#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
+#define TSEC1_PHY_ADDR 2
+#define TSEC2_PHY_ADDR 1
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME "TSEC0"
+
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_PCI
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+/* PCI1 host bridge */
+#define CFG_PCI1_MEM_BASE 0xc0000000
+#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI1_IO_BASE 0xe2000000
+#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
+#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
+
+
+#undef CONFIG_EEPRO100
+#define CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+ #define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE
+ #define PCI_ENET0_MEMADDR CFG_PCI1_MEM_BASE
+ #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */
+#endif
+
+#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
+
+#endif /* CONFIG_PCI */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#ifndef CFG_RAMBOOT
+ #define CFG_ENV_IS_IN_FLASH 1
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+ #define CFG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */
+ #define CFG_ENV_SIZE 0x2000
+#else
+ #define CFG_NO_FLASH 1 /* Flash is not usable now */
+ #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
+ #define CFG_ENV_SIZE 0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/* Common commands */
+#define CFG_CMD_TQM8349_COMMON CFG_CMD_DATE | CFG_CMD_I2C | CFG_CMD_DTT\
+ | CFG_CMD_PING | CFG_CMD_EEPROM \
+ | CFG_CMD_MII | CFG_CMD_JFFS2
+
+#if defined(CFG_RAMBOOT)
+
+#if defined(CONFIG_PCI)
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI \
+ | CFG_CMD_TQM8349_COMMON) \
+ & \
+ ~(CFG_CMD_ENV | CFG_CMD_LOADS))
+#else
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
+ | CFG_CMD_TQM8349_COMMON) \
+ & \
+ ~(CFG_CMD_ENV | CFG_CMD_LOADS))
+#endif
+
+#else /* CFG_RAMBOOT */
+
+#if defined(CONFIG_PCI)
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI \
+ | CFG_CMD_TQM8349_COMMON)
+#else
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_TQM8349_COMMON)
+#endif
+
+#endif /* CFG_RAMBOOT */
+
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LOAD_ADDR 0x2000000 /* default load address */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+
+/*
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 32768
+#define CFG_CACHELINE_SIZE 32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
+#endif
+
+#define CFG_HRCW_LOW (\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+ HRCWL_DDR_TO_SCB_CLK_1X1 |\
+ HRCWL_CSB_TO_CLKIN_4X1 |\
+ HRCWL_VCO_1X2 |\
+ HRCWL_CORE_TO_CSB_2X1)
+
+#if defined(PCI_64BIT)
+#define CFG_HRCW_HIGH (\
+ HRCWH_PCI_HOST |\
+ HRCWH_64_BIT_PCI |\
+ HRCWH_PCI1_ARBITER_ENABLE |\
+ HRCWH_PCI2_ARBITER_DISABLE |\
+ HRCWH_CORE_ENABLE |\
+ HRCWH_FROM_0X00000100 |\
+ HRCWH_BOOTSEQ_DISABLE |\
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_ROM_LOC_LOCAL_16BIT |\
+ HRCWH_TSEC1M_IN_GMII |\
+ HRCWH_TSEC2M_IN_GMII )
+#else
+#define CFG_HRCW_HIGH (\
+ HRCWH_PCI_HOST |\
+ HRCWH_32_BIT_PCI |\
+ HRCWH_PCI1_ARBITER_ENABLE |\
+ HRCWH_PCI2_ARBITER_DISABLE |\
+ HRCWH_CORE_ENABLE |\
+ HRCWH_FROM_0X00000100 |\
+ HRCWH_BOOTSEQ_DISABLE |\
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_ROM_LOC_LOCAL_16BIT |\
+ HRCWH_TSEC1M_IN_GMII |\
+ HRCWH_TSEC2M_IN_GMII )
+#endif
+
+/* i-cache and d-cache disabled */
+#define CFG_HID0_INIT 0x000000000
+#define CFG_HID0_FINAL CFG_HID0_INIT
+#define CFG_HID2 0x000000000
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR D2:DA:5E:44:BC:29
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR 1E:F3:40:21:92:53
+#endif
+
+#define CONFIG_IPADDR 192.168.205.1
+
+#define CONFIG_HOSTNAME tqm8349
+#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx
+#define CONFIG_BOOTFILE /tftpboot/tqm83xx/uImage
+
+#define CONFIG_SERVERIP 192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK 255.255.255.0
+
+#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=tqm83xx\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/opt/eldk/ppc_6xx\0" \
+ "bootfile=/tftpboot/tqm83xx/uImage\0" \
+ "kernel_addr=80060000\0" \
+ "ramdisk_addr=80160000\0" \
+ "load=tftp 100000 /tftpboot/tqm83xx/u-boot.bin\0" \
+ "update=protect off 80000000 8003ffff; " \
+ "era 80000000 8003ffff; cp.b 100000 80000000 40000\0" \
+ "upd=run load;run update\0" \
+ ""
+
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+/*
+ * JFFS2 partitions
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=TQM834x-0"
+
+/* default mtd partition table */
+#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),128k(env),"\
+ "1m(kernel),2m(initrd),"\
+ "-(user);"\
+
+#endif /* __CONFIG_H */
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM850L/uImage\0" \
"kernel_addr=40040000\0" \
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM850M/uImage\0" \
"kernel_addr=40080000\0" \
+++ /dev/null
-/*
- * Copyright 2005 DENX Software Engineering
- * Wolfgang Denk <wd@denx.de>
- * Copyright 2004 Freescale Semiconductor.
- * (C) Copyright 2002,2003 Motorola,Inc.
- * Xianghua Xiao <X.Xiao@motorola.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * TQM8540 board configuration file
- *
- * Make sure you change the MAC address and other network params first,
- * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
-#define CONFIG_MPC8540 1 /* MPC8540 specific */
-#define CONFIG_TQM8540 1 /* TQM8540 board specific */
-
-#undef CONFIG_PCI
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
-#undef CONFIG_DDR_ECC /* only for ECC DDR module */
-#define CONFIG_DDR_DLL /* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
-
-/*
- * sysclk for MPC85xx
- *
- * Two valid values are:
- * 33000000
- * 66000000
- *
- * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
- * is likely the desired value here, so that is now the default.
- * The board, however, can run at 66MHz. In any event, this value
- * must match the settings of some switches. Details can be found
- * in the README.mpc85xxads.
- */
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ 33000000
-#endif
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-
-#undef CFG_DRAM_TEST /* memory test, takes time */
-#define CFG_MEMTEST_START 0x00000000 /* memtest region */
-#define CFG_MEMTEST_END 0x10000000
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
-#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
-#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
-
-/*
- * DDR Setup
- */
-#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
-#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
-
-#if defined(CONFIG_SPD_EEPROM)
- /*
- * Determine DDR configuration from I2C interface.
- */
- #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
-
-#else
- /*
- * Manually set up DDR parameters
- */
- #define CFG_SDRAM_SIZE 512 /* DDR is 256MB */
- #define CFG_DDR_CS0_BNDS 0x0000001f /* 0-256MB */
- #define CFG_DDR_CS0_CONFIG 0x80000102
- #define CFG_DDR_TIMING_1 0x47445331
- #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
- #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
- #define CFG_DDR_MODE 0x40020062 /* DLL,normal,seq,4/2.5 */
- #define CFG_DDR_INTERVAL 0x05160100 /* autocharge,no open page */
-#endif
-
-/*
- * Flash on the Local Bus
- */
-#define CFG_LBC_FLASH_BASE 0xfe000000 /* Localbus SDRAM */
-#define CFG_LBC_FLASH_SIZE 32 /* LBC SDRAM is 32MB */
-
-#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH 32M */
-#define CFG_BR0_PRELIM 0xfe001801 /* port size 32bit */
-
-#define CFG_OR0_PRELIM 0xfe000040 /* 32MB Flash */
-#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
-#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
-#undef CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
-
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
-#else
-#undef CFG_RAMBOOT
-#endif
-
-#define CFG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
-#define CFG_FLASH_EMPTY_INFO
-
-#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
-#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
-#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
-#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
-
-/*
- * LSDMR masks
- */
-#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
-#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
-#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
-#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16))
-#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
-#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
-#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
-#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
-#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
-#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
-#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
-#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27))
-#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
-#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29))
-#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
-
-#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
-
-#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \
- | CFG_LBC_LSDMR_RFCR5 \
- | CFG_LBC_LSDMR_PRETOACT3 \
- | CFG_LBC_LSDMR_ACTTORW3 \
- | CFG_LBC_LSDMR_BL8 \
- | CFG_LBC_LSDMR_WRC2 \
- | CFG_LBC_LSDMR_CL3 \
- | CFG_LBC_LSDMR_RFEN \
- )
-
-/*
- * SDRAM Controller configuration sequence.
- */
-#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
- | CFG_LBC_LSDMR_OP_PCHALL)
-#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
- | CFG_LBC_LSDMR_OP_ARFRSH)
-#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
- | CFG_LBC_LSDMR_OP_ARFRSH)
-#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
- | CFG_LBC_LSDMR_OP_MRW)
-#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
- | CFG_LBC_LSDMR_OP_NORMAL)
-
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 1
-#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
-
-#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
-
-/* Serial Port */
-#define CONFIG_CONS_INDEX 1
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE 1
-#define CFG_NS16550_CLK get_bus_freq(0)
-
-#define CFG_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
-
-/* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
-#endif
-
-/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
-#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
-
-/* RapidIO MMU */
-#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
-#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
-#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CFG_PCI1_MEM_BASE 0x80000000
-#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CFG_PCI1_IO_BASE 0xe2000000
-#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
-
-#if defined(CONFIG_PCI)
-
-#define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
-#undef CONFIG_EEPRO100
-#undef CONFIG_TULIP
-
-#if !defined(CONFIG_PCI_PNP)
- #define PCI_ENET0_IOADDR 0xe0000000
- #define PCI_ENET0_MEMADDR 0xe0000000
- #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
-#endif
-
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
-
-#endif /* CONFIG_PCI */
-
-
-#if defined(CONFIG_TSEC_ENET)
-
-#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 1
-#endif
-
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1 1
-#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
-#define CONFIG_MPC85XX_TSEC2 1
-#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
-#define TSEC1_PHY_ADDR 0
-#define TSEC2_PHY_ADDR 1
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-
-#define CONFIG_MPC85XX_FEC 1
-#define CONFIG_MPC85XX_FEC_NAME "FEC"
-#define FEC_PHY_ADDR 2
-#define FEC_PHYIDX 0
-
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-
-/* Options are TSEC[0-1], FEC */
-#define CONFIG_ETHPRIME "TSEC1"
-
-#endif /* CONFIG_TSEC_ENET */
-
-
-/*
- * Environment
- */
-#ifndef CFG_RAMBOOT
- #define CFG_ENV_IS_IN_FLASH 1
- #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000)
- #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
- #define CFG_ENV_SIZE 0x2000
- #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET-CFG_ENV_SECT_SIZE)
- #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
-#else
- #define CFG_NO_FLASH 1 /* Flash is not usable now */
- #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
- #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
- #define CFG_ENV_SIZE 0x2000
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-#if defined(CFG_RAMBOOT)
-# define CONFIG_CMD_PRIV (CONFIG_CMD_DFL & ~(CFG_CMD_ENV | CFG_CMD_LOADS))
-#else
-# define CONFIG_CMD_PRIV (CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-#endif
-
-#if defined(CONFIG_PCI)
-# define ADD_PCI_CMD (CFG_CMD_PCI)
-#else
-# define ADD_PCI_CMD 0
-#endif
-
-#define CONFIG_COMMANDS (CONFIG_CMD_PRIV | \
- ADD_PCI_CMD | \
- CFG_CMD_I2C | \
- CFG_CMD_PING )
-#include <cmd_confdefs.h>
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_LOAD_ADDR 0x2000000 /* default load address */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
- #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
- #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
-
-/* Cache Configuration */
-#define CFG_DCACHE_SIZE 32768
-#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-
-#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
-
-#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consdev=ttyS0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $bootargs " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
- ":$hostname:$netdev:off panic=1\0" \
- "addcons=setenv bootargs $bootargs " \
- "console=$consdev,$baudrate\0" \
- "flash_nfs=run nfsargs addip addcons;" \
- "bootm $kernel_addr\0" \
- "flash_self=run ramargs addip addcons;" \
- "bootm $kernel_addr $ramdisk_addr\0" \
- "net_nfs=tftp $loadaddr $bootfile;" \
- "run nfsargs addip addcons;bootm\0" \
- "rootpath=/opt/eldk/ppc_85xx\0" \
- "bootfile=/tftpboot/tqm8540/uImage\0" \
- "kernel_addr=FE000000\0" \
- "ramdisk_addr=FE100000\0" \
- ""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#endif /* __CONFIG_H */
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM855L/uImage\0" \
"kernel_addr=40040000\0" \
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM855M/uImage\0" \
"kernel_addr=40080000\0" \
+++ /dev/null
-/*
- * Copyright 2005 DENX Software Engineering
- * Wolfgang Denk <wd@denx.de>
- * Copyright 2004 Freescale Semiconductor.
- * (C) Copyright 2002,2003 Motorola,Inc.
- * Xianghua Xiao <X.Xiao@motorola.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * TQM8560 board configuration file
- *
- * Make sure you change the MAC address and other network params first,
- * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
-#define CONFIG_MPC8560 1 /* MPC8560 specific */
-#define CONFIG_TQM8560 1 /* TQM8560 board specific */
-
-#undef CONFIG_PCI
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
-#undef CONFIG_DDR_ECC /* only for ECC DDR module */
-#define CONFIG_DDR_DLL /* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
-
-/*
- * sysclk for MPC85xx
- *
- * Two valid values are:
- * 33000000
- * 66000000
- *
- * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
- * is likely the desired value here, so that is now the default.
- * The board, however, can run at 66MHz. In any event, this value
- * must match the settings of some switches. Details can be found
- * in the README.mpc85xxads.
- */
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ 33000000
-#endif
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-
-#undef CFG_DRAM_TEST /* memory test, takes time */
-#define CFG_MEMTEST_START 0x00000000 /* memtest region */
-#define CFG_MEMTEST_END 0x10000000
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
-#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
-#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
-
-/*
- * DDR Setup
- */
-#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
-#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
-
-#if defined(CONFIG_SPD_EEPROM)
- /*
- * Determine DDR configuration from I2C interface.
- */
- #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
-
-#else
- /*
- * Manually set up DDR parameters
- */
- #define CFG_SDRAM_SIZE 512 /* DDR is 256MB */
- #define CFG_DDR_CS0_BNDS 0x0000001f /* 0-256MB */
- #define CFG_DDR_CS0_CONFIG 0x80000102
- #define CFG_DDR_TIMING_1 0x47445331
- #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
- #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
- #define CFG_DDR_MODE 0x40020062 /* DLL,normal,seq,4/2.5 */
- #define CFG_DDR_INTERVAL 0x05160100 /* autocharge,no open page */
-#endif
-
-/*
- * Flash on the Local Bus
- */
-#define CFG_LBC_FLASH_BASE 0xfe000000 /* Localbus SDRAM */
-#define CFG_LBC_FLASH_SIZE 32 /* LBC SDRAM is 32MB */
-
-#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH 32M */
-#define CFG_BR0_PRELIM 0xfe001801 /* port size 32bit */
-
-#define CFG_OR0_PRELIM 0xfe000040 /* 32MB Flash */
-#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
-#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
-#undef CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
-
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
-#else
-#undef CFG_RAMBOOT
-#endif
-
-#define CFG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
-#define CFG_FLASH_EMPTY_INFO
-
-#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
-#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
-#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
-#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
-
-/*
- * LSDMR masks
- */
-#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
-#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
-#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
-#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16))
-#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
-#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
-#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
-#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
-#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
-#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
-#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
-#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27))
-#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
-#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29))
-#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
-
-#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
-
-#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \
- | CFG_LBC_LSDMR_RFCR5 \
- | CFG_LBC_LSDMR_PRETOACT3 \
- | CFG_LBC_LSDMR_ACTTORW3 \
- | CFG_LBC_LSDMR_BL8 \
- | CFG_LBC_LSDMR_WRC2 \
- | CFG_LBC_LSDMR_CL3 \
- | CFG_LBC_LSDMR_RFEN \
- )
-
-/*
- * SDRAM Controller configuration sequence.
- */
-#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
- | CFG_LBC_LSDMR_OP_PCHALL)
-#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
- | CFG_LBC_LSDMR_OP_ARFRSH)
-#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
- | CFG_LBC_LSDMR_OP_ARFRSH)
-#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
- | CFG_LBC_LSDMR_OP_MRW)
-#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
- | CFG_LBC_LSDMR_OP_NORMAL)
-
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 1
-#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
-
-#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
-
-/* Serial Port */
-#define CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on something else */
-#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
-
-#define CONFIG_BAUDRATE 115200
-
-#define CFG_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-/* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
-#endif
-
-/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
-#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
-
-/* RapidIO MMU */
-#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
-#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
-#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CFG_PCI1_MEM_BASE 0x80000000
-#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CFG_PCI1_IO_BASE 0xe2000000
-#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
-
-#if defined(CONFIG_PCI)
-
-#define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
-#undef CONFIG_EEPRO100
-#undef CONFIG_TULIP
-
-#if !defined(CONFIG_PCI_PNP)
- #define PCI_ENET0_IOADDR 0xe0000000
- #define PCI_ENET0_MEMADDR 0xe0000000
- #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
-#endif
-
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
-
-#endif /* CONFIG_PCI */
-
-
-#if defined(CONFIG_TSEC_ENET)
-
-#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 1
-#endif
-
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MPC85XX_TSEC2 1
-#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
-#define TSEC2_PHY_ADDR 1
-#define TSEC2_PHYIDX 0
-
-#endif /* CONFIG_TSEC_ENET */
-
-#define CONFIG_ETHER_ON_FCC
-#define CONFIG_ETHER_ON_FCC3
-#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
-#define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
-#define CFG_CPMFCR_RAMTYPE 0
-#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
-
-#define CONFIG_ETHPRIME "TSEC1"
-
-/*
- * Environment
- */
-#ifndef CFG_RAMBOOT
- #define CFG_ENV_IS_IN_FLASH 1
- #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000)
- #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
- #define CFG_ENV_SIZE 0x2000
- #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET-CFG_ENV_SECT_SIZE)
- #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
-#else
- #define CFG_NO_FLASH 1 /* Flash is not usable now */
- #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
- #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
- #define CFG_ENV_SIZE 0x2000
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-#if defined(CFG_RAMBOOT)
-# define CONFIG_CMD_PRIV (CONFIG_CMD_DFL & ~(CFG_CMD_ENV | CFG_CMD_LOADS))
-#else
-# define CONFIG_CMD_PRIV (CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-#endif
-
-#if defined(CONFIG_PCI)
-# define ADD_PCI_CMD (CFG_CMD_PCI)
-#else
-# define ADD_PCI_CMD 0
-#endif
-
-#define CONFIG_COMMANDS (CONFIG_CMD_PRIV | \
- ADD_PCI_CMD | \
- CFG_CMD_I2C | \
- CFG_CMD_PING )
-#include <cmd_confdefs.h>
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_LOAD_ADDR 0x2000000 /* default load address */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
- #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
- #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
-
-/* Cache Configuration */
-#define CFG_DCACHE_SIZE 32768
-#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-
-#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
-
-#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consdev=ttyS0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $bootargs " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
- ":$hostname:$netdev:off panic=1\0" \
- "addcons=setenv bootargs $bootargs " \
- "console=$consdev,$baudrate\0" \
- "flash_nfs=run nfsargs addip addcons;" \
- "bootm $kernel_addr\0" \
- "flash_self=run ramargs addip addcons;" \
- "bootm $kernel_addr $ramdisk_addr\0" \
- "net_nfs=tftp $loadaddr $bootfile;" \
- "run nfsargs addip addcons;bootm\0" \
- "rootpath=/opt/eldk/ppc_85xx\0" \
- "bootfile=/tftpboot/tqm8560/uImage\0" \
- "kernel_addr=FE000000\0" \
- "ramdisk_addr=FE100000\0" \
- ""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Wolfgang Denk <wd@denx.de>
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * TQM85xx (8560/40/55/41) board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE 1 /* BOOKE */
+#define CONFIG_E500 1 /* BOOKE e500 family */
+#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
+
+#define CONFIG_PCI
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+
+/*
+ * Only MPC8540 doesn't have CPM module
+ */
+#ifndef CONFIG_MPC8540
+#define CONFIG_CPM2 1 /* has CPM2 */
+#endif
+
+/*
+ * sysclk for MPC85xx
+ *
+ * Two valid values are:
+ * 33000000
+ * 66000000
+ *
+ * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
+ * is likely the desired value here, so that is now the default.
+ * The board, however, can run at 66MHz. In any event, this value
+ * must match the settings of some switches. Details can be found
+ * in the README.mpc85xxads.
+ */
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ 33333333
+#endif
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+
+#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
+
+#undef CFG_DRAM_TEST /* memory test, takes time */
+#define CFG_MEMTEST_START 0x00000000
+#define CFG_MEMTEST_END 0x10000000
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
+#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
+#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
+#define CONFIG_ADD_RAM_INFO 1 /* print additional info*/
+
+#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
+/* TQM8540 & 8560 need DLL-override */
+#define CONFIG_DDR_DLL /* DLL fix needed */
+#define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */
+#endif /* defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) */
+
+#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
+#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
+#endif /* defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) */
+
+/*
+ * Flash on the Local Bus
+ */
+#define CFG_FLASH0 0xFC000000
+#define CFG_FLASH1 0xF8000000
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 }
+
+#define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */
+#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */
+
+#define CFG_BR0_PRELIM 0xfc001801 /* port size 32bit */
+#define CFG_OR0_PRELIM 0xfc000040 /* 64MB Flash */
+#define CFG_BR1_PRELIM 0xf8001801 /* port size 32bit */
+#define CFG_OR1_PRELIM 0xfc000040 /* 64MB Flash */
+
+#define CFG_FLASH_CFI /* flash is CFI compat. */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
+#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
+
+#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
+#define CFG_MAX_FLASH_SECT 512 /* sectors per device */
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
+#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
+#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
+#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+
+/* Serial Port */
+#if defined(CONFIG_TQM8560)
+
+#define CONFIG_CONS_ON_SCC /* define if console on SCC */
+#undef CONFIG_CONS_NONE /* define if console on something else */
+#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
+
+#else
+
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK get_bus_freq(0)
+
+#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
+
+#endif /* CONFIG_TQM8560 */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */
+
+/* I2C RTC */
+#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
+#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
+
+/* I2C EEPROM */
+/*
+ * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
+ */
+#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
+#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
+
+/* I2C SYSMON (LM75) */
+#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
+#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
+#define CFG_DTT_MAX_TEMP 70
+#define CFG_DTT_LOW_TEMP -30
+#define CFG_DTT_HYSTERESIS 3
+
+/* RapidIO MMU */
+#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
+#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
+#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE 0x80000000
+#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI1_IO_BASE 0xe2000000
+#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
+#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#define CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+
+#endif /* CONFIG_PCI */
+
+
+#define CONFIG_NET_MULTI 1
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_MPC85XX_TSEC1 1
+#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
+#define CONFIG_MPC85XX_TSEC2 1
+#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
+#define TSEC1_PHY_ADDR 2
+#define TSEC2_PHY_ADDR 1
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+#define FEC_PHY_ADDR 3
+#define FEC_PHYIDX 0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+
+/* Options are TSEC[0-1], FEC */
+#define CONFIG_ETHPRIME "TSEC0"
+
+#if defined(CONFIG_TQM8540)
+/*
+ * TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC.
+ * The FEC port is connected on the same signals as the FCC3 port
+ * of the TQM8560 to the baseboard (STK85xx Starterkit).
+ *
+ * On the STK85xx Starterkit the X47/X50 jumper has to be set to
+ * a - d (X50.2 - 3) to enable the FEC port.
+ */
+#define CONFIG_MPC85XX_FEC 1
+#define CONFIG_MPC85XX_FEC_NAME "FEC"
+#endif
+
+#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
+/*
+ * TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port
+ * can be used at once, since only one FCC port is available on the STK85xx
+ * Starterkit.
+ *
+ * To use this port you have to configure U-Boot to use the FCC port 1...2
+ * and set the X47/X50 jumper to:
+ * FCC1: a - b (X47.2 - X50.2)
+ * FCC2: a - c (X50.2 - 1)
+ */
+#define CONFIG_ETHER_ON_FCC
+#define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */
+#endif
+
+#if defined(CONFIG_TQM8560)
+/*
+ * TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port
+ * can be used at once, since only one FCC port is available on the STK85xx
+ * Starterkit.
+ *
+ * To use this port you have to configure U-Boot to use the FCC port 1...3
+ * and set the X47/X50 jumper to:
+ * FCC1: a - b (X47.2 - X50.2)
+ * FCC2: a - c (X50.2 - 1)
+ * FCC3: a - d (X50.2 - 3)
+ */
+#define CONFIG_ETHER_ON_FCC
+#define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */
+#endif
+
+#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
+#define CONFIG_ETHER_ON_FCC1
+#define CFG_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
+#define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
+#define CFG_CPMFCR_RAMTYPE 0
+#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
+#endif
+
+#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
+#define CONFIG_ETHER_ON_FCC2
+#define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+#define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13)
+#define CFG_CPMFCR_RAMTYPE 0
+#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
+#endif
+
+#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
+#define CONFIG_ETHER_ON_FCC3
+#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
+#define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
+#define CFG_CPMFCR_RAMTYPE 0
+#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
+#endif
+
+/*
+ * Environment
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000)
+#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
+#define CFG_ENV_SIZE 0x2000
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_TIMESTAMP /* Print image info with ts */
+
+#if defined(CONFIG_PCI)
+# define ADD_PCI_CMD (CFG_CMD_PCI)
+#else
+# define ADD_PCI_CMD 0
+#endif
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_NFS | \
+ CFG_CMD_SNTP | \
+ ADD_PCI_CMD | \
+ CFG_CMD_I2C | \
+ CFG_CMD_DATE | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_DTT | \
+ CFG_CMD_MII | \
+ CFG_CMD_PING )
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LOAD_ADDR 0x2000000 /* default load address */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE 32768
+#define CFG_CACHELINE_SIZE 32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+
+#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
+
+#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CFG_BOOTFILE \
+ "netdev=eth0\0" \
+ "consdev=ttyS0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs $bootargs " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
+ ":$hostname:$netdev:off panic=1\0" \
+ "addcons=setenv bootargs $bootargs " \
+ "console=$consdev,$baudrate\0" \
+ "flash_nfs=run nfsargs addip addcons;" \
+ "bootm $kernel_addr\0" \
+ "flash_self=run ramargs addip addcons;" \
+ "bootm $kernel_addr $ramdisk_addr\0" \
+ "net_nfs=tftp $loadaddr $bootfile;" \
+ "run nfsargs addip addcons;bootm\0" \
+ "rootpath=/opt/eldk/ppc_85xx\0" \
+ "kernel_addr=FE000000\0" \
+ "ramdisk_addr=FE100000\0" \
+ "load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0" \
+ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
+ "cp.b 100000 fffc0000 40000;" \
+ "setenv filesize;saveenv\0" \
+ "upd=run load;run update\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#endif /* __CONFIG_H */
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM860L/uImage\0" \
"kernel_addr=40040000\0" \
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM860M/uImage\0" \
"kernel_addr=40080000\0" \
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM862L/uImage\0" \
"kernel_addr=40040000\0" \
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM862M/uImage\0" \
"kernel_addr=40080000\0" \
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM866M/uImage\0" \
"kernel_addr=40080000\0" \
#define CONFIG_PCI_IO_SIZE 0x01000000
#define CONFIG_NET_MULTI 1
+#define CONFIG_MII 1
#define CONFIG_EEPRO100 1
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
#else /* MGT5100 */
+#define CONFIG_MII 1
#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_82xx\0" \
"bootfile=/tftpboot/MPC5200/uImage\0" \
""
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
+#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */
#define CFG_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */
-#define CFG_LCD_LOGO_MAX_SIZE (1024*1024)
+#define CFG_VIDEO_LOGO_MAX_SIZE (1 << 20)
/*-----------------------------------------------------------------------
* FPGA stuff
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+#define CONFIG_NET_MULTI 1
+#undef CONFIG_HAS_ETH1
+
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
CONFIG_BOOTP_DNS | \
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
+#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"clean_nv=erase fff20000 ffffffff\0" \
-"update_boss=tftp 100000 PPC/logic157.bin; protect off fff00000 ffffffff; erase fff00000 ffffffff; cp.b 100000 fff00000 $(filesize); tftp 100000 PPC/bootmon157.bin; cp.b 100000 fff20000 $(filesize)\0" \
-"update_lx=tftp 100000 $(kernel); erase $(kernel_addr) ffefffff; cp.b 100000 $(kernel_addr) $(filesize)\0" \
-"update_fs=tftp 100000 $(fs).$(fstype); erase ff840000 ffdfffff; cp.b 100000 ff840000 $(filesize)\0" \
-"update_ub=tftp 100000 $(uboot); protect off fff00000 fff1ffff; erase fff00000 fff1ffff; cp.b 100000 fff00000 $(filesize); protect off ff820000 ff83ffff; erase ff820000 ff83ffff\0" \
-"flashargs=setenv bootargs root=$(rootdev) rw rootfstype=$(fstype)\0" \
-"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0" \
-"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname):$(netdev):off\0" \
-"addmisc=setenv bootargs $(bootargs) console=$(console),$(baudrate) ethaddr=$(ethaddr) panic=1\0" \
-"net_nfs=tftpboot 400000 $(kernel); run nfsargs addip addmisc; bootm\0" \
-"net_self=tftpboot 400000 $(kernel); run flashargs addmisc; bootm\0" \
-"flash_self=run flashargs addmisc; bootm $(kernel_addr)\0" \
-"flash_nfs=run nfsargs addip addmisc; bootm $(kernel_addr)\0" \
+"update_boss=tftp 100000 PPC/logic157.bin; protect off fff00000 ffffffff; erase fff00000 ffffffff; cp.b 100000 fff00000 ${filesize}; tftp 100000 PPC/bootmon157.bin; cp.b 100000 fff20000 ${filesize}\0" \
+"update_lx=tftp 100000 ${kernel}; erase ${kernel_addr} ffefffff; cp.b 100000 ${kernel_addr} ${filesize}\0" \
+"update_fs=tftp 100000 ${fs}.${fstype}; erase ff840000 ffdfffff; cp.b 100000 ff840000 ${filesize}\0" \
+"update_ub=tftp 100000 ${uboot}; protect off fff00000 fff1ffff; erase fff00000 fff1ffff; cp.b 100000 fff00000 ${filesize}; protect off ff820000 ff83ffff; erase ff820000 ff83ffff\0" \
+"flashargs=setenv bootargs root=${rootdev} rw rootfstype=${fstype}\0" \
+"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
+"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \
+"addmisc=setenv bootargs ${bootargs} console=${console},${baudrate} ethaddr=${ethaddr} panic=1\0" \
+"net_nfs=tftpboot 400000 ${kernel}; run nfsargs addip addmisc; bootm\0" \
+"net_self=tftpboot 400000 ${kernel}; run flashargs addmisc; bootm\0" \
+"flash_self=run flashargs addmisc; bootm ${kernel_addr}\0" \
+"flash_nfs=run nfsargs addip addmisc; bootm ${kernel_addr}\0" \
"fstype=cramfs\0" \
"rootpath=/root_fs\0" \
"uboot=PPC/u-boot.bin\0" \
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
+#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
* config for XPedite1000 from XES Inc.
* Ported from EBONY config by Travis B. Sawyer <tsawyer@sandburst.com>
* (C) Copyright 2003 Sandburst Corporation
- * board/config_EBONY.h - configuration for IBM 440GP Ref (Ebony)
+ * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
***********************************************************************/
#ifndef __CONFIG_H
#define CONFIG_PHY3_ADDR 8 /* PHY address phy3 */
#define CONFIG_NET_MULTI 1
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 8192 /* For IBM 440GX CPUs */
+#define CFG_DCACHE_SIZE 8192 /* For AMCC 440GX CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
CFG_CMD_SNTP )
#define CONFIG_NET_MULTI
+#define CONFIG_MII
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
"rootpath=/opt/eldk/ppc_6xx\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath) " \
- "console=ttyS0,$(baudrate)\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
+ "nfsroot=${serverip}:${rootpath} " \
+ "console=ttyS0,${baudrate}\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
"flash_self=run ramargs addip;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
"flash_nfs=run nfsargs addip;" \
- "bootm $(kernel_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "bootm ${kernel_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"bootfile=/tftpboot/tqm5200/uImage\0" \
- "load=tftp 200000 $(u-boot)\0" \
+ "load=tftp 200000 ${u-boot}\0" \
"u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
"update=protect off FC000000 FC05FFFF;" \
"erase FC000000 FC05FFFF;" \
- "cp.b 200000 FC000000 $(filesize);" \
+ "cp.b 200000 FC000000 ${filesize};" \
"protect on FC000000 FC05FFFF\0" \
""
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuation settings for the EP7312 board.
+ *
+ * Modified to work on Armadillo HT1070 ARM720T board
+ * (C) Copyright 2005 Rowel Atienza rowel@diwalabs.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * If we are developing, we might want to start armboot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ */
+/*#define CONFIG_INIT_CRITICAL*/ /* undef for developing */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM7 1 /* This is a ARM7 CPU */
+#define CONFIG_ARMADILLO 1 /* on an Armadillo Board */
+#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */
+#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
+
+#undef CONFIG_USE_IRQ /* don't need them anymore */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
+#define CS8900_BASE 0x20000300 /* armadillo board */
+#define CS8900_BUS16 1
+#undef CS8900_BUS32
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1 1 /* we use Serial line 1 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL) /* | CFG_CMD_JFFS2)*/
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTARGS "root=/dev/ram0 rootfstype=ext2 console=ttyAM0,115200"
+
+#define CONFIG_BOOTCOMMAND "bootm 40000 180000"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "ARMADILLO # " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0xc0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR 0x00040000 /* default load address for armadillo: kernel img is here*/
+
+#define CFG_HZ 2000 /* decrementer freq: 2 kHz */
+
+ /* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB armadillo SDRAM */
+
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE 0x00400000 /* 4 MB */
+
+#define CFG_FLASH_BASE PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* Addr of Environment Sector */
+#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#endif /* __CONFIG_H */
/* #define CONFIG_ENV_OVERWRITE 1 */
#define CONFIG_COMMANDS \
- ((CONFIG_CMD_DFL | \
+ ((CONFIG_CMD_DFL | CFG_CMD_MII |\
CFG_CMD_DHCP ) & \
~(CFG_CMD_BDI | \
CFG_CMD_IMI | \
#define CONFIG_BOOTCOMMAND \
"bootp;" \
"setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"\
+ "nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"\
"bootm"
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/
#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
-#define CFG_INIT_RAM_END (8 << 10)
+#define CFG_INIT_RAM_END (4 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
* DDR SDRAM
*----------------------------------------------------------------------------- */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
-#define SPD_EEPROM_ADDRESS {0x50,0x51} /* SPD i2c spd addresses */
-#define CFG_SDRAM_ONBOARD_SIZE (64 << 20) /* Bamboo has onboard and DIMM-slots!*/
+#undef CONFIG_DDR_ECC /* don't use ECC */
+#define CFG_SIMULATE_SPD_EEPROM 0xff /* simulate spd eeprom on this address */
+#define SPD_EEPROM_ADDRESS {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51}
/*-----------------------------------------------------------------------
* I2C
"netdev=eth0\0" \
"hostname=bamboo\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
- "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
"flash_nfs=run nfsargs addip addtty;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addtty;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/bamboo/uImage\0" \
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
+#define CONFIG_PHY1_ADDR 1
#ifndef CONFIG_BAMBOO_NAND
-#define CONFIG_NET_MULTI 1 /* required for netconsole */
-#define CONFIG_PHY1_ADDR 1
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#endif /* CONFIG_BAMBOO_NAND */
-#define CONFIG_NO_PHY_RESET 1 /* no PHY reset on bamboo!!! */
-
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+#define CONFIG_NET_MULTI 1 /* required for netconsole */
+
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
CFG_CMD_USB | \
+ CFG_CMD_FAT | \
+ CFG_CMD_EXT2 | \
_CFG_CMD_NAND | \
CFG_CMD_SNTP )
+#define CONFIG_SUPPORT_VFAT
+
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE (32<<10) /* For IBM 440 CPUs */
+#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
--- /dev/null
+/********************************************************************
+ *
+ * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms
+ *
+ * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/include/configs/barco.h,v $
+ * $Revision: 1.2 $
+ * $Author: mleeman $
+ * $Date: 2005/02/21 12:48:58 $
+ *
+ * Last ChangeLog Entry
+ * $Log: barco.h,v $
+ * Revision 1.2 2005/02/21 12:48:58 mleeman
+ * update of copyright years (feedback wd)
+ *
+ * Revision 1.1 2005/02/14 09:29:25 mleeman
+ * moved barcohydra.h to barco.h
+ *
+ * Revision 1.4 2005/02/09 12:56:23 mleeman
+ * add generic header to track changes in sources
+ *
+ *
+ *******************************************************************/
+
+/*
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC824X 1
+#define CONFIG_MPC8245 1
+#define CONFIG_BARCOBCD_STREAMING 1
+
+#undef USE_DINK32
+
+#define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */
+#define CONFIG_BAUDRATE 9600
+#define CONFIG_DRAM_SPEED 100 /* MHz */
+
+#define CONFIG_BOOTARGS "mem=32M"
+
+/* Add support for a few extra bootp options like:
+ * - File size
+ * - DNS
+ */
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
+ CONFIG_BOOTP_BOOTFILESIZE | \
+ CONFIG_BOOTP_DNS)
+
+#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+ CFG_CMD_ELF | \
+ CFG_CMD_I2C | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_PCI )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_HUSH_PARSER 1 /* use "hush" command parser */
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_BOOTCOMMAND "boot_default"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP 1 /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR 0x00100000 /* default load address */
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_PCI /* include pci support */
+#undef CONFIG_PCI_PNP
+#undef CFG_CMD_NET
+
+#define PCI_ENET0_IOADDR 0x80000000
+#define PCI_ENET0_MEMADDR 0x80000000
+#define PCI_ENET1_IOADDR 0x81000000
+#define PCI_ENET1_MEMADDR 0x81000000
+
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_MAX_RAM_SIZE 0x02000000
+
+#define CONFIG_LOGBUFFER
+#ifdef CONFIG_LOGBUFFER
+#define CFG_STDOUT_ADDR 0x1FFC000
+#else
+#define CFG_STDOUT_ADDR 0x2B9000
+#endif
+
+#define CFG_RESET_ADDRESS 0xFFF00100
+
+#if defined (USE_DINK32)
+#define CFG_MONITOR_LEN 0x00030000
+#define CFG_MONITOR_BASE 0x00090000
+#define CFG_RAMBOOT 1
+#define CFG_INIT_RAM_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_INIT_RAM_END 0x10000
+#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+#else
+#undef CFG_RAMBOOT
+#define CFG_MONITOR_LEN 0x00030000
+#define CFG_MONITOR_BASE TEXT_BASE
+
+#define CFG_GBL_DATA_SIZE 128
+
+#define CFG_INIT_RAM_ADDR 0x40000000
+#define CFG_INIT_RAM_END 0x1000
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#endif
+
+#define CFG_FLASH_BASE 0xFFF00000
+#define CFG_FLASH_SIZE (8 * 1024 * 1024) /* Unity has onboard 1MByte flash */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x000047A4 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
+/* #define ENV_CRC 0x8BF6F24B XXX - FIXME: gets defined automatically */
+
+#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
+
+#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
+#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
+
+#define CFG_EUMB_ADDR 0xFDF00000
+
+#define CFG_FLASH_RANGE_BASE 0xFFC00000 /* flash memory address range */
+#define CFG_FLASH_RANGE_SIZE 0x00400000
+#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */
+#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */
+
+/*
+ * select i2c support configuration
+ *
+ * Supported configurations are {none, software, hardware} drivers.
+ * If the software driver is chosen, there are some additional
+ * configuration items that the driver uses to drive the port pins.
+ */
+#define CONFIG_HARD_I2C 1 /* To enable I2C support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+#ifdef CONFIG_SOFT_I2C
+#error "Soft I2C is not configured properly. Please review!"
+#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE (iop->pdir |= 0x00010000)
+#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
+#define I2C_READ ((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
+ else iop->pdat &= ~0x00010000
+#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
+ else iop->pdat &= ~0x00020000
+#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
+#endif /* CONFIG_SOFT_I2C */
+
+#define CFG_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
+#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
+
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
+#define CFG_DBUS_SIZE2 1
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+
+
+ /*
+ * NS16550 Configuration (internal DUART)
+ */
+ /*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
+
+#define CFG_ROMNAL 0x0F /*rom/flash next access time */
+#define CFG_ROMFAL 0x1E /*rom/flash access time */
+
+#define CFG_REFINT 0x8F /* no of clock cycles between CBR refresh cycles */
+
+/* the following are for SDRAM only*/
+#define CFG_BSTOPRE 0x25C /* Burst To Precharge, sets open page interval */
+#define CFG_REFREC 8 /* Refresh to activate interval */
+#define CFG_RDLAT 4 /* data latency from read command */
+#define CFG_PRETOACT 3 /* Precharge to activate interval */
+#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
+#define CFG_ACTORW 2 /* Activate to R/W */
+#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
+#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
+
+#define CFG_REGISTERD_TYPE_BUFFER 1
+#define CFG_EXTROM 0
+#define CFG_REGDIMM 0
+
+
+/* memory bank settings*/
+/*
+ * only bits 20-29 are actually used from these vales to set the
+ * start/end address the upper two bits will be 0, and the lower 20
+ * bits will be set to 0x00000 for a start address, or 0xfffff for an
+ * end address
+ */
+#define CFG_BANK0_START 0x00000000
+#define CFG_BANK0_END 0x01FFFFFF
+#define CFG_BANK0_ENABLE 1
+#define CFG_BANK1_START 0x02000000
+#define CFG_BANK1_END 0x02ffffff
+#define CFG_BANK1_ENABLE 0
+#define CFG_BANK2_START 0x03f00000
+#define CFG_BANK2_END 0x03ffffff
+#define CFG_BANK2_ENABLE 0
+#define CFG_BANK3_START 0x04000000
+#define CFG_BANK3_END 0x04ffffff
+#define CFG_BANK3_ENABLE 0
+#define CFG_BANK4_START 0x05000000
+#define CFG_BANK4_END 0x05FFFFFF
+#define CFG_BANK4_ENABLE 0
+#define CFG_BANK5_START 0x06000000
+#define CFG_BANK5_END 0x06FFFFFF
+#define CFG_BANK5_ENABLE 0
+#define CFG_BANK6_START 0x07000000
+#define CFG_BANK6_END 0x07FFFFFF
+#define CFG_BANK6_ENABLE 0
+#define CFG_BANK7_START 0x08000000
+#define CFG_BANK7_END 0x08FFFFFF
+#define CFG_BANK7_ENABLE 0
+/*
+ * Memory bank enable bitmask, specifying which of the banks defined above
+ are actually present. MSB is for bank #7, LSB is for bank #0.
+ */
+#define CFG_BANK_ENABLE 0x01
+
+#define CFG_ODCR 0xff /* configures line driver impedances, */
+ /* see 8240 book for bit definitions */
+#define CFG_PGMAX 0x32 /* how long the 8240 retains the */
+ /* currently accessed page in memory */
+ /* see 8240 book for details */
+
+/* SDRAM 0 - 256MB */
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* stack in DCACHE @ 1GB (no backing mem) */
+#if defined(USE_DINK32)
+#define CFG_IBAT1L (0x40000000 | BATL_PP_00 )
+#define CFG_IBAT1U (0x40000000 | BATU_BL_128K )
+#else
+#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#endif
+
+/* PCI memory */
+#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* Flash, config addrs, etc */
+#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L CFG_IBAT0L
+#define CFG_DBAT0U CFG_IBAT0U
+#define CFG_DBAT1L CFG_IBAT1L
+#define CFG_DBAT1U CFG_IBAT1U
+#define CFG_DBAT2L CFG_IBAT2L
+#define CFG_DBAT2U CFG_IBAT2U
+#define CFG_DBAT3L CFG_IBAT3L
+#define CFG_DBAT3U CFG_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 20 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_CHECKSUM
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+/* values according to the manual */
+
+#define CONFIG_DRAM_50MHZ 1
+#define CONFIG_SDRAM_50MHZ
+
+#define CONFIG_DISK_SPINUP_TIME 1000000
+
+
+#endif /* __CONFIG_H */
"netdev=eth0\0" \
"hostname=bubinga\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
- "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
"flash_nfs=run nfsargs addip addtty;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addtty;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/bubinga/uImage\0" \
#define CONFIG_NET_MULTI 1
#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+
#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */
+#define CFG_DCACHE_SIZE 16384 /* For AMCC 405EP CPU */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_6xx\0" \
"bootfile=/tftpboot/canmb/uImage\0" \
""
#define __CONFIG_H
/* ARM asynchronous clock */
-#define AT91C_MAIN_CLOCK 207360000 /* from 18.432 MHz crystal (18432000 / 4 * 45) */
+#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */
#define AT91_SLOW_CLOCK 32768 /* slow clock */
#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
-#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
#define CONFIG_CMC_PU2 1 /* on an CMC_PU2 Board */
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define USE_920T_MMU 1
#define SMC2_CSR_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */
/* clocks */
-#define PLLAR_VAL 0x202CBE04 /* 207.360 MHz for PCK */
+#define PLLAR_VAL 0x2026BE04 /* 179,712 MHz for PCK */
#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
#define CONFIG_EXTRA_ENV_SETTINGS \
- "net_nfs=tftp $(loadaddr) $(bootfile);run nfsargs addip addcons " \
+ "net_nfs=tftp ${loadaddr} ${bootfile};run nfsargs addip addcons " \
"addmtd;bootm\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
- "net_cramfs=tftp $(loadaddr) $(bootfile); run flashargs addip " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "net_cramfs=tftp ${loadaddr} ${bootfile}; run flashargs addip " \
"addcons addmtd; bootm\0" \
"flash_cramfs=run flashargs addip addcons addmtd; bootm 10030000\0" \
"flashargs=setenv bootargs root=/dev/mtdblock3 ro\0" \
- "addip=setenv bootargs $(bootargs) ethaddr=$(ethaddr) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):" \
- "$(hostname)::off\0" \
- "addcons=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0" \
- "addmtd=setenv bootargs $(bootargs) mtdparts=cmc_pu2:128k(uboot)ro," \
+ "addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
+ "${hostname}::off\0" \
+ "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+ "addmtd=setenv bootargs ${bootargs} mtdparts=cmc_pu2:128k(uboot)ro," \
"64k(environment),768k(linux),4096k(root),-\0" \
- "load=tftp $(loadaddr) $(loadfile)\0" \
+ "load=tftp ${loadaddr} ${loadfile}\0" \
"update=protect off 10000000 1001ffff;erase 10000000 1001ffff; " \
- "cp.b $(loadaddr) 10000000 $(filesize);" \
+ "cp.b ${loadaddr} 10000000 ${filesize};" \
"protect on 10000000 1001ffff\0" \
- "updatel=era 10030000 100effff;tftp $(loadaddr) $(bootfile); " \
- "cp.b $(loadaddr) 10030000 $(filesize)\0" \
- "updatec=era 100f0000 104effff;tftp $(loadaddr) $(cramfsimage); " \
- "cp.b $(loadaddr) 100f0000 $(filesize)\0" \
- "updatej=era 104f0000 107fffff;tftp $(loadaddr) $(jffsimage); " \
- "cp.b $(loadaddr) 104f0000 $(filesize)\0" \
+ "updatel=era 10030000 100effff;tftp ${loadaddr} ${bootfile}; " \
+ "cp.b ${loadaddr} 10030000 ${filesize}\0" \
+ "updatec=era 100f0000 104effff;tftp ${loadaddr} ${cramfsimage}; " \
+ "cp.b ${loadaddr} 100f0000 ${filesize}\0" \
+ "updatej=era 104f0000 107fffff;tftp ${loadaddr} ${jffsimage}; " \
+ "cp.b ${loadaddr} 104f0000 ${filesize}\0" \
"cramfsimage=cramfs_cmc-pu2.img\0" \
"jffsimage=jffs2_cmc-pu2.img\0" \
"loadfile=u-boot_cmc-pu2.bin\0" \
--- /dev/null
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+
+ */
+
+/*************************************************************************
+ * (c) 2005 esd gmbh Hannover
+ *
+ *
+ * from IceCube.h file
+ * by Reinhard Arlt reinhard.arlt@esd-electronics.com
+ *
+ *************************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */
+#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
+#define CONFIG_ICECUBE 1 /* ... on IceCube board */
+#define CONFIG_CPCI5200 1 /* ... on CPCI5200 board */
+#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
+
+#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
+
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
+#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#if 1
+#define CONFIG_PCI 1
+#if 1
+#define CONFIG_PCI_PNP 1
+#endif
+#define CONFIG_PCI_SCAN_SHOW 1
+
+#define CONFIG_PCI_MEM_BUS 0x40000000
+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE 0x10000000
+
+#define CONFIG_PCI_IO_BUS 0x50000000
+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE 0x01000000
+#endif
+
+#define CONFIG_MII
+#if 0 /* test-only !!! */
+#define CONFIG_NET_MULTI 1
+#define CONFIG_EEPRO100 1
+#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
+#define CONFIG_NS8382X 1
+#endif
+
+#define ADD_PCI_CMD CFG_CMD_PCI
+
+#else /* MPC5100 */
+
+#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
+
+#endif
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#if 0
+#define CONFIG_USB_OHCI
+#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
+#define CONFIG_USB_STORAGE
+#else
+#define ADD_USB_CMD 0
+#endif
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_FAT | \
+ CFG_CMD_IDE | \
+ CFG_CMD_I2C | \
+ CFG_CMD_BSP | \
+ CFG_CMD_ELF | \
+ CFG_CMD_EXT2 | \
+ CFG_CMD_DATE | \
+ ADD_PCI_CMD )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
+# define CFG_LOWBOOT 1
+# define CFG_LOWBOOT16 1
+#endif
+#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
+# define CFG_LOWBOOT 1
+# define CFG_LOWBOOT08 1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Welcome to esd CPU CPCI/5200;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
+ "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
+ "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
+ "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
+ "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
+ "loadaddr=01000000\0" \
+ "serverip=192.168.2.99\0" \
+ "gatewayip=10.0.0.79\0" \
+ "user=mu\0" \
+ "target=cpci5200.esd\0" \
+ "script=cpci5200.bat\0" \
+ "image=/tftpboot/vxWorks_cpci5200\0" \
+ "ipaddr=10.0.13.196\0" \
+ "netmask=255.255.0.0\0" \
+ ""
+
+#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
+
+#if defined(CONFIG_MPC5200)
+
+#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
+#define CFG_NVRAM_BASE_ADDR 0xfd010000
+#define CFG_NVRAM_SIZE 32*1024
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
+#endif
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */
+
+#define CFG_I2C_SPEED 86000 /* 100 kHz */
+#define CFG_I2C_SLAVE 0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_EEPROM_PAGE_WRITE_BITS 5
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
+#define CFG_I2C_MULTI_EEPROMS 1
+/*
+ * Flash configuration
+ */
+
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_BASE 0xFE000000
+#define CFG_FLASH_SIZE 0x02000000
+#define CFG_FLASH_INCREMENT 0x01000000
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00000000)
+#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
+#define CFG_MAX_FLASH_SECT 128
+
+#define CFG_FLASH_PROTECTION 1 /* use hardware protection */
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+
+#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
+
+/*
+ * Environment settings
+ */
+#if 1 /* test-only */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SIZE 0x20000
+#define CFG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_OVERWRITE 1
+#else
+#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */
+ /* total size of a CAT24WC32 is 8192 bytes */
+#define CONFIG_ENV_OVERWRITE 1
+#endif
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR 0xF0000000
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_DEFAULT_MBAR 0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
+#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+# define CFG_RAMBOOT 1
+#endif
+
+#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC 1
+/*
+ * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ */
+/* #define CONFIG_FEC_10MBIT 1 */
+#define CONFIG_PHY_ADDR 0x00
+#define CONFIG_UDP_CHECKSUM 1
+
+/*
+ * GPIO configuration
+ */
+#define CFG_GPS_PORT_CONFIG 0x01052444
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL HID0_ICE
+#else
+#define CFG_HID0_INIT 0
+#define CFG_HID0_FINAL 0
+#endif
+
+#define CFG_BOOTCS_START CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG 0x0004DD00
+
+#define CFG_CS0_START CFG_FLASH_BASE
+#define CFG_CS0_SIZE CFG_FLASH_SIZE
+
+#define CFG_CS1_START 0xfd000000
+#define CFG_CS1_SIZE 0x00010000
+#define CFG_CS1_CFG 0x10101410
+
+#define CFG_CS3_START 0xfd010000
+#define CFG_CS3_SIZE 0x00010000
+#define CFG_CS3_CFG 0x10109410
+
+#define CFG_CS_BURST 0x00000000
+#define CFG_CS_DEADCYCLE 0x33333333
+
+#define CFG_RESET_ADDRESS 0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK 0x0001BBBB
+#define CONFIG_USB_CONFIG 0x00001000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
+
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
+#undef CONFIG_IDE_LED /* LED for ide not supported */
+
+#define CONFIG_IDE_RESET /* reset for ide supported */
+#define CONFIG_IDE_PREINIT
+
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
+
+#define CFG_ATA_IDE0_OFFSET 0x0000
+
+#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
+
+/* Offset for data I/O */
+#define CFG_ATA_DATA_OFFSET (0x0060)
+
+/* Offset for normal register accesses */
+#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers */
+#define CFG_ATA_ALT_OFFSET (0x005C)
+
+/* Interval between registers */
+#define CFG_ATA_STRIDE 4
+
+/*-----------------------------------------------------------------------
+ * CPLD stuff
+ */
+#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
+#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */
+
+/* CPLD program pin configuration */
+#define CFG_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */
+#define CFG_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */
+#define CFG_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */
+#define CFG_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */
+
+#define JTAG_GPIO_ADDR_TMS (CFG_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */
+#define JTAG_GPIO_ADDR_TCK (CFG_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */
+#define JTAG_GPIO_ADDR_TDI (CFG_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */
+#define JTAG_GPIO_ADDR_TDO (CFG_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */
+
+#define JTAG_GPIO_ADDR_CFG (CFG_MBAR + 0xB00)
+#define JTAG_GPIO_CFG_SET 0x00000000
+#define JTAG_GPIO_CFG_RESET 0x00F00000
+
+#define JTAG_GPIO_ADDR_EN_TMS (CFG_MBAR + 0xB04)
+#define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */
+#define JTAG_GPIO_TMS_EN_RESET 0x00000000
+#define JTAG_GPIO_ADDR_DDR_TMS (CFG_MBAR + 0xB0C)
+#define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */
+#define JTAG_GPIO_TMS_DDR_RESET 0x00000000
+
+#define JTAG_GPIO_ADDR_EN_TCK (CFG_MBAR + 0xC00)
+#define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */
+#define JTAG_GPIO_TCK_EN_RESET 0x00000000
+#define JTAG_GPIO_ADDR_DDR_TCK (CFG_MBAR + 0xC08)
+#define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */
+#define JTAG_GPIO_TCK_DDR_RESET 0x00000000
+
+#define JTAG_GPIO_ADDR_EN_TDI (CFG_MBAR + 0xC00)
+#define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */
+#define JTAG_GPIO_TDI_EN_RESET 0x00000000
+#define JTAG_GPIO_ADDR_DDR_TDI (CFG_MBAR + 0xC08)
+#define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */
+#define JTAG_GPIO_TDI_DDR_RESET 0x00000000
+
+#define JTAG_GPIO_ADDR_EN_TDO (CFG_MBAR + 0xB04)
+#define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */
+#define JTAG_GPIO_TDO_EN_RESET 0x00000000
+#define JTAG_GPIO_ADDR_DDR_TDO (CFG_MBAR + 0xB0C)
+#define JTAG_GPIO_TDO_DDR_SET 0x00000000
+#define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */
+
+#endif /* __CONFIG_H */
#define CONFIG_BOOTCOMMAND \
"setenv bootargs console=ttyS0,38400 debug " \
"root=/dev/ram rw ramdisk_size=4096 " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm fe000000 fe100000"
#endif
#define CONFIG_BOOTCOMMAND \
"bootp; " \
"setenv bootargs console=ttyS0,38400 debug " \
- "root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#endif
* Cache configuration
*
*/
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
+#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32
#define CONFIG_BOOTCOMMAND \
"setenv bootargs console=ttyS0,38400 debug " \
"root=/dev/ram rw ramdisk_size=4096 " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm ff800000 ff900000"
#endif
#define CONFIG_BOOTCOMMAND \
"bootp; " \
"setenv bootargs console=ttyS0,38400 debug " \
- "root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#endif
* Cache configuration
*
*/
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
+#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32
--- /dev/null
+/*
+ * (C) Copyright 2005 REA Elektronik GmbH <www.rea.de>
+ * Anders Larsen <alarsen@rea.de>
+ *
+ * Configuation settings for the Cogent CSB637 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+#define AT91C_MAIN_CLOCK 184320000 /* from 3.6864 MHz crystal (3686400 * 50) */
+#define AT91C_MASTER_CLOCK 46080000 /* (AT91C_MAIN_CLOCK/4) peripheral clock */
+
+#define AT91_SLOW_CLOCK 32768 /* slow clock */
+
+#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
+#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
+#define CONFIG_CSB637 1 /* on a CSB637 board */
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+#define USE_920T_MMU 1
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define CFG_USE_MAIN_OSCILLATOR 1
+/* flash */
+#define MC_PUIA_VAL 0x00000000
+#define MC_PUP_VAL 0x00000000
+#define MC_PUER_VAL 0x00000000
+#define MC_ASR_VAL 0x00000000
+#define MC_AASR_VAL 0x00000000
+#define EBI_CFGR_VAL 0x00000000
+#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
+
+/* clocks */
+#define PLLAR_VAL 0x2031BE01 /* 184.320000 MHz for PCK */
+#define PLLBR_VAL 0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */
+#define MCKR_VAL 0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */
+
+/* sdram */
+#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define PIOC_BSR_VAL 0x00000000
+#define PIOC_PDR_VAL 0xFFFF0000
+#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
+#define SDRC_CR_VAL 0x21914159 /* set up the SDRAM */
+#define SDRAM 0x20000000 /* address of the SDRAM */
+#define SDRAM1 0x20000080 /* address of the SDRAM */
+#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
+#define SDRC_MR_VAL 0x00000002 /* Precharge All */
+#define SDRC_MR_VAL1 0x00000004 /* refresh */
+#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
+#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
+#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CFG_AT91C_BRGR_DIVISOR 75 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
+
+/*
+ * Hardware drivers
+ */
+
+/* define one of these to choose the DBGU, USART0 or USART1 as console */
+#define CONFIG_DBGU
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+
+#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
+
+#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
+
+#define CONFIG_BOOTDELAY 3
+/* #define CONFIG_ENV_OVERWRITE 1 */
+
+#define CONFIG_COMMANDS \
+ ((CONFIG_CMD_DFL | \
+ CFG_CMD_JFFS2 | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_PING ) & \
+ ~(CFG_CMD_BDI | \
+ CFG_CMD_IMI | \
+ CFG_CMD_AUTOSCRIPT | \
+ CFG_CMD_FPGA | \
+ CFG_CMD_MISC | \
+ CFG_CMD_LOADS ))
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
+#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
+
+#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
+#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
+
+#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
+
+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+/* the following are NOP's in our implementation */
+#define NAND_CTL_CLRALE(nandptr)
+#define NAND_CTL_SETALE(nandptr)
+#define NAND_CTL_CLRCLE(nandptr)
+#define NAND_CTL_SETCLE(nandptr)
+
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x20000000
+#define PHYS_SDRAM_SIZE 0x4000000 /* 64 megs */
+
+#define CFG_MEMTEST_START PHYS_SDRAM
+#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 512*1024 - 4
+#define CFG_ALT_MEMTEST 1
+#define CFG_MEMTEST_SCRATCH CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 4
+
+#define CONFIG_DRIVER_ETHER
+#define CONFIG_NET_RETRY_COUNT 20
+#undef CONFIG_AT91C_USE_RMII
+
+#undef CONFIG_HAS_DATAFLASH
+#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
+#define CFG_MAX_DATAFLASH_BANKS 0
+#define CFG_MAX_DATAFLASH_PAGES 16384
+#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
+#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
+
+/*
+ * FLASH Device configuration
+ */
+#define PHYS_FLASH_1 0x10000000
+#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */
+#define CFG_FLASH_BASE PHYS_FLASH_1
+#define CFG_FLASH_CFI 1 /* flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */
+#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
+#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */
+#define CFG_MAX_FLASH_SECT 64
+
+#define CFG_JFFS2_FIRST_BANK 0
+#define CFG_JFFS2_FIRST_SECTOR 3
+#define CFG_JFFS2_NUM_BANKS 1
+
+#undef CFG_ENV_IS_IN_DATAFLASH
+
+#ifdef CFG_ENV_IS_IN_DATAFLASH
+#define CFG_ENV_OFFSET 0x20000
+#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
+#define CFG_ENV_SIZE 0x2000 /* 0x8000 */
+#else
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* after u-boot.bin */
+#define CFG_ENV_SIZE 0x20000 /* sectors are 128K here */
+#endif /* CFG_ENV_IS_IN_DATAFLASH */
+
+
+#define CFG_LOAD_ADDR 0x21000000 /* default load address */
+
+#define CFG_BAUDRATE_TABLE {115200, 57600, 38400, 19200, 9600 }
+
+#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+
+#ifndef __ASSEMBLY__
+/*-----------------------------------------------------------------------
+ * Board specific extension for bd_info
+ *
+ * This structure is embedded in the global bd_info (bd_t) structure
+ * and can be used by the board specific code (eg board/...)
+ */
+
+struct bd_info_ext {
+ /* helper variable for board environment handling
+ *
+ * env_crc_valid == 0 => uninitialised
+ * env_crc_valid > 0 => environment crc in flash is valid
+ * env_crc_valid < 0 => environment crc in flash is invalid
+ */
+ int env_crc_valid;
+};
+#endif
+
+#define CFG_HZ 1000
+#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
+ /* AT91C_TC_TIMER_DIV1_CLOCK */
+
+#define CONFIG_STACKSIZE (32*1024) /* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
- "addmisc=setenv bootargs $(bootargs) " \
- "console=ttyS0,$(baudrate) " \
+ "addmisc=setenv bootargs ${bootargs} " \
+ "console=ttyS0,${baudrate} " \
"panic=1\0" \
"bootfile=/tftpboot/vmlinux.srec\0" \
- "load=tftp 80500000 $(u-boot)\0" \
+ "load=tftp 80500000 ${u-boot}\0" \
""
#ifdef CONFIG_DBAU1550
#define CONFIG_BOOTCOMMAND \
"tftp 800000 pImage; " \
"setenv bootargs console=ttyS0,9600 init=/linuxrc " \
- "root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):" \
- "$(netmask):$(hostname):eth0:none " \
+ "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:" \
+ "${netmask}:${hostname}:eth0:none " \
"mtdparts=phys:12m(root),-(kernel); " \
"bootm 800000"
*/
/************************************************************************
- * board/config_EBONY.h - configuration for IBM 440GP Ref (Ebony)
+ * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
***********************************************************************/
#ifndef __CONFIG_H
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_EBONY 1 /* Board is ebony */
+#define CONFIG_440GP 1 /* Specifc GP support */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#undef CFG_DRAM_TEST /* Disable-takes long time! */
"netdev=eth0\0" \
"hostname=ebony\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
- "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
"flash_nfs=run nfsargs addip addtty;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addtty;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/ebony/uImage\0" \
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 8 /* PHY address */
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY1_ADDR 9 /* EMAC1 PHY address */
+#define CONFIG_NET_MULTI 1
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
-
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
CFG_CMD_BSP | \
CFG_CMD_DCR | \
CFG_CMD_DHCP | \
+ CFG_CMD_DISPLAY | \
CFG_CMD_DOC | \
CFG_CMD_DTT | \
CFG_CMD_EEPROM | \
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#endif
+#ifdef CFG_EP8260_H2
+#define CFG_FLASH_ERASE_TOUT 240000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+#else
#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
+#endif
#ifndef CFG_RAMBOOT
# define CFG_ENV_IS_IN_FLASH 1
* SCCR - System Clock Control 9-8
*-----------------------------------------------------------------------
*/
+#ifdef CFG_EP8260_H2
+#define CFG_SCCR (SCCR_DFBRG00)
+#else
#define CFG_SCCR (SCCR_DFBRG01)
+#endif
/*-----------------------------------------------------------------------
* RCCR - RISC Controller Configuration 13-7
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
*/
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_DATE | \
+ CFG_CMD_DISPLAY | \
CFG_CMD_DHCP | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_IDE | \
CFG_CMD_NFS | \
CFG_CMD_PCI | \
- CFG_CMD_SNTP)
+ CFG_CMD_SNTP )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
- "bootm $(kernel_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "bootm ${kernel_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_82xx\0" \
""
#define CONFIG_BOOTCOMMAND "run net_nfs"
+#define CONFIG_MISC_INIT_R 1
+
/*
* IPB Bus clocking configuration.
*/
#define CFG_MBAR 0xF0000000
#define CFG_SDRAM_BASE 0x00000000
#define CFG_DEFAULT_MBAR 0x80000000
+#define CFG_DISPLAY_BASE 0x80600000
+#define CFG_STATUS1_BASE 0x80600200
+#define CFG_STATUS2_BASE 0x80600300
/* Settings for XLB = 132 MHz */
#define SDRAM_DDR 1
/* Display H1, Status Inputs, EPLD @0x80600000 */
#define CFG_CS3_START 0x80600000
-#define CFG_CS3_SIZE 0x00000210
-#define CFG_CS3_CFG 0x9800
+#define CFG_CS3_SIZE 0x00100000
+#define CFG_CS3_CFG 0x00019800
#define CFG_CS_BURST 0x00000000
#define CFG_CS_DEADCYCLE 0x33333333
#define CONFIG_ATAPI 1
+#define CONFIG_VIDEO_SMI_LYNXEM
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_LOGO
+
/*
* PCI Mapping:
* 0x40000000 - 0x4fffffff - PCI Memory
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x01000000
+#define CFG_ISA_IO CONFIG_PCI_IO_BUS
+
+/*---------------------------------------------------------------------*/
+/* Display addresses */
+/*---------------------------------------------------------------------*/
+
+#define CFG_DISP_CHR_RAM (CFG_DISPLAY_BASE + 0x38)
+#define CFG_DISP_CWORD (CFG_DISPLAY_BASE + 0x30)
+
#endif /* __CONFIG_H */
#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
CFG_CMD_BEDBUG | \
CFG_CMD_BMP | \
+ CFG_CMD_DISPLAY | \
CFG_CMD_DOC | \
CFG_CMD_EXT2 | \
CFG_CMD_FDC | \
#define CONFIG_EXTRA_ENV_SETTINGS \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off\0" \
- "addmisc=setenv bootargs $(bootargs) " \
- "console=ttyS0,$(baudrate) " \
- "ethaddr=$(ethaddr) " \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off\0" \
+ "addmisc=setenv bootargs ${bootargs} " \
+ "console=ttyS0,${baudrate} " \
+ "ethaddr=${ethaddr} " \
"panic=1\0" \
"flash_nfs=run nfsargs addip addmisc;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addmisc;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 80500000 $(bootfile);" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 80500000 ${bootfile};" \
"run nfsargs addip addmisc;bootm\0" \
"rootpath=/opt/eldk/mips_4KC\0" \
"bootfile=/tftpboot/INCA/uImage\0" \
"kernel_addr=B0040000\0" \
"ramdisk_addr=B0100000\0" \
"u-boot=/tftpboot/INCA/u-boot.bin\0" \
- "load=tftp 80500000 $(u-boot)\0" \
+ "load=tftp 80500000 ${u-boot}\0" \
"update=protect off 1:0-2;era 1:0-2;" \
- "cp.b 80500000 B0000000 $(filesize)\0" \
+ "cp.b 80500000 B0000000 ${filesize}\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
/*
* Autobooting
*/
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
#undef CONFIG_BOOTARGS
+#define CONFIG_ETHADDR 00:a0:a4:03:00:00
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+#define CONFIG_IPADDR 192.168.100.2
+#define CONFIG_SERVERIP 192.168.100.1
+#define CONFIG_NETMASK 255.255.255.0
+#define HOSTNAME inka4x0
+#define CONFIG_BOOTFILE /tftpboot/inka4x0/uImage
+#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx
+
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm $(kernel_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
- "rootpath=/opt/eldk/ppc_82xx\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addcons=setenv bootargs ${bootargs} " \
+ "console=ttyS0,${baudrate}\0" \
+ "flash_nfs=run nfsargs addip addcons;" \
+ "bootm ${kernel_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};" \
+ "run nfsargs addip addcons;bootm\0" \
+ "enable_disp=mw.l 100000 04000000 1;" \
+ "cp.l 100000 f0000b20 1;" \
+ "cp.l 100000 f0000b28 1\0" \
+ "ideargs=setenv bootargs root=/dev/hda1 rw\0" \
+ "ide_boot=ext2load ide 0:1 200000 uImage;" \
+ "run ideargs addip addcons enable_disp;bootm" \
+ "brightness=255\0" \
""
-#define CONFIG_BOOTCOMMAND "run net_nfs"
+#define CONFIG_BOOTCOMMAND "run ide_boot"
/*
* IPB Bus clocking configuration.
*/
/* #define CONFIG_FEC_10MBIT 1 */
#define CONFIG_PHY_ADDR 0x00
+#define CONFIG_MII
/*
* GPIO configuration
#define CFG_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
#define CFG_ATA_IDE0_OFFSET 0x0000
-
#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
-
-/* Offset for data I/O */
-#define CFG_ATA_DATA_OFFSET (0x0060)
-
-/* Offset for normal register accesses */
-#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers */
-#define CFG_ATA_ALT_OFFSET (0x005C)
-
-/* Interval between registers */
-#define CFG_ATA_STRIDE 4
+#define CFG_ATA_DATA_OFFSET 0x0060 /* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) /* Offset for normal register accesses */
+#define CFG_ATA_ALT_OFFSET 0x005C /* Offset for alternate registers */
+#define CFG_ATA_STRIDE 4 /* Interval between registers */
#define CONFIG_ATAPI 1
-#define CFG_BRIGHTNESS 0x20
+
+#define CFG_BRIGHTNESS 0xFF /* LCD Default Brightness (255 = off) */
#endif /* __CONFIG_H */
#ifndef __CONFIG_H
#define __CONFIG_H
-
/*
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
-#define CONFIG_INTEGRATOR 1 /* in an Integrator board */
-#define CONFIG_ARCH_CINTEGRATOR 1 /* Specifically, a CP */
-
-
-#define CFG_MEMTEST_START 0x100000
-#define CFG_MEMTEST_END 0x10000000
-#define CFG_HZ (1000000 / 256) /* Timer 1 is clocked at 1Mhz, with 256 divider */
-#define CFG_TIMERBASE 0x13000100
+#define CFG_MEMTEST_START 0x100000
+#define CFG_MEMTEST_END 0x10000000
+#define CFG_HZ 1000
+#define CFG_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */
+#define CFG_TIMERBASE 0x13000100 /* Timer1 */
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */
+
+#undef CONFIG_INIT_CRITICAL
+#define CONFIG_CM_INIT 1
+#define CONFIG_CM_REMAP 1
+#undef CONFIG_CM_SPD_DETECT
+
/*
* Size of malloc() pool
*/
*/
#define CFG_PL010_SERIAL
#define CONFIG_CONS_INDEX 0
-#define CONFIG_BAUDRATE 38400
+#define CONFIG_BAUDRATE 38400
#define CONFIG_PL01x_PORTS { (void *) (CFG_SERIAL0), (void *) (CFG_SERIAL1) }
-#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CFG_SERIAL0 0x16000000
#define CFG_SERIAL1 0x17000000
/*#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_PCI) */
/*#define CONFIG_NET_MULTI */
-/*#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */
+/*#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */
-#define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY)
+#define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
-#define CONFIG_BOOTDELAY 2
-#define CONFIG_BOOTARGS "root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty"
-#define CONFIG_BOOTCOMMAND ""
+#define CONFIG_BOOTDELAY 2
+#define CONFIG_BOOTARGS "root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty"
+#define CONFIG_BOOTCOMMAND ""
/*
* Miscellaneous configurable options
*/
-#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "Integrator-AP # " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CFG_LOAD_ADDR 0x7fc0 /* default load address */
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
-#define CFG_FLASH_BASE 0x24000000
+#define CFG_FLASH_BASE 0x24000000
/*-----------------------------------------------------------------------
* FLASH and environment organization
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */
/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */
-#define CFG_MAX_FLASH_SECT 128
-#define CFG_ENV_SIZE 32768
+#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
+#define CFG_MAX_FLASH_SECT 128
+#define CFG_ENV_SIZE 32768
#define PHYS_FLASH_1 (CFG_FLASH_BASE)
* PCI definitions
*/
-/*#define CONFIG_PCI /--* include pci support */
+/*#define CONFIG_PCI /--* include pci support */
#undef CONFIG_PCI_PNP
-#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
+#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define DEBUG
#define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
+#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define INTEGRATOR_BOOT_ROM_BASE 0x20000000
-#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000
+#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000
/* PCI Base area */
#define INTEGRATOR_PCI_BASE 0x40000000
#define INTEGRATOR_PCI_SIZE 0x3FFFFFFF
/* memory map as seen by the CPU on the local bus */
-#define CPU_PCI_IO_ADRS 0x60000000 /* PCI I/O space base */
+#define CPU_PCI_IO_ADRS 0x60000000 /* PCI I/O space base */
#define CPU_PCI_IO_SIZE 0x10000
#define CPU_PCI_CNFG_ADRS 0x61000000 /* PCI config space */
#define CPU_PCI_CNFG_SIZE 0x1000000
-#define PCI_MEM_BASE 0x40000000 /* 512M to xxx */
+#define PCI_MEM_BASE 0x40000000 /* 512M to xxx */
/* unused 256M from A0000000-AFFFFFFF might be used for I2O ??? */
-#define INTEGRATOR_PCI_IO_BASE 0x60000000 /* 16M to xxx */
+#define INTEGRATOR_PCI_IO_BASE 0x60000000 /* 16M to xxx */
/* unused (128-16)M from B1000000-B7FFFFFF */
-#define PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */
+#define PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */
/* unused ((128-16)M - 64K) from XXX */
-#define PCI_V3_BASE 0x62000000
+#define PCI_V3_BASE 0x62000000
/* V3 PCI bridge controller */
#define V3_BASE 0x62000000 /* V360EPC registers */
#define PCI_ENET0_MEMADDR (PCI_MEM_BASE)
-#define V3_PCI_VENDOR 0x00000000
-#define V3_PCI_DEVICE 0x00000002
-#define V3_PCI_CMD 0x00000004
-#define V3_PCI_STAT 0x00000006
-#define V3_PCI_CC_REV 0x00000008
-#define V3_PCI_HDR_CF 0x0000000C
-#define V3_PCI_IO_BASE 0x00000010
-#define V3_PCI_BASE0 0x00000014
-#define V3_PCI_BASE1 0x00000018
-#define V3_PCI_SUB_VENDOR 0x0000002C
-#define V3_PCI_SUB_ID 0x0000002E
-#define V3_PCI_ROM 0x00000030
-#define V3_PCI_BPARAM 0x0000003C
-#define V3_PCI_MAP0 0x00000040
-#define V3_PCI_MAP1 0x00000044
-#define V3_PCI_INT_STAT 0x00000048
-#define V3_PCI_INT_CFG 0x0000004C
-#define V3_LB_BASE0 0x00000054
-#define V3_LB_BASE1 0x00000058
-#define V3_LB_MAP0 0x0000005E
-#define V3_LB_MAP1 0x00000062
-#define V3_LB_BASE2 0x00000064
-#define V3_LB_MAP2 0x00000066
-#define V3_LB_SIZE 0x00000068
-#define V3_LB_IO_BASE 0x0000006E
-#define V3_FIFO_CFG 0x00000070
-#define V3_FIFO_PRIORITY 0x00000072
-#define V3_FIFO_STAT 0x00000074
-#define V3_LB_ISTAT 0x00000076
-#define V3_LB_IMASK 0x00000077
-#define V3_SYSTEM 0x00000078
-#define V3_LB_CFG 0x0000007A
-#define V3_PCI_CFG 0x0000007C
-#define V3_DMA_PCI_ADR0 0x00000080
-#define V3_DMA_PCI_ADR1 0x00000090
-#define V3_DMA_LOCAL_ADR0 0x00000084
-#define V3_DMA_LOCAL_ADR1 0x00000094
-#define V3_DMA_LENGTH0 0x00000088
-#define V3_DMA_LENGTH1 0x00000098
-#define V3_DMA_CSR0 0x0000008B
-#define V3_DMA_CSR1 0x0000009B
-#define V3_DMA_CTLB_ADR0 0x0000008C
-#define V3_DMA_CTLB_ADR1 0x0000009C
-#define V3_DMA_DELAY 0x000000E0
-#define V3_MAIL_DATA 0x000000C0
-#define V3_PCI_MAIL_IEWR 0x000000D0
-#define V3_PCI_MAIL_IERD 0x000000D2
-#define V3_LB_MAIL_IEWR 0x000000D4
-#define V3_LB_MAIL_IERD 0x000000D6
-#define V3_MAIL_WR_STAT 0x000000D8
-#define V3_MAIL_RD_STAT 0x000000DA
-#define V3_QBA_MAP 0x000000DC
+#define V3_PCI_VENDOR 0x00000000
+#define V3_PCI_DEVICE 0x00000002
+#define V3_PCI_CMD 0x00000004
+#define V3_PCI_STAT 0x00000006
+#define V3_PCI_CC_REV 0x00000008
+#define V3_PCI_HDR_CF 0x0000000C
+#define V3_PCI_IO_BASE 0x00000010
+#define V3_PCI_BASE0 0x00000014
+#define V3_PCI_BASE1 0x00000018
+#define V3_PCI_SUB_VENDOR 0x0000002C
+#define V3_PCI_SUB_ID 0x0000002E
+#define V3_PCI_ROM 0x00000030
+#define V3_PCI_BPARAM 0x0000003C
+#define V3_PCI_MAP0 0x00000040
+#define V3_PCI_MAP1 0x00000044
+#define V3_PCI_INT_STAT 0x00000048
+#define V3_PCI_INT_CFG 0x0000004C
+#define V3_LB_BASE0 0x00000054
+#define V3_LB_BASE1 0x00000058
+#define V3_LB_MAP0 0x0000005E
+#define V3_LB_MAP1 0x00000062
+#define V3_LB_BASE2 0x00000064
+#define V3_LB_MAP2 0x00000066
+#define V3_LB_SIZE 0x00000068
+#define V3_LB_IO_BASE 0x0000006E
+#define V3_FIFO_CFG 0x00000070
+#define V3_FIFO_PRIORITY 0x00000072
+#define V3_FIFO_STAT 0x00000074
+#define V3_LB_ISTAT 0x00000076
+#define V3_LB_IMASK 0x00000077
+#define V3_SYSTEM 0x00000078
+#define V3_LB_CFG 0x0000007A
+#define V3_PCI_CFG 0x0000007C
+#define V3_DMA_PCI_ADR0 0x00000080
+#define V3_DMA_PCI_ADR1 0x00000090
+#define V3_DMA_LOCAL_ADR0 0x00000084
+#define V3_DMA_LOCAL_ADR1 0x00000094
+#define V3_DMA_LENGTH0 0x00000088
+#define V3_DMA_LENGTH1 0x00000098
+#define V3_DMA_CSR0 0x0000008B
+#define V3_DMA_CSR1 0x0000009B
+#define V3_DMA_CTLB_ADR0 0x0000008C
+#define V3_DMA_CTLB_ADR1 0x0000009C
+#define V3_DMA_DELAY 0x000000E0
+#define V3_MAIL_DATA 0x000000C0
+#define V3_PCI_MAIL_IEWR 0x000000D0
+#define V3_PCI_MAIL_IERD 0x000000D2
+#define V3_LB_MAIL_IEWR 0x000000D4
+#define V3_LB_MAIL_IERD 0x000000D6
+#define V3_MAIL_WR_STAT 0x000000D8
+#define V3_MAIL_RD_STAT 0x000000DA
+#define V3_QBA_MAP 0x000000DC
/* SYSTEM register bits */
-#define V3_SYSTEM_M_RST_OUT (1 << 15)
-#define V3_SYSTEM_M_LOCK (1 << 14)
+#define V3_SYSTEM_M_RST_OUT (1 << 15)
+#define V3_SYSTEM_M_LOCK (1 << 14)
/* PCI_CFG bits */
-#define V3_PCI_CFG_M_RETRY_EN (1 << 10)
-#define V3_PCI_CFG_M_AD_LOW1 (1 << 9)
-#define V3_PCI_CFG_M_AD_LOW0 (1 << 8)
+#define V3_PCI_CFG_M_RETRY_EN (1 << 10)
+#define V3_PCI_CFG_M_AD_LOW1 (1 << 9)
+#define V3_PCI_CFG_M_AD_LOW0 (1 << 8)
/* PCI MAP register bits (PCI -> Local bus) */
-#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000
-#define V3_PCI_MAP_M_RD_POST_INH (1 << 15)
-#define V3_PCI_MAP_M_ROM_SIZE (1 << 11 | 1 << 10)
-#define V3_PCI_MAP_M_SWAP (1 << 9 | 1 << 8)
-#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0
-#define V3_PCI_MAP_M_REG_EN (1 << 1)
-#define V3_PCI_MAP_M_ENABLE (1 << 0)
+#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000
+#define V3_PCI_MAP_M_RD_POST_INH (1 << 15)
+#define V3_PCI_MAP_M_ROM_SIZE (1 << 11 | 1 << 10)
+#define V3_PCI_MAP_M_SWAP (1 << 9 | 1 << 8)
+#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0
+#define V3_PCI_MAP_M_REG_EN (1 << 1)
+#define V3_PCI_MAP_M_ENABLE (1 << 0)
/* 9 => 512M window size */
-#define V3_PCI_MAP_M_ADR_SIZE_512M 0x00000090
+#define V3_PCI_MAP_M_ADR_SIZE_512M 0x00000090
/* A => 1024M window size */
-#define V3_PCI_MAP_M_ADR_SIZE_1024M 0x000000A0
+#define V3_PCI_MAP_M_ADR_SIZE_1024M 0x000000A0
/* LB_BASE register bits (Local bus -> PCI) */
-#define V3_LB_BASE_M_MAP_ADR 0xFFF00000
-#define V3_LB_BASE_M_SWAP (1 << 8 | 1 << 9)
-#define V3_LB_BASE_M_ADR_SIZE 0x000000F0
-#define V3_LB_BASE_M_PREFETCH (1 << 3)
-#define V3_LB_BASE_M_ENABLE (1 << 0)
+#define V3_LB_BASE_M_MAP_ADR 0xFFF00000
+#define V3_LB_BASE_M_SWAP (1 << 8 | 1 << 9)
+#define V3_LB_BASE_M_ADR_SIZE 0x000000F0
+#define V3_LB_BASE_M_PREFETCH (1 << 3)
+#define V3_LB_BASE_M_ENABLE (1 << 0)
/* PCI COMMAND REGISTER bits */
-#define V3_COMMAND_M_FBB_EN (1 << 9)
-#define V3_COMMAND_M_SERR_EN (1 << 8)
-#define V3_COMMAND_M_PAR_EN (1 << 6)
-#define V3_COMMAND_M_MASTER_EN (1 << 2)
-#define V3_COMMAND_M_MEM_EN (1 << 1)
-#define V3_COMMAND_M_IO_EN (1 << 0)
+#define V3_COMMAND_M_FBB_EN (1 << 9)
+#define V3_COMMAND_M_SERR_EN (1 << 8)
+#define V3_COMMAND_M_PAR_EN (1 << 6)
+#define V3_COMMAND_M_MASTER_EN (1 << 2)
+#define V3_COMMAND_M_MEM_EN (1 << 1)
+#define V3_COMMAND_M_IO_EN (1 << 0)
#define INTEGRATOR_SC_BASE 0x11000000
#define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18
#define INTEGRATOR_SC_PCIENABLE \
(INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)
+/*-----------------------------------------------------------------------
+ * There are various dependencies on the core module (CM) fitted
+ * Users should refer to their CM user guide
+ * - when porting adjust u-boot/Makefile accordingly
+ * to define the necessary CONFIG_ s for the CM involved
+ * see e.g. integratorcp_CM926EJ-S_config
+ */
+#include "armcoremodule.h"
-#endif /* __CONFIG_H */
+#endif /* __CONFIG_H */
* High Level Configuration Options
* (easy to change)
*/
-#if 1
-#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
-#else
-#define CONFIG_ARM946ES 1 /* This is an arm946es CPU core */
-#endif
-#define CONFIG_INTEGRATOR 1 /* in an Integrator board */
-#define CONFIG_ARCH_CINTEGRATOR 1 /* Specifically, a CP */
-
+#define CFG_MEMTEST_START 0x100000
+#define CFG_MEMTEST_END 0x10000000
+#define CFG_HZ 1000
+#define CFG_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */
+#define CFG_TIMERBASE 0x13000100
-#define CFG_MEMTEST_START 0x100000
-#define CFG_MEMTEST_END 0x10000000
-#define CFG_HZ (1000000 / 256) /* Timer 1 is clocked at 1Mhz, with 256 divider */
-#define CFG_TIMERBASE 0x13000100
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */
+#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */
/*
* Size of malloc() pool
*/
#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 }
#define CONFIG_CONS_INDEX 0
#define CONFIG_BAUDRATE 38400
-#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CFG_SERIAL0 0x16000000
#define CFG_SERIAL1 0x17000000
#if 0
#define CONFIG_BOOTDELAY 2
-#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0"
+#define CONFIG_BOOTARGS "root=/dev/nfs nfsroot=<IP address>:/<exported rootfs> mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
#define CONFIG_BOOTCOMMAND "bootp ; bootm"
#endif
+/* The kernel command line & boot command below are for a platform flashed with afu.axf
+
+Image 666 Block 0 End Block 0 address 0x24000000 exec 0x24000000- name u-boot
+Image 667 Block 1 End Block 13 address 0x24040000 exec 0x24040000- name u-linux
+Image 668 Block 14 End Block 33 address 0x24380000 exec 0x24380000- name rootfs
+SIB at Block62 End Block62 address 0x24f80000
+
+*/
+#define CONFIG_BOOTDELAY 2
+#define CONFIG_BOOTARGS "root=/dev/mtdblock2 mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0 console=ttyAMA0"
+#define CONFIG_BOOTCOMMAND "cp 0x24080000 0x7fc0 0x100000; bootm"
/*
* Miscellaneous configurable options
*/
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "Integrator-CP # " /* Monitor Command Prompt */
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "Integrator-CP # " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size*/
/* Print Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size*/
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CFG_LOAD_ADDR 0x7fc0 /* default load address */
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
/*-----------------------------------------------------------------------
* FLASH and environment organization
+
+ * Top varies according to amount fitted
+ * Reserve top 4 blocks of flash
+ * - ARM Boot Monitor
+ * - Unused
+ * - SIB block
+ * - U-Boot environment
+ *
+ * Base is always 0x24000000
+
*/
-#define CFG_FLASH_BASE 0x24000000
+#define CFG_FLASH_BASE 0x24000000
#define CFG_MAX_FLASH_SECT 64
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */
-#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */
+#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */
+#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
+
+#define CFG_MONITOR_LEN 0x00100000
+#define CFG_ENV_IS_IN_FLASH (1)
+
+/*
+ * Move up the U-Boot & monitor area if more flash is fitted.
+ * If this U-Boot is to be run on Integrators with varying flash sizes,
+ * drivers/cfi_flash.c::flash_init() can read the Integrator CP_FLASHPROG
+ * register and dynamically assign CFG_ENV_ADDR & CFG_MONITOR_BASE
+ * - CFG_MONITOR_BASE is set to indicate that the environment is not
+ * embedded in the boot monitor(s) area
+ */
+#if ( PHYS_FLASH_SIZE == 0x04000000 )
+
+#define CFG_ENV_ADDR 0x27F00000
+#define CFG_MONITOR_BASE 0x27F40000
+
+#elif (PHYS_FLASH_SIZE == 0x02000000 )
+
+#define CFG_ENV_ADDR 0x25F00000
+#define CFG_MONITOR_BASE 0x25F40000
+
+#else
-#define CFG_MONITOR_BASE 0x24F40000
-#define CFG_ENV_IS_IN_FLASH
#define CFG_ENV_ADDR 0x24F00000
+#define CFG_MONITOR_BASE 0x27F40000
+
+#endif
+
#define CFG_ENV_SECT_SIZE 0x40000 /* 256KB */
#define CFG_ENV_SIZE 8192 /* 8KB */
+/*-----------------------------------------------------------------------
+ * CP control registers
+ */
+#define CPCR_BASE 0xCB000000 /* CP Registers*/
+#define OS_FLASHPROG 0x00000004 /* Flash register*/
+#define CPMASK_EXTRABANK 0x8
+#define CPMASK_FLASHSIZE 0x4
+#define CPMASK_FLWREN 0x2
+#define CPMASK_FLVPPEN 0x1
+
+/*
+ * The ARM boot monitor initializes the board.
+ * However, the default U-Boot code also performs the initialization.
+ * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT
+ * - see documentation supplied with board for details of how to choose the
+ * image to run at reset/power up
+ * e.g. whether the ARM Boot Monitor runs before U-Boot
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+ */
+
+/*
+ * The ARM boot monitor does not relocate U-Boot.
+ * However, the default U-Boot code performs the relocation check,
+ * and may relocate the code if the memory map is changed.
+ * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT
+
+#define SKIP_CONFIG_RELOCATE_UBOOT
+
+ */
+/*-----------------------------------------------------------------------
+ * There are various dependencies on the core module (CM) fitted
+ * Users should refer to their CM user guide
+ * - when porting adjust u-boot/Makefile accordingly
+ * to define the necessary CONFIG_ s for the CM involved
+ * see e.g. cp_926ejs_config
+ */
+
+#include "armcoremodule.h"
+
+/*
+ * If CONFIG_SKIP_LOWLEVEL_INIT is not defined &
+ * the core module has a CM_INIT register
+ * then the U-Boot initialisation code will
+ * e.g. ARM Boot Monitor or pre-loader is repeated once
+ * (to re-initialise any existing CM_INIT settings to safe values).
+ *
+ * This is usually not the desired behaviour since the platform
+ * will either reboot into the ARM monitor (or pre-loader)
+ * or continuously cycle thru it without U-Boot running,
+ * depending upon the setting of Integrator/CP switch S2-4.
+ *
+ * However it may be needed if Integrator/CP switch S2-1
+ * is set OFF to boot direct into U-Boot.
+ * In that case comment out the line below.
+#undef CONFIG_CM_INIT
+ */
#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Rick Bronson <rick@efn.org>
+ *
+ * Configuation settings for the AT91RM9200DK board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Adatped for KwikByte KB920x board from at91rm9200dk.h: 22APR2005
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+#define AT91C_MAIN_CLOCK 180000000 /* from 10 MHz crystal */
+#define AT91C_MASTER_CLOCK 60000000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
+
+#define AT91_SLOW_CLOCK 32768 /* slow clock */
+
+#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
+#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
+/* Only define one of the following, based on board type */
+/* #define CONFIG_KB9200 1 KwikByte KB9202 board */
+/* #define CONFIG_KB9201 1 KwikByte KB9202 board */
+#define CONFIG_KB9202 1 /* KwikByte KB9202 board */
+
+#define CONFIG_KB920x 1 /* Any KB920x board */
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+#define USE_920T_MMU 1
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CFG_LONGHELP
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * Hardware drivers
+ */
+
+/* define one of these to choose the DBGU, USART0 or USART1 as console */
+#define CONFIG_DBGU
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+
+#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
+
+#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_ENV_OVERWRITE 1
+
+#define CONFIG_COMMANDS \
+ ((CONFIG_CMD_DFL | \
+ CFG_CMD_I2C | \
+ CFG_CMD_PING | \
+ CFG_CMD_DHCP ) & \
+ ~(CFG_CMD_BDI | \
+ CFG_CMD_FPGA | \
+ CFG_CMD_MISC))
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x20000000
+#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */
+
+#define CFG_MEMTEST_START PHYS_SDRAM
+#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - (512*1024)
+
+#define CONFIG_DRIVER_ETHER
+#define CONFIG_NET_RETRY_COUNT 20
+
+#define CFG_FLASH_BASE 0x10000000
+
+#ifdef CONFIG_KB9202
+#define PHYS_FLASH_SIZE 0x1000000
+#else
+#define PHYS_FLASH_SIZE 0x200000
+#endif
+
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_MAX_FLASH_SECT 256
+
+#define CONFIG_HARD_I2C
+
+#define CFG_ENV_IS_IN_EEPROM
+
+#ifdef CONFIG_KB9202
+#define CFG_ENV_OFFSET 0x3E00
+#define CFG_ENV_SIZE 0x0200
+#else
+#define CFG_ENV_OFFSET 0x1000
+#define CFG_ENV_SIZE 0x1000
+#endif
+#define CFG_I2C_EEPROM_ADDR 0x50
+#define CFG_EEPROM_PAGE_WRITE_BITS 6
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_I2C_SPEED 50000
+#define CFG_I2C_SLAVE 0 /* not used */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+#define CFG_LOAD_ADDR 0x21000000 /* default load address */
+
+#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
+
+#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+
+#ifndef __ASSEMBLY__
+/*-----------------------------------------------------------------------
+ * Board specific extension for bd_info
+ *
+ * This structure is embedded in the global bd_info (bd_t) structure
+ * and can be used by the board specific code (eg board/...)
+ */
+
+struct bd_info_ext {
+ /* helper variable for board environment handling
+ *
+ * env_crc_valid == 0 => uninitialised
+ * env_crc_valid > 0 => environment crc in flash is valid
+ * env_crc_valid < 0 => environment crc in flash is invalid
+ */
+ int env_crc_valid;
+};
+#endif
+
+#define CFG_HZ 1000
+#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
+ /* AT91C_TC_TIMER_DIV1_CLOCK */
+
+#define CONFIG_STACKSIZE (32*1024) /* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ * John Otken, jotken@softadvances.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * luan.h - configuration for LUAN board
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_LUAN 1 /* Board is Luan */
+#define CONFIG_440SP 1 /* Specific PPC440SP support */
+#define CONFIG_4xx 1 /* PPC4xx family */
+#define CONFIG_440 1
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
+#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc */
+#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
+#define CFG_SDRAM_BASE 0x00000000 /* MUST be zero */
+
+#define CFG_LARGE_FLASH 0xffc00000 /* 4MB flash address CS0 */
+#define CFG_SMALL_FLASH 0xff900000 /* 1MB flash address CS2 */
+#define CFG_SRAM_BASE 0xff800000 /* 1MB SRAM address CS2 */
+#define CFG_EPLD_BASE 0xff000000 /* EPLD and FRAM CS1 */
+
+#define CFG_ISRAM_BASE 0xf8000000 /* internal 8k SRAM (L2 cache) */
+
+#define CFG_PERIPHERAL_BASE 0xf0000000 /* internal peripherals */
+
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
+#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
+
+#if CFG_LARGE_FLASH == 0xffc00000
+#define CFG_FLASH_BASE CFG_LARGE_FLASH
+#else
+#define CFG_FLASH_BASE CFG_SMALL_FLASH
+#endif
+
+#undef CFG_DRAM_TEST
+#if CFG_SRAM_BASE
+#define CFG_KBYTES_SDRAM 1024*2
+#else
+#define CFG_KBYTES_SDRAM 1024
+#endif
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in SDRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE
+#define CFG_INIT_RAM_END (8 << 10)
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CFG_EXT_SERIAL_CLOCK 11059200 /* external 11.059MHz clk */
+#define CONFIG_BAUDRATE 115200
+#undef CONFIG_SERIAL_MULTI
+#undef CONFIG_UART1_CONSOLE /* define if you want console on UART1 */
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+/*
+ * Define here the location of the environment variables (FLASH or EEPROM).
+ * Note: DENX encourages to use redundant environment in FLASH.
+ */
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+
+#define CFG_FLASH_ADDR0 0x555
+#define CFG_FLASH_ADDR1 0x2aa
+#define CFG_FLASH_WORD_SIZE unsigned char
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#undef CONFIG_SPD_EEPROM /* SPD EEPROM init doesn't support DDR2 */
+#define SPD_EEPROM_ADDRESS {0x52,0x53} /* I2C SPD addresses */
+#define IIC0_DIMM0_ADDR 0x52
+#define IIC0_DIMM1_ADDR 0x53
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=luan\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath)\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+ ":$(hostname):$(netdev):off panic=1\0" \
+ "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm $(kernel_addr)\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm $(kernel_addr) $(ramdisk_addr)\0" \
+ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/opt/eldk/ppc_4xx\0" \
+ "bootfile=/tftpboot/luan/uImage\0" \
+ "kernel_addr=fc000000\0" \
+ "ramdisk_addr=fc100000\0" \
+ "load=tftp 100000 /tftpboot/luan/u-boot.bin\0" \
+ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
+ "cp.b 100000 fffc0000 40000;" \
+ "setenv filesize;saveenv\0" \
+ "upd=run load;run update\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 1
+#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+#define CONFIG_NET_MULTI /* needed for NetConsole */
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#ifdef DEBUG
+#define CONFIG_PANIC_HANG
+#else
+#define CONFIG_HW_WATCHDOG /* watchdog */
+#endif
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_CACHE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_ELF | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_MII | \
+ CFG_CMD_NET | \
+ CFG_CMD_NFS | \
+ CFG_CMD_PCI | \
+ CFG_CMD_PING | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SETGETDCR | \
+ CFG_CMD_SDRAM | \
+ 0)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+#undef CONFIG_LYNXKDI /* support kdi files */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_PCI)
+
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
+#define CFG_PCI_TARGET_INIT
+#undef CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
+#define CFG_PCI_SUBSYS_DEVICEID 0x4403 /* whatever */
+
+#endif /* CONFIG_COMMANDS & CFG_CMD_PCI */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+#endif /* __CONFIG_H */
#define CONFIG_NETMASK 255.255.0.0
#define CONFIG_IPADDR 192.168.0.21
#define CONFIG_SERVERIP 192.168.0.250
-#define CONFIG_BOOTCOMMAND "bootm 40000"
+#define CONFIG_BOOTCOMMAND "bootm 80000"
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
#define CONFIG_CMDLINE_TAG
+#define CONFIG_TIMESTAMP
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
-#define CFG_LOAD_ADDR 0xa8000000 /* default load address */
+#define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */
#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
-/* FIXME */
+/* NOTE: many default partitioning schemes assume the kernel starts at the
+ * second sector, not an environment. You have been warned!
+ */
+#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE
#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr of Environment Sector */
-#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
+#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
+#define CFG_ENV_SIZE (PHYS_FLASH_SECT_SIZE / 16)
/*
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs */
+#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
/*-----------------------------------------------------------------------
--- /dev/null
+/*
+ * 2004-2005 Gary Jennejohn <garyj@denx.de>
+ *
+ * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
+ * ebenard@eukrea.com
+ *
+ * Configuration settings for the MP2USB board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 45) */
+#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */
+
+#define AT91_SLOW_CLOCK 32768 /* slow clock */
+
+#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
+#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
+#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
+#define CONFIG_MP2USB 1 /* on an MP2USB Board */
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+#define USE_920T_MMU 1
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#define CFG_ATMEL_PLL_INIT_BUG 1
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define CFG_USE_MAIN_OSCILLATOR 1
+/* flash */
+#define MC_PUIA_VAL 0x00000000
+#define MC_PUP_VAL 0x00000000
+#define MC_PUER_VAL 0x00000000
+#define MC_ASR_VAL 0x00000000
+#define MC_AASR_VAL 0x00000000
+#define EBI_CFGR_VAL 0x00000000
+#define SMC2_CSR_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */
+
+/* clocks */
+#define PLLAR_VAL 0x20263E04 /* 180 MHz for PCK */
+#define PLLBR_VAL 0x1048bE0E /* 48 MHz (divider by 2 for USB) */
+#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 60MHz from PLLA */
+
+/* sdram */
+#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define PIOC_BSR_VAL 0x00000000
+#define PIOC_PDR_VAL 0xFFFF0000
+#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
+#define SDRC_CR_VAL 0x3211295A /* set up the SDRAM */
+#define SDRAM 0x20000000 /* address of the SDRAM */
+#define SDRAM1 0x20000020 /* address of the SDRAM */
+#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
+#define SDRC_MR_VAL 0x00000002 /* Precharge All */
+#define SDRC_MR_VAL1 0x00000004 /* refresh */
+#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
+#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
+#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CFG_AT91C_BRGR_DIVISOR 33 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK /(baudrate * 16) */
+
+/*
+ * Hardware drivers
+ */
+
+/* define one of these to choose the DBGU, USART0 or USART1 as console */
+#define CONFIG_DBGU
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+
+#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
+
+#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
+
+#define CONFIG_USB_OHCI 1
+#define CONFIG_USB_KEYBOARD 1
+#define CONFIG_USB_STORAGE 1
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_AT91C_PQFP_UHPBUG 1
+
+#undef CONFIG_HARD_I2C
+
+#ifdef CONFIG_HARD_I2C
+#define CFG_I2C_SPEED 0 /* not used */
+#define CFG_I2C_SLAVE 0 /* not used */
+#define CONFIG_RTC_RS5C372A /* RICOH I2C RTC */
+#define CFG_I2C_RTC_ADDR 0x32
+#define CFG_I2C_EEPROM_ADDR 0x50
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW
+#endif
+/* still about 20 kB free with this defined */
+#define CFG_LONGHELP
+
+#define CONFIG_BOOTDELAY 3
+
+#ifdef CONFIG_HARD_I2C
+#define CONFIG_COMMANDS \
+ ((CONFIG_CMD_DFL | \
+ CFG_CMD_DATE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_I2C | \
+ CFG_CMD_NFS | \
+ CFG_CMD_SNTP | \
+ CFG_CMD_MISC))
+#else
+#define CONFIG_COMMANDS \
+ ((CONFIG_CMD_DFL | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_NFS | \
+ CFG_CMD_SNTP | \
+ CFG_CMD_USB | \
+ CFG_CMD_CACHE) & \
+ ~(CFG_CMD_BDI | \
+ CFG_CMD_IMI | \
+ CFG_CMD_AUTOSCRIPT | \
+ CFG_CMD_FPGA | \
+ CFG_CMD_MISC | \
+ CFG_CMD_LOADS ))
+#define CONFIG_TIMESTAMP
+#endif
+#define CFG_LONGHELP
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x20000000
+#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
+
+#define CFG_MEMTEST_START PHYS_SDRAM
+#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
+
+#define CONFIG_DRIVER_ETHER
+#define CONFIG_NET_RETRY_COUNT 20
+#undef CONFIG_AT91C_USE_RMII
+
+#define PHYS_FLASH_1 0x10000000
+#define PHYS_FLASH_SIZE 0x1000000 /* 16 megs main flash */
+#define CFG_FLASH_BASE PHYS_FLASH_1
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_MAX_FLASH_SECT 256
+#define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */
+#define CFG_FLASH_LOCK_TOUT (10*CFG_HZ) /* Timeout for Flash Set Lock Bit */
+#define CFG_FLASH_UNLOCK_TOUT (10*CFG_HZ) /* Timeout for Flash Clear Lock Bits */
+#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x20000 /* after u-boot.bin */
+#define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_ENV_OFFSET)
+#define CFG_ENV_SIZE 0x20000
+
+#define CFG_LOAD_ADDR 0x21000000 /* default load address */
+
+#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
+
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_MAXARGS 32 /* max number of command args */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+
+#define CFG_DEVICE_DEREGISTER /* needs device_deregister */
+#define LITTLEENDIAN 1 /* used by usb_ohci.c */
+
+#ifndef __ASSEMBLY__
+/*-----------------------------------------------------------------------
+ * Board specific extension for bd_info
+ *
+ * This structure is embedded in the global bd_info (bd_t) structure
+ * and can be used by the board specific code (eg board/...)
+ */
+
+struct bd_info_ext {
+ /* helper variable for board environment handling
+ *
+ * env_crc_valid == 0 => uninitialised
+ * env_crc_valid > 0 => environment crc in flash is valid
+ * env_crc_valid < 0 => environment crc in flash is invalid
+ */
+ int env_crc_valid;
+};
+#endif /* __ASSEMBLY__ */
+
+#define CFG_HZ 1000
+#define CFG_HZ_CLOCK (AT91C_MASTER_CLOCK/2) /* AT91C_TC0_CMR is implicitly set to */
+ /* AT91C_TC_TIMER_DIV1_CLOCK */
+
+#define CONFIG_STACKSIZE (32*1024) /* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#define CFG_DEVICE_NULLDEV 1 /* enble null device */
+#undef CONFIG_SILENT_CONSOLE /* enable silent startup */
+
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n"
+#define CONFIG_AUTOBOOT_STOP_STR " "
+#define CONFIG_AUTOBOOT_DELAY_STR "d"
+
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200
+#define CONFIG_O2DNT 1 /* ... on O2DNT board */
+
+#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
+
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE 5 /* console is on PSC5 */
+#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI 1
+#define CONFIG_PCI_PNP 1
+/* #define CONFIG_PCI_SCAN_SHOW 1 */
+
+#define CONFIG_PCI_MEM_BUS 0x40000000
+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE 0x10000000
+
+#define CONFIG_PCI_IO_BUS 0x50000000
+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE 0x01000000
+
+#define CFG_XLB_PIPELINING 1
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_EEPRO100
+#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
+#define CONFIG_NS8382X 1
+
+#define ADD_PCI_CMD CFG_CMD_PCI
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_FAT | \
+ CFG_CMD_I2C | \
+ CFG_CMD_NFS | \
+ CFG_CMD_MII | \
+ CFG_CMD_PING | \
+ ADD_PCI_CMD )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
+# define CFG_LOWBOOT 1
+#else
+# error "TEXT_BASE must be 0xFF000000"
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "flash_nfs=run nfsargs addip;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
+ "rootpath=/opt/eldk/ppc_82xx\0" \
+ "bootfile=/tftpboot/MPC5200/uImage\0" \
+ ""
+
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#if defined(CONFIG_MPC5200)
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+
+#if defined(CFG_IPBSPEED_133)
+/*
+ * PCI Bus clocking configuration
+ *
+ * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
+ * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
+ * been tested with a IPB Bus Clock of 66 MHz.
+ */
+#define CFG_PCISPEED_66 /* define for 66MHz speed */
+#endif
+#endif
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */
+
+#define CFG_I2C_SPEED 100000 /* 100 kHz */
+#define CFG_I2C_SLAVE 0x7F
+
+/*
+ * EEPROM configuration:
+ *
+ * O2DNT board is equiped with Ramtron FRAM device FM24CL16
+ * 16 Kib Ferroelectric Nonvolatile serial RAM memory
+ * organized as 2048 x 8 bits and addressable as eight I2C devices
+ * 0x50 ... 0x57 each 256 bytes in size
+ *
+ */
+#define CFG_I2C_FRAM
+#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+/*
+ * There is no write delay with FRAM, write operations are performed at bus
+ * speed. Thus, no status polling or write delay is needed.
+ */
+/*#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70*/
+
+
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_BASE 0xFF000000
+#define CFG_FLASH_SIZE 0x01000000
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000)
+
+#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
+#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
+#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
+#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SIZE 0x20000
+#define CFG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_OVERWRITE 1
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR 0xF0000000
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_DEFAULT_MBAR 0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
+#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
+
+
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC 1
+/*
+ * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ */
+/* #define CONFIG_FEC_10MBIT 1 */
+#define CONFIG_PHY_ADDR 0x00
+
+/*
+ * GPIO configuration
+ */
+/*#define CFG_GPS_PORT_CONFIG 0x10002004 */
+#define CFG_GPS_PORT_CONFIG 0x00002006 /* no CAN */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL HID0_ICE
+#else
+#define CFG_HID0_INIT 0
+#define CFG_HID0_FINAL 0
+#endif
+
+#define CFG_BOOTCS_START CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
+
+#ifdef CFG_PCISPEED_66
+/*
+ * For 66 MHz PCI clock additional Wait State is needed for CS0 (flash).
+ */
+#define CFG_BOOTCS_CFG 0x00057801 /* for pci_clk = 66 MHz */
+#else
+#define CFG_BOOTCS_CFG 0x00047801 /* for pci_clk = 33 MHz */
+#endif
+
+#define CFG_CS0_START CFG_FLASH_BASE
+#define CFG_CS0_SIZE CFG_FLASH_SIZE
+
+#define CFG_CS_BURST 0x00000000
+#define CFG_CS_DEADCYCLE 0x33333333
+
+#define CFG_RESET_ADDRESS 0xff000000
+
+#endif /* __CONFIG_H */
/************************************************************************
- * OCOTEA.h - configuration for IBM 440GX Ref (Ocotea)
+ * OCOTEA.h - configuration for AMCC 440GX Ref (Ocotea)
***********************************************************************/
#ifndef __CONFIG_H
"netdev=eth0\0" \
"hostname=ocotea\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
- "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
"flash_nfs=run nfsargs addip addtty;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addtty;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/ocotea/uImage\0" \
#define CONFIG_PHY1_ADDR 2
#define CONFIG_PHY2_ADDR 0x10
#define CONFIG_PHY3_ADDR 0x18
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_PHY_RESET_DELAY 1000
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-#define CFG_HZ 100 /* decrementer freq: 1 ms ticks */
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE /* include NetConsole support */
/*-----------------------------------------------------------------------
* PCI stuff
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 32768 /* For IBM 440 CPUs */
+#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
/*#define CONFIG_VIRTIO 1 #* Using Virtio simulator */
/* Clock config to target*/
-#define PRCM_CONFIG_II 1
-/*#define PRCM_CONFIG_III 1 */
-
-/* Memory configuration on board */
-/*#define CONFIG_OPTIMIZE_DDR 1 */
+#define PRCM_CONFIG_II 1
+/* #define PRCM_CONFIG_III 1 */
#include <asm/arch/omap2420.h> /* get chip and board defs */
#ifdef CFG_NAND_BOOT
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_NAND | CFG_CMD_JFFS2)
#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_JFFS2)
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_JFFS2) & ~CFG_CMD_AUTOSCRIPT)
#endif
-/* I'd like to get to these. Snap kernel loads if we make MMC go */
- /* #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_NAND | CFG_CMD_JFFS2 | CFG_CMD_DHCP | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_I2C) */
-
#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#define NAND_WP_OFF() do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0)
#define NAND_WP_ON() do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0)
-
#define NAND_CTL_CLRALE(nandptr)
#define NAND_CTL_SETALE(nandptr)
#define NAND_CTL_CLRCLE(nandptr)
#define NAND_DISABLE_CE(nand)
#define NAND_ENABLE_CE(nand)
-
#define CONFIG_BOOTDELAY 3
#ifdef NFS_BOOT_DEFAULTS
#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */
#define PHYS_SDRAM_2 OMAP2420_SDRC_CS1
+#define PHYS_FLASH_SECT_SIZE SZ_128K
#define PHYS_FLASH_1 H4_CS0_BASE /* Flash Bank #1 */
#define PHYS_FLASH_SIZE_1 SZ_32M
#define PHYS_FLASH_2 (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */
#define PHYS_FLASH_SIZE_2 SZ_32M
-#define CFG_FLASH_BASE PHYS_FLASH_1
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
+#define CFG_FLASH_BASE PHYS_FLASH_1
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
+#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */
+#define CFG_MONITOR_LEN SZ_128K /* Reserve 1 sector */
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + PHYS_FLASH_SIZE_1 }
#ifdef CFG_NAND_BOOT
#define CFG_ENV_IS_IN_NAND 1
#else
#define CFG_ENV_ADDR (CFG_FLASH_BASE + SZ_128K)
#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
+#define CFG_ENV_OFFSET ( CFG_MONITOR_BASE + CFG_MONITOR_LEN ) /* Environment after Monitor */
#endif
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
+#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
+
/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT (30*75*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT (30*75*CFG_HZ) /* Timeout for Flash Write */
+#define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */
#define CFG_JFFS2_MEM_NAND
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * board/config_p3p440.h - configuration for Prodrive P3P440
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_P3P440 1 /* Board is P3P440 */
+#define CONFIG_440GP 1 /* Specifc GP support */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */
+#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
+#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
+#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
+
+#define CFG_USB_BASE (CFG_PERIPHERAL_BASE + 0x00000000)
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0*/
+#define CFG_SDRAM_TABLE { \
+ {(256 << 20), 0x000C4001}, /* 256MB mode 3, 13x10(4) */ \
+ {(64 << 20), 0x00082001}} /* 64MB mode 2, 12x9(4) */
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CFG_EXT_SERIAL_CLOCK
+#define CONFIG_BAUDRATE 115200
+
+#define CFG_BAUDRATE_TABLE \
+ { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
+ 57600, 115200, 230400, 460800, 921600 }
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+
+/*-----------------------------------------------------------------------
+ * I2C RTC
+ *----------------------------------------------------------------------*/
+#define CONFIG_RTC_MAX6900 1 /* MAX6900 RTC */
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (PCF8594C) for environment
+ *----------------------------------------------------------------------*/
+#define CFG_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */
+#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
+/* mask of address bits that overflow into the "EEPROM chip address" */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */
+ /* 8 byte page write mode using */
+ /* last 3 bits of the address */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Default configuration (environment varibles...)
+ *----------------------------------------------------------------------*/
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=p3p440\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/opt/eldk/ppc_4xx\0" \
+ "bootfile=/tftpboot/p3p440/uImage\0" \
+ "kernel_addr=ff800000\0" \
+ "ramdisk_addr=ff810000\0" \
+ "load=tftp 100000 /tftpboot/p3p440/u-boot.bin\0" \
+ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
+ "cp.b 100000 fffc0000 40000;" \
+ "setenv filesize;saveenv\0" \
+ "upd=run load;run update\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run net_nfs"
+
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 0x1c /* PHY address */
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY1_ADDR 0x1d /* EMAC1 PHY address */
+#define CONFIG_NET_MULTI 1
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_DATE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_ELF | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_MII | \
+ CFG_CMD_NET | \
+ CFG_CMD_NFS | \
+ CFG_CMD_PCI | \
+ CFG_CMD_PING | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_SNTP )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
+#define CFG_PCI_TARGET_INIT /* let board init pci target */
+
+#define CONFIG_DISABLE_PISE_TEST /* disable PISE test (PCIX only)*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH0 0xFF800000
+#define CFG_FLASH1 0xFF000000
+#define CFG_FLASH2 0xFE800000
+#define CFG_FLASH3 0xFE000000
+#define CFG_USB 0xF0000000
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
+#define CFG_EBC_PB0AP 0x03050200
+#define CFG_EBC_PB0CR (CFG_FLASH0 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1, NOR-FLASH) initialization */
+#define CFG_EBC_PB1AP 0x03050200
+#define CFG_EBC_PB1CR (CFG_FLASH1 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (Flash Bank 2, NOR-FLASH) initialization */
+#define CFG_EBC_PB2AP 0x03050200
+#define CFG_EBC_PB2CR (CFG_FLASH2 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 3 (Flash Bank 3, NOR-FLASH) initialization */
+#define CFG_EBC_PB3AP 0x03050200
+#define CFG_EBC_PB3CR (CFG_FLASH3 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 7 (USB controller) initialization */
+#define CFG_EBC_PB7AP 0x02015000
+#define CFG_EBC_PB7CR (CFG_USB | 0xFE000) /* BAS=0xF00,BS=128MB,BU=R/W,BW=16bit*/
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH3, CFG_FLASH2, CFG_FLASH1, CFG_FLASH0 }
+
+#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
+
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 405 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file contains the configuration parameters for the dbau1x00 board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
+#define CONFIG_PB1X00 1
+#define CONFIG_AU1X00 1 /* alchemy series cpu */
+
+#ifdef CONFIG_PB1000
+#define CONFIG_AU1000 1
+#else
+#ifdef CONFIG_PB1100
+#define CONFIG_AU1100 1
+#else
+#ifdef CONFIG_PB1500
+#define CONFIG_AU1500 1
+#else
+#error "No valid board set"
+#endif
+#endif
+#endif
+
+#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
+
+#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
+
+#define CONFIG_BAUDRATE 115200
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "addmisc=setenv bootargs ${bootargs} " \
+ "console=ttyS0,${baudrate} " \
+ "panic=1\0" \
+ "bootfile=/vmlinux.img\0" \
+ "load=tftp 80500000 ${u-boot}\0" \
+ ""
+/* Boot from NFS root */
+#define CONFIG_BOOTCOMMAND "bootp; setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; bootm"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "Pb1x00 # " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args*/
+
+#define CFG_MALLOC_LEN 128*1024
+
+#define CFG_BOOTPARAMS_LEN 128*1024
+
+#define CFG_HZ 396000000 /* FIXME causes overflow in net.c */
+
+#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */
+
+#define CFG_LOAD_ADDR 0x81000000 /* default load address */
+
+#define CFG_MEMTEST_START 0x80100000
+#undef CFG_MEMTEST_START
+#define CFG_MEMTEST_START 0x80200000
+#define CFG_MEMTEST_END 0x83800000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
+
+#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
+#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
+
+/* The following #defines are needed to get flash environment right */
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_MONITOR_LEN (192 << 10)
+
+#define CFG_INIT_SP_OFFSET 0x4000000
+
+/* We boot from this flash, selected with dip switch */
+#define CFG_FLASH_BASE PHYS_FLASH_2
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */
+
+#define CFG_ENV_IS_NOWHERE 1
+
+/* Address and size of Primary Environment Sector */
+#define CFG_ENV_ADDR 0xB0030000
+#define CFG_ENV_SIZE 0x10000
+
+#define CONFIG_FLASH_16BIT
+
+#define CONFIG_NR_DRAM_BANKS 2
+
+#define CONFIG_NET_MULTI
+
+#define CONFIG_MEMSIZE_IN_BYTES
+
+
+/*---USB -------------------------------------------*/
+#if 0
+#define CONFIG_USB_OHCI
+#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#else
+#define ADD_USB_CMD 0
+#endif
+
+/*---ATA PCMCIA ------------------------------------*/
+#if 0
+#define CFG_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
+#define CFG_PCMCIA_MEM_ADDR 0x20000000
+#define CONFIG_PCMCIA_SLOT_A
+
+#define CONFIG_ATAPI 1
+#define CONFIG_MAC_PARTITION 1
+
+/* We run CF in "true ide" mode or a harddrive via pcmcia */
+#define CONFIG_IDE_PCMCIA 1
+
+/* We only support one slot for now */
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
+
+#undef CONFIG_IDE_LED /* LED for ide not supported */
+#undef CONFIG_IDE_RESET /* reset for ide not supported */
+
+#define CFG_ATA_IDE0_OFFSET 0x0000
+
+#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O */
+#define CFG_ATA_DATA_OFFSET 8
+
+/* Offset for normal register accesses */
+#define CFG_ATA_REG_OFFSET 0
+
+/* Offset for alternate registers */
+#define CFG_ATA_ALT_OFFSET 0x0100
+
+#endif
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 16384
+#define CFG_ICACHE_SIZE 16384
+#define CFG_CACHELINE_SIZE 32
+
+#define CONFIG_COMMANDS \
+ (((CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_PING) & \
+ ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | CFG_CMD_IDE | \
+ CFG_CMD_LOADS | CFG_CMD_RUN | CFG_CMD_LOADB | CFG_CMD_ELF | \
+ CFG_CMD_BDI | CFG_CMD_BEDBUG)) | ADD_USB_CMD)
+#include <cmd_confdefs.h>
+
+#endif /* __CONFIG_H */
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
--- /dev/null
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * (c) 2005 esd gmbh Hannover
+ *
+ *
+ * from IceCube.h file
+ * by Reinhard Arlt reinhard.arlt@esd-electronics.com
+ *
+ *************************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */
+#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
+#define CONFIG_ICECUBE 1 /* ... on IceCube board */
+#define CONFIG_PF5200 1 /* ... on PF5200 board */
+#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
+
+#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
+
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
+#if 0 /* test-only */
+#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
+#else
+#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
+#endif
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI 1
+#define CONFIG_PCI_PNP 1
+#define CONFIG_PCI_SCAN_SHOW 1
+
+#define CONFIG_PCI_MEM_BUS 0x40000000
+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE 0x10000000
+
+#define CONFIG_PCI_IO_BUS 0x50000000
+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE 0x01000000
+
+#define CONFIG_MII 1
+#if 0 /* test-only !!! */
+#define CONFIG_NET_MULTI 1
+#define CONFIG_EEPRO100 1
+#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
+#define CONFIG_NS8382X 1
+#endif
+
+#define ADD_PCI_CMD CFG_CMD_PCI
+
+#else /* MPC5100 */
+
+#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
+
+#endif
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#if 0
+#define CONFIG_USB_OHCI
+#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
+#define CONFIG_USB_STORAGE
+#else
+#define ADD_USB_CMD 0
+#endif
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_FAT | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IDE | \
+ CFG_CMD_BSP | \
+ CFG_CMD_ELF | \
+ ADD_PCI_CMD )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
+# define CFG_LOWBOOT 1
+# define CFG_LOWBOOT16 1
+#endif
+#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
+# define CFG_LOWBOOT 1
+# define CFG_LOWBOOT08 1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Welcome to ParaFinder pf5200;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
+ "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
+ "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
+ "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
+ "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
+ "loadaddr=01000000\0" \
+ "serverip=192.168.2.99\0" \
+ "gatewayip=10.0.0.79\0" \
+ "user=mu\0" \
+ "target=pf5200.esd\0" \
+ "script=pf5200.bat\0" \
+ "image=/tftpboot/vxWorks_pf5200\0" \
+ "ipaddr=10.0.13.196\0" \
+ "netmask=255.255.0.0\0" \
+ ""
+
+#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
+
+#if defined(CONFIG_MPC5200)
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
+#endif
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
+
+#define CFG_I2C_SPEED 86000 /* 100 kHz */
+#define CFG_I2C_SLAVE 0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_EEPROM_PAGE_WRITE_BITS 5
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
+#define CFG_I2C_MULTI_EEPROMS 1
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_BASE 0xFE000000
+#define CFG_FLASH_SIZE 0x02000000
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00000000)
+#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
+#define CFG_MAX_FLASH_SECT 512
+
+#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
+
+/*
+ * Environment settings
+ */
+#if 1 /* test-only */
+#define CFG_ENV_IS_IN_FLASH 0
+#define CFG_ENV_SIZE 0x10000
+#define CFG_ENV_SECT_SIZE 0x10000
+#define CONFIG_ENV_OVERWRITE 1
+#else
+#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */
+ /* total size of a CAT24WC32 is 8192 bytes */
+#define CONFIG_ENV_OVERWRITE 1
+#endif
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR 0xF0000000
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_DEFAULT_MBAR 0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
+#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+# define CFG_RAMBOOT 1
+#endif
+
+#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC 1
+/*
+ * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ */
+/* #define CONFIG_FEC_10MBIT 1 */
+#define CONFIG_PHY_ADDR 0x00
+#define CONFIG_UDP_CHECKSUM 1
+
+/*
+ * GPIO configuration
+ */
+#define CFG_GPS_PORT_CONFIG 0x01052444
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL HID0_ICE
+#else
+#define CFG_HID0_INIT 0
+#define CFG_HID0_FINAL 0
+#endif
+
+#define CFG_BOOTCS_START CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG 0x0004DD00
+
+#define CFG_CS0_START CFG_FLASH_BASE
+#define CFG_CS0_SIZE CFG_FLASH_SIZE
+
+#define CFG_CS1_START 0xfd000000
+#define CFG_CS1_SIZE 0x00010000
+#define CFG_CS1_CFG 0x10101410
+
+#define CFG_CS_BURST 0x00000000
+#define CFG_CS_DEADCYCLE 0x33333333
+
+#define CFG_RESET_ADDRESS 0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK 0x0001BBBB
+#define CONFIG_USB_CONFIG 0x00001000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
+
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
+#undef CONFIG_IDE_LED /* LED for ide not supported */
+
+#define CONFIG_IDE_RESET /* reset for ide supported */
+#define CONFIG_IDE_PREINIT
+
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
+
+#define CFG_ATA_IDE0_OFFSET 0x0000
+
+#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
+
+/* Offset for data I/O */
+#define CFG_ATA_DATA_OFFSET (0x0060)
+
+/* Offset for normal register accesses */
+#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers */
+#define CFG_ATA_ALT_OFFSET (0x005C)
+
+/* Interval between registers */
+#define CFG_ATA_STRIDE 4
+
+/*-----------------------------------------------------------------------
+ * CPLD stuff
+ */
+#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
+#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */
+
+/* CPLD program pin configuration */
+#define CFG_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */
+#define CFG_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */
+#define CFG_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */
+#define CFG_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */
+
+#define JTAG_GPIO_ADDR_TMS (CFG_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */
+#define JTAG_GPIO_ADDR_TCK (CFG_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */
+#define JTAG_GPIO_ADDR_TDI (CFG_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */
+#define JTAG_GPIO_ADDR_TDO (CFG_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */
+
+#define JTAG_GPIO_ADDR_CFG (CFG_MBAR + 0xB00)
+#define JTAG_GPIO_CFG_SET 0x00000000
+#define JTAG_GPIO_CFG_RESET 0x00F00000
+
+#define JTAG_GPIO_ADDR_EN_TMS (CFG_MBAR + 0xB04)
+#define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */
+#define JTAG_GPIO_TMS_EN_RESET 0x00000000
+#define JTAG_GPIO_ADDR_DDR_TMS (CFG_MBAR + 0xB0C)
+#define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */
+#define JTAG_GPIO_TMS_DDR_RESET 0x00000000
+
+#define JTAG_GPIO_ADDR_EN_TCK (CFG_MBAR + 0xC00)
+#define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */
+#define JTAG_GPIO_TCK_EN_RESET 0x00000000
+#define JTAG_GPIO_ADDR_DDR_TCK (CFG_MBAR + 0xC08)
+#define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */
+#define JTAG_GPIO_TCK_DDR_RESET 0x00000000
+
+#define JTAG_GPIO_ADDR_EN_TDI (CFG_MBAR + 0xC00)
+#define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */
+#define JTAG_GPIO_TDI_EN_RESET 0x00000000
+#define JTAG_GPIO_ADDR_DDR_TDI (CFG_MBAR + 0xC08)
+#define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */
+#define JTAG_GPIO_TDI_DDR_RESET 0x00000000
+
+#define JTAG_GPIO_ADDR_EN_TDO (CFG_MBAR + 0xB04)
+#define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */
+#define JTAG_GPIO_TDO_EN_RESET 0x00000000
+#define JTAG_GPIO_ADDR_DDR_TDO (CFG_MBAR + 0xB0C)
+#define JTAG_GPIO_TDO_DDR_SET 0x00000000
+#define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */
+
+#endif /* __CONFIG_H */
"echo;" \
"bootp;" \
"setenv bootargs root=/dev/ram0 rw " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"bootm"
#endif /* CONFIG_BOOT_ROOT_INITRD */
"version;" \
"echo;" \
"bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"bootm"
#endif /* CONFIG_BOOT_ROOT_NFS */
#define CONFIG_EXTRA_ENV_SETTINGS \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off\0" \
- "addmisc=setenv bootargs $(bootargs) " \
- "console=ttyS0,$(baudrate) " \
- "ethaddr=$(ethaddr) " \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off\0" \
+ "addmisc=setenv bootargs ${bootargs} " \
+ "console=ttyS0,${baudrate} " \
+ "ethaddr=${ethaddr} " \
"panic=1\0" \
"flash_nfs=run nfsargs addip addmisc;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addmisc;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 80500000 $(bootfile);" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 80500000 ${bootfile};" \
"run nfsargs addip addmisc;bootm\0" \
"rootpath=/opt/eldk/mips_5KC\0" \
"bootfile=/tftpboot/purple/uImage\0" \
"kernel_addr=B0040000\0" \
"ramdisk_addr=B0100000\0" \
"u-boot=/tftpboot/purple/u-boot.bin\0" \
- "load=tftp 80500000 $(u-boot)\0" \
+ "load=tftp 80500000 ${u-boot}\0" \
"update=protect off 1:0-4;era 1:0-4;" \
- "cp.b 80500000 B0000000 $(filesize)\0" \
+ "cp.b 80500000 B0000000 ${filesize}\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copied from lubbock.h
+ *
+ * (C) Copyright 2004
+ * BEC Systems <http://bec-systems.com>
+ * Cliff Brake <cliff.brake@gmail.com>
+ * Configuation settings for the Accelent/Vibren PXA255 IDP
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/pxa-regs.h>
+
+/*
+ * If we are developing, we might want to start armboot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ */
+#define CONFIG_INIT_CRITICAL /* undef for developing */
+
+/*
+ * define the following to enable debug blinks. A debug blink function
+ * must be defined in memsetup.S
+ */
+#undef DEBUG_BLINK_ENABLE
+#undef DEBUG_BLINKC_ENABLE
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
+
+#undef CONFIG_LCD
+#ifdef CONFIG_LCD
+#define CONFIG_SHARP_LM8V31
+#endif
+
+#define CONFIG_MMC 1
+#define BOARD_LATE_INIT 1
+
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+
+/*
+ * PXA250 IDP memory map information
+ */
+
+#define IDP_CS5_ETH_OFFSET 0x03400000
+
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_SMC91111
+#define CONFIG_SMC91111_BASE (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300)
+#define CONFIG_SMC_USE_32_BIT 1
+/* #define CONFIG_SMC_USE_IOFUNCS */
+
+/* the following has to be set high -- suspect something is wrong with
+ * with the tftp timeout routines. FIXME!!!
+ */
+#define CONFIG_NET_RETRY_COUNT 100
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_DHCP )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTCOMMAND "bootm 40000"
+#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
+#define CONFIG_CMDLINE_TAG
+
+/*
+ * Current memory map for Vibren supplied Linux images:
+ *
+ * Flash:
+ * 0 - 0x3ffff (size = 0x40000): bootloader
+ * 0x40000 - 0x13ffff (size = 0x100000): kernel
+ * 0x140000 - 0x1f3ffff (size = 0x1e00000): jffs
+ *
+ * RAM:
+ * 0xa0008000 - kernel is loaded
+ * 0xa3000000 - Uboot runs (48MB into RAM)
+ *
+ */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "prog_boot_mmc=" \
+ "mw.b 0xa0000000 0xff 0x40000; " \
+ "if mmcinit && " \
+ "fatload mmc 0 0xa0000000 u-boot.bin; " \
+ "then " \
+ "protect off 0x0 0x3ffff; " \
+ "erase 0x0 0x3ffff; " \
+ "cp.b 0xa0000000 0x0 0x40000; " \
+ "reset;" \
+ "fi\0" \
+ "prog_uzImage_mmc=" \
+ "mw.b 0xa0000000 0xff 0x100000; " \
+ "if mmcinit && " \
+ "fatload mmc 0 0xa0000000 uzImage; " \
+ "then " \
+ "protect off 0x40000 0xfffff; " \
+ "erase 0x40000 0xfffff; " \
+ "cp.b 0xa0000000 0x40000 0x100000; " \
+ "fi\0" \
+ "prog_jffs_mmc=" \
+ "mw.b 0xa0000000 0xff 0x1e00000; " \
+ "if mmcinit && " \
+ "fatload mmc 0 0xa0000000 root.jffs; " \
+ "then " \
+ "protect off 0x140000 0x1f3ffff; " \
+ "erase 0x140000 0x1f3ffff; " \
+ "cp.b 0xa0000000 0x140000 0x1e00000; " \
+ "fi\0" \
+ "boot_mmc=" \
+ "if mmcinit && " \
+ "fatload mmc 0 0xa1000000 uzImage && " \
+ "then " \
+ "bootm 0xa1000000; " \
+ "fi\0" \
+ "prog_boot_net=" \
+ "mw.b 0xa0000000 0xff 0x100000; " \
+ "if bootp 0xa0000000 u-boot.bin; " \
+ "then " \
+ "protect off 0x0 0x3ffff; " \
+ "erase 0x0 0x3ffff; " \
+ "cp.b 0xa0000000 0x0 0x40000; " \
+ "reset; " \
+ "fi\0" \
+ "prog_uzImage_net=" \
+ "mw.b 0xa0000000 0xff 0x100000; " \
+ "if bootp 0xa0000000 uzImage; " \
+ "then " \
+ "protect off 0x40000 0xfffff; " \
+ "erase 0x40000 0xfffff; " \
+ "cp.b 0xa0000000 0x40000 0x100000; " \
+ "fi\0" \
+ "prog_jffs_net=" \
+ "mw.b 0xa0000000 0xff 0x1e00000; " \
+ "if bootp 0xa0000000 root.jffs; " \
+ "then " \
+ "protect off 0x140000 0x1f3ffff; " \
+ "erase 0x140000 0x1f3ffff; " \
+ "cp.b 0xa0000000 0x140000 0x1e00000; " \
+ "fi\0"
+
+
+/* "erase_env=" */
+/* "protect off" */
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER 1
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+#define CFG_LONGHELP /* undef to save memory */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT "$ " /* Monitor Command Prompt */
+#else
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#endif
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_DEVICE_NULLDEV 1
+
+#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR 0xa0800000 /* default load address */
+
+#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
+
+#define RTC 1 /* enable 32KHz osc */
+
+ /* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_MMC_BASE 0xF0000000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 4 /* we have 1 banks of DRAM */
+#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
+#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
+#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
+
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
+#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
+#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
+#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
+
+#define CFG_DRAM_BASE 0xa0000000
+#define CFG_DRAM_SIZE 0x04000000
+
+#define CFG_FLASH_BASE PHYS_FLASH_1
+
+/*
+ * GPIO settings
+ */
+
+#define CFG_GAFR0_L_VAL 0x80001005
+#define CFG_GAFR0_U_VAL 0xa5128012
+#define CFG_GAFR1_L_VAL 0x699a9558
+#define CFG_GAFR1_U_VAL 0xaaa5aa6a
+#define CFG_GAFR2_L_VAL 0xaaaaaaaa
+#define CFG_GAFR2_U_VAL 0x2
+#define CFG_GPCR0_VAL 0x1800400
+#define CFG_GPCR1_VAL 0x0
+#define CFG_GPCR2_VAL 0x0
+#define CFG_GPDR0_VAL 0xc1818440
+#define CFG_GPDR1_VAL 0xfcffab82
+#define CFG_GPDR2_VAL 0x1ffff
+#define CFG_GPSR0_VAL 0x8000
+#define CFG_GPSR1_VAL 0x3f0002
+#define CFG_GPSR2_VAL 0x1c000
+
+#define CFG_PSSR_VAL 0x20
+
+/*
+ * Memory settings
+ */
+#define CFG_MSC0_VAL 0x29DCA4D2
+#define CFG_MSC1_VAL 0x43AC494C
+#define CFG_MSC2_VAL 0x39D449D4
+#define CFG_MDCNFG_VAL 0x090009C9
+#define CFG_MDREFR_VAL 0x0085C017
+#define CFG_MDMRS_VAL 0x00220022
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CFG_MECR_VAL 0x00000003
+#define CFG_MCMEM0_VAL 0x00014405
+#define CFG_MCMEM1_VAL 0x00014405
+#define CFG_MCATT0_VAL 0x00014405
+#define CFG_MCATT1_VAL 0x00014405
+#define CFG_MCIO0_VAL 0x00014405
+#define CFG_MCIO1_VAL 0x00014405
+
+/*
+ * FLASH and environment organization
+ */
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER 1
+
+#define CFG_MONITOR_BASE 0
+#define CFG_MONITOR_LEN 0x40000
+
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
+
+/* put cfg at end of flash for now */
+#define CFG_ENV_IS_IN_FLASH 1
+ /* Addr of Environment Sector */
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000)
+#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE 0x40000
+
+#endif /* __CONFIG_H */
#define CONFIG_EXTRA_ENV_SETTINGS \
"serial#=12345\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off\0"
+ "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0"
/*
* Select the more full-featured memory test (Barr embedded systems)
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
"tftpboot 0x140000 /bdi2000/u-boot.bin; " \
"protect off 60000000 6003FFFF; " \
"erase 60000000 6003FFFF; " \
- "cp.b 140000 60000000 $(filesize); " \
+ "cp.b 140000 60000000 ${filesize}; " \
"protect on 60000000 6003FFFF\0" \
"copyenv="\
"protect off 60040000 6004FFFF; " \
"echo\\;" \
"bootp\\;" \
"setenv bootargs root=/dev/ram0 rw quiet " \
- "ip=\\$(ipaddr):\\$(serverip):\\$(gatewayip):\\$(netmask):\\$(hostname)::off\\;" \
+ "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
"run boot-hook\\;" \
"bootm\0" \
"root-on-initrd-debug="\
"echo\\;" \
"bootp\\;" \
"setenv bootargs root=/dev/ram0 rw debug " \
- "ip=\\$(ipaddr):\\$(serverip):\\$(gatewayip):\\$(netmask):\\$(hostname)::off\\;" \
+ "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
"run debug-hook\\;" \
"run boot-hook\\;" \
"bootm\0" \
"echo\\;" \
"bootp\\;" \
"setenv bootargs root=/dev/nfs rw quiet " \
- "nfsroot=\\$(serverip):\\$(rootpath) " \
- "ip=\\$(ipaddr):\\$(serverip):\\$(gatewayip):\\$(netmask):\\$(hostname)::off\\;" \
+ "nfsroot=\\${serverip}:\\${rootpath} " \
+ "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
"run boot-hook\\;" \
"bootm\0" \
"root-on-nfs-debug="\
"echo\\;" \
"bootp\\;" \
"setenv bootargs root=/dev/nfs rw debug " \
- "nfsroot=\\$(serverip):\\$(rootpath) " \
- "ip=\\$(ipaddr):\\$(serverip):\\$(gatewayip):\\$(netmask):\\$(hostname)::off\\;" \
+ "nfsroot=\\${serverip}:\\${rootpath} " \
+ "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
"run debug-hook\\;" \
"run boot-hook\\;" \
"bootm\0" \
"setenv checkhostname;" \
"setenv ethaddr 00:09:70:00:00:01;" \
"bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) debug " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} debug " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"run debug-hook;" \
"run boot-hook;" \
"bootm\0" \
"debug-hook="\
- "echo ipaddr $(ipaddr);" \
- "echo serverip $(serverip);" \
- "echo gatewayip $(gatewayip);" \
- "echo netmask $(netmask);" \
- "echo hostname $(hostname)\0" \
+ "echo ipaddr ${ipaddr};" \
+ "echo serverip ${serverip};" \
+ "echo gatewayip ${gatewayip};" \
+ "echo netmask ${netmask};" \
+ "echo hostname ${hostname}\0" \
"ana=run adc ; run dac\0" \
"adc=run adc-12 ; run adc-34\0" \
"adc-12=echo ### ADC-12 ; imd.b e 81 e\0" \
"echo;" \
"bootp;" \
"setenv bootargs root=/dev/ram0 rw quiet " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"run boot-hook;" \
"bootm"
#endif /* CONFIG_BOOT_ROOT_INITRD */
"version;" \
"echo;" \
"bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) quiet " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} quiet " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"run boot-hook;" \
"bootm"
#endif /* CONFIG_BOOT_ROOT_NFS */
#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot for the sbc405;echo;echo Type \"? or help\" to get on-line help;echo"
#define CONFIG_RAMBOOT \
- "setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+ "setenv bootargs root=/dev/ram rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"bootm ffc00000 ffca0000"
#define CONFIG_NFSBOOT \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"bootm ffc00000"
#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND "version;echo;tftpboot $(loadaddr) $(loadfile);bootvx" /* autoboot command */
+#define CONFIG_BOOTCOMMAND "version;echo;tftpboot ${loadaddr} ${loadfile};bootvx" /* autoboot command */
#define CONFIG_MII 1 /* MII PHY management */
"env_endaddr=FF03FFFF\0" \
"loadfile=vxWorks.st\0" \
"loadaddr=0x01000000\0" \
- "net_load=tftpboot $(loadaddr) $(loadfile)\0" \
+ "net_load=tftpboot ${loadaddr} ${loadfile}\0" \
"uboot_startaddr=FFFC0000\0" \
"uboot_endaddr=FFFFFFFF\0" \
- "update=tftp $(loadaddr) u-boot.bin;" \
- "protect off $(uboot_startaddr) $(uboot_endaddr);" \
- "era $(uboot_startaddr) $(uboot_endaddr);" \
- "cp.b $(loadaddr) $(uboot_startaddr) $(filesize);" \
- "protect on $(uboot_startaddr) $(uboot_endaddr)\0" \
- "zapenv=protect off $(env_startaddr) $(env_endaddr);" \
- "era $(env_startaddr) $(env_endaddr);" \
- "protect on $(env_startaddr) $(env_endaddr)\0"
+ "update=tftp ${loadaddr} u-boot.bin;" \
+ "protect off ${uboot_startaddr} ${uboot_endaddr};" \
+ "era ${uboot_startaddr} ${uboot_endaddr};" \
+ "cp.b ${loadaddr} ${uboot_startaddr} ${filesize};" \
+ "protect on ${uboot_startaddr} ${uboot_endaddr}\0" \
+ "zapenv=protect off ${env_startaddr} ${env_endaddr};" \
+ "era ${env_startaddr} ${env_endaddr};" \
+ "protect on ${env_startaddr} ${env_endaddr}\0"
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
+#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
*
* => printenv bootcmd
* bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw
- * nfsroot=$(serverip):$(rootpath)
- * ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;run boot-hook;bootm
+ * nfsroot=${serverip}:${rootpath}
+ * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm
*
* => run root-on-initrd
* => printenv bootcmd
* bootcmd=version;echo;bootp;setenv bootargs root=/dev/ram0 rw
- * ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;run boot-hook;bootm
+ * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm
*
* => run root-on-nfs
* => printenv bootcmd
* bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw
- * nfsroot=$(serverip):$(rootpath)
- * ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;run boot-hook;bootm
+ * nfsroot=${serverip}:${rootpath}
+ * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm
*
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"tftpboot 0x140000 /bdi2000/u-boot.bin;" \
"protect off 1:0;" \
"erase 1:0;" \
- "cp.b 140000 40000000 $(filesize);" \
+ "cp.b 140000 40000000 ${filesize};" \
"protect on 1:0\0" \
"zapenv="\
"protect off 1:1;" \
"echo;" \
"bootp;" \
"setenv bootargs root=/dev/ram0 rw " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"run boot-hook;" \
"bootm\0" \
"root-on-nfs="\
"echo;" \
"bootp;" \
"setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+ "nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"run boot-hook;" \
"bootm\0" \
"boot-hook=echo\0"
"echo;" \
"bootp;" \
"setenv bootargs root=/dev/ram0 rw " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"bootm"
#endif /* CONFIG_BOOT_ROOT_INITRD */
"version;" \
"echo;" \
"bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"bootm"
#endif /* CONFIG_BOOT_ROOT_NFS */
"rootpath=/opt/eldk/ppc_6xx\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
"flash_self=run ramargs addip;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
"flash_nfs=run nfsargs addip;" \
- "bootm $(kernel_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "bootm ${kernel_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"bootfile=/tftpboot/tqm5200/uImage\0" \
- "load=tftp 200000 $(u-boot)\0" \
+ "load=tftp 200000 ${u-boot}\0" \
"u-boot=/tftpboot/tqm5200/u-boot.bin" CONFIG_U_BOOT_SUFFIX \
"update=protect off FC000000 FC05FFFF;" \
"erase FC000000 FC05FFFF;" \
- "cp.b 200000 FC000000 $(filesize);" \
+ "cp.b 200000 FC000000 ${filesize};" \
"protect on FC000000 FC05FFFF\0" \
""
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */
+#define CONFIG_BAUDRATE 115200 /* console baudrate = 115.2kbps */
#define CONFIG_XIN 10000000 /* 10 MHz input xtal */
#define CONFIG_CRC32_VERIFY 1
#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
-/* Note: change below for your network setting!!!
- * This was done just to facilitate manufacturing test and configuration.
- */
-#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
+/*****************************************************************************/
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE 1
-#define CONFIG_SERVERIP 192.168.08.1
-#define CONFIG_IPADDR 192.168.08.85
-#define CONFIG_GATEWAYIP 192.168.08.1
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_HOSTNAME stx_xtc
-#define CONFIG_ROOTPATH /xtcroot
-#define CONFIG_BOOTFILE uImage
-#define CONFIG_LOADADDR 0x1000000
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE 8192
+#define OF_CPU "PowerPC,MPC870@0"
+#define OF_TBCLK (MPC8XX_HZ / 16)
#endif /* __CONFIG_H */
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 0x210000 $(bootfile);run nfsargs addip;bootm\0" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 0x210000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/sinovee/ppc8xx-linux-2.0/target\0" \
"bootfile=pImage-sc855t\0" \
"kernel_addr=48000000\0" \
"ramdisk_addr=48100000\0" \
""
#define CONFIG_BOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"tftpboot 0x210000 pImage-sc855t;bootm 0x210000"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
"netboot=dhcp;tftp;run netargs; bootm\0" \
"nfsargs=setenv bootargs root=/dev/nfs ip=dhcp\0" \
"localargs=setenv bootargs root=1F02 ip=dhcp\0" \
- "addmisc=setenv bootargs $(bootargs) " \
- "console=ttyS0,$(baudrate) " \
+ "addmisc=setenv bootargs ${bootargs} " \
+ "console=ttyS0,${baudrate} " \
"read-only=readonly\0" \
"netargs=run nfsargs addmisc\0" \
"flash_nfs=run nfsargs addmisc;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_local=run localargs addmisc;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"netboot_initrd=dhcp;tftp;tftp 80600000 initrd;" \
"setenv bootargs root=/dev/ram ramdisk_size=8192 ip=dhcp;"\
"run addmisc;" \
"ramdisk_addr=B0100000\0" \
"u-boot=u-boot.bin\0" \
"bootfile=uImage\0" \
- "load=dhcp;tftp 80400000 $(u-boot)\0" \
- "load_kernel=dhcp;tftp 80400000 $(bootfile)\0" \
+ "load=dhcp;tftp 80400000 ${u-boot}\0" \
+ "load_kernel=dhcp;tftp 80400000 ${bootfile}\0" \
"update_uboot=run load;" \
"protect off BFC00000 BFC3FFFF;" \
"erase BFC00000 BFC3FFFF;" \
- "cp.b 80400000 BFC00000 $(filesize)\0" \
+ "cp.b 80400000 BFC00000 ${filesize}\0" \
"update_kernel=run load_kernel;" \
"erase BFC60000 BFD5FFFF;" \
- "cp.b 80400000 BFC60000 $(filesize)\0" \
+ "cp.b 80400000 BFC60000 ${filesize}\0" \
"initenv=erase bfc40000 bfc5ffff\0" \
""
/*#define CONFIG_BOOTCOMMAND "run flash_local" */
CFG_CMD_BSP | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
- CFG_CMD_USB | \
CFG_CMD_FAT | \
+ CFG_CMD_JFFS2 | \
CFG_CMD_NFS | \
- CFG_CMD_SNTP )
+ CFG_CMD_SNTP | \
+ CFG_CMD_USB )
#else
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CONFIG_COMMANDS_ADD_HWFLOW | \
CFG_CMD_BSP | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
- CFG_CMD_USB | \
CFG_CMD_FAT | \
+ CFG_CMD_JFFS2 | \
CFG_CMD_NFS | \
- CFG_CMD_SNTP )
+ CFG_CMD_SNTP | \
+ CFG_CMD_USB )
#endif
/* moved up */
#else /* !CFG_HUSH_PARSER */
#define CONFIG_EXTRA_ENV_SETTINGS \
"nfs_args=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"rootpath=/opt/eldk/arm_920TDI\0" \
"ram_args=setenv bootargs root=/dev/ram rw\0" \
- "add_net=setenv bootargs $(bootargs) ethaddr=$(ethaddr) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off\0" \
- "add_misc=setenv bootargs $(bootargs) console=ttyS0 panic=1\0" \
+ "add_net=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \
+ "add_misc=setenv bootargs ${bootargs} console=ttyS0 panic=1\0" \
"u-boot=/tftpboot/TRAB/u-boot.bin\0" \
- "load=tftp C100000 $(u-boot)\0" \
+ "load=tftp C100000 ${u-boot}\0" \
"update=protect off 0 5FFFF;era 0 5FFFF;" \
- "cp.b C100000 0 $(filesize)\0" \
+ "cp.b C100000 0 ${filesize}\0" \
"loadfile=/tftpboot/TRAB/uImage\0" \
"loadaddr=c400000\0" \
- "net_load=tftpboot $(loadaddr) $(loadfile)\0" \
+ "net_load=tftpboot ${loadaddr} ${loadfile}\0" \
"net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \
"kernel_addr=000C0000\0" \
- "flash_nfs=run nfs_args add_net add_misc;bootm $(kernel_addr)\0" \
+ "flash_nfs=run nfs_args add_net add_misc;bootm ${kernel_addr}\0" \
"mdm_init1=ATZ\0" \
"mdm_init2=ATS0=1\0" \
"mdm_flow_control=rts/cts\0"
#else /* !CFG_HUSH_PARSER */
#define CONFIG_EXTRA_ENV_SETTINGS \
"nfs_args=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"rootpath=/opt/eldk/arm_920TDI\0" \
"ram_args=setenv bootargs root=/dev/ram rw\0" \
- "add_net=setenv bootargs $(bootargs) ethaddr=$(ethaddr) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off\0" \
- "add_misc=setenv bootargs $(bootargs) console=ttyS0 panic=1\0" \
+ "add_net=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \
+ "add_misc=setenv bootargs ${bootargs} console=ttyS0 panic=1\0" \
"u-boot=/tftpboot/TRAB/u-boot.bin\0" \
- "load=tftp C100000 $(u-boot)\0" \
+ "load=tftp C100000 ${u-boot}\0" \
"update=protect off 0 3FFFF;era 0 3FFFF;" \
- "cp.b C100000 0 $(filesize);" \
+ "cp.b C100000 0 ${filesize};" \
"setenv filesize;saveenv\0" \
"loadfile=/tftpboot/TRAB/uImage\0" \
"loadaddr=C400000\0" \
- "net_load=tftpboot $(loadaddr) $(loadfile)\0" \
+ "net_load=tftpboot ${loadaddr} ${loadfile}\0" \
"net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \
"kernel_addr=000C0000\0" \
- "flash_nfs=run nfs_args add_net add_misc;bootm $(kernel_addr)\0" \
+ "flash_nfs=run nfs_args add_net add_misc;bootm ${kernel_addr}\0" \
"mdm_init1=ATZ\0" \
"mdm_init2=ATS0=1\0" \
"mdm_flow_control=rts/cts\0"
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MONITOR_LEN (256 << 10)
+/* Dynamic MTD partition support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=0"
+
+/* production flash layout */
+#define MTDPARTS_DEFAULT "mtdparts=0:32k(Firmware1)ro," \
+ "16k(Env1)," \
+ "16k(Env2)," \
+ "320k(Firmware2)ro," \
+ "896k(Kernel)," \
+ "5376k(Root-FS)," \
+ "1408k(JFFS2)," \
+ "-(VFD)"
+
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define CFG_ENV_SIZE 0x4000
#define CFG_ENV_SECT_SIZE 0x20000
#else
-#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x8000)
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000)
#define CFG_ENV_SIZE 0x4000
#define CFG_ENV_SECT_SIZE 0x4000
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
- "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
"flash_nfs=run nfsargs addip addtty;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addtty;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/uc100/uImage\0" \
"ramdisk_addr=40100000\0" \
"load=tftp 100000 /tftpboot/uc100/u-boot.bin\0" \
"update=protect off 40700000 4073ffff;era 40700000 4073ffff;" \
- "cp.b 100000 40700000 $(filesize);" \
+ "cp.b 100000 40700000 ${filesize};" \
"setenv filesize;saveenv\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
"ramdisk_addr=FF800000\0" \
"u-boot_startaddr=FFB00000\0" \
"u-boot_endaddr=FFB2FFFF\0" \
- "nfsargs=setenv bootargs console=ttyS0,$(baudrate) root=/dev/nfs rw \
-nfsroot=$(nfsrootip):$(rootpath) ip=dhcp\0" \
- "ramargs=setenv bootargs console=ttyS0,$(baudrate) root=/dev/ram0\0" \
- "smargs=setenv bootargs console=ttyS0,$(baudrate) root=/dev/mtdblock1 ro\0" \
- "fwargs=setenv bootargs console=ttyS0,$(baudrate) root=/dev/sda2 ro\0" \
- "nfsboot=run nfsargs;bootm $(kernel_addr)\0" \
- "ramboot=run ramargs;bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "smboot=run smargs;bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "fwboot=run fwargs;bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "update_u-boot=tftp $(loadaddr) /bdi2000/u-boot.bin;protect off \
-$(u-boot_startaddr) $(u-boot_endaddr);era $(u-boot_startaddr) \
-$(u-boot_endaddr);cp.b $(loadaddr) $(u-boot_startaddr) $(filesize);\
-protect on $(u-boot_startaddr) $(u-boot_endaddr)"
+ "nfsargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/nfs rw \
+nfsroot=${nfsrootip}:${rootpath} ip=dhcp\0" \
+ "ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram0\0" \
+ "smargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/mtdblock1 ro\0" \
+ "fwargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/sda2 ro\0" \
+ "nfsboot=run nfsargs;bootm ${kernel_addr}\0" \
+ "ramboot=run ramargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "smboot=run smargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "fwboot=run fwargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "update_u-boot=tftp ${loadaddr} /bdi2000/u-boot.bin;protect off \
+${u-boot_startaddr} ${u-boot_endaddr};era ${u-boot_startaddr} \
+${u-boot_endaddr};cp.b ${loadaddr} ${u-boot_startaddr} ${filesize};\
+protect on ${u-boot_startaddr} ${u-boot_endaddr}"
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BOOTCOMMAND \
"tftpboot; " \
"setenv bootargs console=tty0 " \
- "root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_AUTOLOAD "n" /* no autoload */
#define CONFIG_PREBOOT "run setup"
#define CONFIG_EXTRA_ENV_SETTINGS \
- "setup=setenv bootargs console=ttyS0,$(baudrate) " \
+ "setup=setenv bootargs console=ttyS0,${baudrate} " \
"root=/dev/nfs ip=dhcp\0" \
"update=erase c000000 c03ffff; " \
- "cp.b 10400000 c000000 $(filesize)\0"
+ "cp.b 10400000 c000000 ${filesize}\0"
#else
#define CONFIG_BOOTDELAY 3
#undef CONFIG_BOOTARGS /* boot command will set bootargs */
"netdev=eth0\0" \
"hostname=walnut\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
- "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
"flash_nfs=run nfsargs addip addtty;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addtty;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/walnut/uImage\0" \
#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+#define CONFIG_NET_MULTI /* needed for NetConsole */
+
/*-----------------------------------------------------------------------
* I2C stuff
*-----------------------------------------------------------------------
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
+#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
-#define CONFIG_YELLOWSTONE 1 /* Board is BAMBOO */
-#define CONFIG_440GR 1 /* Specific PPC440GR support */
-
-#define CONFIG_4xx 1 /* ... PPC4xx family */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#undef CFG_DRAM_TEST /* disable - takes long time! */
+#define CONFIG_YOLLOWSTONE 1 /* Board is Yellowstone */
+#define CONFIG_440GR 1 /* Specific PPC440EP support */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
+
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CFG_FLASH_BASE 0xf0000000 /* start of FLASH */
-#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
-#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory */
-#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
-#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
-#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
-
+#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
+#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
+#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
+#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
+#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
+#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
/*Don't change either of these*/
-#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
-#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs */
+#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/
+#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/
/*Don't change either of these*/
-#define CFG_USB_DEVICE 0x50000000
-#define CFG_NVRAM_BASE_ADDR 0x80000000
-#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000)
+#define CFG_USB_DEVICE 0x50000000
+#define CFG_NVRAM_BASE_ADDR 0x80000000
+#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000)
+#define CFG_BOOT_BASE_ADDR 0xf0000000
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/
-#define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */
-#define CFG_INIT_RAM_END 0x2000
-#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
+#define CFG_INIT_RAM_END (8 << 10)
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
-#define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */
-#define CFG_SDRAM_BANKS (2)
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_SERIAL_MULTI 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SERIAL_MULTI 1
/*define this if you want console on UART1*/
#undef CONFIG_UART1_CONSOLE
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*-----------------------------------------------------------------------
- * NVRAM/RTC
- *
- * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
- * The DS1558 code assumes this condition
- *
+ * Environment
*----------------------------------------------------------------------*/
-#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
-#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
+/*
+ * Define here the location of the environment variables (FLASH or EEPROM).
+ * Note: DENX encourages to use redundant environment in FLASH.
+ */
+#if 1
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+#else
+#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
+#endif
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
-#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
+
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
-#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 120000 /* Timeout for Flash Write (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
+#define CFG_KBYTES_SDRAM (128 * 1024) /* 128MB */
+#define CFG_SDRAM_BANKS (2)
+
/*-----------------------------------------------------------------------
* I2C
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#undef CFG_ENV_IS_IN_NVRAM /*No NVRAM on board*/
-#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
-#define CFG_ENV_IS_IN_EEPROM 1
-
-/* Define to allow the user to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
#define CFG_I2C_MULTI_EEPROMS
-#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
-#define CFG_ENV_OFFSET 0x0
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
-#define CONFIG_BOOTCOMMAND "bootm 0xfe000000" /* autoboot command */
-#define CONFIG_BOOTDELAY 3 /* disable autoboot */
+#ifdef CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
+#define CFG_ENV_OFFSET 0x0
+#endif /* CFG_ENV_IS_IN_EEPROM */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=yellowstone\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/opt/eldk/ppc_4xx\0" \
+ "bootfile=/tftpboot/yellowstone/uImage\0" \
+ "kernel_addr=fc000000\0" \
+ "ramdisk_addr=fc100000\0" \
+ "load=tftp 100000 /tftpboot/yellowstone/u-boot.bin\0" \
+ "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \
+ "cp.b 100000 fff80000 80000;" \
+ "setenv filesize;saveenv\0" \
+ "upd=run load;run update\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_BAUDRATE 115200
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_NET_MULTI 1 /* required for netconsole */
-#define CONFIG_PHY1_ADDR 3
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_NET_MULTI 1 /* required for netconsole */
+#define CONFIG_PHY1_ADDR 3
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 10.0.4.251
-#define CONFIG_ETHADDR 00:10:EC:00:12:34
-#define CONFIG_ETH1ADDR 00:10:EC:00:12:35
-#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
-#define CONFIG_SERVERIP 10.0.4.115
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE /* include NetConsole support */
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_HW_WATCHDOG /* watchdog */
#endif
-#ifdef CONFIG_440EP
- /* Need to define POST */
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_ECHO | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- /* CFG_CMD_EXT2 |*/ \
- /* CFG_CMD_FAT |*/ \
- CFG_CMD_I2C | \
- /* CFG_CMD_IDE |*/ \
- CFG_CMD_IRQ | \
- /* CFG_CMD_KGDB |*/ \
- CFG_CMD_MII | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- CFG_CMD_FLASH | \
- /* CFG_CMD_SPI |*/ \
- CFG_CMD_USB | \
- 0 ) & ~CFG_CMD_IMLS)
-#else
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_ECHO | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- /* CFG_CMD_EXT2 |*/ \
- /* CFG_CMD_FAT |*/ \
- CFG_CMD_I2C | \
- /* CFG_CMD_IDE |*/ \
- CFG_CMD_IRQ | \
- /* CFG_CMD_KGDB |*/ \
- CFG_CMD_MII | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- CFG_CMD_FLASH | \
- /* CFG_CMD_SPI |*/ \
- 0 ) & ~CFG_CMD_IMLS)
-#endif
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_ELF | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_MII | \
+ CFG_CMD_NET | \
+ CFG_CMD_NFS | \
+ CFG_CMD_PCI | \
+ CFG_CMD_PING | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SDRAM)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-#define CONFIG_LYNXKDI 1 /* support kdi files */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+#define CONFIG_LYNXKDI 1 /* support kdi files */
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
/* General PCI */
-#define CONFIG_PCI /* include pci support */
-#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
+#define CONFIG_PCI /* include pci support */
+#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
+#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT
-#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
-#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
+#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
/*
* For booting Linux, the board info and command line data
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
+
#endif /* __CONFIG_H */
"netdev=eth0\0" \
"hostname=yosemite\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
- "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
"flash_nfs=run nfsargs addip addtty;" \
- "bootm $(kernel_addr)\0" \
+ "bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addtty;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/yosemite/uImage\0" \
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
-#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE /* include NetConsole support */
/* Partitions */
#define CONFIG_MAC_PARTITION
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
+ CFG_CMD_FAT | \
+ CFG_CMD_EXT2 | \
CFG_CMD_USB )
+#define CONFIG_SUPPORT_VFAT
+
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE (32<<10) /* For IBM 440 CPUs */
+#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
| CRAMFS_FLAG_WRONG_SIGNATURE \
| CRAMFS_FLAG_SHIFTED_ROOT_OFFSET )
+#if __BYTE_ORDER == __LITTLE_ENDIAN
#define CRAMFS_16(x) (x)
#define CRAMFS_24(x) (x)
#define CRAMFS_32(x) (x)
#define CRAMFS_GET_OFFSET(x) ((x)->offset)
#define CRAMFS_SET_OFFSET(x,y) ((x)->offset = (y))
#define CRAMFS_SET_NAMELEN(x,y) ((x)->namelen = (y))
+#elif __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __KERNEL__
+#define CRAMFS_16(x) swab16(x)
+#define CRAMFS_24(x) ((swab32(x)) >> 8)
+#define CRAMFS_32(x) swab32(x)
+#else /* not __KERNEL__ */
+#define CRAMFS_16(x) bswap_16(x)
+#define CRAMFS_24(x) ((bswap_32(x)) >> 8)
+#define CRAMFS_32(x) bswap_32(x)
+#endif /* not __KERNEL__ */
+#define CRAMFS_GET_NAMELEN(x) (((u8*)(x))[8] & 0x3f)
+#define CRAMFS_GET_OFFSET(x) ((CRAMFS_24(((u32*)(x))[2] & 0xffffff) << 2) |\
+ ((((u32*)(x))[2] & 0xc0000000) >> 30))
+#define CRAMFS_SET_NAMELEN(x,y) (((u8*)(x))[8] = (((0x3f & (y))) | \
+ (0xc0 & ((u8*)(x))[8])))
+#define CRAMFS_SET_OFFSET(x,y) (((u32*)(x))[2] = (((y) & 3) << 30) | \
+ CRAMFS_24((((y) & 0x03ffffff) >> 2)) | \
+ (((u32)(((u8*)(x))[8] & 0x3f)) << 24))
+#else
+#error "__BYTE_ORDER must be __LITTLE_ENDIAN or __BIG_ENDIAN"
+#endif
/* Uncompression interfaces to the underlying zlib */
int cramfs_uncompress_block(void *dst, void *src, int srclen);
/****************** function prototypes **********************/
-static unsigned int dm9161_IsPhyConnected(AT91PS_EMAC p_mac);
-static unsigned char dm9161_GetLinkSpeed(AT91PS_EMAC p_mac);
-static unsigned char dm9161_AutoNegotiate(AT91PS_EMAC p_mac, int *status);
-static unsigned char dm9161_InitPhy(AT91PS_EMAC p_mac);
+unsigned int dm9161_IsPhyConnected(AT91PS_EMAC p_mac);
+unsigned char dm9161_GetLinkSpeed(AT91PS_EMAC p_mac);
+unsigned char dm9161_AutoNegotiate(AT91PS_EMAC p_mac, int *status);
+unsigned char dm9161_InitPhy(AT91PS_EMAC p_mac);
/*
- * (C) Copyright 2000-2004
+ * (C) Copyright 2000-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
/* common/flash.c */
extern void flash_protect (int flag, ulong from, ulong to, flash_info_t *info);
-extern int flash_write (uchar *, ulong, ulong);
+extern int flash_write (char *, ulong, ulong);
extern flash_info_t *addr2info (ulong);
extern int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt);
#define MX_MANUFACT 0x00C200C2 /* MXIC manuf. ID in D23..D16, D7..D0 */
#define TOSH_MANUFACT 0x00980098 /* TOSHIBA manuf. ID in D23..D16, D7..D0 */
#define MT2_MANUFACT 0x002C002C /* alternate MICRON manufacturer ID*/
-#define EXCEL_MANUFACT 0x004A004A /* Excel Semiconductor */
+#define EXCEL_MANUFACT 0x004A004A /* Excel Semiconductor */
/* Micron Technologies (INTEL compat.) */
#define MT_ID_28F400_T 0x44704470 /* 28F400B3 ID ( 4 M, top boot sector) */
#define AMD_ID_LV040B 0x4F /* 29LV040B ID */
/* 4 Mbit, 512K x 8, */
/* 8 64K x 8 uniform sectors */
-
+#define AMD_ID_F033C 0xA3 /* 29LV033C ID */
+ /* 32 Mbit, 4Mbits x 8, */
+ /* 64 64K x 8 uniform sectors */
+#define AMD_ID_F065D 0x93 /* 29LV065D ID */
+ /* 64 Mbit, 8Mbits x 8, */
+ /* 126 64K x 8 uniform sectors */
+#define ATM_ID_LV040 0x13 /* 29LV040B ID */
+ /* 4 Mbit, 512K x 8, */
+ /* 8 64K x 8 uniform sectors */
#define AMD_ID_F040B 0xA4 /* 29F040B ID */
/* 4 Mbit, 512K x 8, */
/* 8 64K x 8 uniform sectors */
#define AMD_ID_F016D 0xAD /* 29F016 ID ( 2 M x 8) */
#define AMD_ID_F032B 0x41 /* 29F032 ID ( 4 M x 8) */
#define AMD_ID_LV116DT 0xC7 /* 29LV116DT ( 2 M x 8, top boot sect) */
-#define AMD_ID_LV116DB 0x4C /* 29LV116DB ( 2 M x 8, bottom boot sect) */
+#define AMD_ID_LV116DB 0x4C /* 29LV116DB ( 2 M x 8, bottom boot sect) */
#define AMD_ID_LV016B 0xc8 /* 29LV016 ID ( 2 M x 8) */
-#define AMD_ID_PL160CB 0x22452245 /* 29PL160CB ID (16 M, bottom boot sect */
+#define AMD_ID_PL160CB 0x22452245 /* 29PL160CB ID (16 M, bottom boot sect */
#define AMD_ID_LV400T 0x22B922B9 /* 29LV400T ID ( 4 M, top boot sector) */
#define AMD_ID_LV400B 0x22BA22BA /* 29LV400B ID ( 4 M, bottom boot sect) */
#define AMD_ID_LV160B 0x22492249 /* 29LV160B ID (16 M, bottom boot sect) */
#define AMD_ID_DL163T 0x22282228 /* 29DL163T ID (16 M, top boot sector) */
-#define AMD_ID_DL163B 0x222B222B /* 29DL163B ID (16 M, bottom boot sect) */
+#define AMD_ID_DL163B 0x222B222B /* 29DL163B ID (16 M, bottom boot sect) */
#define AMD_ID_LV320T 0x22F622F6 /* 29LV320T ID (32 M, top boot sector) */
#define MX_ID_LV320T 0x22A722A7 /* 29LV320T by Macronix, AMD compatible */
#define AMD_ID_DL640 0x227E227E /* 29DL640D ID (64 M, dual boot sectors)*/
#define AMD_ID_MIRROR 0x227E227E /* 1st ID word for MirrorBit family */
-#define AMD_ID_DL640G_2 0x22022202 /* 2nd ID word for AM29DL640G at 0x38 */
-#define AMD_ID_DL640G_3 0x22012201 /* 3rd ID word for AM29DL640G at 0x3c */
-#define AMD_ID_LV640U_2 0x220C220C /* 2nd ID word for AM29LV640M at 0x38 */
-#define AMD_ID_LV640U_3 0x22012201 /* 3rd ID word for AM29LV640M at 0x3c */
+#define AMD_ID_DL640G_2 0x22022202 /* 2nd ID word for AM29DL640G at 0x38 */
+#define AMD_ID_DL640G_3 0x22012201 /* 3rd ID word for AM29DL640G at 0x3c */
+#define AMD_ID_LV640U_2 0x220C220C /* 2nd ID word for AM29LV640M at 0x38 */
+#define AMD_ID_LV640U_3 0x22012201 /* 3rd ID word for AM29LV640M at 0x3c */
#define AMD_ID_LV640MT_2 0x22102210 /* 2nd ID word for AM29LV640MT at 0x38 */
#define AMD_ID_LV640MT_3 0x22012201 /* 3rd ID word for AM29LV640MT at 0x3c */
#define AMD_ID_LV640MB_2 0x22102210 /* 2nd ID word for AM29LV640MB at 0x38 */
#define AMD_ID_LV256U_3 0x22012201 /* 3rd ID word for AM29LV256M at 0x3c */
#define AMD_ID_GL064M_2 0x22132213 /* 2nd ID word for S29GL064M-R6 */
#define AMD_ID_GL064M_3 0x22012201 /* 3rd ID word for S29GL064M-R6 */
+#define AMD_ID_GL064MT_2 0x22102210 /* 2nd ID word for S29GL064M-R3 (top boot sector) */
+#define AMD_ID_GL064MT_3 0x22012201 /* 3rd ID word for S29GL064M-R3 (top boot sector) */
-#define AMD_ID_LV320B_2 0x221A221A /* 2d ID word for AM29LV320MB at 0x38 */
+#define AMD_ID_LV320B_2 0x221A221A /* 2d ID word for AM29LV320MB at 0x38 */
#define AMD_ID_LV320B_3 0x22002200 /* 3d ID word for AM29LV320MB at 0x3c */
#define AMD_ID_LV640U 0x22D722D7 /* 29LV640U ID (64 M, uniform sectors) */
+#define AMD_ID_LV650U 0x22D722D7 /* 29LV650U ID (64 M, uniform sectors) */
#define ATM_ID_BV1614 0x000000C0 /* 49BV1614 ID */
#define ATM_ID_BV1614A 0x000000C8 /* 49BV1614A ID */
#define INTEL_ID_28F320J3A 0x00160016 /* 32M = 128K x 32 */
#define INTEL_ID_28F640J3A 0x00170017 /* 64M = 128K x 64 */
#define INTEL_ID_28F128J3A 0x00180018 /* 128M = 128K x 128 */
+#define INTEL_ID_28F256J3A 0x001D001D /* 256M = 128K x 256 */
#define INTEL_ID_28F256L18T 0x880D880D /* 256M = 128K x 255 + 32k x 4 */
#define INTEL_ID_28F64K3 0x88018801 /* 64M = 32K x 255 + 32k x 4 */
#define INTEL_ID_28F128K3 0x88028802 /* 128M = 64K x 255 + 32k x 4 */
#define FLASH_AMDL324T 0x0014 /* AMD AM29DL324 */
#define FLASH_AMDL324B 0x0015
-#define FLASH_AMDLV033C 0x0018
-#define FLASH_AMDLV065D 0x001A
+#define FLASH_AMDLV033C 0x0018
+#define FLASH_AMDLV065D 0x001A
#define FLASH_AMDL640 0x0016 /* AMD AM29DL640D */
#define FLASH_AMD016 0x0018 /* AMD AM29F016D */
-#define FLASH_AMDL640MB 0x0019 /* AMD AM29LV640MB (64M, bottom boot sect)*/
-#define FLASH_AMDL640MT 0x001A /* AMD AM29LV640MT (64M, top boot sect) */
+#define FLASH_AMDL640MB 0x0019 /* AMD AM29LV640MB (64M, bottom boot sect)*/
+#define FLASH_AMDL640MT 0x001A /* AMD AM29LV640MT (64M, top boot sect) */
#define FLASH_SST200A 0x0040 /* SST 39xF200A ID ( 2M = 128K x 16 ) */
#define FLASH_SST400A 0x0042 /* SST 39xF400A ID ( 4M = 256K x 16 ) */
#define FLASH_AM033C 0x0091 /* AMD AM29LV033 ( 32M = 4M x 8 ) */
#define FLASH_LH28F016SCT 0x0092 /* Sharp 28F016SCT ( 8 Meg Flash SIMM ) */
#define FLASH_28F160F3B 0x0093 /* Intel 28F160F3B ( 16M = 1M x 16 ) */
+#define FLASH_AM065D 0x0093
#define FLASH_28F640J5 0x0099 /* INTEL 28F640J5 ( 64M = 128K x 64) */
#define FLASH_28F320C3B 0x009F /* Intel 28F320C3B ( 32M = 2M x 16 ) */
#define FLASH_28F640C3T 0x00A0 /* Intel 28F640C3T ( 64M = 4M x 16 ) */
#define FLASH_28F640C3B 0x00A1 /* Intel 28F640C3B ( 64M = 4M x 16 ) */
-#define FLASH_AMLV320U 0x00A2 /* AMD 29LV320M ( 32M = 2M x 16 ) */
-#define FLASH_AMLV640U 0x00A4 /* AMD 29LV640M ( 64M = 4M x 16 ) */
+#define FLASH_AMLV320U 0x00A2 /* AMD 29LV320M ( 32M = 2M x 16 ) */
+
+#define FLASH_AM033 0x00A3 /* AMD AmL033C90V1 (32M = 4M x 8) */
+#define FLASH_AM065 0x0093 /* AMD AmL065DU12RI (64M = 8M x 8) */
+#define FLASH_AT040 0x00A5 /* Amtel AT49LV040 (4M = 512K x 8) */
+
+#define FLASH_AMLV640U 0x00A4 /* AMD 29LV640M ( 64M = 4M x 16 ) */
#define FLASH_AMLV128U 0x00A6 /* AMD 29LV128M ( 128M = 8M x 16 ) */
-#define FLASH_AMLV320B 0x00A7 /* AMD 29LV320MB ( 32M = 2M x 16 ) */
+#define FLASH_AMLV320B 0x00A7 /* AMD 29LV320MB ( 32M = 2M x 16 ) */
#define FLASH_AMLV320T 0x00A8 /* AMD 29LV320MT ( 32M = 2M x 16 ) */
#define FLASH_AMLV256U 0x00AA /* AMD 29LV256M ( 256M = 16M x 16 ) */
-#define FLASH_MXLV320B 0x00AB /* MX 29LV320MB ( 32M = 2M x 16 ) */
+#define FLASH_MXLV320B 0x00AB /* MX 29LV320MB ( 32M = 2M x 16 ) */
#define FLASH_MXLV320T 0x00AC /* MX 29LV320MT ( 32M = 2M x 16 ) */
#define FLASH_28F256L18T 0x00B0 /* Intel 28F256L18T 256M = 128K x 255 + 32k x 4 */
#define FLASH_AMDL163T 0x00B2 /* AMD AM29DL163T (2M x 16 ) */
#define FLASH_AMDL163B 0x00B3
#define FLASH_28F64K3 0x00B4 /* Intel 28F64K3 ( 64M) */
-#define FLASH_28F128K3 0x00B6 /* Intel 28F128K3 ( 128M = 8M x 16 ) */
-#define FLASH_28F256K3 0x00B8 /* Intel 28F256K3 ( 256M = 16M x 16 ) */
+#define FLASH_28F128K3 0x00B6 /* Intel 28F128K3 ( 128M = 8M x 16 ) */
+#define FLASH_28F256K3 0x00B8 /* Intel 28F256K3 ( 256M = 16M x 16 ) */
#define FLASH_28F320J3A 0x00C0 /* INTEL 28F320J3A ( 32M = 128K x 32) */
#define FLASH_28F640J3A 0x00C2 /* INTEL 28F640J3A ( 64M = 128K x 64) */
#define FLASH_28F128J3A 0x00C4 /* INTEL 28F128J3A (128M = 128K x 128) */
+#define FLASH_28F256J3A 0x00C6 /* INTEL 28F256J3A (256M = 128K x 256) */
#define FLASH_FUJLV650 0x00D0 /* Fujitsu MBM 29LV650UE/651UE */
-#define FLASH_MT28S4M16LC 0x00E1 /* Micron MT28S4M16LC */
+#define FLASH_MT28S4M16LC 0x00E1 /* Micron MT28S4M16LC */
#define FLASH_S29GL064M 0x00F0 /* Spansion S29GL064M-R6 */
#define FLASH_UNKNOWN 0xFFFF /* unknown flash type */
#define FLASH_MAN_MX 0x00030000 /* MXIC */
#define FLASH_MAN_STM 0x00040000
#define FLASH_MAN_TOSH 0x00050000 /* Toshiba */
-#define FLASH_MAN_EXCEL 0x00060000 /* Excel Semiconductor */
+#define FLASH_MAN_EXCEL 0x00060000 /* Excel Semiconductor */
#define FLASH_MAN_SST 0x00100000
#define FLASH_MAN_INTEL 0x00300000
#define FLASH_MAN_MT 0x00400000
#define FLASH_MAN_SHARP 0x00500000
+#define FLASH_MAN_ATM 0x00600000
#define FLASH_TYPEMASK 0x0000FFFF /* extract FLASH type information */
/* root function definitions */
extern void fpga_init( ulong reloc_off );
extern int fpga_add( fpga_type devtype, void *desc );
-extern const int fpga_count( void );
+extern int fpga_count( void );
extern int fpga_load( int devnum, void *buf, size_t bsize );
extern int fpga_dump( int devnum, void *buf, size_t bsize );
extern int fpga_info( int devnum );
--- /dev/null
+/*
+ * OF Flat tree builder
+ *
+ */
+
+#ifndef FT_BUILD_H
+#define FT_BUILD_H
+
+#include <linux/types.h>
+#include <asm/u-boot.h>
+
+/* Definitions used by the flattened device tree */
+#define OF_DT_HEADER 0xd00dfeed /* marker */
+#define OF_DT_BEGIN_NODE 0x1 /* Start of node, full name */
+#define OF_DT_END_NODE 0x2 /* End node */
+#define OF_DT_PROP 0x3 /* Property: name off, size,
+ * content */
+#define OF_DT_NOP 0x4 /* nop */
+#define OF_DT_END 0x9
+
+#define OF_DT_VERSION 0x10
+
+struct boot_param_header {
+ u32 magic; /* magic word OF_DT_HEADER */
+ u32 totalsize; /* total size of DT block */
+ u32 off_dt_struct; /* offset to structure */
+ u32 off_dt_strings; /* offset to strings */
+ u32 off_mem_rsvmap; /* offset to memory reserve map */
+ u32 version; /* format version */
+ u32 last_comp_version; /* last compatible version */
+ /* version 2 fields below */
+ u32 boot_cpuid_phys; /* Physical CPU id we're booting on */
+ /* version 3 fields below */
+ u32 dt_strings_size; /* size of the DT strings block */
+};
+
+struct ft_cxt {
+ struct boot_param_header *bph;
+ int max_size; /* maximum size of tree */
+ int overflow; /* set when this happens */
+ u8 *p, *pstr, *pres; /* running pointers */
+ u8 *p_begin, *pstr_begin, *pres_begin; /* starting pointers */
+ u8 *p_anchor; /* start of constructed area */
+ int struct_size, strings_size, res_size;
+};
+
+void ft_begin_node(struct ft_cxt *cxt, const char *name);
+void ft_end_node(struct ft_cxt *cxt);
+
+void ft_begin_tree(struct ft_cxt *cxt);
+int ft_end_tree(struct ft_cxt *cxt);
+
+void ft_nop(struct ft_cxt *cxt);
+void ft_prop(struct ft_cxt *cxt, const char *name, const void *data, int sz);
+void ft_prop_str(struct ft_cxt *cxt, const char *name, const char *str);
+void ft_prop_int(struct ft_cxt *cxt, const char *name, int val);
+void ft_begin(struct ft_cxt *cxt, void *blob, int max_size);
+void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size);
+
+void ft_setup(void *blob, int size, bd_t * bd);
+
+void ft_dump_blob(const void *bphp);
+void ft_merge_blob(struct ft_cxt *cxt, void *blob);
+void *ft_get_prop(void *bphp, const char *propname, int *szp);
+
+#endif
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
*/
#ifndef __IMAGE_H__
#endif /* OPTIMIZE */
-static __inline__ __const__ __u16 __fswab16(__u16 x)
+static __inline__ __attribute__((const)) __u16 __fswab16(__u16 x)
{
return __arch__swab16(x);
}
__arch__swab16s(addr);
}
-static __inline__ __const__ __u32 __fswab32(__u32 x)
+static __inline__ __attribute__((const)) __u32 __fswab32(__u32 x)
{
return __arch__swab32(x);
}
}
#ifdef __BYTEORDER_HAS_U64__
-static __inline__ __const__ __u64 __fswab64(__u64 x)
+static __inline__ __attribute__((const)) __u64 __fswab64(__u64 x)
{
# ifdef __SWAB_64_THRU_32__
__u32 h = x >> 32;
* linux/include/linux/mtd/nand.h
*
* Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
- * Steven J. Hill <sjhill@realitydiluted.com>
- * Thomas Gleixner <tglx@linutronix.de>
+ * Steven J. Hill <sjhill@cotw.com>
+ * Thomas Gleixner <gleixner@autronix.de>
*
- * $Id: nand.h,v 1.68 2004/11/12 10:40:37 gleixner Exp $
+ * $Id: nand.h,v 1.7 2003/07/24 23:30:46 a0384864 Exp $
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* command delay times for different chips
* 04-28-2002 TG OOB config defines moved from nand.c to avoid duplicate
* defines in jffs2/wbuf.c
- * 08-07-2002 TG forced bad block location to byte 5 of OOB, even if
- * CONFIG_MTD_NAND_ECC_JFFS2 is not set
- * 08-10-2002 TG extensions to nand_chip structure to support HW-ECC
- *
- * 08-29-2002 tglx nand_chip structure: data_poi for selecting
- * internal / fs-driver buffer
- * support for 6byte/512byte hardware ECC
- * read_ecc, write_ecc extended for different oob-layout
- * oob layout selections: NAND_NONE_OOB, NAND_JFFS2_OOB,
- * NAND_YAFFS_OOB
- * 11-25-2002 tglx Added Manufacturer code FUJITSU, NATIONAL
- * Split manufacturer and device ID structures
- *
- * 02-08-2004 tglx added option field to nand structure for chip anomalities
- * 05-25-2004 tglx added bad block table support, ST-MICRO manufacturer id
- * update of nand_chip structure description
*/
#ifndef __LINUX_MTD_NAND_H
#define __LINUX_MTD_NAND_H
-#include <linux/mtd/compat.h>
-#include <linux/mtd/mtd.h>
-
-struct mtd_info;
-/* Scan and identify a NAND device */
-extern int nand_scan (struct mtd_info *mtd, int max_chips);
-/* Free resources held by the NAND device */
-extern void nand_release (struct mtd_info *mtd);
-
-/* Read raw data from the device without ECC */
-extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, size_t ooblen);
-
-
-/* The maximum number of NAND chips in an array */
-#define NAND_MAX_CHIPS 8
-
-/* This constant declares the max. oobsize / page, which
- * is supported now. If you add a chip with bigger oobsize/page
- * adjust this accordingly.
- */
-#define NAND_MAX_OOBSIZE 64
-
-/*
- * Constants for hardware specific CLE/ALE/NCE function
-*/
-/* Select the chip by setting nCE to low */
-#define NAND_CTL_SETNCE 1
-/* Deselect the chip by setting nCE to high */
-#define NAND_CTL_CLRNCE 2
-/* Select the command latch by setting CLE to high */
-#define NAND_CTL_SETCLE 3
-/* Deselect the command latch by setting CLE to low */
-#define NAND_CTL_CLRCLE 4
-/* Select the address latch by setting ALE to high */
-#define NAND_CTL_SETALE 5
-/* Deselect the address latch by setting ALE to low */
-#define NAND_CTL_CLRALE 6
-/* Set write protection by setting WP to high. Not used! */
-#define NAND_CTL_SETWP 7
-/* Clear write protection by setting WP to low. Not used! */
-#define NAND_CTL_CLRWP 8
-
+#ifdef CONFIG_NEW_NAND_CODE
+#include "nand_new.h"
+#else
/*
* Standard NAND flash commands
*/
#define NAND_CMD_READOOB 0x50
#define NAND_CMD_ERASE1 0x60
#define NAND_CMD_STATUS 0x70
-#define NAND_CMD_STATUS_MULTI 0x71
#define NAND_CMD_SEQIN 0x80
#define NAND_CMD_READID 0x90
#define NAND_CMD_ERASE2 0xd0
#define NAND_CMD_RESET 0xff
-/* Extended commands for large page devices */
-#define NAND_CMD_READSTART 0x30
-#define NAND_CMD_CACHEDPROG 0x15
-
-/* Status bits */
-#define NAND_STATUS_FAIL 0x01
-#define NAND_STATUS_FAIL_N1 0x02
-#define NAND_STATUS_TRUE_READY 0x20
-#define NAND_STATUS_READY 0x40
-#define NAND_STATUS_WP 0x80
-
-/*
- * Constants for ECC_MODES
- */
-
-/* No ECC. Usage is not recommended ! */
-#define NAND_ECC_NONE 0
-/* Software ECC 3 byte ECC per 256 Byte data */
-#define NAND_ECC_SOFT 1
-/* Hardware ECC 3 byte ECC per 256 Byte data */
-#define NAND_ECC_HW3_256 2
-/* Hardware ECC 3 byte ECC per 512 Byte data */
-#define NAND_ECC_HW3_512 3
-/* Hardware ECC 3 byte ECC per 512 Byte data */
-#define NAND_ECC_HW6_512 4
-/* Hardware ECC 8 byte ECC per 512 Byte data */
-#define NAND_ECC_HW8_512 6
-/* Hardware ECC 12 byte ECC per 2048 Byte data */
-#define NAND_ECC_HW12_2048 7
-
/*
- * Constants for Hardware ECC
-*/
-/* Reset Hardware ECC for read */
-#define NAND_ECC_READ 0
-/* Reset Hardware ECC for write */
-#define NAND_ECC_WRITE 1
-/* Enable Hardware ECC before syndrom is read back from flash */
-#define NAND_ECC_READSYN 2
-
-/* Option constants for bizarre disfunctionality and real
-* features
-*/
-/* Chip can not auto increment pages */
-#define NAND_NO_AUTOINCR 0x00000001
-/* Buswitdh is 16 bit */
-#define NAND_BUSWIDTH_16 0x00000002
-/* Device supports partial programming without padding */
-#define NAND_NO_PADDING 0x00000004
-/* Chip has cache program function */
-#define NAND_CACHEPRG 0x00000008
-/* Chip has copy back function */
-#define NAND_COPYBACK 0x00000010
-/* AND Chip which has 4 banks and a confusing page / block
- * assignment. See Renesas datasheet for further information */
-#define NAND_IS_AND 0x00000020
-/* Chip has a array of 4 pages which can be read without
- * additional ready /busy waits */
-#define NAND_4PAGE_ARRAY 0x00000040
-
-/* Options valid for Samsung large page devices */
-#define NAND_SAMSUNG_LP_OPTIONS \
- (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
-
-/* Macros to identify the above */
-#define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
-#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
-#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
-#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
-
-/* Mask to zero out the chip options, which come from the id table */
-#define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
-
-/* Non chip related options */
-/* Use a flash based bad block table. This option is passed to the
- * default bad block table function. */
-#define NAND_USE_FLASH_BBT 0x00010000
-/* The hw ecc generator provides a syndrome instead a ecc value on read
- * This can only work if we have the ecc bytes directly behind the
- * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */
-#define NAND_HWECC_SYNDROME 0x00020000
-
-
-/* Options set by nand scan */
-/* Nand scan has allocated oob_buf */
-#define NAND_OOBBUF_ALLOC 0x40000000
-/* Nand scan has allocated data_buf */
-#define NAND_DATABUF_ALLOC 0x80000000
-
-
-/*
- * nand_state_t - chip states
* Enumeration for NAND flash chip state
*/
typedef enum {
FL_READING,
FL_WRITING,
FL_ERASING,
- FL_SYNCING,
- FL_CACHEDPRG,
+ FL_SYNCING
} nand_state_t;
-/* Keep gcc happy */
-struct nand_chip;
-#if 0
-/**
- * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices
- * @lock: protection lock
- * @active: the mtd device which holds the controller currently
+/*
+ * NAND Private Flash Chip Data
+ *
+ * Structure overview:
+ *
+ * IO_ADDR - address to access the 8 I/O lines of the flash device
+ *
+ * hwcontrol - hardwarespecific function for accesing control-lines
+ *
+ * dev_ready - hardwarespecific function for accesing device ready/busy line
+ *
+ * chip_lock - spinlock used to protect access to this structure
+ *
+ * wq - wait queue to sleep on if a NAND operation is in progress
+ *
+ * state - give the current state of the NAND device
+ *
+ * page_shift - number of address bits in a page (column address bits)
+ *
+ * data_buf - data buffer passed to/from MTD user modules
+ *
+ * data_cache - data cache for redundant page access and shadow for
+ * ECC failure
+ *
+ * ecc_code_buf - used only for holding calculated or read ECCs for
+ * a page read or written when ECC is in use
+ *
+ * reserved - padding to make structure fall on word boundary if
+ * when ECC is in use
*/
-struct nand_hw_control {
- spinlock_t lock;
- struct nand_chip *active;
+struct Nand {
+ char floor, chip;
+ unsigned long curadr;
+ unsigned char curmode;
+ /* Also some erase/write/pipeline info when we get that far */
};
-#endif
-
-/**
- * struct nand_chip - NAND Private Flash Chip Data
- * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
- * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
- * @read_byte: [REPLACEABLE] read one byte from the chip
- * @write_byte: [REPLACEABLE] write one byte to the chip
- * @read_word: [REPLACEABLE] read one word from the chip
- * @write_word: [REPLACEABLE] write one word to the chip
- * @write_buf: [REPLACEABLE] write data from the buffer to the chip
- * @read_buf: [REPLACEABLE] read data from the chip into the buffer
- * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
- * @select_chip: [REPLACEABLE] select chip nr
- * @block_bad: [REPLACEABLE] check, if the block is bad
- * @block_markbad: [REPLACEABLE] mark the block bad
- * @hwcontrol: [BOARDSPECIFIC] hardwarespecific function for accesing control-lines
- * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
- * If set to NULL no access to ready/busy is available and the ready/busy information
- * is read from the chip status register
- * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
- * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
- * @calculate_ecc: [REPLACEABLE] function for ecc calculation or readback from ecc hardware
- * @correct_data: [REPLACEABLE] function for ecc correction, matching to ecc generator (sw/hw)
- * @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only
- * be provided if a hardware ECC is available
- * @erase_cmd: [INTERN] erase command write function, selectable due to AND support
- * @scan_bbt: [REPLACEABLE] function to scan bad block table
- * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines
- * @eccsize: [INTERN] databytes used per ecc-calculation
- * @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step
- * @eccsteps: [INTERN] number of ecc calculation steps per page
- * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
- * @chip_lock: [INTERN] spinlock used to protect access to this structure and the chip
- * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
- * @state: [INTERN] the current state of the NAND device
- * @page_shift: [INTERN] number of address bits in a page (column address bits)
- * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
- * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
- * @chip_shift: [INTERN] number of address bits in one chip
- * @data_buf: [INTERN] internal buffer for one page + oob
- * @oob_buf: [INTERN] oob buffer for one eraseblock
- * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized
- * @data_poi: [INTERN] pointer to a data buffer
- * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
- * special functionality. See the defines for further explanation
- * @badblockpos: [INTERN] position of the bad block marker in the oob area
- * @numchips: [INTERN] number of physical chips
- * @chipsize: [INTERN] the size of one chip for multichip arrays
- * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
- * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
- * @autooob: [REPLACEABLE] the default (auto)placement scheme
- * @bbt: [INTERN] bad block table pointer
- * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
- * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
- * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
- * @controller: [OPTIONAL] a pointer to a hardware controller structure which is shared among multiple independend devices
- * @priv: [OPTIONAL] pointer to private chip date
- */
struct nand_chip {
- void __iomem *IO_ADDR_R;
- void __iomem *IO_ADDR_W;
-
- u_char (*read_byte)(struct mtd_info *mtd);
- void (*write_byte)(struct mtd_info *mtd, u_char byte);
- u16 (*read_word)(struct mtd_info *mtd);
- void (*write_word)(struct mtd_info *mtd, u16 word);
-
- void (*write_buf)(struct mtd_info *mtd, const u_char *buf, int len);
- void (*read_buf)(struct mtd_info *mtd, u_char *buf, int len);
- int (*verify_buf)(struct mtd_info *mtd, const u_char *buf, int len);
- void (*select_chip)(struct mtd_info *mtd, int chip);
- int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
- int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
- void (*hwcontrol)(struct mtd_info *mtd, int cmd);
- int (*dev_ready)(struct mtd_info *mtd);
- void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
- int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state);
- int (*calculate_ecc)(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code);
- int (*correct_data)(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc);
- void (*enable_hwecc)(struct mtd_info *mtd, int mode);
- void (*erase_cmd)(struct mtd_info *mtd, int page);
- int (*scan_bbt)(struct mtd_info *mtd);
- int eccmode;
- int eccsize;
- int eccbytes;
- int eccsteps;
- int chip_delay;
-#if 0
- spinlock_t chip_lock;
- wait_queue_head_t wq;
- nand_state_t state;
-#endif
int page_shift;
- int phys_erase_shift;
- int bbt_erase_shift;
- int chip_shift;
u_char *data_buf;
- u_char *oob_buf;
- int oobdirty;
- u_char *data_poi;
- unsigned int options;
- int badblockpos;
- int numchips;
- unsigned long chipsize;
- int pagemask;
- int pagebuf;
- struct nand_oobinfo *autooob;
- uint8_t *bbt;
- struct nand_bbt_descr *bbt_td;
- struct nand_bbt_descr *bbt_md;
- struct nand_bbt_descr *badblock_pattern;
- struct nand_hw_control *controller;
- void *priv;
+ u_char *data_cache;
+ int cache_page;
+ u_char ecc_code_buf[6];
+ u_char reserved[2];
+ char ChipID; /* Type of DiskOnChip */
+ struct Nand *chips;
+ int chipshift;
+ char* chips_name;
+ unsigned long erasesize;
+ unsigned long mfr; /* Flash IDs - only one type of flash per device */
+ unsigned long id;
+ char* name;
+ int numchips;
+ char page256;
+ char pageadrlen;
+ unsigned long IO_ADDR; /* address to access the 8 I/O lines to the flash device */
+ unsigned long totlen;
+ uint oobblock; /* Size of OOB blocks (e.g. 512) */
+ uint oobsize; /* Amount of OOB data per block (e.g. 16) */
+ uint eccsize;
+ int bus16;
};
/*
*/
#define NAND_MFR_TOSHIBA 0x98
#define NAND_MFR_SAMSUNG 0xec
-#define NAND_MFR_FUJITSU 0x04
-#define NAND_MFR_NATIONAL 0x8f
-#define NAND_MFR_RENESAS 0x07
-#define NAND_MFR_STMICRO 0x20
-/**
- * struct nand_flash_dev - NAND Flash Device ID Structure
+/*
+ * NAND Flash Device ID Structure
+ *
+ * Structure overview:
+ *
+ * name - Complete name of device
+ *
+ * manufacture_id - manufacturer ID code of device.
+ *
+ * model_id - model ID code of device.
+ *
+ * chipshift - total number of address bits for the device which
+ * is used to calculate address offsets and the total
+ * number of bytes the device is capable of.
*
- * @name: Identify the device type
- * @id: device ID code
- * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
- * If the pagesize is 0, then the real pagesize
- * and the eraseize are determined from the
- * extended id bytes in the chip
- * @erasesize: Size of an erase block in the flash device.
- * @chipsize: Total chipsize in Mega Bytes
- * @options: Bitfield to store chip relevant options
+ * page256 - denotes if flash device has 256 byte pages or not.
+ *
+ * pageadrlen - number of bytes minus one needed to hold the
+ * complete address into the flash array. Keep in
+ * mind that when a read or write is done to a
+ * specific address, the address is input serially
+ * 8 bits at a time. This structure member is used
+ * by the read/write routines as a loop index for
+ * shifting the address out 8 bits at a time.
+ *
+ * erasesize - size of an erase block in the flash device.
*/
struct nand_flash_dev {
- char *name;
- int id;
- unsigned long pagesize;
- unsigned long chipsize;
- unsigned long erasesize;
- unsigned long options;
-};
-
-/**
- * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
- * @name: Manufacturer name
- * @id: manufacturer ID code of device.
-*/
-struct nand_manufacturers {
- int id;
char * name;
+ int manufacture_id;
+ int model_id;
+ int chipshift;
+ char page256;
+ char pageadrlen;
+ unsigned long erasesize;
+ int bus16;
};
-extern struct nand_flash_dev nand_flash_ids[];
-extern struct nand_manufacturers nand_manuf_ids[];
-
-/**
- * struct nand_bbt_descr - bad block table descriptor
- * @options: options for this descriptor
- * @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE
- * when bbt is searched, then we store the found bbts pages here.
- * Its an array and supports up to 8 chips now
- * @offs: offset of the pattern in the oob area of the page
- * @veroffs: offset of the bbt version counter in the oob are of the page
- * @version: version read from the bbt page during scan
- * @len: length of the pattern, if 0 no pattern check is performed
- * @maxblocks: maximum number of blocks to search for a bbt. This number of
- * blocks is reserved at the end of the device where the tables are
- * written.
- * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
- * bad) block in the stored bbt
- * @pattern: pattern to identify bad block table or factory marked good /
- * bad blocks, can be NULL, if len = 0
- *
- * Descriptor for the bad block table marker and the descriptor for the
- * pattern which identifies good and bad blocks. The assumption is made
- * that the pattern and the version count are always located in the oob area
- * of the first block.
- */
-struct nand_bbt_descr {
- int options;
- int pages[NAND_MAX_CHIPS];
- int offs;
- int veroffs;
- uint8_t version[NAND_MAX_CHIPS];
- int len;
- int maxblocks;
- int reserved_block_code;
- uint8_t *pattern;
-};
-
-/* Options for the bad block table descriptors */
-
-/* The number of bits used per block in the bbt on the device */
-#define NAND_BBT_NRBITS_MSK 0x0000000F
-#define NAND_BBT_1BIT 0x00000001
-#define NAND_BBT_2BIT 0x00000002
-#define NAND_BBT_4BIT 0x00000004
-#define NAND_BBT_8BIT 0x00000008
-/* The bad block table is in the last good block of the device */
-#define NAND_BBT_LASTBLOCK 0x00000010
-/* The bbt is at the given page, else we must scan for the bbt */
-#define NAND_BBT_ABSPAGE 0x00000020
-/* The bbt is at the given page, else we must scan for the bbt */
-#define NAND_BBT_SEARCH 0x00000040
-/* bbt is stored per chip on multichip devices */
-#define NAND_BBT_PERCHIP 0x00000080
-/* bbt has a version counter at offset veroffs */
-#define NAND_BBT_VERSION 0x00000100
-/* Create a bbt if none axists */
-#define NAND_BBT_CREATE 0x00000200
-/* Search good / bad pattern through all pages of a block */
-#define NAND_BBT_SCANALLPAGES 0x00000400
-/* Scan block empty during good / bad block scan */
-#define NAND_BBT_SCANEMPTY 0x00000800
-/* Write bbt if neccecary */
-#define NAND_BBT_WRITE 0x00001000
-/* Read and write back block contents when writing bbt */
-#define NAND_BBT_SAVECONTENT 0x00002000
-/* Search good / bad pattern on the first and the second page */
-#define NAND_BBT_SCAN2NDPAGE 0x00004000
-
-/* The maximum number of blocks to scan for a bbt */
-#define NAND_BBT_SCAN_MAXBLOCKS 4
-
-extern int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd);
-extern int nand_update_bbt (struct mtd_info *mtd, loff_t offs);
-extern int nand_default_bbt (struct mtd_info *mtd);
-extern int nand_isbad_bbt (struct mtd_info *mtd, loff_t offs, int allowbbt);
-extern int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbbt);
-
/*
* Constants for oob configuration
*/
-#define NAND_SMALL_BADBLOCK_POS 5
-#define NAND_LARGE_BADBLOCK_POS 0
-
+#define NAND_NOOB_ECCPOS0 0
+#define NAND_NOOB_ECCPOS1 1
+#define NAND_NOOB_ECCPOS2 2
+#define NAND_NOOB_ECCPOS3 3
+#define NAND_NOOB_ECCPOS4 6
+#define NAND_NOOB_ECCPOS5 7
+#define NAND_NOOB_BADBPOS -1
+#define NAND_NOOB_ECCVPOS -1
+
+#define NAND_JFFS2_OOB_ECCPOS0 0
+#define NAND_JFFS2_OOB_ECCPOS1 1
+#define NAND_JFFS2_OOB_ECCPOS2 2
+#define NAND_JFFS2_OOB_ECCPOS3 3
+#define NAND_JFFS2_OOB_ECCPOS4 6
+#define NAND_JFFS2_OOB_ECCPOS5 7
+#define NAND_JFFS2_OOB_BADBPOS 5
+#define NAND_JFFS2_OOB_ECCVPOS 4
+
+#define NAND_JFFS2_OOB8_FSDAPOS 6
+#define NAND_JFFS2_OOB16_FSDAPOS 8
+#define NAND_JFFS2_OOB8_FSDALEN 2
+#define NAND_JFFS2_OOB16_FSDALEN 8
+
+unsigned long nand_probe(unsigned long physadr);
+#endif /* !CONFIG_NEW_NAND_CODE */
#endif /* __LINUX_MTD_NAND_H */
--- /dev/null
+/*
+ * linux/include/linux/mtd/nand.h
+ *
+ * Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
+ * Steven J. Hill <sjhill@realitydiluted.com>
+ * Thomas Gleixner <tglx@linutronix.de>
+ *
+ * $Id: nand.h,v 1.68 2004/11/12 10:40:37 gleixner Exp $
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Info:
+ * Contains standard defines and IDs for NAND flash devices
+ *
+ * Changelog:
+ * 01-31-2000 DMW Created
+ * 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers
+ * so it can be used by other NAND flash device
+ * drivers. I also changed the copyright since none
+ * of the original contents of this file are specific
+ * to DoC devices. David can whack me with a baseball
+ * bat later if I did something naughty.
+ * 10-11-2000 SJH Added private NAND flash structure for driver
+ * 10-24-2000 SJH Added prototype for 'nand_scan' function
+ * 10-29-2001 TG changed nand_chip structure to support
+ * hardwarespecific function for accessing control lines
+ * 02-21-2002 TG added support for different read/write adress and
+ * ready/busy line access function
+ * 02-26-2002 TG added chip_delay to nand_chip structure to optimize
+ * command delay times for different chips
+ * 04-28-2002 TG OOB config defines moved from nand.c to avoid duplicate
+ * defines in jffs2/wbuf.c
+ * 08-07-2002 TG forced bad block location to byte 5 of OOB, even if
+ * CONFIG_MTD_NAND_ECC_JFFS2 is not set
+ * 08-10-2002 TG extensions to nand_chip structure to support HW-ECC
+ *
+ * 08-29-2002 tglx nand_chip structure: data_poi for selecting
+ * internal / fs-driver buffer
+ * support for 6byte/512byte hardware ECC
+ * read_ecc, write_ecc extended for different oob-layout
+ * oob layout selections: NAND_NONE_OOB, NAND_JFFS2_OOB,
+ * NAND_YAFFS_OOB
+ * 11-25-2002 tglx Added Manufacturer code FUJITSU, NATIONAL
+ * Split manufacturer and device ID structures
+ *
+ * 02-08-2004 tglx added option field to nand structure for chip anomalities
+ * 05-25-2004 tglx added bad block table support, ST-MICRO manufacturer id
+ * update of nand_chip structure description
+ */
+#ifndef __LINUX_MTD_NAND_NEW_H
+#define __LINUX_MTD_NAND_NEW_H
+
+#include <linux/mtd/compat.h>
+#include <linux/mtd/mtd.h>
+
+struct mtd_info;
+/* Scan and identify a NAND device */
+extern int nand_scan (struct mtd_info *mtd, int max_chips);
+/* Free resources held by the NAND device */
+extern void nand_release (struct mtd_info *mtd);
+
+/* Read raw data from the device without ECC */
+extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, size_t ooblen);
+
+
+
+/* This constant declares the max. oobsize / page, which
+ * is supported now. If you add a chip with bigger oobsize/page
+ * adjust this accordingly.
+ */
+#define NAND_MAX_OOBSIZE 64
+
+/*
+ * Constants for hardware specific CLE/ALE/NCE function
+*/
+/* Select the chip by setting nCE to low */
+#define NAND_CTL_SETNCE 1
+/* Deselect the chip by setting nCE to high */
+#define NAND_CTL_CLRNCE 2
+/* Select the command latch by setting CLE to high */
+#define NAND_CTL_SETCLE 3
+/* Deselect the command latch by setting CLE to low */
+#define NAND_CTL_CLRCLE 4
+/* Select the address latch by setting ALE to high */
+#define NAND_CTL_SETALE 5
+/* Deselect the address latch by setting ALE to low */
+#define NAND_CTL_CLRALE 6
+/* Set write protection by setting WP to high. Not used! */
+#define NAND_CTL_SETWP 7
+/* Clear write protection by setting WP to low. Not used! */
+#define NAND_CTL_CLRWP 8
+
+/*
+ * Standard NAND flash commands
+ */
+#define NAND_CMD_READ0 0
+#define NAND_CMD_READ1 1
+#define NAND_CMD_PAGEPROG 0x10
+#define NAND_CMD_READOOB 0x50
+#define NAND_CMD_ERASE1 0x60
+#define NAND_CMD_STATUS 0x70
+#define NAND_CMD_STATUS_MULTI 0x71
+#define NAND_CMD_SEQIN 0x80
+#define NAND_CMD_READID 0x90
+#define NAND_CMD_ERASE2 0xd0
+#define NAND_CMD_RESET 0xff
+
+/* Extended commands for large page devices */
+#define NAND_CMD_READSTART 0x30
+#define NAND_CMD_CACHEDPROG 0x15
+
+/* Status bits */
+#define NAND_STATUS_FAIL 0x01
+#define NAND_STATUS_FAIL_N1 0x02
+#define NAND_STATUS_TRUE_READY 0x20
+#define NAND_STATUS_READY 0x40
+#define NAND_STATUS_WP 0x80
+
+/*
+ * Constants for ECC_MODES
+ */
+
+/* No ECC. Usage is not recommended ! */
+#define NAND_ECC_NONE 0
+/* Software ECC 3 byte ECC per 256 Byte data */
+#define NAND_ECC_SOFT 1
+/* Hardware ECC 3 byte ECC per 256 Byte data */
+#define NAND_ECC_HW3_256 2
+/* Hardware ECC 3 byte ECC per 512 Byte data */
+#define NAND_ECC_HW3_512 3
+/* Hardware ECC 3 byte ECC per 512 Byte data */
+#define NAND_ECC_HW6_512 4
+/* Hardware ECC 8 byte ECC per 512 Byte data */
+#define NAND_ECC_HW8_512 6
+/* Hardware ECC 12 byte ECC per 2048 Byte data */
+#define NAND_ECC_HW12_2048 7
+
+/*
+ * Constants for Hardware ECC
+*/
+/* Reset Hardware ECC for read */
+#define NAND_ECC_READ 0
+/* Reset Hardware ECC for write */
+#define NAND_ECC_WRITE 1
+/* Enable Hardware ECC before syndrom is read back from flash */
+#define NAND_ECC_READSYN 2
+
+/* Option constants for bizarre disfunctionality and real
+* features
+*/
+/* Chip can not auto increment pages */
+#define NAND_NO_AUTOINCR 0x00000001
+/* Buswitdh is 16 bit */
+#define NAND_BUSWIDTH_16 0x00000002
+/* Device supports partial programming without padding */
+#define NAND_NO_PADDING 0x00000004
+/* Chip has cache program function */
+#define NAND_CACHEPRG 0x00000008
+/* Chip has copy back function */
+#define NAND_COPYBACK 0x00000010
+/* AND Chip which has 4 banks and a confusing page / block
+ * assignment. See Renesas datasheet for further information */
+#define NAND_IS_AND 0x00000020
+/* Chip has a array of 4 pages which can be read without
+ * additional ready /busy waits */
+#define NAND_4PAGE_ARRAY 0x00000040
+
+/* Options valid for Samsung large page devices */
+#define NAND_SAMSUNG_LP_OPTIONS \
+ (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
+
+/* Macros to identify the above */
+#define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
+#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
+#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
+#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
+
+/* Mask to zero out the chip options, which come from the id table */
+#define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
+
+/* Non chip related options */
+/* Use a flash based bad block table. This option is passed to the
+ * default bad block table function. */
+#define NAND_USE_FLASH_BBT 0x00010000
+/* The hw ecc generator provides a syndrome instead a ecc value on read
+ * This can only work if we have the ecc bytes directly behind the
+ * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */
+#define NAND_HWECC_SYNDROME 0x00020000
+
+
+/* Options set by nand scan */
+/* Nand scan has allocated oob_buf */
+#define NAND_OOBBUF_ALLOC 0x40000000
+/* Nand scan has allocated data_buf */
+#define NAND_DATABUF_ALLOC 0x80000000
+
+
+/*
+ * nand_state_t - chip states
+ * Enumeration for NAND flash chip state
+ */
+typedef enum {
+ FL_READY,
+ FL_READING,
+ FL_WRITING,
+ FL_ERASING,
+ FL_SYNCING,
+ FL_CACHEDPRG,
+} nand_state_t;
+
+/* Keep gcc happy */
+struct nand_chip;
+
+#if 0
+/**
+ * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices
+ * @lock: protection lock
+ * @active: the mtd device which holds the controller currently
+ */
+struct nand_hw_control {
+ spinlock_t lock;
+ struct nand_chip *active;
+};
+#endif
+
+/**
+ * struct nand_chip - NAND Private Flash Chip Data
+ * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
+ * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
+ * @read_byte: [REPLACEABLE] read one byte from the chip
+ * @write_byte: [REPLACEABLE] write one byte to the chip
+ * @read_word: [REPLACEABLE] read one word from the chip
+ * @write_word: [REPLACEABLE] write one word to the chip
+ * @write_buf: [REPLACEABLE] write data from the buffer to the chip
+ * @read_buf: [REPLACEABLE] read data from the chip into the buffer
+ * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
+ * @select_chip: [REPLACEABLE] select chip nr
+ * @block_bad: [REPLACEABLE] check, if the block is bad
+ * @block_markbad: [REPLACEABLE] mark the block bad
+ * @hwcontrol: [BOARDSPECIFIC] hardwarespecific function for accesing control-lines
+ * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
+ * If set to NULL no access to ready/busy is available and the ready/busy information
+ * is read from the chip status register
+ * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
+ * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
+ * @calculate_ecc: [REPLACEABLE] function for ecc calculation or readback from ecc hardware
+ * @correct_data: [REPLACEABLE] function for ecc correction, matching to ecc generator (sw/hw)
+ * @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only
+ * be provided if a hardware ECC is available
+ * @erase_cmd: [INTERN] erase command write function, selectable due to AND support
+ * @scan_bbt: [REPLACEABLE] function to scan bad block table
+ * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines
+ * @eccsize: [INTERN] databytes used per ecc-calculation
+ * @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step
+ * @eccsteps: [INTERN] number of ecc calculation steps per page
+ * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
+ * @chip_lock: [INTERN] spinlock used to protect access to this structure and the chip
+ * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
+ * @state: [INTERN] the current state of the NAND device
+ * @page_shift: [INTERN] number of address bits in a page (column address bits)
+ * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
+ * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
+ * @chip_shift: [INTERN] number of address bits in one chip
+ * @data_buf: [INTERN] internal buffer for one page + oob
+ * @oob_buf: [INTERN] oob buffer for one eraseblock
+ * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized
+ * @data_poi: [INTERN] pointer to a data buffer
+ * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
+ * special functionality. See the defines for further explanation
+ * @badblockpos: [INTERN] position of the bad block marker in the oob area
+ * @numchips: [INTERN] number of physical chips
+ * @chipsize: [INTERN] the size of one chip for multichip arrays
+ * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
+ * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
+ * @autooob: [REPLACEABLE] the default (auto)placement scheme
+ * @bbt: [INTERN] bad block table pointer
+ * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
+ * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
+ * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
+ * @controller: [OPTIONAL] a pointer to a hardware controller structure which is shared among multiple independend devices
+ * @priv: [OPTIONAL] pointer to private chip date
+ */
+
+struct nand_chip {
+ void __iomem *IO_ADDR_R;
+ void __iomem *IO_ADDR_W;
+
+ u_char (*read_byte)(struct mtd_info *mtd);
+ void (*write_byte)(struct mtd_info *mtd, u_char byte);
+ u16 (*read_word)(struct mtd_info *mtd);
+ void (*write_word)(struct mtd_info *mtd, u16 word);
+
+ void (*write_buf)(struct mtd_info *mtd, const u_char *buf, int len);
+ void (*read_buf)(struct mtd_info *mtd, u_char *buf, int len);
+ int (*verify_buf)(struct mtd_info *mtd, const u_char *buf, int len);
+ void (*select_chip)(struct mtd_info *mtd, int chip);
+ int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
+ int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
+ void (*hwcontrol)(struct mtd_info *mtd, int cmd);
+ int (*dev_ready)(struct mtd_info *mtd);
+ void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
+ int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state);
+ int (*calculate_ecc)(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code);
+ int (*correct_data)(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc);
+ void (*enable_hwecc)(struct mtd_info *mtd, int mode);
+ void (*erase_cmd)(struct mtd_info *mtd, int page);
+ int (*scan_bbt)(struct mtd_info *mtd);
+ int eccmode;
+ int eccsize;
+ int eccbytes;
+ int eccsteps;
+ int chip_delay;
+#if 0
+ spinlock_t chip_lock;
+ wait_queue_head_t wq;
+ nand_state_t state;
+#endif
+ int page_shift;
+ int phys_erase_shift;
+ int bbt_erase_shift;
+ int chip_shift;
+ u_char *data_buf;
+ u_char *oob_buf;
+ int oobdirty;
+ u_char *data_poi;
+ unsigned int options;
+ int badblockpos;
+ int numchips;
+ unsigned long chipsize;
+ int pagemask;
+ int pagebuf;
+ struct nand_oobinfo *autooob;
+ uint8_t *bbt;
+ struct nand_bbt_descr *bbt_td;
+ struct nand_bbt_descr *bbt_md;
+ struct nand_bbt_descr *badblock_pattern;
+ struct nand_hw_control *controller;
+ void *priv;
+};
+
+/*
+ * NAND Flash Manufacturer ID Codes
+ */
+#define NAND_MFR_TOSHIBA 0x98
+#define NAND_MFR_SAMSUNG 0xec
+#define NAND_MFR_FUJITSU 0x04
+#define NAND_MFR_NATIONAL 0x8f
+#define NAND_MFR_RENESAS 0x07
+#define NAND_MFR_STMICRO 0x20
+
+/**
+ * struct nand_flash_dev - NAND Flash Device ID Structure
+ *
+ * @name: Identify the device type
+ * @id: device ID code
+ * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
+ * If the pagesize is 0, then the real pagesize
+ * and the eraseize are determined from the
+ * extended id bytes in the chip
+ * @erasesize: Size of an erase block in the flash device.
+ * @chipsize: Total chipsize in Mega Bytes
+ * @options: Bitfield to store chip relevant options
+ */
+struct nand_flash_dev {
+ char *name;
+ int id;
+ unsigned long pagesize;
+ unsigned long chipsize;
+ unsigned long erasesize;
+ unsigned long options;
+};
+
+/**
+ * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
+ * @name: Manufacturer name
+ * @id: manufacturer ID code of device.
+*/
+struct nand_manufacturers {
+ int id;
+ char * name;
+};
+
+extern struct nand_flash_dev nand_flash_ids[];
+extern struct nand_manufacturers nand_manuf_ids[];
+
+/**
+ * struct nand_bbt_descr - bad block table descriptor
+ * @options: options for this descriptor
+ * @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE
+ * when bbt is searched, then we store the found bbts pages here.
+ * Its an array and supports up to 8 chips now
+ * @offs: offset of the pattern in the oob area of the page
+ * @veroffs: offset of the bbt version counter in the oob are of the page
+ * @version: version read from the bbt page during scan
+ * @len: length of the pattern, if 0 no pattern check is performed
+ * @maxblocks: maximum number of blocks to search for a bbt. This number of
+ * blocks is reserved at the end of the device where the tables are
+ * written.
+ * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
+ * bad) block in the stored bbt
+ * @pattern: pattern to identify bad block table or factory marked good /
+ * bad blocks, can be NULL, if len = 0
+ *
+ * Descriptor for the bad block table marker and the descriptor for the
+ * pattern which identifies good and bad blocks. The assumption is made
+ * that the pattern and the version count are always located in the oob area
+ * of the first block.
+ */
+struct nand_bbt_descr {
+ int options;
+ int pages[NAND_MAX_CHIPS];
+ int offs;
+ int veroffs;
+ uint8_t version[NAND_MAX_CHIPS];
+ int len;
+ int maxblocks;
+ int reserved_block_code;
+ uint8_t *pattern;
+};
+
+/* Options for the bad block table descriptors */
+
+/* The number of bits used per block in the bbt on the device */
+#define NAND_BBT_NRBITS_MSK 0x0000000F
+#define NAND_BBT_1BIT 0x00000001
+#define NAND_BBT_2BIT 0x00000002
+#define NAND_BBT_4BIT 0x00000004
+#define NAND_BBT_8BIT 0x00000008
+/* The bad block table is in the last good block of the device */
+#define NAND_BBT_LASTBLOCK 0x00000010
+/* The bbt is at the given page, else we must scan for the bbt */
+#define NAND_BBT_ABSPAGE 0x00000020
+/* The bbt is at the given page, else we must scan for the bbt */
+#define NAND_BBT_SEARCH 0x00000040
+/* bbt is stored per chip on multichip devices */
+#define NAND_BBT_PERCHIP 0x00000080
+/* bbt has a version counter at offset veroffs */
+#define NAND_BBT_VERSION 0x00000100
+/* Create a bbt if none axists */
+#define NAND_BBT_CREATE 0x00000200
+/* Search good / bad pattern through all pages of a block */
+#define NAND_BBT_SCANALLPAGES 0x00000400
+/* Scan block empty during good / bad block scan */
+#define NAND_BBT_SCANEMPTY 0x00000800
+/* Write bbt if neccecary */
+#define NAND_BBT_WRITE 0x00001000
+/* Read and write back block contents when writing bbt */
+#define NAND_BBT_SAVECONTENT 0x00002000
+/* Search good / bad pattern on the first and the second page */
+#define NAND_BBT_SCAN2NDPAGE 0x00004000
+
+/* The maximum number of blocks to scan for a bbt */
+#define NAND_BBT_SCAN_MAXBLOCKS 4
+
+extern int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd);
+extern int nand_update_bbt (struct mtd_info *mtd, loff_t offs);
+extern int nand_default_bbt (struct mtd_info *mtd);
+extern int nand_isbad_bbt (struct mtd_info *mtd, loff_t offs, int allowbbt);
+extern int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbbt);
+
+/*
+* Constants for oob configuration
+*/
+#define NAND_SMALL_BADBLOCK_POS 5
+#define NAND_LARGE_BADBLOCK_POS 0
+
+#endif /* __LINUX_MTD_NAND_NEW_H */
#endif /* __PPC__ */
-#if defined (__ARM__) || defined (__I386__)
+#if defined (__ARM__) || defined (__I386__) || defined (__M68K__)
struct stat {
unsigned short st_dev;
#ifndef _miiphy_h_
#define _miiphy_h_
+#include <net.h>
-int miiphy_read(unsigned char addr, unsigned char reg, unsigned short * value);
-int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value);
-int miiphy_info(unsigned char addr, unsigned int *oui, unsigned char *model,
- unsigned char *rev);
-int miiphy_reset(unsigned char addr);
-int miiphy_speed(unsigned char addr);
-int miiphy_duplex(unsigned char addr);
+int miiphy_read(char *devname, unsigned char addr, unsigned char reg,
+ unsigned short *value);
+int miiphy_write(char *devname, unsigned char addr, unsigned char reg,
+ unsigned short value);
+int miiphy_info(char *devname, unsigned char addr, unsigned int *oui,
+ unsigned char *model, unsigned char *rev);
+int miiphy_reset(char *devname, unsigned char addr);
+int miiphy_speed(char *devname, unsigned char addr);
+int miiphy_duplex(char *devname, unsigned char addr);
#ifdef CFG_FAULT_ECHO_LINK_DOWN
-int miiphy_link(unsigned char addr);
+int miiphy_link(char *devname, unsigned char addr);
#endif
+void miiphy_init(void);
+
+void miiphy_register(char *devname,
+ int (* read)(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value),
+ int (* write)(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value));
+
+int miiphy_set_current_dev(char *devname);
+char *miiphy_get_current_dev(void);
+
+void miiphy_listdev(void);
+
+#define BB_MII_DEVNAME "bbmii"
+
+int bb_miiphy_read (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value);
+int bb_miiphy_write (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value);
/* phy seed setup */
#define AUTO 99
#define MPC5XXX_GPIO (CFG_MBAR + 0x0b00)
#define MPC5XXX_WU_GPIO (CFG_MBAR + 0x0c00)
#define MPC5XXX_PCI (CFG_MBAR + 0x0d00)
+#define MPC5XXX_SPI (CFG_MBAR + 0x0f00)
#define MPC5XXX_USB (CFG_MBAR + 0x1000)
#define MPC5XXX_SDMA (CFG_MBAR + 0x1200)
#define MPC5XXX_XLBARB (CFG_MBAR + 0x1f00)
volatile u8 ctur; /* PSC + 0x18 */
volatile u8 reserved5[3];
volatile u8 ctlr; /* PSC + 0x1c */
- volatile u8 reserved6[19];
+ volatile u8 reserved6[3];
+ volatile u16 ccr; /* PSC + 0x20 */
+ volatile u8 reserved7[14];
volatile u8 ivr; /* PSC + 0x30 */
- volatile u8 reserved7[3];
- volatile u8 ip; /* PSC + 0x34 */
volatile u8 reserved8[3];
- volatile u8 op1; /* PSC + 0x38 */
+ volatile u8 ip; /* PSC + 0x34 */
volatile u8 reserved9[3];
- volatile u8 op0; /* PSC + 0x3c */
+ volatile u8 op1; /* PSC + 0x38 */
volatile u8 reserved10[3];
- volatile u8 sicr; /* PSC + 0x40 */
+ volatile u8 op0; /* PSC + 0x3c */
volatile u8 reserved11[3];
+ volatile u32 sicr; /* PSC + 0x40 */
volatile u8 ircr1; /* PSC + 0x44 */
volatile u8 reserved12[3];
volatile u8 ircr2; /* PSC + 0x44 */
volatile u32 mdr; /* I2Cn + 0x10 */
};
+struct mpc5xxx_spi {
+ volatile u8 cr1; /* SPI + 0x0F00 */
+ volatile u8 cr2; /* SPI + 0x0F01 */
+ volatile u8 reserved1[2];
+ volatile u8 brr; /* SPI + 0x0F04 */
+ volatile u8 sr; /* SPI + 0x0F05 */
+ volatile u8 reserved2[3];
+ volatile u8 dr; /* SPI + 0x0F09 */
+ volatile u8 reserved3[3];
+ volatile u8 pdr; /* SPI + 0x0F0D */
+ volatile u8 reserved4[2];
+ volatile u8 ddr; /* SPI + 0x0F10 */
+};
+
+
+struct mpc5xxx_gpt {
+ volatile u32 emsr; /* GPT + Timer# * 0x10 + 0x00 */
+ volatile u32 cir; /* GPT + Timer# * 0x10 + 0x04 */
+ volatile u32 pwmcr; /* GPT + Timer# * 0x10 + 0x08 */
+ volatile u32 sr; /* GPT + Timer# * 0x10 + 0x0c */
+};
+
+struct mpc5xxx_gpt_0_7 {
+ struct mpc5xxx_gpt gpt0;
+ struct mpc5xxx_gpt gpt1;
+ struct mpc5xxx_gpt gpt2;
+ struct mpc5xxx_gpt gpt3;
+ struct mpc5xxx_gpt gpt4;
+ struct mpc5xxx_gpt gpt5;
+ struct mpc5xxx_gpt gpt6;
+ struct mpc5xxx_gpt gpt7;
+};
+
+struct mscan_buffer {
+ volatile u8 idr[0x8]; /* 0x00 */
+ volatile u8 dsr[0x10]; /* 0x08 */
+ volatile u8 dlr; /* 0x18 */
+ volatile u8 tbpr; /* 0x19 */ /* This register is not applicable for receive buffers */
+ volatile u16 rsrv1; /* 0x1A */
+ volatile u8 tsrh; /* 0x1C */
+ volatile u8 tsrl; /* 0x1D */
+ volatile u16 rsrv2; /* 0x1E */
+};
+
+struct mpc5xxx_mscan {
+ volatile u8 canctl0; /* MSCAN + 0x00 */
+ volatile u8 canctl1; /* MSCAN + 0x01 */
+ volatile u16 rsrv1; /* MSCAN + 0x02 */
+ volatile u8 canbtr0; /* MSCAN + 0x04 */
+ volatile u8 canbtr1; /* MSCAN + 0x05 */
+ volatile u16 rsrv2; /* MSCAN + 0x06 */
+ volatile u8 canrflg; /* MSCAN + 0x08 */
+ volatile u8 canrier; /* MSCAN + 0x09 */
+ volatile u16 rsrv3; /* MSCAN + 0x0A */
+ volatile u8 cantflg; /* MSCAN + 0x0C */
+ volatile u8 cantier; /* MSCAN + 0x0D */
+ volatile u16 rsrv4; /* MSCAN + 0x0E */
+ volatile u8 cantarq; /* MSCAN + 0x10 */
+ volatile u8 cantaak; /* MSCAN + 0x11 */
+ volatile u16 rsrv5; /* MSCAN + 0x12 */
+ volatile u8 cantbsel; /* MSCAN + 0x14 */
+ volatile u8 canidac; /* MSCAN + 0x15 */
+ volatile u16 rsrv6[3]; /* MSCAN + 0x16 */
+ volatile u8 canrxerr; /* MSCAN + 0x1C */
+ volatile u8 cantxerr; /* MSCAN + 0x1D */
+ volatile u16 rsrv7; /* MSCAN + 0x1E */
+ volatile u8 canidar0; /* MSCAN + 0x20 */
+ volatile u8 canidar1; /* MSCAN + 0x21 */
+ volatile u16 rsrv8; /* MSCAN + 0x22 */
+ volatile u8 canidar2; /* MSCAN + 0x24 */
+ volatile u8 canidar3; /* MSCAN + 0x25 */
+ volatile u16 rsrv9; /* MSCAN + 0x26 */
+ volatile u8 canidmr0; /* MSCAN + 0x28 */
+ volatile u8 canidmr1; /* MSCAN + 0x29 */
+ volatile u16 rsrv10; /* MSCAN + 0x2A */
+ volatile u8 canidmr2; /* MSCAN + 0x2C */
+ volatile u8 canidmr3; /* MSCAN + 0x2D */
+ volatile u16 rsrv11; /* MSCAN + 0x2E */
+ volatile u8 canidar4; /* MSCAN + 0x30 */
+ volatile u8 canidar5; /* MSCAN + 0x31 */
+ volatile u16 rsrv12; /* MSCAN + 0x32 */
+ volatile u8 canidar6; /* MSCAN + 0x34 */
+ volatile u8 canidar7; /* MSCAN + 0x35 */
+ volatile u16 rsrv13; /* MSCAN + 0x36 */
+ volatile u8 canidmr4; /* MSCAN + 0x38 */
+ volatile u8 canidmr5; /* MSCAN + 0x39 */
+ volatile u16 rsrv14; /* MSCAN + 0x3A */
+ volatile u8 canidmr6; /* MSCAN + 0x3C */
+ volatile u8 canidmr7; /* MSCAN + 0x3D */
+ volatile u16 rsrv15; /* MSCAN + 0x3E */
+
+ struct mscan_buffer canrxfg; /* MSCAN + 0x40 */ /* Foreground receive buffer */
+ struct mscan_buffer cantxfg; /* MSCAN + 0x60 */ /* Foreground transmit buffer */
+ };
+
/* function prototypes */
void loadtask(int basetask, int tasks);
#define BR6 0x5030
#define BR7 0x5038
-#define BR_BA 0xFFFF8000
-#define BR_BA_SHIFT 15
-#define BR_PS 0x00001800
-#define BR_PS_SHIFT 11
-#define BR_DECC 0x00000600
-#define BR_DECC_SHIFT 9
-#define BR_WP 0x00000100
-#define BR_WP_SHIFT 8
-#define BR_MSEL 0x000000E0
-#define BR_MSEL_SHIFT 5
-#define BR_V 0x00000001
-#define BR_V_SHIFT 0
-#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
+#define BR_BA 0xFFFF8000
+#define BR_BA_SHIFT 15
+#define BR_PS 0x00001800
+#define BR_PS_SHIFT 11
+#define BR_PS_8 0x00000800 /* Port Size 8 bit */
+#define BR_PS_16 0x00001000 /* Port Size 16 bit */
+#define BR_PS_32 0x00001800 /* Port Size 32 bit */
+#define BR_DECC 0x00000600
+#define BR_DECC_SHIFT 9
+#define BR_WP 0x00000100
+#define BR_WP_SHIFT 8
+#define BR_MSEL 0x000000E0
+#define BR_MSEL_SHIFT 5
+#define BR_MS_GPCM 0x00000000 /* GPCM */
+#define BR_MS_SDRAM 0x00000060 /* SDRAM */
+#define BR_MS_UPMA 0x00000080 /* UPMA */
+#define BR_MS_UPMB 0x000000A0 /* UPMB */
+#define BR_MS_UPMC 0x000000C0 /* UPMC */
+#define BR_V 0x00000001
+#define BR_V_SHIFT 0
+#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
#define OR0 0x5004
#define OR1 0x500C
#define OR6 0x5034
#define OR7 0x503C
-#define OR_GPCM_AM 0xFFFF8000
-#define OR_GPCM_AM_SHIFT 15
-#define OR_GPCM_BCTLD 0x00001000
-#define OR_GPCM_BCTLD_SHIFT 12
-#define OR_GPCM_CSNT 0x00000800
-#define OR_GPCM_CSNT_SHIFT 11
-#define OR_GPCM_ACS 0x00000600
-#define OR_GPCM_ACS_SHIFT 9
-#define OR_GPCM_XACS 0x00000100
-#define OR_GPCM_XACS_SHIFT 8
-#define OR_GPCM_SCY 0x000000F0
-#define OR_GPCM_SCY_SHIFT 4
-#define OR_GPCM_SETA 0x00000008
-#define OR_GPCM_SETA_SHIFT 3
-#define OR_GPCM_TRLX 0x00000004
-#define OR_GPCM_TRLX_SHIFT 2
-#define OR_GPCM_EHTR 0x00000002
-#define OR_GPCM_EHTR_SHIFT 1
-#define OR_GPCM_EAD 0x00000001
-#define OR_GPCM_EAD_SHIFT 0
+#define OR_GPCM_AM 0xFFFF8000
+#define OR_GPCM_AM_SHIFT 15
+#define OR_GPCM_BCTLD 0x00001000
+#define OR_GPCM_BCTLD_SHIFT 12
+#define OR_GPCM_CSNT 0x00000800
+#define OR_GPCM_CSNT_SHIFT 11
+#define OR_GPCM_ACS 0x00000600
+#define OR_GPCM_ACS_SHIFT 9
+#define OR_GPCM_ACS_0b10 0x00000400
+#define OR_GPCM_ACS_0b11 0x00000600
+#define OR_GPCM_XACS 0x00000100
+#define OR_GPCM_XACS_SHIFT 8
+#define OR_GPCM_SCY 0x000000F0
+#define OR_GPCM_SCY_SHIFT 4
+#define OR_GPCM_SCY_1 0x00000010
+#define OR_GPCM_SCY_2 0x00000020
+#define OR_GPCM_SCY_3 0x00000030
+#define OR_GPCM_SCY_4 0x00000040
+#define OR_GPCM_SCY_5 0x00000050
+#define OR_GPCM_SCY_6 0x00000060
+#define OR_GPCM_SCY_7 0x00000070
+#define OR_GPCM_SCY_8 0x00000080
+#define OR_GPCM_SCY_9 0x00000090
+#define OR_GPCM_SCY_10 0x000000a0
+#define OR_GPCM_SCY_11 0x000000b0
+#define OR_GPCM_SCY_12 0x000000c0
+#define OR_GPCM_SCY_13 0x000000d0
+#define OR_GPCM_SCY_14 0x000000e0
+#define OR_GPCM_SCY_15 0x000000f0
+#define OR_GPCM_SETA 0x00000008
+#define OR_GPCM_SETA_SHIFT 3
+#define OR_GPCM_TRLX 0x00000004
+#define OR_GPCM_TRLX_SHIFT 2
+#define OR_GPCM_EHTR 0x00000002
+#define OR_GPCM_EHTR_SHIFT 1
+#define OR_GPCM_EAD 0x00000001
+#define OR_GPCM_EAD_SHIFT 0
#define OR_UPM_AM 0xFFFF8000
#define OR_UPM_AM_SHIFT 15
static inline int nand_read(nand_info_t *info, ulong ofs, ulong *len, u_char *buf)
{
- return info->read(info, ofs, *len, len, buf);
+ return info->read(info, ofs, *len, (size_t *)len, buf);
}
static inline int nand_write(nand_info_t *info, ulong ofs, ulong *len, u_char *buf)
{
- return info->write(info, ofs, *len, len, buf);
+ return info->write(info, ofs, *len, (size_t *)len, buf);
}
static inline int nand_block_isbad(nand_info_t *info, ulong ofs)
extern void eth_set_current(void); /* set nterface to ethcur var. */
#endif
extern struct eth_device *eth_get_dev(void); /* get the current device MAC */
+extern struct eth_device *eth_get_dev_by_name(char *devname); /* get device */
extern int eth_get_dev_index (void); /* get the device index */
extern void eth_set_enetaddr(int num, char* a); /* Set new MAC address */
extern ushort getenv_VLAN(char *);
/* copy a filename (allow for "..." notation, limit length) */
-extern void copy_filename (uchar *dst, uchar *src, int size);
+extern void copy_filename (char *dst, char *src, int size);
/**********************************************************************/
--- /dev/null
+/***********************************************************************
+ *
+ * Copyright 2003 by FS Forth-Systeme GmbH.
+ * All rights reserved.
+ *
+ * $Id$
+ * @Author: Markus Pietrek
+ * @Descr: Defines the NS7520 ethernet registers.
+ * Stick with the old ETH prefix names instead going to the
+ * new EFE names in the manual.
+ * NS7520_ETH_* refer to NS7520 Hardware
+ * Reference/January 2003 [1]
+ * PHY_LXT971_* refer to Intel LXT971 Datasheet
+ * #249414 Rev. 02 [2]
+ * Partly derived from netarm_eth_module.h
+ *
+ * Modified by Arthur Shipkowski <art@videon-central.com> from the
+ * Linux version to be properly formatted for U-Boot (i.e. no C++ comments)
+ *
+ ***********************************************************************/
+
+#ifndef FS_NS7520_ETH_H
+#define FS_NS7520_ETH_H
+
+#ifdef CONFIG_DRIVER_NS7520_ETHERNET
+
+#include "lxt971a.h"
+
+/* The port addresses */
+
+#define NS7520_ETH_MODULE_BASE (0xFF800000)
+
+#define get_eth_reg_addr(c) \
+ ((volatile unsigned int*) ( NS7520_ETH_MODULE_BASE+(unsigned int) (c)))
+#define NS7520_ETH_EGCR (0x0000) /* Ethernet Gen Control */
+#define NS7520_ETH_EGSR (0x0004) /* Ethernet Gen Status */
+#define NS7520_ETH_FIFO (0x0008) /* FIFO Data */
+#define NS7520_ETH_FIFOL (0x000C) /* FIFO Data Last */
+#define NS7520_ETH_ETSR (0x0010) /* Ethernet Transmit Status */
+#define NS7520_ETH_ERSR (0x0014) /* Ethernet Receive Status */
+#define NS7520_ETH_MAC1 (0x0400) /* MAC Config 1 */
+#define NS7520_ETH_MAC2 (0x0404) /* MAC Config 2 */
+#define NS7520_ETH_IPGT (0x0408) /* Back2Back InterPacket Gap */
+#define NS7520_ETH_IPGR (0x040C) /* non back2back InterPacket Gap */
+#define NS7520_ETH_CLRT (0x0410) /* Collision Window/Retry */
+#define NS7520_ETH_MAXF (0x0414) /* Maximum Frame Register */
+#define NS7520_ETH_SUPP (0x0418) /* PHY Support */
+#define NS7520_ETH_TEST (0x041C) /* Test Register */
+#define NS7520_ETH_MCFG (0x0420) /* MII Management Configuration */
+#define NS7520_ETH_MCMD (0x0424) /* MII Management Command */
+#define NS7520_ETH_MADR (0x0428) /* MII Management Address */
+#define NS7520_ETH_MWTD (0x042C) /* MII Management Write Data */
+#define NS7520_ETH_MRDD (0x0430) /* MII Management Read Data */
+#define NS7520_ETH_MIND (0x0434) /* MII Management Indicators */
+#define NS7520_ETH_SMII (0x0438) /* SMII Status Register */
+#define NS7520_ETH_SA1 (0x0440) /* Station Address 1 */
+#define NS7520_ETH_SA2 (0x0444) /* Station Address 2 */
+#define NS7520_ETH_SA3 (0x0448) /* Station Address 3 */
+#define NS7520_ETH_SAFR (0x05C0) /* Station Address Filter */
+#define NS7520_ETH_HT1 (0x05D0) /* Hash Table 1 */
+#define NS7520_ETH_HT2 (0x05D4) /* Hash Table 2 */
+#define NS7520_ETH_HT3 (0x05D8) /* Hash Table 3 */
+#define NS7520_ETH_HT4 (0x05DC) /* Hash Table 4 */
+
+/* EGCR Ethernet General Control Register Bit Fields*/
+
+#define NS7520_ETH_EGCR_ERX (0x80000000) /* Enable Receive FIFO */
+#define NS7520_ETH_EGCR_ERXDMA (0x40000000) /* Enable Receive DMA */
+#define NS7520_ETH_EGCR_ERXLNG (0x20000000) /* Accept Long packets */
+#define NS7520_ETH_EGCR_ERXSHT (0x10000000) /* Accept Short packets */
+#define NS7520_ETH_EGCR_ERXREG (0x08000000) /* Enable Receive Data Interrupt */
+#define NS7520_ETH_EGCR_ERFIFOH (0x04000000) /* Enable Receive Half-Full Int */
+#define NS7520_ETH_EGCR_ERXBR (0x02000000) /* Enable Receive buffer ready */
+#define NS7520_ETH_EGCR_ERXBAD (0x01000000) /* Accept bad receive packets */
+#define NS7520_ETH_EGCR_ETX (0x00800000) /* Enable Transmit FIFO */
+#define NS7520_ETH_EGCR_ETXDMA (0x00400000) /* Enable Transmit DMA */
+#define NS7520_ETH_EGCR_ETXWM_R (0x00300000) /* Enable Transmit FIFO mark Reserv */
+#define NS7520_ETH_EGCR_ETXWM_75 (0x00200000) /* Enable Transmit FIFO mark 75% */
+#define NS7520_ETH_EGCR_ETXWM_50 (0x00100000) /* Enable Transmit FIFO mark 50% */
+#define NS7520_ETH_EGCR_ETXWM_25 (0x00000000) /* Enable Transmit FIFO mark 25% */
+#define NS7520_ETH_EGCR_ETXREG (0x00080000) /* Enable Transmit Data Read Int */
+#define NS7520_ETH_EGCR_ETFIFOH (0x00040000) /* Enable Transmit Fifo Half Int */
+#define NS7520_ETH_EGCR_ETXBC (0x00020000) /* Enable Transmit Buffer Compl Int */
+#define NS7520_ETH_EGCR_EFULLD (0x00010000) /* Enable Full Duplex Operation */
+#define NS7520_ETH_EGCR_MODE_MA (0x0000C000) /* Mask */
+#define NS7520_ETH_EGCR_MODE_SEE (0x0000C000) /* 10 Mbps SEEQ ENDEC PHY */
+#define NS7520_ETH_EGCR_MODE_LEV (0x00008000) /* 10 Mbps Level1 ENDEC PHY */
+#define NS7520_ETH_EGCR_RES1 (0x00002000) /* Reserved */
+#define NS7520_ETH_EGCR_RXCINV (0x00001000) /* Invert the receive clock input */
+#define NS7520_ETH_EGCR_TXCINV (0x00000800) /* Invert the transmit clock input */
+#define NS7520_ETH_EGCR_PNA (0x00000400) /* pSOS pNA buffer */
+#define NS7520_ETH_EGCR_MAC_RES (0x00000200) /* MAC Software reset */
+#define NS7520_ETH_EGCR_ITXA (0x00000100) /* Insert Transmit Source Address */
+#define NS7520_ETH_EGCR_ENDEC_MA (0x000000FC) /* ENDEC media control bits */
+#define NS7520_ETH_EGCR_EXINT_MA (0x00000003) /* Mask */
+#define NS7520_ETH_EGCR_EXINT_RE (0x00000003) /* Reserved */
+#define NS7520_ETH_EGCR_EXINT_TP (0x00000002) /* TP-PMD Mode */
+#define NS7520_ETH_EGCR_EXINT_10 (0x00000001) /* 10-MBit Mode */
+#define NS7520_ETH_EGCR_EXINT_NO (0x00000000) /* MII normal operation */
+
+/* EGSR Ethernet General Status Register Bit Fields*/
+
+#define NS7520_ETH_EGSR_RES1 (0xC0000000) /* Reserved */
+#define NS7520_ETH_EGSR_RXFDB_MA (0x30000000) /* Receive FIFO mask */
+#define NS7520_ETH_EGSR_RXFDB_3 (0x30000000) /* Receive FIFO 3 bytes available */
+#define NS7520_ETH_EGSR_RXFDB_2 (0x20000000) /* Receive FIFO 2 bytes available */
+#define NS7520_ETH_EGCR_RXFDB_1 (0x10000000) /* Receive FIFO 1 Bytes available */
+#define NS7520_ETH_EGCR_RXFDB_4 (0x00000000) /* Receive FIFO 4 Bytes available */
+#define NS7520_ETH_EGSR_RXREGR (0x08000000) /* Receive Register Ready */
+#define NS7520_ETH_EGSR_RXFIFOH (0x04000000) /* Receive FIFO Half Full */
+#define NS7520_ETH_EGSR_RXBR (0x02000000) /* Receive Buffer Ready */
+#define NS7520_ETH_EGSR_RXSKIP (0x01000000) /* Receive Buffer Skip */
+#define NS7520_ETH_EGSR_RES2 (0x00F00000) /* Reserved */
+#define NS7520_ETH_EGSR_TXREGE (0x00080000) /* Transmit Register Empty */
+#define NS7520_ETH_EGSR_TXFIFOH (0x00040000) /* Transmit FIFO half empty */
+#define NS7520_ETH_EGSR_TXBC (0x00020000) /* Transmit buffer complete */
+#define NS7520_ETH_EGSR_TXFIFOE (0x00010000) /* Transmit FIFO empty */
+#define NS7520_ETH_EGSR_RXPINS (0x0000FC00) /* ENDEC Phy Status */
+#define NS7520_ETH_EGSR_RES3 (0x000003FF) /* Reserved */
+
+/* ETSR Ethernet Transmit Status Register Bit Fields*/
+
+#define NS7520_ETH_ETSR_RES1 (0xFFFF0000) /* Reserved */
+#define NS7520_ETH_ETSR_TXOK (0x00008000) /* Packet transmitted OK */
+#define NS7520_ETH_ETSR_TXBR (0x00004000) /* Broadcast packet transmitted */
+#define NS7520_ETH_ETSR_TXMC (0x00002000) /* Multicast packet transmitted */
+#define NS7520_ETH_ETSR_TXAL (0x00001000) /* Transmit abort - late collision */
+#define NS7520_ETH_ETSR_TXAED (0x00000800) /* Transmit abort - deferral */
+#define NS7520_ETH_ETSR_TXAEC (0x00000400) /* Transmit abort - exc collisions */
+#define NS7520_ETH_ETSR_TXAUR (0x00000200) /* Transmit abort - underrun */
+#define NS7520_ETH_ETSR_TXAJ (0x00000100) /* Transmit abort - jumbo */
+#define NS7520_ETH_ETSR_RES2 (0x00000080) /* Reserved */
+#define NS7520_ETH_ETSR_TXDEF (0x00000040) /* Transmit Packet Deferred */
+#define NS7520_ETH_ETSR_TXCRC (0x00000020) /* Transmit CRC error */
+#define NS7520_ETH_ETSR_RES3 (0x00000010) /* Reserved */
+#define NS7520_ETH_ETSR_TXCOLC (0x0000000F) /* Transmit Collision Count */
+
+/* ERSR Ethernet Receive Status Register Bit Fields*/
+
+#define NS7520_ETH_ERSR_RXSIZE (0xFFFF0000) /* Receive Buffer Size */
+#define NS7520_ETH_ERSR_RXCE (0x00008000) /* Receive Carrier Event */
+#define NS7520_ETH_ERSR_RXDV (0x00004000) /* Receive Data Violation Event */
+#define NS7520_ETH_ERSR_RXOK (0x00002000) /* Receive Packet OK */
+#define NS7520_ETH_ERSR_RXBR (0x00001000) /* Receive Broadcast Packet */
+#define NS7520_ETH_ERSR_RXMC (0x00000800) /* Receive Multicast Packet */
+#define NS7520_ETH_ERSR_RXCRC (0x00000400) /* Receive Packet has CRC error */
+#define NS7520_ETH_ERSR_RXDR (0x00000200) /* Receive Packet has dribble error */
+#define NS7520_ETH_ERSR_RXCV (0x00000100) /* Receive Packet code violation */
+#define NS7520_ETH_ERSR_RXLNG (0x00000080) /* Receive Packet too long */
+#define NS7520_ETH_ERSR_RXSHT (0x00000040) /* Receive Packet too short */
+#define NS7520_ETH_ERSR_ROVER (0x00000020) /* Recive overflow */
+#define NS7520_ETH_ERSR_RES (0x0000001F) /* Reserved */
+
+/* MAC1 MAC Configuration Register 1 Bit Fields*/
+
+#define NS7520_ETH_MAC1_RES1 (0xFFFF0000) /* Reserved */
+#define NS7520_ETH_MAC1_SRST (0x00008000) /* Soft Reset */
+#define NS7520_ETH_MAC1_SIMMRST (0x00004000) /* Simulation Reset */
+#define NS7520_ETH_MAC1_RES2 (0x00003000) /* Reserved */
+#define NS7520_ETH_MAC1_RPEMCSR (0x00000800) /* Reset PEMCS/RX */
+#define NS7520_ETH_MAC1_RPERFUN (0x00000400) /* Reset PERFUN */
+#define NS7520_ETH_MAC1_RPEMCST (0x00000200) /* Reset PEMCS/TX */
+#define NS7520_ETH_MAC1_RPETFUN (0x00000100) /* Reset PETFUN */
+#define NS7520_ETH_MAC1_RES3 (0x000000E0) /* Reserved */
+#define NS7520_ETH_MAC1_LOOPBK (0x00000010) /* Internal Loopback */
+#define NS7520_ETH_MAC1_TXFLOW (0x00000008) /* TX flow control */
+#define NS7520_ETH_MAC1_RXFLOW (0x00000004) /* RX flow control */
+#define NS7520_ETH_MAC1_PALLRX (0x00000002) /* Pass ALL receive frames */
+#define NS7520_ETH_MAC1_RXEN (0x00000001) /* Receive enable */
+
+/* MAC Configuration Register 2 Bit Fields*/
+
+#define NS7520_ETH_MAC2_RES1 (0xFFFF8000) /* Reserved */
+#define NS7520_ETH_MAC2_EDEFER (0x00004000) /* Excess Deferral */
+#define NS7520_ETH_MAC2_BACKP (0x00002000) /* Backpressure/NO back off */
+#define NS7520_ETH_MAC2_NOBO (0x00001000) /* No back off */
+#define NS7520_ETH_MAC2_RES2 (0x00000C00) /* Reserved */
+#define NS7520_ETH_MAC2_LONGP (0x00000200) /* Long Preable enforcement */
+#define NS7520_ETH_MAC2_PUREP (0x00000100) /* Pure preamble enforcement */
+#define NS7520_ETH_MAC2_AUTOP (0x00000080) /* Auto detect PAD enable */
+#define NS7520_ETH_MAC2_VLANP (0x00000040) /* VLAN pad enable */
+#define NS7520_ETH_MAC2_PADEN (0x00000020) /* PAD/CRC enable */
+#define NS7520_ETH_MAC2_CRCEN (0x00000010) /* CRC enable */
+#define NS7520_ETH_MAC2_DELCRC (0x00000008) /* Delayed CRC */
+#define NS7520_ETH_MAC2_HUGE (0x00000004) /* Huge frame enable */
+#define NS7520_ETH_MAC2_FLENC (0x00000002) /* Frame length checking */
+#define NS7520_ETH_MAC2_FULLD (0x00000001) /* Full duplex */
+
+/* IPGT Back-to-Back Inter-Packet-Gap Register Bit Fields*/
+
+#define NS7520_ETH_IPGT_RES (0xFFFFFF80) /* Reserved */
+#define NS7520_ETH_IPGT_IPGT (0x0000007F) /* Back-to-Back Interpacket Gap */
+
+/* IPGR Non Back-to-Back Inter-Packet-Gap Register Bit Fields*/
+
+#define NS7520_ETH_IPGR_RES1 (0xFFFF8000) /* Reserved */
+#define NS7520_ETH_IPGR_IPGR1 (0x00007F00) /* Non Back-to-back Interpacket Gap */
+#define NS7520_ETH_IPGR_RES2 (0x00000080) /* Reserved */
+#define NS7520_ETH_IPGR_IPGR2 (0x0000007F) /* Non back-to-back Interpacket Gap */
+
+/* CLRT Collision Windows/Collision Retry Register Bit Fields*/
+
+#define NS7520_ETH_CLRT_RES1 (0xFFFFC000) /* Reserved */
+#define NS7520_ETH_CLRT_CWIN (0x00003F00) /* Collision Windows */
+#define NS7520_ETH_CLRT_RES2 (0x000000F0) /* Reserved */
+#define NS7520_ETH_CLRT_RETX (0x0000000F) /* Retransmission maximum */
+
+/* MAXF Maximum Frame Register Bit Fields*/
+
+#define NS7520_ETH_MAXF_RES1 (0xFFFF0000) /* Reserved */
+#define NS7520_ETH_MAXF_MAXF (0x0000FFFF) /* Maximum frame length */
+
+/* SUPP PHY Support Register Bit Fields*/
+
+#define NS7520_ETH_SUPP_RES1 (0xFFFFFF00) /* Reserved */
+#define NS7520_ETH_SUPP_RPE100X (0x00000080) /* Reset PE100X module */
+#define NS7520_ETH_SUPP_FORCEQ (0x00000040) /* Force Quit */
+#define NS7520_ETH_SUPP_NOCIPH (0x00000020) /* No Cipher */
+#define NS7520_ETH_SUPP_DLINKF (0x00000010) /* Disable link fail */
+#define NS7520_ETH_SUPP_RPE10T (0x00000008) /* Reset PE10T module */
+#define NS7520_ETH_SUPP_RES2 (0x00000004) /* Reserved */
+#define NS7520_ETH_SUPP_JABBER (0x00000002) /* Enable Jabber protection */
+#define NS7520_ETH_SUPP_BITMODE (0x00000001) /* Bit Mode */
+
+/* TEST Register Bit Fields*/
+
+#define NS7520_ETH_TEST_RES1 (0xFFFFFFF8) /* Reserved */
+#define NS7520_ETH_TEST_TBACK (0x00000004) /* Test backpressure */
+#define NS7520_ETH_TEST_TPAUSE (0x00000002) /* Test Pause */
+#define NS7520_ETH_TEST_SPQ (0x00000001) /* Shortcut pause quanta */
+
+/* MCFG MII Management Configuration Register Bit Fields*/
+
+#define NS7520_ETH_MCFG_RES1 (0xFFFF0000) /* Reserved */
+#define NS7520_ETH_MCFG_RMIIM (0x00008000) /* Reset MII management */
+#define NS7520_ETH_MCFG_RES2 (0x00007FE0) /* Reserved */
+#define NS7520_ETH_MCFG_CLKS_MA (0x0000001C) /* Clock Select */
+#define NS7520_ETH_MCFG_CLKS_4 (0x00000004) /* Sysclk / 4 */
+#define NS7520_ETH_MCFG_CLKS_6 (0x00000008) /* Sysclk / 6 */
+#define NS7520_ETH_MCFG_CLKS_8 (0x0000000C) /* Sysclk / 8 */
+#define NS7520_ETH_MCFG_CLKS_10 (0x00000010) /* Sysclk / 10 */
+#define NS7520_ETH_MCFG_CLKS_14 (0x00000014) /* Sysclk / 14 */
+#define NS7520_ETH_MCFG_CLKS_20 (0x00000018) /* Sysclk / 20 */
+#define NS7520_ETH_MCFG_CLKS_28 (0x0000001C) /* Sysclk / 28 */
+#define NS7520_ETH_MCFG_SPRE (0x00000002) /* Suppress preamble */
+#define NS7520_ETH_MCFG_SCANI (0x00000001) /* Scan increment */
+
+/* MCMD MII Management Command Register Bit Fields*/
+
+#define NS7520_ETH_MCMD_RES1 (0xFFFFFFFC) /* Reserved */
+#define NS7520_ETH_MCMD_SCAN (0x00000002) /* Automatically Scan for Read Data */
+#define NS7520_ETH_MCMD_READ (0x00000001) /* Single scan for Read Data */
+
+/* MCMD MII Management Address Register Bit Fields*/
+
+#define NS7520_ETH_MADR_RES1 (0xFFFFE000) /* Reserved */
+#define NS7520_ETH_MADR_DADR (0x00001F00) /* MII PHY device address */
+#define NS7520_ETH_MADR_RES2 (0x000000E0) /* Reserved */
+#define NS7520_ETH_MADR_RADR (0x0000001F) /* MII PHY register address */
+
+/* MWTD MII Management Write Data Register Bit Fields*/
+
+#define NS7520_ETH_MWTD_RES1 (0xFFFF0000) /* Reserved */
+#define NS7520_ETH_MWTD_MWTD (0x0000FFFF) /* MII Write Data */
+
+/* MRRD MII Management Read Data Register Bit Fields*/
+
+#define NS7520_ETH_MRRD_RES1 (0xFFFF0000) /* Reserved */
+#define NS7520_ETH_MRRD_MRDD (0x0000FFFF) /* MII Read Data */
+
+/* MIND MII Management Indicators Register Bit Fields*/
+
+#define NS7520_ETH_MIND_RES1 (0xFFFFFFF8) /* Reserved */
+#define NS7520_ETH_MIND_NVALID (0x00000004) /* Read Data not valid */
+#define NS7520_ETH_MIND_SCAN (0x00000002) /* Automatically scan for read data */
+#define NS7520_ETH_MIND_BUSY (0x00000001) /* MII interface busy */
+
+/* SMII Status Register Bit Fields*/
+
+#define NS7520_ETH_SMII_RES1 (0xFFFFFFE0) /* Reserved */
+#define NS7520_ETH_SMII_CLASH (0x00000010) /* MAC-to-MAC with PHY */
+#define NS7520_ETH_SMII_JABBER (0x00000008) /* Jabber condition present */
+#define NS7520_ETH_SMII_LINK (0x00000004) /* Link OK */
+#define NS7520_ETH_SMII_DUPLEX (0x00000002) /* Full-duplex operation */
+#define NS7520_ETH_SMII_SPEED (0x00000001) /* 100 Mbps */
+
+/* SA1 Station Address 1 Register Bit Fields*/
+
+#define NS7520_ETH_SA1_RES1 (0xFFFF0000) /* Reserved */
+#define NS7520_ETH_SA1_OCTET1 (0x0000FF00) /* Station Address octet 1 */
+#define NS7520_ETH_SA1_OCTET2 (0x000000FF) /* Station Address octet 2 */
+
+/* SA2 Station Address 2 Register Bit Fields*/
+
+#define NS7520_ETH_SA2_RES1 (0xFFFF0000) /* Reserved */
+#define NS7520_ETH_SA2_OCTET3 (0x0000FF00) /* Station Address octet 3 */
+#define NS7520_ETH_SA2_OCTET4 (0x000000FF) /* Station Address octet 4 */
+
+/* SA3 Station Address 3 Register Bit Fields*/
+
+#define NS7520_ETH_SA3_RES1 (0xFFFF0000) /* Reserved */
+#define NS7520_ETH_SA3_OCTET5 (0x0000FF00) /* Station Address octet 5 */
+#define NS7520_ETH_SA3_OCTET6 (0x000000FF) /* Station Address octet 6 */
+
+/* SAFR Station Address Filter Register Bit Fields*/
+
+#define NS7520_ETH_SAFR_RES1 (0xFFFFFFF0) /* Reserved */
+#define NS7520_ETH_SAFR_PRO (0x00000008) /* Enable Promiscuous mode */
+#define NS7520_ETH_SAFR_PRM (0x00000004) /* Accept ALL multicast packets */
+#define NS7520_ETH_SAFR_PRA (0x00000002) /* Accept multicast packets table */
+#define NS7520_ETH_SAFR_BROAD (0x00000001) /* Accept ALL Broadcast packets */
+
+/* HT1 Hash Table 1 Register Bit Fields*/
+
+#define NS7520_ETH_HT1_RES1 (0xFFFF0000) /* Reserved */
+#define NS7520_ETH_HT1_HT1 (0x0000FFFF) /* CRC value 15-0 */
+
+/* HT2 Hash Table 2 Register Bit Fields*/
+
+#define NS7520_ETH_HT2_RES1 (0xFFFF0000) /* Reserved */
+#define NS7520_ETH_HT2_HT2 (0x0000FFFF) /* CRC value 31-16 */
+
+/* HT3 Hash Table 3 Register Bit Fields*/
+
+#define NS7520_ETH_HT3_RES1 (0xFFFF0000) /* Reserved */
+#define NS7520_ETH_HT3_HT3 (0x0000FFFF) /* CRC value 47-32 */
+
+/* HT4 Hash Table 4 Register Bit Fields*/
+
+#define NS7520_ETH_HT4_RES1 (0xFFFF0000) /* Reserved */
+#define NS7520_ETH_HT4_HT4 (0x0000FFFF) /* CRC value 63-48 */
+
+#endif /* CONFIG_DRIVER_NS7520_ETHERNET */
+
+#endif /* FS_NS7520_ETH_H */
#define PCI_DEVICE_ID_CT_65554 0x00e4
#define PCI_DEVICE_ID_CT_65555 0x00e5
#define PCI_DEVICE_ID_CT_69000 0x00c0
+#define PCI_DEVICE_ID_CT_69030 0x0c30
#define PCI_VENDOR_ID_MIRO 0x1031
#define PCI_DEVICE_ID_MIRO_36050 0x5601
#define ivor13 0x19d /* interrupt vector offset register 13 */
#define ivor14 0x19e /* interrupt vector offset register 14 */
#define ivor15 0x19f /* interrupt vector offset register 15 */
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
#define mcsrr0 0x23a /* machine check save/restore register 0 */
#define mcsrr1 0x23b /* mahcine check save/restore register 1 */
#define mcsr 0x23c /* machine check status register */
#define sdr_plbtr 0x4200
#define sdr_mfr 0x4300 /* SDR0_MFR reg */
-
/*-----------------------------------------------------------------------------
| SDRAM Controller
+----------------------------------------------------------------------------*/
#define mem_eccesr 0x0098 /* ECC error status */
/*-----------------------------------------------------------------------------
- | Extrnal Bus Controller
+ | External Bus Controller
+----------------------------------------------------------------------------*/
#define EBC_DCR_BASE 0x12
#define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */
#define pbear 0x20 /* periph bus error addr reg */
#define pbesr 0x21 /* periph bus error status reg */
#define xbcfg 0x23 /* external bus configuration reg */
-#define xbcid 0x23 /* external bus core id reg */
+#define xbcid 0x24 /* external bus core id reg */
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
/*-----------------------------------------------------------------------------
| L2 Cache
+----------------------------------------------------------------------------*/
-#if defined (CONFIG_440GX)
+#if defined (CONFIG_440GX) || defined(CONFIG_440SP)
#define L2_CACHE_BASE 0x030
#define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */
#define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */
| Clocking, Power Management and Chip Control
+----------------------------------------------------------------------------*/
#define CNTRL_DCR_BASE 0x0b0
-#if defined (CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
#define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */
#define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */
#define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */
#define cpc0_strp2 (CNTRL_DCR_BASE+0x36) /* Power-on config reg 2 (RO) */
#define cpc0_strp3 (CNTRL_DCR_BASE+0x37) /* Power-on config reg 3 (RO) */
+#define cpc0_gpio (CNTRL_DCR_BASE+0x38) /* GPIO config reg (440GP) */
+
#define cntrl0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */
#define cntrl1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */
/*---------------------------------------------------------------------------+
| Universal interrupt controller 0 interrupts (UIC0)
+---------------------------------------------------------------------------*/
+#if defined(CONFIG_440SP)
+#define UIC_U0 0x80000000 /* UART 0 */
+#define UIC_U1 0x40000000 /* UART 1 */
+#define UIC_IIC0 0x20000000 /* IIC */
+#define UIC_IIC1 0x10000000 /* IIC */
+#define UIC_PIM 0x08000000 /* PCI0 inbound message */
+#define UIC_PCRW 0x04000000 /* PCI0 command write register */
+#define UIC_PPM 0x02000000 /* PCI0 power management */
+#define UIC_PVPD 0x01000000 /* PCI0 VPD Access */
+#define UIC_MSI0 0x00800000 /* PCI0 MSI level 0 */
+#define UIC_P1IM 0x00400000 /* PCI1 Inbound Message */
+#define UIC_P1CRW 0x00200000 /* PCI1 command write register */
+#define UIC_P1PM 0x00100000 /* PCI1 power management */
+#define UIC_P1VPD 0x00080000 /* PCI1 VPD Access */
+#define UIC_P1MSI0 0x00040000 /* PCI1 MSI level 0 */
+#define UIC_P2IM 0x00020000 /* PCI2 inbound message */
+#define UIC_P2CRW 0x00010000 /* PCI2 command register write */
+#define UIC_P2PM 0x00008000 /* PCI2 power management */
+#define UIC_P2VPD 0x00004000 /* PCI2 VPD access */
+#define UIC_P2MSI0 0x00002000 /* PCI2 MSI level 0 */
+#define UIC_D0CPF 0x00001000 /* DMA0 command pointer */
+#define UIC_D0CSF 0x00000800 /* DMA0 command status */
+#define UIC_D1CPF 0x00000400 /* DMA1 command pointer */
+#define UIC_D1CSF 0x00000200 /* DMA1 command status */
+#define UIC_I2OID 0x00000100 /* I2O inbound doorbell */
+#define UIC_I2OPLF 0x00000080 /* I2O inbound post list */
+#define UIC_I2O0LL 0x00000040 /* I2O0 low latency PLB write */
+#define UIC_I2O1LL 0x00000020 /* I2O1 low latency PLB write */
+#define UIC_I2O0HB 0x00000010 /* I2O0 high bandwidth PLB write */
+#define UIC_I2O1HB 0x00000008 /* I2O1 high bandwidth PLB write */
+#define UIC_GPTCT 0x00000004 /* GPT count timer */
+#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
+#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
+#else /* CONFIG_440SP */
#define UIC_U0 0x80000000 /* UART 0 */
#define UIC_U1 0x40000000 /* UART 1 */
#define UIC_IIC0 0x20000000 /* IIC */
#define UIC_EIR6 0x00000004 /* External interrupt 6 */
#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
+#endif /* CONFIG_440SP */
/* For compatibility with 405 code */
#define UIC_MAL_TXEOB UIC_MTE
/*---------------------------------------------------------------------------+
| Universal interrupt controller 1 interrupts (UIC1)
+---------------------------------------------------------------------------*/
+#if defined(CONFIG_440SP)
+#define UIC_EIR0 0x80000000 /* External interrupt 0 */
+#define UIC_MS 0x40000000 /* MAL SERR */
+#define UIC_MTDE 0x20000000 /* MAL TXDE */
+#define UIC_MRDE 0x10000000 /* MAL RXDE */
+#define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
+#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
+#define UIC_MTE 0x02000000 /* MAL TXEOB */
+#define UIC_MRE 0x01000000 /* MAL RXEOB */
+#define UIC_P0MSI1 0x00800000 /* PCI0 MSI level 1 */
+#define UIC_P1MSI1 0x00400000 /* PCI1 MSI level 1 */
+#define UIC_P2MSI1 0x00200000 /* PCI2 MSI level 1 */
+#define UIC_L2C 0x00100000 /* L2 cache */
+#define UIC_CT0 0x00080000 /* GPT compare timer 0 */
+#define UIC_CT1 0x00040000 /* GPT compare timer 1 */
+#define UIC_CT2 0x00020000 /* GPT compare timer 2 */
+#define UIC_CT3 0x00010000 /* GPT compare timer 3 */
+#define UIC_CT4 0x00008000 /* GPT compare timer 4 */
+#define UIC_EIR1 0x00004000 /* External interrupt 1 */
+#define UIC_EIR2 0x00002000 /* External interrupt 2 */
+#define UIC_EIR3 0x00001000 /* External interrupt 3 */
+#define UIC_EIR4 0x00000800 /* External interrupt 4 */
+#define UIC_EIR5 0x00000400 /* External interrupt 5 */
+#define UIC_DMAE 0x00000200 /* DMA error */
+#define UIC_I2OE 0x00000100 /* I2O error */
+#define UIC_SRE 0x00000080 /* Serial ROM error */
+#define UIC_P0AE 0x00000040 /* PCI0 asynchronous error */
+#define UIC_P1AE 0x00000020 /* PCI1 asynchronous error */
+#define UIC_P2AE 0x00000010 /* PCI2 asynchronous error */
+#define UIC_ETH0 0x00000008 /* Ethernet 0 */
+#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
+#define UIC_ETH1 0x00000002 /* Reserved */
+#define UIC_XOR 0x00000001 /* XOR */
+#else /* CONFIG_440SP */
#define UIC_MS 0x80000000 /* MAL SERR */
#define UIC_MTDE 0x40000000 /* MAL TXDE */
#define UIC_MRDE 0x20000000 /* MAL RXDE */
#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
#define UIC_ETH1 0x00000002 /* Ethernet 1 */
#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
+#endif /* CONFIG_440SP */
/* For compatibility with 405 code */
#define UIC_MAL_SERR UIC_MS
#define EBC_BXAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23)
#define EBC_BXAP_BCE_DISABLE 0x00000000
#define EBC_BXAP_BCE_ENABLE 0x00400000
+#define EBC_BXAP_BCT_MASK 0x00300000
+#define EBC_BXAP_BCT_2TRANS 0x00000000
+#define EBC_BXAP_BCT_4TRANS 0x00100000
+#define EBC_BXAP_BCT_8TRANS 0x00200000
+#define EBC_BXAP_BCT_16TRANS 0x00300000
#define EBC_BXAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18)
#define EBC_BXAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
#define EBC_BXAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14)
#define EBC_CFG_PR_128 0x0000C000
/*-----------------------------------------------------------------------------+
-| SDR 0 Bit Settings
+| SDR0 Bit Settings
+-----------------------------------------------------------------------------*/
-#define SDR0_SDSTP0_ENG_MASK 0x80000000
-#define SDR0_SDSTP0_ENG_PLLDIS 0x00000000
-#define SDR0_SDSTP0_ENG_PLLENAB 0x80000000
-#define SDR0_SDSTP0_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
-#define SDR0_SDSTP0_ENG_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
-#define SDR0_SDSTP0_SRC_MASK 0x40000000
-#define SDR0_SDSTP0_SRC_PLLOUTA 0x00000000
-#define SDR0_SDSTP0_SRC_PLLOUTB 0x40000000
-#define SDR0_SDSTP0_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
-#define SDR0_SDSTP0_SRC_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
-#define SDR0_SDSTP0_SEL_MASK 0x38000000
-#define SDR0_SDSTP0_SEL_PLLOUT 0x00000000
-#define SDR0_SDSTP0_SEL_CPU 0x08000000
-#define SDR0_SDSTP0_SEL_EBC 0x28000000
-#define SDR0_SDSTP0_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<27)
-#define SDR0_SDSTP0_SEL_DECODE(n) ((((unsigned long)(n))>>27)&0x07)
-#define SDR0_SDSTP0_TUNE_MASK 0x07FE0000
-#define SDR0_SDSTP0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<17)
-#define SDR0_SDSTP0_TUNE_DECODE(n) ((((unsigned long)(n))>>17)&0x3FF)
-#define SDR0_SDSTP0_FBDV_MASK 0x0001F000
-#define SDR0_SDSTP0_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
-#define SDR0_SDSTP0_FBDV_DECODE(n) ((((((unsigned long)(n))>>12)-1)&0x1F)+1)
-#define SDR0_SDSTP0_FWDVA_MASK 0x00000F00
-#define SDR0_SDSTP0_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<8)
-#define SDR0_SDSTP0_FWDVA_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x0F)+1)
-#define SDR0_SDSTP0_FWDVB_MASK 0x000000E0
-#define SDR0_SDSTP0_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<5)
-#define SDR0_SDSTP0_FWDVB_DECODE(n) ((((((unsigned long)(n))>>5)-1)&0x07)+1)
-#define SDR0_SDSTP0_PRBDV0_MASK 0x0000001C
-#define SDR0_SDSTP0_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<2)
-#define SDR0_SDSTP0_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>2)-1)&0x07)+1)
-#define SDR0_SDSTP0_OPBDV0_MASK 0x00000003
-#define SDR0_SDSTP0_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<0)
-#define SDR0_SDSTP0_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x03)+1)
-
-#define SDR0_SDSTP1_LFBDV_MASK 0xFC000000
-#define SDR0_SDSTP1_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<26)
-#define SDR0_SDSTP1_LFBDV_DECODE(n) ((((unsigned long)(n))>>26)&0x3F)
-#define SDR0_SDSTP1_EBCDV0_MASK 0x03000000
-#define SDR0_SDSTP1_EBCDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
-#define SDR0_SDSTP1_EBCDV0_DECODE(n) ((((unsigned long)(n))>>24)&0x03)
-#define SDR0_SDSTP1_MALDV0_MASK 0x00C00000
-#define SDR0_SDSTP1_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<22)
-#define SDR0_SDSTP1_MALDV0_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
-#define SDR0_SDSTP1_RW_MASK 0x00300000
-#define SDR0_SDSTP1_RW_8BIT 0x00000000
-#define SDR0_SDSTP1_RW_16BIT 0x00100000
-#define SDR0_SDSTP1_RW_32BIT 0x00200000
-#define SDR0_SDSTP1_RW_ENCODE(n) ((((unsigned long)(n))&0x03)<<20)
-#define SDR0_SDSTP1_RW_DECODE(n) ((((unsigned long)(n))>>20)&0x03)
-#define SDR0_SDSTP1_EARV_MASK 0x00080000
-#define SDR0_SDSTP1_EARV_EBC 0x00000000
-#define SDR0_SDSTP1_EARV_PCI 0x00080000
-#define SDR0_SDSTP1_PAE_MASK 0x00040000
-#define SDR0_SDSTP1_PAE_DISABLE 0x00000000
-#define SDR0_SDSTP1_PAE_ENABLE 0x00040000
-#define SDR0_SDSTP1_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18)
-#define SDR0_SDSTP1_PAE_DECODE(n) ((((unsigned long)(n))>>18)&0x01)
-#define SDR0_SDSTP1_PHCE_MASK 0x00020000
-#define SDR0_SDSTP1_PHCE_DISABLE 0x00000000
-#define SDR0_SDSTP1_PHCE_ENABLE 0x00020000
-#define SDR0_SDSTP1_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17)
-#define SDR0_SDSTP1_PHCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01)
-#define SDR0_SDSTP1_PISE_MASK 0x00010000
-#define SDR0_SDSTP1_PISE_DISABLE 0x00000000
-#define SDR0_SDSTP1_PISE_ENABLE 0x00010000
-#define SDR0_SDSTP1_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16)
-#define SDR0_SDSTP1_PISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01)
-#define SDR0_SDSTP1_PCWE_MASK 0x00008000
-#define SDR0_SDSTP1_PCWE_DISABLE 0x00000000
-#define SDR0_SDSTP1_PCWE_ENABLE 0x00008000
-#define SDR0_SDSTP1_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15)
-#define SDR0_SDSTP1_PCWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01)
-#define SDR0_SDSTP1_PPIM_MASK 0x00008000
-#define SDR0_SDSTP1_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11)
-#define SDR0_SDSTP1_PPIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F)
-#define SDR0_SDSTP1_PR64E_MASK 0x00000400
-#define SDR0_SDSTP1_PR64E_DISABLE 0x00000000
-#define SDR0_SDSTP1_PR64E_ENABLE 0x00000400
-#define SDR0_SDSTP1_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<10)
-#define SDR0_SDSTP1_PR64E_DECODE(n) ((((unsigned long)(n))>>10)&0x01)
-#define SDR0_SDSTP1_PXFS_MASK 0x00000300
-#define SDR0_SDSTP1_PXFS_HIGH 0x00000000
-#define SDR0_SDSTP1_PXFS_MED 0x00000100
-#define SDR0_SDSTP1_PXFS_LOW 0x00000200
-#define SDR0_SDSTP1_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
-#define SDR0_SDSTP1_PXFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
-#define SDR0_SDSTP1_PDM_MASK 0x00000040
-#define SDR0_SDSTP1_PDM_MULTIPOINT 0x00000000
-#define SDR0_SDSTP1_PDM_P2P 0x00000040
-#define SDR0_SDSTP1_PDM_ENCODE(n) ((((unsigned long)(n))&0x01)<<6)
-#define SDR0_SDSTP1_PDM_DECODE(n) ((((unsigned long)(n))>>6)&0x01)
-#define SDR0_SDSTP1_EPS_MASK 0x00000038
-#define SDR0_SDSTP1_EPS_GROUP0 0x00000000
-#define SDR0_SDSTP1_EPS_GROUP1 0x00000008
-#define SDR0_SDSTP1_EPS_GROUP2 0x00000010
-#define SDR0_SDSTP1_EPS_GROUP3 0x00000018
-#define SDR0_SDSTP1_EPS_GROUP4 0x00000020
-#define SDR0_SDSTP1_EPS_GROUP5 0x00000028
-#define SDR0_SDSTP1_EPS_GROUP6 0x00000030
-#define SDR0_SDSTP1_EPS_GROUP7 0x00000038
-#define SDR0_SDSTP1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<3)
-#define SDR0_SDSTP1_EPS_DECODE(n) ((((unsigned long)(n))>>3)&0x07)
-#define SDR0_SDSTP1_RMII_MASK 0x00000004
-#define SDR0_SDSTP1_RMII_100MBIT 0x00000000
-#define SDR0_SDSTP1_RMII_10MBIT 0x00000004
-#define SDR0_SDSTP1_RMII_ENCODE(n) ((((unsigned long)(n))&0x01)<<2)
-#define SDR0_SDSTP1_RMII_DECODE(n) ((((unsigned long)(n))>>2)&0x01)
-#define SDR0_SDSTP1_TRE_MASK 0x00000002
-#define SDR0_SDSTP1_TRE_DISABLE 0x00000000
-#define SDR0_SDSTP1_TRE_ENABLE 0x00000002
-#define SDR0_SDSTP1_TRE_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
-#define SDR0_SDSTP1_TRE_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
-#define SDR0_SDSTP1_NTO1_MASK 0x00000001
-#define SDR0_SDSTP1_NTO1_DISABLE 0x00000000
-#define SDR0_SDSTP1_NTO1_ENABLE 0x00000001
-#define SDR0_SDSTP1_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<0)
-#define SDR0_SDSTP1_NTO1_DECODE(n) ((((unsigned long)(n))>>0)&0x01)
-
-#define SDR0_EBC_RW_MASK 0x30000000
-#define SDR0_EBC_RW_8BIT 0x00000000
-#define SDR0_EBC_RW_16BIT 0x10000000
-#define SDR0_EBC_RW_32BIT 0x20000000
-#define SDR0_EBC_RW_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
-#define SDR0_EBC_RW_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
+#define SDR0_SDCS_SDD (0x80000000 >> 31)
+
+#if defined(CONFIG_440GP)
+#define CPC0_STRP1_PAE_MASK (0x80000000 >> 11)
+#define CPC0_STRP1_PISE_MASK (0x80000000 >> 13)
+#endif /* defined(CONFIG_440GP) */
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
+#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13)
+#define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15)
+#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21)
+#define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27)
+#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
#define SDR0_UARTX_UXICS_MASK 0xF0000000
#define SDR0_UARTX_UXICS_PLB 0x20000000
/*-----------------------------------------------------------------------------+
| Clocking
+-----------------------------------------------------------------------------*/
-#if !defined (CONFIG_440GX) && !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
+#if !defined (CONFIG_440GX) && !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && !defined(CONFIG_440SP)
#define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */
#define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */
#define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */
/******************************************************************************
* GPIO macro register defines
******************************************************************************/
+#if defined(CONFIG_440GP)
+#define GPIO_BASE0 (CFG_PERIPHERAL_BASE+0x00000700)
+
+#define GPIO0_OR (GPIO_BASE0+0x0)
+#define GPIO0_TCR (GPIO_BASE0+0x4)
+#define GPIO0_ODR (GPIO_BASE0+0x18)
+#define GPIO0_IR (GPIO_BASE0+0x1C)
+#endif /* CONFIG_440GP */
+
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define GPIO_BASE0 (CFG_PERIPHERAL_BASE+0x00000B00)
#define GPIO_BASE1 (CFG_PERIPHERAL_BASE+0x00000C00)
| ported to handle 440GP and 440GX multiple EMACs
+----------------------------------------------------------------------------*/
-#ifndef _emacgx_enet_h_
-#define _emacgx_enet_h_
+#ifndef _PPC4XX_ENET_H_
+#define _PPC4XX_ENET_H_
-#if defined(CONFIG_440)
#include <net.h>
#include "405_mal.h"
int rx;
int rx_prot_err;
int int_err;
- int pkts_tx;
- int pkts_rx;
- int pkts_handled;
+ int pkts_tx;
+ int pkts_rx;
+ int pkts_handled;
short tx_err_log[MAX_ERR_LOG];
short rx_err_log[MAX_ERR_LOG];
} EMAC_STATS_ST, *EMAC_STATS_PST;
-/* Structure containing variables used by the shared code (440gx_enet.c) */
-typedef struct emac_440gx_hw_st {
+/* Structure containing variables used by the shared code (4xx_enet.c) */
+typedef struct emac_4xx_hw_st {
uint32_t hw_addr; /* EMAC offset */
uint32_t tah_addr; /* TAH offset */
uint32_t phy_id;
int is_receiving; /* sync with eth interrupt */
int print_speed; /* print speed message upon start */
EMAC_STATS_ST stats;
-} EMAC_440GX_HW_ST, *EMAC_440GX_HW_PST;
+} EMAC_4XX_HW_ST, *EMAC_4XX_HW_PST;
#if defined(CONFIG_440GX)
#define EMAC_NUM_DEV 4
-#elif defined(CONFIG_440) && !defined(CONFIG_440GX)
+#elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \
+ defined(CONFIG_NET_MULTI) && \
+ !defined(CONFIG_440SP)
#define EMAC_NUM_DEV 2
#else
-#warning Bad configuration
+#define EMAC_NUM_DEV 1
#endif
#define TAH_SSR5 (TAH_BASE + 0x28) /* Segment Size Reg 5 (R/W) */
#define TAH_TSR (TAH_BASE + 0x2C) /* Transmit Status Register (RO) */
-
/* TAH Revision */
#define TAH_REV_RN_M (0x000FFF00) /* Revision Number */
#define TAH_REV_BN_M (0x000000FF) /* Branch Revision Number */
/* Ethernet MAC Regsiter Addresses */
+#if defined(CONFIG_440)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00)
#else
#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)
#endif
+#else
+#define EMAC_BASE 0xEF600800
+#endif
#define EMAC_M0 (EMAC_BASE)
#define EMAC_M1 (EMAC_BASE + 4)
#define EMAC_M0_WKE (0x04000000)
/* on 440GX EMAC_MR1 has a different layout! */
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
/* MODE Reg 1 */
#define EMAC_M1_FDE (0x80000000)
#define EMAC_M1_ILE (0x40000000)
/* all the errors we care about */
#define EMAC_RX_ERRORS (0x03FF)
-#endif /* CONFIG_440 */
-#endif /* _enetLib_h_ */
+#endif /* _PPC4XX_ENET_H_ */
#ifndef _SM501_H_
#define _SM501_H_
+#define PCI_VENDOR_SM 0x126f
+#define PCI_DEVICE_SM501 0x0501
+
typedef struct {
unsigned int Index;
unsigned int Value;
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _SPARTAN3_H_
+#define _SPARTAN3_H_
+
+#include <xilinx.h>
+
+extern int Spartan3_load( Xilinx_desc *desc, void *image, size_t size );
+extern int Spartan3_dump( Xilinx_desc *desc, void *buf, size_t bsize );
+extern int Spartan3_info( Xilinx_desc *desc );
+extern int Spartan3_reloc( Xilinx_desc *desc, ulong reloc_off );
+
+/* Slave Parallel Implementation function table */
+typedef struct {
+ Xilinx_pre_fn pre;
+ Xilinx_pgm_fn pgm;
+ Xilinx_init_fn init;
+ Xilinx_err_fn err;
+ Xilinx_done_fn done;
+ Xilinx_clk_fn clk;
+ Xilinx_cs_fn cs;
+ Xilinx_wr_fn wr;
+ Xilinx_rdata_fn rdata;
+ Xilinx_wdata_fn wdata;
+ Xilinx_busy_fn busy;
+ Xilinx_abort_fn abort;
+ Xilinx_post_fn post;
+ int relocated;
+} Xilinx_Spartan3_Slave_Parallel_fns;
+
+/* Slave Serial Implementation function table */
+typedef struct {
+ Xilinx_pre_fn pre;
+ Xilinx_pgm_fn pgm;
+ Xilinx_clk_fn clk;
+ Xilinx_init_fn init;
+ Xilinx_done_fn done;
+ Xilinx_wr_fn wr;
+ int relocated;
+} Xilinx_Spartan3_Slave_Serial_fns;
+
+/* Device Image Sizes
+ *********************************************************************/
+/* Spartan-III (1.2V) */
+#define XILINX_XC3S50_SIZE 439264/8
+#define XILINX_XC3S200_SIZE 1047616/8
+#define XILINX_XC3S400_SIZE 1699136/8
+#define XILINX_XC3S1000_SIZE 3223488/8
+#define XILINX_XC3S1500_SIZE 5214784/8
+#define XILINX_XC3S2000_SIZE 7673024/8
+#define XILINX_XC3S4000_SIZE 11316864/8
+#define XILINX_XC3S5000_SIZE 13271936/8
+
+/* Descriptor Macros
+ *********************************************************************/
+/* Spartan-II devices */
+#define XILINX_XC3S50_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie }
+
+#define XILINX_XC3S200_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie }
+
+#define XILINX_XC3S400_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie }
+
+#define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie }
+
+#define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie }
+
+#define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan3, iface, XILINX_XC3S2000E_SIZE, fn_table, cookie }
+
+#define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan3, iface, XILINX_XC3S4000E_SIZE, fn_table, cookie }
+
+#define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan3, iface, XILINX_XC3S5000E_SIZE, fn_table, cookie }
+
+#endif /* _SPARTAN3_H_ */
void reset_5xx_watchdog(volatile immap_t *immr);
#endif
-/* IBM 4xx */
+/* AMCC 4xx */
#if defined(CONFIG_4xx) && !defined(__ASSEMBLY__)
void reset_4xx_watchdog(void);
#endif
#define CFG_SPARTAN2 CFG_FPGA_DEV( 0x1 )
#define CFG_VIRTEX_E CFG_FPGA_DEV( 0x2 )
#define CFG_VIRTEX2 CFG_FPGA_DEV( 0x4 )
+#define CFG_SPARTAN3 CFG_FPGA_DEV( 0x8 )
#define CFG_XILINX_SPARTAN2 (CFG_FPGA_XILINX | CFG_SPARTAN2)
#define CFG_XILINX_VIRTEX_E (CFG_FPGA_XILINX | CFG_VIRTEX_E)
#define CFG_XILINX_VIRTEX2 (CFG_FPGA_XILINX | CFG_VIRTEX2)
+#define CFG_XILINX_SPARTAN3 (CFG_FPGA_XILINX | CFG_SPARTAN3)
/* XXX - Add new models here */
Xilinx_Spartan2, /* Spartan-II Family */
Xilinx_VirtexE, /* Virtex-E Family */
Xilinx_Virtex2, /* Virtex2 Family */
+ Xilinx_Spartan3, /* Spartan-III Family */
max_xilinx_type /* insert all new types before this */
} Xilinx_Family; /* end, typedef Xilinx_Family */
do_reset (cmdtp, flag, argc, argv);
}
-#if defined(CONFIG_B2) || defined(CONFIG_EVB4510)
+#if defined(CONFIG_B2) || defined(CONFIG_EVB4510) || defined(CONFIG_ARMADILLO)
/*
*we need to copy the ramdisk to SRAM to let Linux boot
*/
/*
- * (C) Copyright 2002
+ * (C) Copyright 2002-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2002
* MA 02111-1307 USA
*/
+/*
+ * To match the U-Boot user interface on ARM platforms to the U-Boot
+ * standard (as on PPC platforms), some messages with debug character
+ * are removed from the default U-Boot build.
+ *
+ * Define DEBUG here if you want additional info as shown below
+ * printed upon startup:
+ *
+ * U-Boot code: 00F00000 -> 00F3C774 BSS: -> 00FC3274
+ * IRQ Stack: 00ebff7c
+ * FIQ Stack: 00ebef7c
+ */
+
#include <common.h>
#include <command.h>
#include <malloc.h>
static int display_banner (void)
{
printf ("\n\n%s\n\n", version_string);
- printf ("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
- _armboot_start, _bss_start, _bss_end);
+ debug ("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
+ _armboot_start, _bss_start, _bss_end);
#ifdef CONFIG_MODEM_SUPPORT
- puts ("Modem Support enabled\n");
+ debug ("Modem Support enabled\n");
#endif
#ifdef CONFIG_USE_IRQ
- printf ("IRQ Stack: %08lx\n", IRQ_STACK_START);
- printf ("FIQ Stack: %08lx\n", FIQ_STACK_START);
+ debug ("IRQ Stack: %08lx\n", IRQ_STACK_START);
+ debug ("FIQ Stack: %08lx\n", FIQ_STACK_START);
#endif
return (0);
DECLARE_GLOBAL_DATA_PTR;
int i;
+#ifdef DEBUG
puts ("RAM Configuration:\n");
for(i=0; i<CONFIG_NR_DRAM_BANKS; i++) {
printf ("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
print_size (gd->bd->bi_dram[i].size, "\n");
}
+#else
+ ulong size = 0;
+
+ for (i=0; i<CONFIG_NR_DRAM_BANKS; i++) {
+ size += gd->bd->bi_dram[i].size;
+ }
+ puts("DRAM: ");
+ print_size(size, "\n");
+#endif
return (0);
}
*/
typedef int (init_fnc_t) (void);
+int print_cpuinfo (void); /* test-only */
+
init_fnc_t *init_sequence[] = {
cpu_init, /* basic cpu dependent setup */
board_init, /* basic board dependent setup */
serial_init, /* serial communications setup */
console_init_f, /* stage 1 init of console */
display_banner, /* say that we are here */
+#if defined(CONFIG_DISPLAY_CPUINFO)
+ print_cpuinfo, /* display cpu info (and speed) */
+#endif
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+ checkboard, /* display board info */
+#endif
dram_init, /* configure available RAM banks */
display_dram_config,
-#if defined(CONFIG_VCMA9) || defined (CONFIG_CMC_PU2)
- checkboard,
-#endif
NULL,
};
if (s)
s = (*e) ? e + 1 : e;
}
+
+#ifdef CONFIG_HAS_ETH1
+ i = getenv_r ("eth1addr", tmp, sizeof (tmp));
+ s = (i > 0) ? tmp : NULL;
+
+ for (reg = 0; reg < 6; ++reg) {
+ gd->bd->bi_enet1addr[reg] = s ? simple_strtoul (s, &e, 16) : 0;
+ if (s)
+ s = (*e) ? e + 1 : e;
+ }
+#endif
}
devices_init (); /* get the devices list going. */
+#ifdef CONFIG_CMC_PU2
+ load_sernum_ethaddr ();
+#endif /* CONFIG_CMC_PU2 */
+
jumptable_init ();
console_init_r (); /* fully init console as a device */
#ifdef BOARD_LATE_INIT
board_late_init ();
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+#if defined(CONFIG_NET_MULTI)
puts ("Net: ");
+#endif
eth_initialize(gd->bd);
#endif
/* main_loop() can return to retry autoboot, if so just run it again. */
*/
char *strswab(const char *s)
{
- char *p;
+ char *p, *q;
if ((NULL == s) || ('\0' == *s)) {
return (NULL);
}
- for (p = ((char *)s + 1); '\0' != *p; p += 2) {
+ for (p=(char *)s, q=p+1; (*p != '\0') && (*q != '\0'); p+=2, q+=2) {
char tmp;
- tmp = *(p-1);
- *(p-1) = *p;
- *p = tmp;
+
+ tmp = *p;
+ *p = *q;
+ *q = tmp;
}
return (char *) s;
misc_init_r();
#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_NET) && (0)
- WATCHDOG_RESET();
-# ifdef DEBUG
- puts ("Reset Ethernet PHY\n");
-# endif
- reset_phy();
-#endif
-
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) && !(CONFIG_COMMANDS & CFG_CMD_IDE)
WATCHDOG_RESET();
puts ("PCMCIA:");
doc_init();
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+#if defined(CONFIG_NET_MULTI)
WATCHDOG_RESET();
puts("Net: ");
+#endif
eth_initialize(gd->bd);
#endif
+#if (CONFIG_COMMANDS & CFG_CMD_NET) && (0)
+ WATCHDOG_RESET();
+# ifdef DEBUG
+ puts ("Reset Ethernet PHY\n");
+# endif
+ reset_phy();
+#endif
+
#ifdef CONFIG_LAST_STAGE_INIT
WATCHDOG_RESET();
/*
#include <net.h>
#include <environment.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#if ( ((CFG_ENV_ADDR+CFG_ENV_SIZE) < CFG_MONITOR_BASE) || \
(CFG_ENV_ADDR >= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)) ) || \
defined(CFG_ENV_IS_IN_NVRAM)
*/
static void mem_malloc_init (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
ulong dest_addr = CFG_MONITOR_BASE + gd->reloc_off;
mem_malloc_end = dest_addr;
static int init_func_ram (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_BOARD_TYPES
int board_type = gd->board_type;
#else
static int init_baudrate (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
- uchar tmp[64]; /* long enough for environment variables */
+ char tmp[64]; /* long enough for environment variables */
int i = getenv_r ("baudrate", tmp, sizeof (tmp));
gd->baudrate = (i > 0)
void board_init_f(ulong bootflag)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gd_t gd_data, *id;
bd_t *bd;
init_fnc_t **init_fnc_ptr;
ulong addr, addr_sp, len = (ulong)&uboot_end - CFG_MONITOR_BASE;
+ ulong *s;
#ifdef CONFIG_PURPLE
void copy_code (ulong);
#endif
*/
addr_sp -= 16;
addr_sp &= ~0xF;
- *((ulong *) addr_sp)-- = 0;
- *((ulong *) addr_sp)-- = 0;
+ s = (ulong *)addr_sp;
+ *s-- = 0;
+ *s-- = 0;
+ addr_sp = (ulong)s;
debug ("Stack Pointer at: %08lx\n", addr_sp);
/*
void board_init_r (gd_t *id, ulong dest_addr)
{
- DECLARE_GLOBAL_DATA_PTR;
cmd_tbl_t *cmdtp;
ulong size;
extern void malloc_bin_reloc (void);
misc_init_r ();
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+#if defined(CONFIG_NET_MULTI)
puts ("Net: ");
+#endif
eth_initialize(gd->bd);
#endif
checksum = ntohl (hdr->ih_hcrc);
hdr->ih_hcrc = 0;
- if (crc32 (0, (char *) data, len) != checksum) {
+ if (crc32 (0, (uchar *) data, len) != checksum) {
printf ("Bad Header Checksum\n");
SHOW_BOOT_PROGRESS (-11);
do_reset (cmdtp, flag, argc, argv);
ulong csum = 0;
printf (" Verifying Checksum ... ");
- csum = crc32 (0, (char *) data, len);
+ csum = crc32 (0, (uchar *) data, len);
if (csum != ntohl (hdr->ih_dcrc)) {
printf ("Bad Data CRC\n");
SHOW_BOOT_PROGRESS (-12);
#endif
#include <environment.h>
+DECLARE_GLOBAL_DATA_PTR;
#if defined(CFG_ENV_IS_EMBEDDED)
#define TOTAL_MALLOC_LEN CFG_MALLOC_LEN
*/
static void mem_malloc_init (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
ulong dest_addr = CFG_MONITOR_BASE + gd->reloc_off;
mem_malloc_end = dest_addr;
static int init_baudrate (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
- uchar tmp[64]; /* long enough for environment variables */
+ char tmp[64]; /* long enough for environment variables */
int i = getenv_r ("baudrate", tmp, sizeof (tmp));
gd->baudrate = (i > 0)
/***********************************************************************/
+#ifdef CONFIG_ADD_RAM_INFO
+void board_add_ram_info(int);
+#endif
+
static int init_func_ram (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_BOARD_TYPES
int board_type = gd->board_type;
#else
puts ("DRAM: ");
if ((gd->ram_size = initdram (board_type)) > 0) {
- print_size (gd->ram_size, "\n");
+ print_size (gd->ram_size, "");
+#ifdef CONFIG_ADD_RAM_INFO
+ board_add_ram_info(0);
+#endif
+ putc('\n');
return (0);
}
puts (failed);
void board_init_f (ulong bootflag)
{
- DECLARE_GLOBAL_DATA_PTR;
-
bd_t *bd;
ulong len, addr, addr_sp;
+ ulong *s;
gd_t *id;
init_fnc_t **init_fnc_ptr;
#ifdef CONFIG_PRAM
/*
* reserve protected RAM
*/
- i = getenv_r ("pram", tmp, sizeof (tmp));
- reg = (i > 0) ? simple_strtoul (tmp, NULL, 10) : CONFIG_PRAM;
+ i = getenv_r ("pram", (char *)tmp, sizeof (tmp));
+ reg = (i > 0) ? simple_strtoul ((const char *)tmp, NULL, 10) : CONFIG_PRAM;
addr -= (reg << 10); /* size is in kB */
debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
#endif /* CONFIG_PRAM */
*/
addr -= len;
addr &= ~(4096 - 1);
+#ifdef CONFIG_E500
+ /* round down to next 64 kB limit so that IVPR stays aligned */
+ addr &= ~(65536 - 1);
+#endif
debug ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr);
*/
addr_sp -= 16;
addr_sp &= ~0xF;
- *((ulong *) addr_sp)-- = 0;
- *((ulong *) addr_sp)-- = 0;
+ s = (ulong *)addr_sp;
+ *s-- = 0;
+ *s-- = 0;
+ addr_sp = (ulong)s;
debug ("Stack Pointer at: %08lx\n", addr_sp);
/*
bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
#ifdef CFG_EXTBDINFO
- strncpy (bd->bi_s_version, "1.2", sizeof (bd->bi_s_version));
- strncpy (bd->bi_r_version, U_BOOT_VERSION, sizeof (bd->bi_r_version));
+ strncpy ((char *)bd->bi_s_version, "1.2", sizeof (bd->bi_s_version));
+ strncpy ((char *)bd->bi_r_version, U_BOOT_VERSION, sizeof (bd->bi_r_version));
bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */
bd->bi_plb_busfreq = gd->bus_clk;
/* NOTREACHED - relocate_code() does not return */
}
-
/************************************************************************
*
* This is the next part if the initialization sequence: we are now
*
************************************************************************
*/
-
void board_init_r (gd_t *id, ulong dest_addr)
{
- DECLARE_GLOBAL_DATA_PTR;
cmd_tbl_t *cmdtp;
char *s, *e;
bd_t *bd;
hermes_start_lxt980 ((int) bd->bi_ethspeed);
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_NET) && ( \
- defined(CONFIG_CCM) || \
- defined(CONFIG_ELPT860) || \
- defined(CONFIG_EP8260) || \
- defined(CONFIG_IP860) || \
- defined(CONFIG_IVML24) || \
- defined(CONFIG_IVMS8) || \
- defined(CONFIG_MPC8260ADS) || \
- defined(CONFIG_MPC8266ADS) || \
- defined(CONFIG_MPC8560ADS) || \
- defined(CONFIG_PCU_E) || \
- defined(CONFIG_RPXSUPER) || \
- defined(CONFIG_STXGP3) || \
- defined(CONFIG_SPD823TS) || \
- defined(CONFIG_RESET_PHY_R) )
-
- WATCHDOG_RESET ();
- debug ("Reset Ethernet PHY\n");
- reset_phy ();
-#endif
-
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
WATCHDOG_RESET ();
puts ("KGDB: ");
nand_init(); /* go init the NAND */
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+#if defined(CONFIG_NET_MULTI)
WATCHDOG_RESET ();
puts ("Net: ");
+#endif
eth_initialize (bd);
#endif
+#if (CONFIG_COMMANDS & CFG_CMD_NET) && ( \
+ defined(CONFIG_CCM) || \
+ defined(CONFIG_ELPT860) || \
+ defined(CONFIG_EP8260) || \
+ defined(CONFIG_IP860) || \
+ defined(CONFIG_IVML24) || \
+ defined(CONFIG_IVMS8) || \
+ defined(CONFIG_MPC8260ADS) || \
+ defined(CONFIG_MPC8266ADS) || \
+ defined(CONFIG_MPC8560ADS) || \
+ defined(CONFIG_PCU_E) || \
+ defined(CONFIG_RPXSUPER) || \
+ defined(CONFIG_STXGP3) || \
+ defined(CONFIG_SPD823TS) || \
+ defined(CONFIG_RESET_PHY_R) )
+
+ WATCHDOG_RESET ();
+ debug ("Reset Ethernet PHY\n");
+ reset_phy ();
+#endif
+
#ifdef CONFIG_POST
post_run (NULL, POST_RAM | post_bootmode_get(0));
#endif
/* Also take the logbuffer into account (pram is in kB) */
pram += (LOGBUFF_LEN+LOGBUFF_OVERHEAD)/1024;
#endif
- sprintf (memsz, "%ldk", (bd->bi_memsize / 1024) - pram);
- setenv ("mem", memsz);
+ sprintf ((char *)memsz, "%ldk", (bd->bi_memsize / 1024) - pram);
+ setenv ("mem", (char *)memsz);
}
#endif
#ifdef CONFIG_MODEM_SUPPORT
/* called from main loop (common/main.c) */
+/* 'inline' - We have to do it fast */
+static inline void mdm_readline(char *buf, int bufsiz)
+{
+ char c;
+ char *p;
+ int n;
+
+ n = 0;
+ p = buf;
+ for(;;) {
+ c = serial_getc();
+
+ /* dbg("(%c)", c); */
+
+ switch(c) {
+ case '\r':
+ break;
+ case '\n':
+ *p = '\0';
+ return;
+
+ default:
+ if(n++ > bufsiz) {
+ *p = '\0';
+ return; /* sanity check */
+ }
+ *p = c;
+ p++;
+ break;
+ }
+ }
+}
+
extern void dbg(const char *fmt, ...);
int mdm_init (void)
{
char *init_str;
int i;
extern char console_buffer[];
- static inline void mdm_readline(char *buf, int bufsiz);
extern void enable_putc(void);
extern int hwflow_onoff(int);
return 0;
}
-/* 'inline' - We have to do it fast */
-static inline void mdm_readline(char *buf, int bufsiz)
-{
- char c;
- char *p;
- int n;
-
- n = 0;
- p = buf;
- for(;;) {
- c = serial_getc();
-
- /* dbg("(%c)", c); */
-
- switch(c) {
- case '\r':
- break;
- case '\n':
- *p = '\0';
- return;
-
- default:
- if(n++ > bufsiz) {
- *p = '\0';
- return; /* sanity check */
- }
- *p = c;
- p++;
- break;
- }
- }
-}
#endif
#if 0 /* We could use plain global data, but the resulting code is bigger */
/* Retrieve extended information (we must parse the vendor area) */
if (NetReadLong((ulong*)&bp->bp_vend[0]) == htonl(BOOTP_VENDOR_MAGIC))
- BootpVendorProcess(&bp->bp_vend[4], len);
+ BootpVendorProcess((uchar *)&bp->bp_vend[4], len);
NetSetTimeout(0, (thand_f *)0);
u8 *x;
#endif
#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_SEND_HOSTNAME)
- uchar *hostname;
+ char *hostname;
#endif
*e++ = 99; /* RFC1048 Magic Cookie */
unsigned char bi_enetaddr[6];
int reg;
char *e,*s;
- uchar tmp[64];
+ char tmp[64];
ulong tst1, tst2, sum, m_mask, m_value = 0;
if (BootpTry ==0) {
/* Request additional information from the BOOTP/DHCP server */
#if (CONFIG_COMMANDS & CFG_CMD_DHCP)
- ext_len = DhcpExtended(bp->bp_vend, DHCP_DISCOVER, 0, 0);
+ ext_len = DhcpExtended((u8 *)bp->bp_vend, DHCP_DISCOVER, 0, 0);
#else
- ext_len = BootpExtended(bp->bp_vend);
+ ext_len = BootpExtended((u8 *)bp->bp_vend);
#endif /* CFG_CMD_DHCP */
/*
* Copy options from OFFER packet if present
*/
NetCopyIP(&OfferedIP, &bp->bp_yiaddr);
- extlen = DhcpExtended(bp->bp_vend, DHCP_REQUEST, NetDHCPServerIP, OfferedIP);
+ extlen = DhcpExtended((u8 *)bp->bp_vend, DHCP_REQUEST, NetDHCPServerIP, OfferedIP);
pktlen = BOOTP_SIZE - sizeof(bp->bp_vend) + extlen;
iplen = BOOTP_HDR_SIZE - sizeof(bp->bp_vend) + extlen;
dhcp_state = REQUESTING;
if (NetReadLong((ulong*)&bp->bp_vend[0]) == htonl(BOOTP_VENDOR_MAGIC))
- DhcpOptionsProcess(&bp->bp_vend[4]);
+ DhcpOptionsProcess((u8 *)&bp->bp_vend[4]);
BootpCopyNetParams(bp); /* Store net params from reply */
case REQUESTING:
debug ("DHCP State: REQUESTING\n");
- if ( DhcpMessageType(bp->bp_vend) == DHCP_ACK ) {
+ if ( DhcpMessageType((u8 *)bp->bp_vend) == DHCP_ACK ) {
char *s;
if (NetReadLong((ulong*)&bp->bp_vend[0]) == htonl(BOOTP_VENDOR_MAGIC))
- DhcpOptionsProcess(&bp->bp_vend[4]);
+ DhcpOptionsProcess((u8 *)&bp->bp_vend[4]);
BootpCopyNetParams(bp); /* Store net params from reply */
dhcp_state = BOUND;
puts ("DHCP client bound to address ");
#include <common.h>
#include <command.h>
#include <net.h>
+#include <miiphy.h>
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
extern int pcnet_initialize(bd_t*);
extern int plb2800_eth_initialize(bd_t*);
extern int ppc_4xx_eth_initialize(bd_t *);
-extern int ppc_440x_eth_initialize(bd_t *);
extern int rtl8139_initialize(bd_t*);
extern int rtl8169_initialize(bd_t*);
extern int scc_initialize(bd_t*);
return eth_current;
}
+struct eth_device *eth_get_dev_by_name(char *devname)
+{
+ struct eth_device *dev, *target_dev;
+
+ if (!eth_devices)
+ return NULL;
+
+ dev = eth_devices;
+ target_dev = NULL;
+ do {
+ if (strcmp(devname, dev->name) == 0) {
+ target_dev = dev;
+ break;
+ }
+ dev = dev->next;
+ } while (dev != eth_devices);
+
+ return target_dev;
+}
+
int eth_get_dev_index (void)
{
struct eth_device *dev;
int eth_initialize(bd_t *bis)
{
- unsigned char enetvar[32], env_enetaddr[6];
+ char enetvar[32], env_enetaddr[6];
int i, eth_number = 0;
char *tmp, *end;
eth_devices = NULL;
eth_current = NULL;
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+ miiphy_init();
+#endif
+
#ifdef CONFIG_DB64360
mv6436x_eth_initialize(bis);
#endif
#ifdef CONFIG_DB64460
mv6446x_eth_initialize(bis);
#endif
-#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
- ( defined(CONFIG_440) && !defined(CONFIG_NET_MULTI) )
+#if defined(CONFIG_4xx) && !defined(CONFIG_IOP480) && !defined(CONFIG_AP1000)
ppc_4xx_eth_initialize(bis);
#endif
-#if defined(CONFIG_440) && defined(CONFIG_NET_MULTI)
- ppc_440x_eth_initialize(bis);
-#endif
#ifdef CONFIG_INCA_IP_SWITCH
inca_switch_initialize(bis);
#endif
#ifdef SCC_ENET
scc_initialize(bis);
#endif
-#if defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
- fec_initialize(bis);
-#endif
#if defined(CONFIG_MPC5xxx_FEC)
mpc5xxx_fec_initialize(bis);
#endif
tsec_initialize(bis, 3, CONFIG_MPC83XX_TSEC4_NAME);
# endif
#endif
+#if defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+ fec_initialize(bis);
+#endif
#if defined(CONFIG_AU1X00)
au1x00_enet_initialize(bis);
#endif
debug ( "Setting new HW address on %s\n"
"New Address is %02X:%02X:%02X:%02X:%02X:%02X\n",
dev->name,
- dev->enetaddr[0], dev->enetaddr[1],
- dev->enetaddr[2], dev->enetaddr[3],
- dev->enetaddr[4], dev->enetaddr[5]);
+ enetaddr[0], enetaddr[1],
+ enetaddr[2], enetaddr[3],
+ enetaddr[4], enetaddr[5]);
memcpy(dev->enetaddr, enetaddr, 6);
}
{
return (eth_current ? eth_current->name : "unknown");
}
+#elif (CONFIG_COMMANDS & CFG_CMD_NET) && !defined(CONFIG_NET_MULTI)
+
+extern int at91rm9200_miiphy_initialize(bd_t *bis);
+extern int emac4xx_miiphy_initialize(bd_t *bis);
+extern int mcf52x2_miiphy_initialize(bd_t *bis);
+extern int ns7520_miiphy_initialize(bd_t *bis);
+
+int eth_initialize(bd_t *bis)
+{
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+ miiphy_init();
+#endif
+
+#if defined(CONFIG_AT91RM9200)
+ at91rm9200_miiphy_initialize(bis);
+#endif
+#if defined(CONFIG_4xx) && !defined(CONFIG_IOP480) \
+ && !defined(CONFIG_AP1000) && !defined(CONFIG_405)
+ emac4xx_miiphy_initialize(bis);
+#endif
+#if defined(CONFIG_MCF52x2)
+ mcf52x2_miiphy_initialize(bis);
+#endif
+#if defined(CONFIG_NETARM)
+ ns7520_miiphy_initialize(bis);
+#endif
+ return 0;
+}
#endif
/*
* Echo the inverted link state to the fault LED.
*/
- if(miiphy_link(CFG_FAULT_MII_ADDR)) {
+ if(miiphy_link(eth_get_dev()->name, CFG_FAULT_MII_ADDR)) {
status_led_set (STATUS_LED_RED, STATUS_LED_OFF);
} else {
status_led_set (STATUS_LED_RED, STATUS_LED_ON);
/*
* Echo the inverted link state to the fault LED.
*/
- if(miiphy_link(CFG_FAULT_MII_ADDR)) {
+ if(miiphy_link(eth_get_dev()->name, CFG_FAULT_MII_ADDR)) {
status_led_set (STATUS_LED_RED, STATUS_LED_OFF);
} else {
status_led_set (STATUS_LED_RED, STATUS_LED_ON);
int odd;
ulong result = 0;
ushort leftover;
+ ushort *p;
if (len > 0) {
odd = 1 & (ulong)buff;
buff++;
}
while (len > 1) {
- result += *((const ushort *)buff)++;
+ p = (ushort *)buff;
+ result += *p++;
+ buff = (uchar *)p;
if (result & 0x80000000)
result = (result & 0xFFFF) + (result >> 16);
len -= 2;
}
if (len) {
leftover = (signed short)(*(const signed char *)buff);
- /* * XXX CISCO SUCKS big time! (and blows too) */
+ /* CISCO SUCKS big time! (and blows too):
+ * CDP uses the IP checksum algorithm with a twist;
+ * for the last byte it *sign* extends and sums.
+ */
result = (result & 0xffff0000) | ((result + leftover) & 0x0000ffff);
}
while (result >> 16)
NetCksum(uchar * ptr, int len)
{
ulong xsum;
+ ushort *p = (ushort *)ptr;
xsum = 0;
while (len-- > 0)
- xsum += *((ushort *)ptr)++;
+ xsum += *p++;
xsum = (xsum & 0xffff) + (xsum >> 16);
xsum = (xsum & 0xffff) + (xsum >> 16);
return (xsum & 0xffff);
ip->ip_sum = ~NetCksum((uchar *)ip, IP_HDR_SIZE_NO_UDP / 2);
}
-void copy_filename (uchar *dst, uchar *src, int size)
+void copy_filename (char *dst, char *src, int size)
{
if (*src && (*src == '"')) {
++src;
static char *tftp_filename;
#ifdef CFG_DIRECT_FLASH_TFTP
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+extern flash_info_t flash_info[];
#endif
static __inline__ void
}
if (rc) { /* Flash is destination for this packet */
- rc = flash_write ((uchar *)src, (ulong)(load_addr+offset), len);
+ rc = flash_write ((char *)src, (ulong)(load_addr+offset), len);
if (rc) {
flash_perror (rc);
NetState = NETLOOP_FAIL;
volatile uchar * pkt;
volatile uchar * xp;
int len = 0;
+ volatile ushort *s;
/*
* We will always be sending some sort of packet, so
case STATE_RRQ:
xp = pkt;
- *((ushort *)pkt)++ = htons(TFTP_RRQ);
+ s = (ushort *)pkt;
+ *s++ = htons(TFTP_RRQ);
+ pkt = (uchar *)s;
strcpy ((char *)pkt, tftp_filename);
pkt += strlen(tftp_filename) + 1;
strcpy ((char *)pkt, "octet");
case STATE_DATA:
case STATE_OACK:
xp = pkt;
- *((ushort *)pkt)++ = htons(TFTP_ACK);
- *((ushort *)pkt)++ = htons(TftpBlock);
+ s = (ushort *)pkt;
+ *s++ = htons(TFTP_ACK);
+ *s++ = htons(TftpBlock);
+ pkt = (uchar *)s;
len = pkt - xp;
break;
case STATE_TOO_LARGE:
xp = pkt;
- *((ushort *)pkt)++ = htons(TFTP_ERROR);
- *((ushort *)pkt)++ = htons(3);
+ s = (ushort *)pkt;
+ *s++ = htons(TFTP_ERROR);
+ *s++ = htons(3);
+ pkt = (uchar *)s;
strcpy ((char *)pkt, "File too large");
pkt += 14 /*strlen("File too large")*/ + 1;
len = pkt - xp;
case STATE_BAD_MAGIC:
xp = pkt;
- *((ushort *)pkt)++ = htons(TFTP_ERROR);
- *((ushort *)pkt)++ = htons(2);
+ s = (ushort *)pkt;
+ *s++ = htons(TFTP_ERROR);
+ *s++ = htons(2);
+ pkt = (uchar *)s;
strcpy ((char *)pkt, "File has bad magic");
pkt += 18 /*strlen("File has bad magic")*/ + 1;
len = pkt - xp;
TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len)
{
ushort proto;
+ ushort *s;
if (dest != TftpOurPort) {
return;
}
len -= 2;
/* warning: don't use increment (++) in ntohs() macros!! */
- proto = *((ushort *)pkt)++;
+ s = (ushort *)pkt;
+ proto = *s++;
+ pkt = (uchar *)s;
switch (ntohs(proto)) {
case TFTP_RRQ:
void
TftpStart (void)
{
+#ifdef CONFIG_TFTP_PORT
+ char *ep; /* Environment pointer */
+#endif
+
if (BootFile[0] == '\0') {
sprintf(default_filename, "%02lX%02lX%02lX%02lX.img",
NetOurIP & 0xFF,
TftpServerPort = WELL_KNOWN_PORT;
TftpTimeoutCount = 0;
TftpState = STATE_RRQ;
+ /* Use a pseudo-random port unless a specific port is set */
TftpOurPort = 1024 + (get_timer(0) % 3072);
+#ifdef CONFIG_TFTP_PORT
+ if ((ep = getenv("tftpdstp")) != NULL) {
+ TftpServerPort = simple_strtol(ep, NULL, 10);
+ }
+ if ((ep = getenv("tftpsrcp")) != NULL) {
+ TftpOurPort= simple_strtol(ep, NULL, 10);
+ }
+#endif
TftpBlock = 0;
/* zero out server ether in case the server ip has changed */
static int memory_post_dataline(unsigned long long * pmem)
{
- unsigned long long temp64;
+ unsigned long long temp64 = 0;
int num_patterns = sizeof(pattern)/ sizeof(pattern[0]);
int i;
unsigned int hi, lo, pathi, patlo;
int ret = 0;
if (ret == 0)
- ret = memory_post_dataline ((long long *)start);
+ ret = memory_post_dataline ((unsigned long long *)start);
WATCHDOG_RESET ();
if (ret == 0)
- ret = memory_post_addrline ((long *)start, (long *)start, size);
+ ret = memory_post_addrline ((ulong *)start, (ulong *)start, size);
WATCHDOG_RESET ();
if (ret == 0)
- ret = memory_post_addrline ((long *)(start + size - 8),
- (long *)start, size);
+ ret = memory_post_addrline ((ulong *)(start + size - 8),
+ (ulong *)start, size);
WATCHDOG_RESET ();
if (ret == 0)
ret = memory_post_test1 (start, size, 0x00000000);
if (bbclk.year>9) {
printf("ds1302: Year was corrupted, fixing\n");
- bbclk.year10=100; /* 2000 - why not? ;) */
+ bbclk.year10=100/10; /* 2000 - why not? ;) */
bbclk.year=0;
mod=1;
}
FILE *fp;
bitmap_t bmp;
bitmap_t *b = &bmp;
- uint16_t n_colors;
+ uint16_t data_offset, n_colors;
if (argc < 2) {
fprintf (stderr, "Usage: %s file\n", argv[0]);
* read width and height of the image, and the number of colors used;
* ignore the rest
*/
- skip_bytes (fp, 16);
+ skip_bytes (fp, 8);
+ fread (&data_offset, sizeof (uint16_t), 1, fp);
+ skip_bytes (fp, 6);
fread (&b->width, sizeof (uint16_t), 1, fp);
skip_bytes (fp, 2);
fread (&b->height, sizeof (uint16_t), 1, fp);
/*
* Repair endianess.
*/
+ data_offset = le_short(data_offset);
b->width = le_short(b->width);
b->height = le_short(b->height);
n_colors = le_short(n_colors);
);
}
+ /* seek to offset indicated by file header */
+ fseek(fp, (long)data_offset, SEEK_SET);
+
/* read the bitmap; leave room for default color map */
printf ("\n");
printf ("};\n");
if (HaveRedundEnv && stat (DEVNAME (1), &st)) {
fprintf (stderr,
"Cannot access MTD device %s: %s\n",
- DEVNAME (2), strerror (errno));
+ DEVNAME (1), strerror (errno));
return 1;
}
return 0;
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND \
"bootp; " \
- "setenv bootargs root=/dev/nfs nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "setenv bootargs root=/dev/nfs nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
extern void fw_printenv(int argc, char *argv[]);
if (opt_type == IH_TYPE_MULTI || opt_type == IH_TYPE_SCRIPT) {
char *file = datafile;
- unsigned long size;
+ uint32_t size;
for (;;) {
char *sep = NULL;
#include <common.h>
#include <flash.h>
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+extern flash_info_t flash_info[]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
#endif
/*---------------------------------------------------------------------*/
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[];
static ulong flash_get_size (ulong addr, flash_info_t *info);
static int flash_get_offsets (ulong base, flash_info_t *info);
projects / platform / kernel / u-boot.git / commitdiff