mtd: fsl-quadspi: Actually clear TX FIFO upon write

QUADSPI_MCR_CLR_TXF_MASK is the correct mask for clearing the TX FIFO.

Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
index 4fe13dd..1946c6d 100644 (file)
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -539,7 +539,7 @@ static int fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
 
        /* clear the TX FIFO. */
        tmp = readl(q->iobase + QUADSPI_MCR);
-       writel(tmp | QUADSPI_MCR_CLR_RXF_MASK, q->iobase + QUADSPI_MCR);
+       writel(tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR);
 
        /* fill the TX data to the FIFO */
        for (j = 0, i = ((count + 3) / 4); j < i; j++) {