r300/compiler: implement TXD and TXL opcodes

diff --git a/src/mesa/drivers/dri/r300/compiler/r500_fragprog.c b/src/mesa/drivers/dri/r300/compiler/r500_fragprog.c
index 140eeed..5e0be6b 100644 (file)
--- a/src/mesa/drivers/dri/r300/compiler/r500_fragprog.c
+++ b/src/mesa/drivers/dri/r300/compiler/r500_fragprog.c
@@ -70,6 +70,8 @@ static int r500_swizzle_is_native(rc_opcode opcode, struct rc_src_register reg)
        if (opcode == RC_OPCODE_TEX ||
            opcode == RC_OPCODE_TXB ||
            opcode == RC_OPCODE_TXP ||
+           opcode == RC_OPCODE_TXD ||
+           opcode == RC_OPCODE_TXL ||
            opcode == RC_OPCODE_KIL) {
                if (reg.Abs)
                        return 0;

diff --git a/src/mesa/drivers/dri/r300/compiler/r500_fragprog_emit.c b/src/mesa/drivers/dri/r300/compiler/r500_fragprog_emit.c
index 5f2588b..c30cd75 100644 (file)
--- a/src/mesa/drivers/dri/r300/compiler/r500_fragprog_emit.c
+++ b/src/mesa/drivers/dri/r300/compiler/r500_fragprog_emit.c
@@ -396,6 +396,12 @@ static int emit_tex(struct r300_fragment_program_compiler *c, struct rc_sub_inst
        case RC_OPCODE_TXP:
                code->inst[ip].inst1 |= R500_TEX_INST_PROJ;
                break;
+       case RC_OPCODE_TXD:
+               code->inst[ip].inst1 |= R500_TEX_INST_DXDY;
+               break;
+       case RC_OPCODE_TXL:
+               code->inst[ip].inst1 |= R500_TEX_INST_LOD;
+               break;
        default:
                error("emit_tex can't handle opcode %s\n", rc_get_opcode_info(inst->Opcode)->Name);
        }
@@ -413,6 +419,18 @@ static int emit_tex(struct r300_fragment_program_compiler *c, struct rc_sub_inst
                | (GET_SWZ(inst->TexSwizzle, 3) << 30)
                ;
 
+       if (inst->Opcode == RC_OPCODE_TXD) {
+               use_temporary(code, inst->SrcReg[1].Index);
+               use_temporary(code, inst->SrcReg[2].Index);
+
+               /* DX and DY parameters are specified in a separate register. */
+               code->inst[ip].inst3 =
+                       R500_DX_ADDR(inst->SrcReg[1].Index) |
+                       (translate_strq_swizzle(inst->SrcReg[1].Swizzle) << 8) |
+                       R500_DY_ADDR(inst->SrcReg[2].Index) |
+                       (translate_strq_swizzle(inst->SrcReg[2].Swizzle) << 24);
+       }
+
        return 1;
 }
 

diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
index e3e498e..afd78ad 100644 (file)
--- a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
@@ -481,6 +481,7 @@ void rc_compute_sources_for_writemask(
                        break;
                case RC_OPCODE_TXB:
                case RC_OPCODE_TXP:
+               case RC_OPCODE_TXL:
                        srcmasks[0] |= RC_MASK_W;
                        /* Fall through */
                case RC_OPCODE_TEX:
@@ -500,6 +501,33 @@ void rc_compute_sources_for_writemask(
                                        break;
                        }
                        break;
+               case RC_OPCODE_TXD:
+                       switch (inst->U.I.TexSrcTarget) {
+                               case RC_TEXTURE_1D_ARRAY:
+                                       srcmasks[0] |= RC_MASK_Y;
+                                       /* Fall through. */
+                               case RC_TEXTURE_1D:
+                                       srcmasks[0] |= RC_MASK_X;
+                                       srcmasks[1] |= RC_MASK_X;
+                                       srcmasks[2] |= RC_MASK_X;
+                                       break;
+                               case RC_TEXTURE_2D_ARRAY:
+                                       srcmasks[0] |= RC_MASK_Z;
+                                       /* Fall through. */
+                               case RC_TEXTURE_2D:
+                               case RC_TEXTURE_RECT:
+                                       srcmasks[0] |= RC_MASK_XY;
+                                       srcmasks[1] |= RC_MASK_XY;
+                                       srcmasks[2] |= RC_MASK_XY;
+                                       break;
+                               case RC_TEXTURE_3D:
+                               case RC_TEXTURE_CUBE:
+                                       srcmasks[0] |= RC_MASK_XYZ;
+                                       srcmasks[1] |= RC_MASK_XYZ;
+                                       srcmasks[2] |= RC_MASK_XYZ;
+                                       break;
+                       }
+                       break;
                case RC_OPCODE_DST:
                        srcmasks[0] |= RC_MASK_Y | RC_MASK_Z;
                        srcmasks[1] |= RC_MASK_Y | RC_MASK_W;

diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_optimize.c b/src/mesa/drivers/dri/r300/compiler/radeon_optimize.c
index 21ea25d..5b4fba8 100644 (file)
--- a/src/mesa/drivers/dri/r300/compiler/radeon_optimize.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_optimize.c
@@ -91,6 +91,8 @@ static void copy_propagate_scan_read(void * data, struct rc_instruction * inst,
                                (inst->U.I.Opcode == RC_OPCODE_TEX ||
                                inst->U.I.Opcode == RC_OPCODE_TXB ||
                                inst->U.I.Opcode == RC_OPCODE_TXP ||
+                               inst->U.I.Opcode == RC_OPCODE_TXD ||
+                               inst->U.I.Opcode == RC_OPCODE_TXL ||
                                inst->U.I.Opcode == RC_OPCODE_KIL)){
                reader_data->Abort = 1;
                return;

diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_program_tex.c b/src/mesa/drivers/dri/r300/compiler/radeon_program_tex.c
index cef448e..8d16b2c 100644 (file)
--- a/src/mesa/drivers/dri/r300/compiler/radeon_program_tex.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_program_tex.c
@@ -142,6 +142,8 @@ int radeonTransformTEX(
        if (inst->U.I.Opcode != RC_OPCODE_TEX &&
                inst->U.I.Opcode != RC_OPCODE_TXB &&
                inst->U.I.Opcode != RC_OPCODE_TXP &&
+               inst->U.I.Opcode != RC_OPCODE_TXD &&
+               inst->U.I.Opcode != RC_OPCODE_TXL &&
                inst->U.I.Opcode != RC_OPCODE_KIL)
                return 0;