clk: meson: make pll rst bit as optional

Compared with the previous SoCs, self-adaption current module
is newly added for A1, and there is no reset parameter except the
fixed pll. Since we use clk-pll generic driver for A1 pll
implementation, rst bit should be optional to support new behavior.

Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
Link: https://lore.kernel.org/r/20230523135351.19133-2-ddrokosov@sberdevices.ru
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index afefeba..314ca94 100644 (file)
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -295,10 +295,14 @@ static int meson_clk_pll_init(struct clk_hw *hw)
        struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
 
        if (pll->init_count) {
-               meson_parm_write(clk->map, &pll->rst, 1);
+               if (MESON_PARM_APPLICABLE(&pll->rst))
+                       meson_parm_write(clk->map, &pll->rst, 1);
+
                regmap_multi_reg_write(clk->map, pll->init_regs,
                                       pll->init_count);
-               meson_parm_write(clk->map, &pll->rst, 0);
+
+               if (MESON_PARM_APPLICABLE(&pll->rst))
+                       meson_parm_write(clk->map, &pll->rst, 0);
        }
 
        return 0;
@@ -309,8 +313,11 @@ static int meson_clk_pll_is_enabled(struct clk_hw *hw)
        struct clk_regmap *clk = to_clk_regmap(hw);
        struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
 
-       if (meson_parm_read(clk->map, &pll->rst) ||
-           !meson_parm_read(clk->map, &pll->en) ||
+       if (MESON_PARM_APPLICABLE(&pll->rst) &&
+           meson_parm_read(clk->map, &pll->rst))
+               return 0;
+
+       if (!meson_parm_read(clk->map, &pll->en) ||
            !meson_parm_read(clk->map, &pll->l))
                return 0;
 
@@ -341,13 +348,15 @@ static int meson_clk_pll_enable(struct clk_hw *hw)
                return 0;
 
        /* Make sure the pll is in reset */
-       meson_parm_write(clk->map, &pll->rst, 1);
+       if (MESON_PARM_APPLICABLE(&pll->rst))
+               meson_parm_write(clk->map, &pll->rst, 1);
 
        /* Enable the pll */
        meson_parm_write(clk->map, &pll->en, 1);
 
        /* Take the pll out reset */
-       meson_parm_write(clk->map, &pll->rst, 0);
+       if (MESON_PARM_APPLICABLE(&pll->rst))
+               meson_parm_write(clk->map, &pll->rst, 0);
 
        if (meson_clk_pll_wait_lock(hw))
                return -EIO;
@@ -361,7 +370,8 @@ static void meson_clk_pll_disable(struct clk_hw *hw)
        struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
 
        /* Put the pll is in reset */
-       meson_parm_write(clk->map, &pll->rst, 1);
+       if (MESON_PARM_APPLICABLE(&pll->rst))
+               meson_parm_write(clk->map, &pll->rst, 1);
 
        /* Disable the pll */
        meson_parm_write(clk->map, &pll->en, 0);