BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
/* SSSE3. */
-BDESC (OPTION_MASK_ISA_SSSE3, 0, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT)
+BDESC (OPTION_MASK_ISA_SSSE3, 0, CODE_FOR_ssse3_palignrv1ti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT)
BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT)
/* SSE4.1 */
shift = GEN_INT (min * GET_MODE_UNIT_BITSIZE (d->vmode));
if (GET_MODE_SIZE (d->vmode) == 16)
{
- target = gen_reg_rtx (TImode);
- emit_insn (gen_ssse3_palignrti (target, gen_lowpart (TImode, dcopy.op1),
- gen_lowpart (TImode, dcopy.op0), shift));
+ target = gen_reg_rtx (V1TImode);
+ emit_insn (gen_ssse3_palignrv1ti (target,
+ gen_lowpart (V1TImode, dcopy.op1),
+ gen_lowpart (V1TImode, dcopy.op0),
+ shift));
}
else
{
(define_mode_iterator VIMAX_AVX2
[(V2TI "TARGET_AVX2") V1TI])
-;; ??? This should probably be dropped in favor of VIMAX_AVX2_AVX512BW.
-(define_mode_iterator SSESCALARMODE
- [(V4TI "TARGET_AVX512BW") (V2TI "TARGET_AVX2") TI])
-
(define_mode_iterator VI12_AVX2
[(V32QI "TARGET_AVX2") V16QI
(V16HI "TARGET_AVX2") V8HI])
(V4HI "ssse3") (V8HI "ssse3") (V16HI "avx2") (V32HI "avx512bw")
(V4SI "ssse3") (V8SI "avx2")
(V2DI "ssse3") (V4DI "avx2")
- (TI "ssse3") (V2TI "avx2") (V4TI "avx512bw")])
+ (V1TI "ssse3") (V2TI "avx2") (V4TI "avx512bw")])
(define_mode_attr sse4_1_avx2
[(V16QI "sse4_1") (V32QI "avx2") (V64QI "avx512bw")
(set_attr "mode" "<sseinsnmode>")])
(define_insn "<ssse3_avx2>_palignr<mode>"
- [(set (match_operand:SSESCALARMODE 0 "register_operand" "=x,<v_Yw>")
- (unspec:SSESCALARMODE
- [(match_operand:SSESCALARMODE 1 "register_operand" "0,<v_Yw>")
- (match_operand:SSESCALARMODE 2 "vector_operand" "xBm,<v_Yw>m")
+ [(set (match_operand:VIMAX_AVX2_AVX512BW 0 "register_operand" "=x,<v_Yw>")
+ (unspec:VIMAX_AVX2_AVX512BW
+ [(match_operand:VIMAX_AVX2_AVX512BW 1 "register_operand" "0,<v_Yw>")
+ (match_operand:VIMAX_AVX2_AVX512BW 2 "vector_operand" "xBm,<v_Yw>m")
(match_operand:SI 3 "const_0_to_255_mul_8_operand")]
UNSPEC_PALIGNR))]
"TARGET_SSSE3"
gcc_unreachable ();
}
}
- "TARGET_SSSE3 && reload_completed
- && SSE_REGNO_P (REGNO (operands[0]))"
+ "(TARGET_SSSE3 && reload_completed
+ && SSE_REGNO_P (REGNO (operands[0])))
+ || operands[3] == const0_rtx
+ || INTVAL (operands[3]) == 64"
[(set (match_dup 0)
(lshiftrt:V1TI (match_dup 0) (match_dup 3)))]
{
+ if (operands[3] == const0_rtx)
+ {
+ if (!rtx_equal_p (operands[0], operands[2]))
+ emit_move_insn (operands[0], operands[2]);
+ else
+ emit_note (NOTE_INSN_DELETED);
+ DONE;
+ }
+ else if (INTVAL (operands[3]) == 64)
+ {
+ if (!rtx_equal_p (operands[0], operands[1]))
+ emit_move_insn (operands[0], operands[1]);
+ else
+ emit_note (NOTE_INSN_DELETED);
+ DONE;
+ }
+
/* Emulate MMX palignrdi with SSE psrldq. */
rtx op0 = lowpart_subreg (V2DImode, operands[0],
GET_MODE (operands[0]));
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O2 -mssse3" } */
+
+typedef long long __attribute__ ((__vector_size__ (8))) T;
+
+T x;
+T y;
+T z;
+
+void foo()
+{
+ z = __builtin_ia32_palignr (x, y, 0);
+}
+
+void bar()
+{
+ z = __builtin_ia32_palignr (x, y, 64);
+}
+/* { dg-final { scan-assembler-not "punpcklqdq" } } */
+/* { dg-final { scan-assembler-not "pshufd" } } */
+/* { dg-final { scan-assembler-not "psrldq" } } */