MIPS: mm: c-r4k: Detect instruction cache aliases

The *Aptiv cores can use the CONF7/IAR bit to detect if the core
has hardware support to remove instruction cache aliasing.

This also defines the CONF7/AR bit in order to avoid using
the '16' magic number.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6499/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index bbc3dd4..0c74617 100644 (file)
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -653,6 +653,9 @@
 
 #define MIPS_CONF7_RPS         (_ULCAST_(1) << 2)
 
+#define MIPS_CONF7_IAR         (_ULCAST_(1) << 10)
+#define MIPS_CONF7_AR          (_ULCAST_(1) << 16)
+
 /*  EntryHI bit definition */
 #define MIPS_ENTRYHI_EHINV     (_ULCAST_(1) << 10)
 

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index c14259e..8f1d549 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1117,9 +1117,14 @@ static void probe_pcache(void)
        case CPU_PROAPTIV:
                if (current_cpu_type() == CPU_74K)
                        alias_74k_erratum(c);
-               if ((read_c0_config7() & (1 << 16))) {
-                       /* effectively physically indexed dcache,
-                          thus no virtual aliases. */
+               if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
+                   (c->icache.waysize > PAGE_SIZE))
+                       c->icache.flags |= MIPS_CACHE_ALIASES;
+               if (read_c0_config7() & MIPS_CONF7_AR) {
+                       /*
+                        * Effectively physically indexed dcache,
+                        * thus no virtual aliases.
+                       */
                        c->dcache.flags |= MIPS_CACHE_PINDEX;
                        break;
                }