ARM: OMAP4/5: Remove dead code against CONFIG_SYS_CLOCKS_ENABLE_ALL

The commit
 f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls"
removed the config option aimed towards moving that stuff into kernel, which
renders some code unreachable. Remove that code.

Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>

diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index dfa3760..8e7411d 100644 (file)
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -418,55 +418,6 @@ static void setup_dplls(void)
 #endif
 }
 
-#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
-static void setup_non_essential_dplls(void)
-{
-       u32 abe_ref_clk;
-       const struct dpll_params *params;
-
-       /* IVA */
-       clrsetbits_le32((*prcm)->cm_bypclk_dpll_iva,
-               CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
-
-       params = get_iva_dpll_params(*dplls_data);
-       do_setup_dpll((*prcm)->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
-
-       /* Configure ABE dpll */
-       params = get_abe_dpll_params(*dplls_data);
-#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
-       abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
-
-       if (omap_revision() == DRA752_ES1_0)
-               /* Select the sys clk for dpll_abe */
-               clrsetbits_le32((*prcm)->cm_abe_pll_sys_clksel,
-                               CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK,
-                               CM_ABE_PLL_SYS_CLKSEL_SYSCLK2);
-#else
-       abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
-       /*
-        * We need to enable some additional options to achieve
-        * 196.608MHz from 32768 Hz
-        */
-       setbits_le32((*prcm)->cm_clkmode_dpll_abe,
-                       CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
-                       CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
-                       CM_CLKMODE_DPLL_LPMODE_EN_MASK|
-                       CM_CLKMODE_DPLL_REGM4XEN_MASK);
-       /* Spend 4 REFCLK cycles at each stage */
-       clrsetbits_le32((*prcm)->cm_clkmode_dpll_abe,
-                       CM_CLKMODE_DPLL_RAMP_RATE_MASK,
-                       1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
-#endif
-
-       /* Select the right reference clk */
-       clrsetbits_le32((*prcm)->cm_abe_pll_ref_clksel,
-                       CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
-                       abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
-       /* Lock the dpll */
-       do_setup_dpll((*prcm)->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe");
-}
-#endif
-
 u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic)
 {
        u32 offset_code;
@@ -760,10 +711,6 @@ void prcm_init(void)
                timer_init();
                scale_vcores(*omap_vcores);
                setup_dplls();
-#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
-               setup_non_essential_dplls();
-               enable_non_essential_clocks();
-#endif
                setup_warmreset_time();
                break;
        default:

diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c
index 1b2f439..4dec73e 100644 (file)
--- a/arch/arm/cpu/armv7/omap4/hw_data.c
+++ b/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -399,91 +399,6 @@ void enable_basic_uboot_clocks(void)
                         1);
 }
 
-/*
- * Enable non-essential clock domains, modules and
- * do some additional special settings needed
- */
-void enable_non_essential_clocks(void)
-{
-       u32 const clk_domains_non_essential[] = {
-               (*prcm)->cm_mpu_m3_clkstctrl,
-               (*prcm)->cm_ivahd_clkstctrl,
-               (*prcm)->cm_dsp_clkstctrl,
-               (*prcm)->cm_dss_clkstctrl,
-               (*prcm)->cm_sgx_clkstctrl,
-               (*prcm)->cm1_abe_clkstctrl,
-               (*prcm)->cm_c2c_clkstctrl,
-               (*prcm)->cm_cam_clkstctrl,
-               (*prcm)->cm_dss_clkstctrl,
-               (*prcm)->cm_sdma_clkstctrl,
-               0
-       };
-
-       u32 const clk_modules_hw_auto_non_essential[] = {
-               (*prcm)->cm_l3instr_l3_3_clkctrl,
-               (*prcm)->cm_l3instr_l3_instr_clkctrl,
-               (*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
-               (*prcm)->cm_l3init_hsi_clkctrl,
-               0
-       };
-
-       u32 const clk_modules_explicit_en_non_essential[] = {
-               (*prcm)->cm1_abe_aess_clkctrl,
-               (*prcm)->cm1_abe_pdm_clkctrl,
-               (*prcm)->cm1_abe_dmic_clkctrl,
-               (*prcm)->cm1_abe_mcasp_clkctrl,
-               (*prcm)->cm1_abe_mcbsp1_clkctrl,
-               (*prcm)->cm1_abe_mcbsp2_clkctrl,
-               (*prcm)->cm1_abe_mcbsp3_clkctrl,
-               (*prcm)->cm1_abe_slimbus_clkctrl,
-               (*prcm)->cm1_abe_timer5_clkctrl,
-               (*prcm)->cm1_abe_timer6_clkctrl,
-               (*prcm)->cm1_abe_timer7_clkctrl,
-               (*prcm)->cm1_abe_timer8_clkctrl,
-               (*prcm)->cm1_abe_wdt3_clkctrl,
-               (*prcm)->cm_l4per_gptimer9_clkctrl,
-               (*prcm)->cm_l4per_gptimer10_clkctrl,
-               (*prcm)->cm_l4per_gptimer11_clkctrl,
-               (*prcm)->cm_l4per_gptimer3_clkctrl,
-               (*prcm)->cm_l4per_gptimer4_clkctrl,
-               (*prcm)->cm_l4per_hdq1w_clkctrl,
-               (*prcm)->cm_l4per_mcbsp4_clkctrl,
-               (*prcm)->cm_l4per_mcspi2_clkctrl,
-               (*prcm)->cm_l4per_mcspi3_clkctrl,
-               (*prcm)->cm_l4per_mcspi4_clkctrl,
-               (*prcm)->cm_l4per_mmcsd3_clkctrl,
-               (*prcm)->cm_l4per_mmcsd4_clkctrl,
-               (*prcm)->cm_l4per_mmcsd5_clkctrl,
-               (*prcm)->cm_l4per_uart1_clkctrl,
-               (*prcm)->cm_l4per_uart2_clkctrl,
-               (*prcm)->cm_l4per_uart4_clkctrl,
-               (*prcm)->cm_wkup_keyboard_clkctrl,
-               (*prcm)->cm_wkup_wdtimer2_clkctrl,
-               (*prcm)->cm_cam_iss_clkctrl,
-               (*prcm)->cm_cam_fdif_clkctrl,
-               (*prcm)->cm_dss_dss_clkctrl,
-               (*prcm)->cm_sgx_sgx_clkctrl,
-               0
-       };
-
-       /* Enable optional functional clock for ISS */
-       setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
-
-       /* Enable all optional functional clocks of DSS */
-       setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
-
-       do_enable_clocks(clk_domains_non_essential,
-                        clk_modules_hw_auto_non_essential,
-                        clk_modules_explicit_en_non_essential,
-                        0);
-
-       /* Put camera module in no sleep mode */
-       clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
-                       MODULE_CLKCTRL_MODULEMODE_MASK,
-                       CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
-                       MODULE_CLKCTRL_MODULEMODE_SHIFT);
-}
-
 void hw_data_init(void)
 {
        u32 omap_rev = omap_revision();

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 5268a1f..32998aa 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -486,94 +486,6 @@ void enable_basic_uboot_clocks(void)
                         1);
 }
 
-/*
- * Enable non-essential clock domains, modules and
- * do some additional special settings needed
- */
-void enable_non_essential_clocks(void)
-{
-       u32 const clk_domains_non_essential[] = {
-               (*prcm)->cm_mpu_m3_clkstctrl,
-               (*prcm)->cm_ivahd_clkstctrl,
-               (*prcm)->cm_dsp_clkstctrl,
-               (*prcm)->cm_dss_clkstctrl,
-               (*prcm)->cm_sgx_clkstctrl,
-               (*prcm)->cm1_abe_clkstctrl,
-               (*prcm)->cm_c2c_clkstctrl,
-               (*prcm)->cm_cam_clkstctrl,
-               (*prcm)->cm_dss_clkstctrl,
-               (*prcm)->cm_sdma_clkstctrl,
-               0
-       };
-
-       u32 const clk_modules_hw_auto_non_essential[] = {
-               (*prcm)->cm_mpu_m3_mpu_m3_clkctrl,
-               (*prcm)->cm_ivahd_ivahd_clkctrl,
-               (*prcm)->cm_ivahd_sl2_clkctrl,
-               (*prcm)->cm_dsp_dsp_clkctrl,
-               (*prcm)->cm_l3instr_l3_3_clkctrl,
-               (*prcm)->cm_l3instr_l3_instr_clkctrl,
-               (*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
-               (*prcm)->cm_l3init_hsi_clkctrl,
-               (*prcm)->cm_l4per_hdq1w_clkctrl,
-               0
-       };
-
-       u32 const clk_modules_explicit_en_non_essential[] = {
-               (*prcm)->cm1_abe_aess_clkctrl,
-               (*prcm)->cm1_abe_pdm_clkctrl,
-               (*prcm)->cm1_abe_dmic_clkctrl,
-               (*prcm)->cm1_abe_mcasp_clkctrl,
-               (*prcm)->cm1_abe_mcbsp1_clkctrl,
-               (*prcm)->cm1_abe_mcbsp2_clkctrl,
-               (*prcm)->cm1_abe_mcbsp3_clkctrl,
-               (*prcm)->cm1_abe_slimbus_clkctrl,
-               (*prcm)->cm1_abe_timer5_clkctrl,
-               (*prcm)->cm1_abe_timer6_clkctrl,
-               (*prcm)->cm1_abe_timer7_clkctrl,
-               (*prcm)->cm1_abe_timer8_clkctrl,
-               (*prcm)->cm1_abe_wdt3_clkctrl,
-               (*prcm)->cm_l4per_gptimer9_clkctrl,
-               (*prcm)->cm_l4per_gptimer10_clkctrl,
-               (*prcm)->cm_l4per_gptimer11_clkctrl,
-               (*prcm)->cm_l4per_gptimer3_clkctrl,
-               (*prcm)->cm_l4per_gptimer4_clkctrl,
-               (*prcm)->cm_l4per_mcspi2_clkctrl,
-               (*prcm)->cm_l4per_mcspi3_clkctrl,
-               (*prcm)->cm_l4per_mcspi4_clkctrl,
-               (*prcm)->cm_l4per_mmcsd3_clkctrl,
-               (*prcm)->cm_l4per_mmcsd4_clkctrl,
-               (*prcm)->cm_l4per_mmcsd5_clkctrl,
-               (*prcm)->cm_l4per_uart1_clkctrl,
-               (*prcm)->cm_l4per_uart2_clkctrl,
-               (*prcm)->cm_l4per_uart4_clkctrl,
-               (*prcm)->cm_wkup_keyboard_clkctrl,
-               (*prcm)->cm_wkup_wdtimer2_clkctrl,
-               (*prcm)->cm_cam_iss_clkctrl,
-               (*prcm)->cm_cam_fdif_clkctrl,
-               (*prcm)->cm_dss_dss_clkctrl,
-               (*prcm)->cm_sgx_sgx_clkctrl,
-               0
-       };
-
-       /* Enable optional functional clock for ISS */
-       setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
-
-       /* Enable all optional functional clocks of DSS */
-       setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
-
-       do_enable_clocks(clk_domains_non_essential,
-                        clk_modules_hw_auto_non_essential,
-                        clk_modules_explicit_en_non_essential,
-                        0);
-
-       /* Put camera module in no sleep mode */
-       clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
-                       MODULE_CLKCTRL_MODULEMODE_MASK,
-                       CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
-                       MODULE_CLKCTRL_MODULEMODE_SHIFT);
-}
-
 const struct ctrl_ioregs ioregs_omap5430 = {
        .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
        .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,

diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index a78f990..4efc89e 100644 (file)
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -567,7 +567,6 @@ u32 omap_ddr_clk(void);
 u32 get_sys_clk_index(void);
 void enable_basic_clocks(void);
 void enable_basic_uboot_clocks(void);
-void enable_non_essential_clocks(void);
 void scale_vcores(struct vcores_data const *);
 u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
 void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);