* m10300-opc.c: DSP instrutions which only write to one general

        register have no restrictions on matching operands.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index cfc56c5..2f0de06 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,7 +1,12 @@
+start-sanitize-am33
 Mon Oct 12 10:43:51 1998  Jeffrey A Law  (law@cygnus.com)
 
+        * m10300-opc.c: DSP instrutions which only write to one general
+        register have no restrictions on matching operands.
+
        * m10300-opc.c (lsr_add): Fix typo for "lsr_add imm,reg,reg,reg" case.
 
+end-sanitize-am33
 Fri Oct  9 14:01:56 1998  Doug Evans  <devans@seba.cygnus.com>
 
        * m32r-opc.h,m32r-opc.c: Regenerate.

diff --git a/opcodes/m10300-opc.c b/opcodes/m10300-opc.c
index b8c8c62..bb385b8 100644 (file)
--- a/opcodes/m10300-opc.c
+++ b/opcodes/m10300-opc.c
@@ -1214,10 +1214,10 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "add_sub",   0xf7300000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
 { "add_sub",   0xf7240000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
 { "add_sub",   0xf7340000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, SIMM4_2, RN0}},
-{ "add_cmp",   0xf7400000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
-{ "add_cmp",   0xf7500000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
-{ "add_cmp",   0xf7440000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
-{ "add_cmp",   0xf7540000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, SIMM4_2, RN0}},
+{ "add_cmp",   0xf7400000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
+{ "add_cmp",   0xf7500000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
+{ "add_cmp",   0xf7440000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
+{ "add_cmp",   0xf7540000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, SIMM4_2, RN0}},
 { "add_mov",   0xf7600000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
 { "add_mov",   0xf7700000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
 { "add_mov",   0xf7640000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
@@ -1234,30 +1234,30 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "add_asl",   0xf7d00000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
 { "add_asl",   0xf7c40000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
 { "add_asl",   0xf7d40000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, IMM4_2, RN0}},
-{ "cmp_add",   0xf7010000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
-{ "cmp_add",   0xf7110000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
-{ "cmp_add",   0xf7050000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
-{ "cmp_add",   0xf7150000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, SIMM4_2, RN0}},
-{ "cmp_sub",   0xf7210000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
-{ "cmp_sub",   0xf7310000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
-{ "cmp_sub",   0xf7250000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
-{ "cmp_sub",   0xf7350000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, SIMM4_2, RN0}},
-{ "cmp_mov",   0xf7610000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
-{ "cmp_mov",   0xf7710000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
-{ "cmp_mov",   0xf7650000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
-{ "cmp_mov",   0xf7750000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, SIMM4_2, RN0}},
-{ "cmp_asr",   0xf7810000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
-{ "cmp_asr",   0xf7910000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
-{ "cmp_asr",   0xf7850000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
-{ "cmp_asr",   0xf7950000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, IMM4_2, RN0}},
-{ "cmp_lsr",   0xf7a10000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
-{ "cmp_lsr",   0xf7b10000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
-{ "cmp_lsr",   0xf7a50000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
-{ "cmp_lsr",   0xf7b50000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, IMM4_2, RN0}},
-{ "cmp_asl",   0xf7c10000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
-{ "cmp_asl",   0xf7d10000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
-{ "cmp_asl",   0xf7c50000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
-{ "cmp_asl",   0xf7d50000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, IMM4_2, RN0}},
+{ "cmp_add",   0xf7010000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
+{ "cmp_add",   0xf7110000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
+{ "cmp_add",   0xf7050000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
+{ "cmp_add",   0xf7150000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, SIMM4_2, RN0}},
+{ "cmp_sub",   0xf7210000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
+{ "cmp_sub",   0xf7310000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
+{ "cmp_sub",   0xf7250000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
+{ "cmp_sub",   0xf7350000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, SIMM4_2, RN0}},
+{ "cmp_mov",   0xf7610000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
+{ "cmp_mov",   0xf7710000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
+{ "cmp_mov",   0xf7650000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
+{ "cmp_mov",   0xf7750000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, SIMM4_2, RN0}},
+{ "cmp_asr",   0xf7810000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
+{ "cmp_asr",   0xf7910000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
+{ "cmp_asr",   0xf7850000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
+{ "cmp_asr",   0xf7950000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, IMM4_2, RN0}},
+{ "cmp_lsr",   0xf7a10000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
+{ "cmp_lsr",   0xf7b10000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
+{ "cmp_lsr",   0xf7a50000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
+{ "cmp_lsr",   0xf7b50000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, IMM4_2, RN0}},
+{ "cmp_asl",   0xf7c10000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
+{ "cmp_asl",   0xf7d10000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
+{ "cmp_asl",   0xf7c50000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
+{ "cmp_asl",   0xf7d50000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, IMM4_2, RN0}},
 { "sub_add",   0xf7020000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
 { "sub_add",   0xf7120000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
 { "sub_add",   0xf7060000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
@@ -1266,10 +1266,10 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "sub_sub",   0xf7320000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
 { "sub_sub",   0xf7260000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
 { "sub_sub",   0xf7360000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, SIMM4_2, RN0}},
-{ "sub_cmp",   0xf7420000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
-{ "sub_cmp",   0xf7520000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
-{ "sub_cmp",   0xf7460000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
-{ "sub_cmp",   0xf7560000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, SIMM4_2, RN0}},
+{ "sub_cmp",   0xf7420000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
+{ "sub_cmp",   0xf7520000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
+{ "sub_cmp",   0xf7460000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
+{ "sub_cmp",   0xf7560000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, SIMM4_2, RN0}},
 { "sub_mov",   0xf7620000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
 { "sub_mov",   0xf7720000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
 { "sub_mov",   0xf7660000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
@@ -1294,10 +1294,10 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "mov_sub",   0xf7330000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
 { "mov_sub",   0xf7270000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
 { "mov_sub",   0xf7370000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, SIMM4_2, RN0}},
-{ "mov_cmp",   0xf7430000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
-{ "mov_cmp",   0xf7530000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
-{ "mov_cmp",   0xf7470000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
-{ "mov_cmp",   0xf7570000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, SIMM4_2, RN0}},
+{ "mov_cmp",   0xf7430000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
+{ "mov_cmp",   0xf7530000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
+{ "mov_cmp",   0xf7470000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
+{ "mov_cmp",   0xf7570000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, SIMM4_2, RN0}},
 { "mov_mov",   0xf7630000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
 { "mov_mov",   0xf7730000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
 { "mov_mov",   0xf7670000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
@@ -1318,8 +1318,8 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "and_add",   0xf7180000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
 { "and_sub",   0xf7280000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
 { "and_sub",   0xf7380000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
-{ "and_cmp",   0xf7480000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
-{ "and_cmp",   0xf7580000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
+{ "and_cmp",   0xf7480000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
+{ "and_cmp",   0xf7580000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
 { "and_mov",   0xf7680000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
 { "and_mov",   0xf7780000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
 { "and_asr",   0xf7880000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
@@ -1328,26 +1328,26 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "and_lsr",   0xf7b80000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
 { "and_asl",   0xf7c80000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
 { "and_asl",   0xf7d80000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
-{ "dmach_add", 0xf7090000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
-{ "dmach_add", 0xf7190000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
-{ "dmach_sub", 0xf7290000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
-{ "dmach_sub", 0xf7390000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
-{ "dmach_cmp", 0xf7490000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
-{ "dmach_cmp", 0xf7590000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
-{ "dmach_mov", 0xf7690000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
-{ "dmach_mov", 0xf7790000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
-{ "dmach_asr", 0xf7890000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
-{ "dmach_asr", 0xf7990000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
-{ "dmach_lsr", 0xf7a90000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
-{ "dmach_lsr", 0xf7b90000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
-{ "dmach_asl", 0xf7c90000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
-{ "dmach_asl", 0xf7d90000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
+{ "dmach_add", 0xf7090000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
+{ "dmach_add", 0xf7190000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
+{ "dmach_sub", 0xf7290000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
+{ "dmach_sub", 0xf7390000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
+{ "dmach_cmp", 0xf7490000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
+{ "dmach_cmp", 0xf7590000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
+{ "dmach_mov", 0xf7690000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
+{ "dmach_mov", 0xf7790000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
+{ "dmach_asr", 0xf7890000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
+{ "dmach_asr", 0xf7990000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
+{ "dmach_lsr", 0xf7a90000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
+{ "dmach_lsr", 0xf7b90000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
+{ "dmach_asl", 0xf7c90000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
+{ "dmach_asl", 0xf7d90000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
 { "xor_add",   0xf70a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
 { "xor_add",   0xf71a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
 { "xor_sub",   0xf72a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
 { "xor_sub",   0xf73a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
-{ "xor_cmp",   0xf74a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
-{ "xor_cmp",   0xf75a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
+{ "xor_cmp",   0xf74a0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
+{ "xor_cmp",   0xf75a0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
 { "xor_mov",   0xf76a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
 { "xor_mov",   0xf77a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
 { "xor_asr",   0xf78a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
@@ -1360,8 +1360,8 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "swhw_add",  0xf71b0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
 { "swhw_sub",  0xf72b0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
 { "swhw_sub",  0xf73b0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
-{ "swhw_cmp",  0xf74b0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
-{ "swhw_cmp",  0xf75b0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
+{ "swhw_cmp",  0xf74b0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
+{ "swhw_cmp",  0xf75b0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
 { "swhw_mov",  0xf76b0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
 { "swhw_mov",  0xf77b0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
 { "swhw_asr",  0xf78b0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
@@ -1374,8 +1374,8 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "or_add",    0xf71c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
 { "or_sub",    0xf72c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
 { "or_sub",    0xf73c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
-{ "or_cmp",    0xf74c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
-{ "or_cmp",    0xf75c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
+{ "or_cmp",    0xf74c0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
+{ "or_cmp",    0xf75c0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
 { "or_mov",    0xf76c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
 { "or_mov",    0xf77c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
 { "or_asr",    0xf78c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
@@ -1388,8 +1388,8 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "sat16_add", 0xf71d0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
 { "sat16_sub", 0xf72d0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
 { "sat16_sub", 0xf73d0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
-{ "sat16_cmp", 0xf74d0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
-{ "sat16_cmp", 0xf75d0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
+{ "sat16_cmp", 0xf74d0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
+{ "sat16_cmp", 0xf75d0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
 { "sat16_mov", 0xf76d0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
 { "sat16_mov", 0xf77d0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
 { "sat16_asr", 0xf78d0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
@@ -1401,8 +1401,8 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 /* Ugh.  Synthetic instructions.  */
 { "add_and",   0xf7080000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
 { "add_and",   0xf7180000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
-{ "add_dmach", 0xf7090000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
-{ "add_dmach", 0xf7190000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
+{ "add_dmach", 0xf7090000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
+{ "add_dmach", 0xf7190000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
 { "add_or",    0xf70c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
 { "add_or",    0xf71c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
 { "add_sat16", 0xf70d0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
@@ -1417,12 +1417,12 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "asl_add",   0xf7d40000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, SIMM4_6, RN4}},
 { "asl_and",   0xf7c80000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
 { "asl_and",   0xf7d80000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
-{ "asl_cmp",   0xf7c10000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
-{ "asl_cmp",   0xf7d10000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4, }},
-{ "asl_cmp",   0xf7c50000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, SIMM4_6, RN4}},
-{ "asl_cmp",   0xf7d50000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, SIMM4_6, RN4}},
-{ "asl_dmach", 0xf7c90000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
-{ "asl_dmach", 0xf7d90000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
+{ "asl_cmp",   0xf7c10000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
+{ "asl_cmp",   0xf7d10000,  0xffff0000,  0x0,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4, }},
+{ "asl_cmp",   0xf7c50000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, SIMM4_6, RN4}},
+{ "asl_cmp",   0xf7d50000,  0xffff0000,  0x0,  FMT_D10, AM33,   {IMM4_2, RN0, SIMM4_6, RN4}},
+{ "asl_dmach", 0xf7c90000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
+{ "asl_dmach", 0xf7d90000,  0xffff0000,  0x0,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
 { "asl_mov",   0xf7c30000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
 { "asl_mov",   0xf7d30000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
 { "asl_mov",   0xf7c70000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, SIMM4_6, RN4}},
@@ -1445,12 +1445,12 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "asr_add",   0xf7940000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, SIMM4_6, RN4}},
 { "asr_and",   0xf7880000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
 { "asr_and",   0xf7980000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
-{ "asr_cmp",   0xf7810000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
-{ "asr_cmp",   0xf7910000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4, }},
-{ "asr_cmp",   0xf7850000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, SIMM4_6, RN4}},
-{ "asr_cmp",   0xf7950000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, SIMM4_6, RN4}},
-{ "asr_dmach", 0xf7890000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
-{ "asr_dmach", 0xf7990000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
+{ "asr_cmp",   0xf7810000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
+{ "asr_cmp",   0xf7910000,  0xffff0000,  0x0,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4, }},
+{ "asr_cmp",   0xf7850000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, SIMM4_6, RN4}},
+{ "asr_cmp",   0xf7950000,  0xffff0000,  0x0,  FMT_D10, AM33,   {IMM4_2, RN0, SIMM4_6, RN4}},
+{ "asr_dmach", 0xf7890000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
+{ "asr_dmach", 0xf7990000,  0xffff0000,  0x0,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
 { "asr_mov",   0xf7830000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
 { "asr_mov",   0xf7930000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
 { "asr_mov",   0xf7870000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, SIMM4_6, RN4}},
@@ -1467,30 +1467,30 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "asr_swhw",  0xf79b0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
 { "asr_xor",   0xf78a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
 { "asr_xor",   0xf79a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
-{ "cmp_and",   0xf7480000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
-{ "cmp_and",   0xf7580000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
-{ "cmp_dmach", 0xf7490000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
-{ "cmp_dmach", 0xf7590000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
-{ "cmp_or",    0xf74c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
-{ "cmp_or",    0xf75c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
-{ "cmp_sat16", 0xf74d0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
-{ "cmp_sat16", 0xf75d0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
-{ "cmp_swhw",  0xf74b0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
-{ "cmp_swhw",  0xf75b0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
-{ "cmp_xor",   0xf74a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
-{ "cmp_xor",   0xf75a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
+{ "cmp_and",   0xf7480000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
+{ "cmp_and",   0xf7580000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
+{ "cmp_dmach", 0xf7490000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
+{ "cmp_dmach", 0xf7590000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
+{ "cmp_or",    0xf74c0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
+{ "cmp_or",    0xf75c0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
+{ "cmp_sat16", 0xf74d0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
+{ "cmp_sat16", 0xf75d0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
+{ "cmp_swhw",  0xf74b0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
+{ "cmp_swhw",  0xf75b0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
+{ "cmp_xor",   0xf74a0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
+{ "cmp_xor",   0xf75a0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
 { "lsr_add",   0xf7a00000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
 { "lsr_add",   0xf7b00000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
 { "lsr_add",   0xf7a40000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, SIMM4_6, RN4}},
 { "lsr_add",   0xf7b40000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, SIMM4_6, RN4}},
 { "lsr_and",   0xf7a80000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
 { "lsr_and",   0xf7b80000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
-{ "lsr_cmp",   0xf7a10000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
-{ "lsr_cmp",   0xf7b10000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4, }},
-{ "lsr_cmp",   0xf7a50000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, SIMM4_6, RN4}},
-{ "lsr_cmp",   0xf7b50000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, SIMM4_6, RN4}},
-{ "lsr_dmach", 0xf7a90000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
-{ "lsr_dmach", 0xf7b90000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
+{ "lsr_cmp",   0xf7a10000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
+{ "lsr_cmp",   0xf7b10000,  0xffff0000,  0x0,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4, }},
+{ "lsr_cmp",   0xf7a50000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, SIMM4_6, RN4}},
+{ "lsr_cmp",   0xf7b50000,  0xffff0000,  0x0,  FMT_D10, AM33,   {IMM4_2, RN0, SIMM4_6, RN4}},
+{ "lsr_dmach", 0xf7a90000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
+{ "lsr_dmach", 0xf7b90000,  0xffff0000,  0x0,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
 { "lsr_mov",   0xf7a30000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
 { "lsr_mov",   0xf7b30000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
 { "lsr_mov",   0xf7a70000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, SIMM4_6, RN4}},
@@ -1509,8 +1509,8 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "lsr_xor",   0xf7ba0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
 { "mov_and",   0xf7680000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
 { "mov_and",   0xf7780000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
-{ "mov_dmach", 0xf7690000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
-{ "mov_dmach", 0xf7790000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
+{ "mov_dmach", 0xf7690000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
+{ "mov_dmach", 0xf7790000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
 { "mov_or",    0xf76c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
 { "mov_or",    0xf77c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
 { "mov_sat16", 0xf76d0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
@@ -1521,8 +1521,8 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "mov_xor",   0xf77a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
 { "sub_and",   0xf7280000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
 { "sub_and",   0xf7380000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
-{ "sub_dmach", 0xf7290000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
-{ "sub_dmach", 0xf7390000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
+{ "sub_dmach", 0xf7290000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
+{ "sub_dmach", 0xf7390000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
 { "sub_or",    0xf72c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
 { "sub_or",    0xf73c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
 { "sub_sat16", 0xf72d0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},