2012-11-30 Oleg Raikhman <oleg@adapteva.com>

            Joern Rennecke  <joern.rennecke@embecosm.com>

cpu:
        * epiphany.cpu (keyword gr-names): Move sb/sl/ip after r9/r10/r12.
        (load_insn): Add NO-DIS attribute to x, p, d, dpm, dl0, dl0.l.
        (testset-insn): Add NO_DIS attribute to t.l.
        (store-insn): Add NO-DIS attribute to x.l, p.l, d.l, dpm.l, dl0.l.
        (move-insns): Add NO-DIS attribute to cmov.l.
        (op-mmr-movts): Add NO-DIS attribute to movts.l.
        (op-mmr-movfs): Add NO-DIS attribute to movfs.l.
        (op-rrr): Add NO-DIS attribute to .l.
        (shift-rrr): Add NO-DIS attribute to .l.
        (op-shift-rri): Add NO-DIS attribute to i32.l.
        (bitrl, movtl): Add NO-DIS attribute.
        (op-iextrrr): Add NO-DIS attribute to .l
        (op-two_operands-float, op-fabs-float): Add NO-DIS attribute to f32.l.
        (op-fix2float-float, op-float2fix-float, op-fextop-float): Likewise.

opcodes:
        * epiphany-desc.c, epiphany-desc.h, epiphany-opc.c: Regenerate.

diff --git a/cpu/ChangeLog b/cpu/ChangeLog
index bd82d13..1dbf760 100644 (file)
--- a/cpu/ChangeLog
+++ b/cpu/ChangeLog
@@ -1,3 +1,21 @@
+2012-11-30  Oleg Raikhman  <oleg@adapteva.com>
+           Joern Rennecke  <joern.rennecke@embecosm.com>
+
+       * epiphany.cpu (keyword gr-names): Move sb/sl/ip after r9/r10/r12.
+       (load_insn): Add NO-DIS attribute to x, p, d, dpm, dl0, dl0.l.
+       (testset-insn): Add NO_DIS attribute to t.l.
+       (store-insn): Add NO-DIS attribute to x.l, p.l, d.l, dpm.l, dl0.l.
+       (move-insns): Add NO-DIS attribute to cmov.l.
+       (op-mmr-movts): Add NO-DIS attribute to movts.l.
+       (op-mmr-movfs): Add NO-DIS attribute to movfs.l.
+       (op-rrr): Add NO-DIS attribute to .l.
+       (shift-rrr): Add NO-DIS attribute to .l.
+       (op-shift-rri): Add NO-DIS attribute to i32.l.
+       (bitrl, movtl): Add NO-DIS attribute.
+       (op-iextrrr): Add NO-DIS attribute to .l
+       (op-two_operands-float, op-fabs-float): Add NO-DIS attribute to f32.l.
+       (op-fix2float-float, op-float2fix-float, op-fextop-float): Likewise.
+
 2012-02-27  Alan Modra  <amodra@gmail.com>
 
        * mt.opc (print_dollarhex): Trim values to 32 bits.

diff --git a/cpu/epiphany.cpu b/cpu/epiphany.cpu
index a11011b..33c81d0 100644 (file)
--- a/cpu/epiphany.cpu
+++ b/cpu/epiphany.cpu
@@ -352,7 +352,7 @@
   (prefix "")
   (values
 ; some preferred aliases
-   (sb 9) (sl 10) (fp 11) (ip 12) (sp 13) (lr 14)
+   (fp 11) (sp 13) (lr 14)
 ; the default register names
    (r0  0)  (r1  1)  (r2  2)  (r3  3)  (r4  4)  (r5  5)  (r6  6)  (r7  7)
    (r8  8)  (r9  9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15)
@@ -365,6 +365,7 @@
 ; some less popular aliases
    (a1  0) (a2  1) (a3  2) (a4  3) (v1  4) (v2  5) (v3  6) (v4  7)
    (v5  8) (v6  9) (v7 10) (v8 11)
+   (sb 9) (sl 10) (ip 12)
    )
   )
 
@@ -1428,7 +1429,7 @@
 
     (dnmi (.sym name "x")
          (.str "load " mode " indexed")
-         ()
+         (NO-DIS)
          (.str name ".l $rd6,[$rn6,$direction$rm6]")
          (emit  (.sym name "x.l") rd6 rn6 direction rm6)
          )
@@ -1453,7 +1454,7 @@
 
     (dnmi (.sym name "p")
          (.str "load " mode " postmodify")
-         ()
+         (NO-DIS)
          (.str name ".l $rd6,[$rn6],$direction$rm6")
          (emit  (.sym name "p.l") rd6 rn6 direction rm6)
          )
@@ -1494,7 +1495,7 @@
 
     (dnmi (.sym name "d")
          (.str "load " mode " displacement")
-         ()
+         (NO-DIS)
          (.str name ".l $rd6,[$rn6,$dpmi$disp11]")
          (emit  (.sym name "d.l") rd6 rn6  dpmi disp11)
          )
@@ -1519,7 +1520,7 @@
 
     (dnmi (.sym name "dpm")
          (.str "load " mode " displacement post-modify")
-         ()
+         (NO-DIS)
          (.str name ".l $rd6,[$rn6],$dpmi$disp11")
          (emit  (.sym name "dpm.l") rd6 rn6  dpmi disp11)
          )
@@ -1532,12 +1533,12 @@
          (emit (.sym name "d16.s") rd rn (disp3 0))
          )
     (dnmi (.sym name "dl0") "load with 0 disp"
-         ()
+         (NO-DIS)
          (.str name " $rd6,[$rn6]")
          (emit (.sym name "d.l") rd6 rn6 (dpmi 0) (disp11 0))
          )
     (dnmi (.sym name "dl0.l") "load with 0 disp"
-         ()
+         (NO-DIS)
          (.str name ".l $rd6,[$rn6]")
          (emit (.sym name "d.l") rd6 rn6 (dpmi 0) (disp11 0))
          )
@@ -1594,7 +1595,7 @@
 
     (dnmi  (.sym name "t.l")
           (.str "testset " mode ".l indexed")
-          ()
+          (NO-DIS)
           (.str name ".l $rd6,[$rn6,$direction$rm6]")
           (emit (.sym name "t") rd6 rn6 direction rm6)
           )
@@ -1640,7 +1641,7 @@
 
     (dnmi (.sym name "x.l")
          (.str "store" mode " indexed")
-         ()
+         (NO-DIS)
          (.str name ".l $rd6,[$rn6,$direction$rm6]")
          (emit  (.sym name "x")  rd6 rn6 direction rm6)
          )
@@ -1676,7 +1677,7 @@
                 )
     (dnmi (.sym name "p.l")
          (.str "store " mode " postmodify")
-         ()
+         (NO-DIS)
          (.str name ".l $rd6,[$rn6],$direction$rm6")
          (emit (.sym name "p") rd6 rn6 direction rm6)
          )
@@ -1714,7 +1715,7 @@
 
     (dnmi (.sym name "d.l")
          (.str "store " mode " displacement")
-         ()
+         (NO-DIS)
          (.str name ".l $rd6,[$rn6,$dpmi$disp11]")
          (emit (.sym name "d") rd6 rn6 dpmi disp11)
          )
@@ -1737,7 +1738,7 @@
                 )
     (dnmi (.sym name "dpm.l")
          (.str "store " mode " displacement post-modify")
-         ()
+         (NO-DIS)
          (.str name ".l $rd6,[$rn6],$dpmi$disp11")
          (emit (.sym name "dpm") rd6 rn6 dpmi disp11)
          )
@@ -1756,7 +1757,7 @@
          )
 
     (dnmi (.sym name "dl0.l")  "store w 0 disp"
-         ()
+         (NO-DIS)
          (.str name ".l $rd6,[$rn6]")
          (emit (.sym name "d") rd6 rn6 (dpmi 0) (disp11 0))
          )
@@ -1798,7 +1799,7 @@
                 )
     (dnmi (.sym "cmov.l" cond)
          (.str "move register " cond)
-         ()
+         (NO-DIS)
          (.str "mov" name ".l $rd6,$rn6")
          (emit (.sym "cmov" cond) rd6 rn6)
          )
@@ -1859,7 +1860,7 @@
 
     (dnmi (.sym "movts.l" name)
          (.str "move to " name)
-         ()
+         (NO-DIS)
          (.str "movts.l $" sdreg ",$rd6")
          (emit (.sym "movts" name) sdreg rd6)
          )
@@ -1903,7 +1904,7 @@
 
     (dnmi (.sym "movfs.l" name)
          (.str "move from " name)
-         ()
+         (NO-DIS)
          (.str "movfs.l $rd6,$" snreg)
          (emit (.sym "movfs" name) rd6 snreg)
          )
@@ -2165,7 +2166,7 @@
 
     (dnmi (.sym name ".l")
          (.str name)
-         ()
+         (NO-DIS)
          (.str name ".l $rd6,$rn6,$rm6")
          (emit (.sym name) rd6 rn6 rm6)
          )
@@ -2307,7 +2308,7 @@
 
     (dnmi (.sym name ".l")
          (.str name)
-         ()
+         (NO-DIS)
          (.str name ".l $rd6,$rn6,$rm6")
          (emit (.sym name) rd6 rn6 rm6)
          )
@@ -2349,7 +2350,7 @@
 
     (dnmi (.sym name "i32.l")
          (.str name)
-         ()
+         (NO-DIS)
          (.str name ".l $rd6,$rn6,$shift")
          (emit (.sym name "i32") rd6  rn6 shift)
          )
@@ -2411,7 +2412,7 @@
             ()
             )
 (dnmi bitrl "bit reverse l"
-      ()
+      (NO-DIS)
       ("bitr.l $rd6,$rn6")
       (emit bitr rd6 rn6)
       )
@@ -2441,7 +2442,7 @@
 
     (dnmi (.sym name ".l")
          (.str name)
-         ()
+         (NO-DIS)
          (.str name ".l $rd6,$rn6,$rm6")
          (emit (.sym name) rd6  rn6 rm6)
          )
@@ -2496,7 +2497,7 @@
             )
 (dnmi movtl
       "movt imm16"
-      ()
+      (NO-DIS)
       "movt.l $rd6,$imm16"
       (emit movt rd6 imm16)
       )
@@ -2581,7 +2582,7 @@
 
            (if (or (and invExcEnbit bisbit)
                    (or (and ovfExcEnbit bvsbit) (and unExcEnbit busbit)))
-               (sequence ()    
+               (sequence ()
                  (set expcause0bit (const 1))
                  (set expcause1bit (const 1))
                  (call-exception #x4 #x2)))
@@ -2602,7 +2603,7 @@
 
     (dnmi (.sym "f_" name "f32.l")
          (.str "f_" name)
-         ()
+         (NO-DIS)
          (.str "f" name ".l $rd6,$rn6,$rm6")
          (emit  (.sym "f_" name "f32") rd6  rn6 rm6)
          )
@@ -2686,7 +2687,7 @@
 
     (dnmi  (.sym "f_" name "f32.l")
           (.str "f_" name)
-          ()
+          (NO-DIS)
           (.str "f" name ".l $rd6,$rn6")
           (emit (.sym "f_" name "f32") rd6  rn6)
           )
@@ -2746,7 +2747,7 @@
 
     (dnmi (.sym "f_" name "f32.l")
          (.str "f_" name)
-         ()
+         (NO-DIS)
          (.str "f" name ".l $rd6,$rn6")
          (emit (.sym "f_" name "f32")  rd6 rn6)
          )
@@ -2830,7 +2831,7 @@
 
     (dnmi (.sym "f_" name "f32.l")
          (.str "f_" name)
-         ()
+         (NO-DIS)
          (.str "f" name ".l $rd6,$rn6")
          (emit (.sym "f_" name "f32") rd6  rn6)
          )
@@ -2919,7 +2920,7 @@
 
     (dnmi (.sym "f_" name "f32.l")
          (.str "f_" name)
-         ()
+         (NO-DIS)
          (.str "f" name ".l $frd6,$frn6")
          (emit (.sym "f_" name "f32") frd6 frn6)
          )

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index db35dba..05a092c 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2012-11-30  Oleg Raikhman  <oleg@adapteva.com>
+           Joern Rennecke  <joern.rennecke@embecosm.com>
+
+       * epiphany-desc.c, epiphany-desc.h, epiphany-opc.c: Regenerate.
+
 2012-11-29  Roland McGrath  <mcgrathr@google.com>
 
        * s390-mkopc.c (file_header): Add const.

diff --git a/opcodes/epiphany-desc.c b/opcodes/epiphany-desc.c
index 271f8a7..973b214 100644 (file)
--- a/opcodes/epiphany-desc.c
+++ b/opcodes/epiphany-desc.c
@@ -131,10 +131,7 @@ static const CGEN_MACH epiphany_cgen_mach_table[] = {
 
 static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_gr_names_entries[] =
 {
-  { "sb", 9, {0, {{{0, 0}}}}, 0, 0 },
-  { "sl", 10, {0, {{{0, 0}}}}, 0, 0 },
   { "fp", 11, {0, {{{0, 0}}}}, 0, 0 },
-  { "ip", 12, {0, {{{0, 0}}}}, 0, 0 },
   { "sp", 13, {0, {{{0, 0}}}}, 0, 0 },
   { "lr", 14, {0, {{{0, 0}}}}, 0, 0 },
   { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
@@ -212,7 +209,10 @@ static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_gr_names_entries[] =
   { "v5", 8, {0, {{{0, 0}}}}, 0, 0 },
   { "v6", 9, {0, {{{0, 0}}}}, 0, 0 },
   { "v7", 10, {0, {{{0, 0}}}}, 0, 0 },
-  { "v8", 11, {0, {{{0, 0}}}}, 0, 0 }
+  { "v8", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "sb", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "sl", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "ip", 12, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD epiphany_cgen_opval_gr_names =

diff --git a/opcodes/epiphany-desc.h b/opcodes/epiphany-desc.h
index 430210e..4aada65 100644 (file)
--- a/opcodes/epiphany-desc.h
+++ b/opcodes/epiphany-desc.h
@@ -124,27 +124,27 @@ typedef enum insn_dc_25_2 {
 
 /* Enum declaration for .  */
 typedef enum gr_names {
-  H_REGISTERS_SB = 9, H_REGISTERS_SL = 10, H_REGISTERS_FP = 11, H_REGISTERS_IP = 12
- , H_REGISTERS_SP = 13, H_REGISTERS_LR = 14, H_REGISTERS_R0 = 0, H_REGISTERS_R1 = 1
- , H_REGISTERS_R2 = 2, H_REGISTERS_R3 = 3, H_REGISTERS_R4 = 4, H_REGISTERS_R5 = 5
- , H_REGISTERS_R6 = 6, H_REGISTERS_R7 = 7, H_REGISTERS_R8 = 8, H_REGISTERS_R9 = 9
- , H_REGISTERS_R10 = 10, H_REGISTERS_R11 = 11, H_REGISTERS_R12 = 12, H_REGISTERS_R13 = 13
- , H_REGISTERS_R14 = 14, H_REGISTERS_R15 = 15, H_REGISTERS_R16 = 16, H_REGISTERS_R17 = 17
- , H_REGISTERS_R18 = 18, H_REGISTERS_R19 = 19, H_REGISTERS_R20 = 20, H_REGISTERS_R21 = 21
- , H_REGISTERS_R22 = 22, H_REGISTERS_R23 = 23, H_REGISTERS_R24 = 24, H_REGISTERS_R25 = 25
- , H_REGISTERS_R26 = 26, H_REGISTERS_R27 = 27, H_REGISTERS_R28 = 28, H_REGISTERS_R29 = 29
- , H_REGISTERS_R30 = 30, H_REGISTERS_R31 = 31, H_REGISTERS_R32 = 32, H_REGISTERS_R33 = 33
- , H_REGISTERS_R34 = 34, H_REGISTERS_R35 = 35, H_REGISTERS_R36 = 36, H_REGISTERS_R37 = 37
- , H_REGISTERS_R38 = 38, H_REGISTERS_R39 = 39, H_REGISTERS_R40 = 40, H_REGISTERS_R41 = 41
- , H_REGISTERS_R42 = 42, H_REGISTERS_R43 = 43, H_REGISTERS_R44 = 44, H_REGISTERS_R45 = 45
- , H_REGISTERS_R46 = 46, H_REGISTERS_R47 = 47, H_REGISTERS_R48 = 48, H_REGISTERS_R49 = 49
- , H_REGISTERS_R50 = 50, H_REGISTERS_R51 = 51, H_REGISTERS_R52 = 52, H_REGISTERS_R53 = 53
- , H_REGISTERS_R54 = 54, H_REGISTERS_R55 = 55, H_REGISTERS_R56 = 56, H_REGISTERS_R57 = 57
- , H_REGISTERS_R58 = 58, H_REGISTERS_R59 = 59, H_REGISTERS_R60 = 60, H_REGISTERS_R61 = 61
- , H_REGISTERS_R62 = 62, H_REGISTERS_R63 = 63, H_REGISTERS_A1 = 0, H_REGISTERS_A2 = 1
- , H_REGISTERS_A3 = 2, H_REGISTERS_A4 = 3, H_REGISTERS_V1 = 4, H_REGISTERS_V2 = 5
- , H_REGISTERS_V3 = 6, H_REGISTERS_V4 = 7, H_REGISTERS_V5 = 8, H_REGISTERS_V6 = 9
- , H_REGISTERS_V7 = 10, H_REGISTERS_V8 = 11
+  H_REGISTERS_FP = 11, H_REGISTERS_SP = 13, H_REGISTERS_LR = 14, H_REGISTERS_R0 = 0
+ , H_REGISTERS_R1 = 1, H_REGISTERS_R2 = 2, H_REGISTERS_R3 = 3, H_REGISTERS_R4 = 4
+ , H_REGISTERS_R5 = 5, H_REGISTERS_R6 = 6, H_REGISTERS_R7 = 7, H_REGISTERS_R8 = 8
+ , H_REGISTERS_R9 = 9, H_REGISTERS_R10 = 10, H_REGISTERS_R11 = 11, H_REGISTERS_R12 = 12
+ , H_REGISTERS_R13 = 13, H_REGISTERS_R14 = 14, H_REGISTERS_R15 = 15, H_REGISTERS_R16 = 16
+ , H_REGISTERS_R17 = 17, H_REGISTERS_R18 = 18, H_REGISTERS_R19 = 19, H_REGISTERS_R20 = 20
+ , H_REGISTERS_R21 = 21, H_REGISTERS_R22 = 22, H_REGISTERS_R23 = 23, H_REGISTERS_R24 = 24
+ , H_REGISTERS_R25 = 25, H_REGISTERS_R26 = 26, H_REGISTERS_R27 = 27, H_REGISTERS_R28 = 28
+ , H_REGISTERS_R29 = 29, H_REGISTERS_R30 = 30, H_REGISTERS_R31 = 31, H_REGISTERS_R32 = 32
+ , H_REGISTERS_R33 = 33, H_REGISTERS_R34 = 34, H_REGISTERS_R35 = 35, H_REGISTERS_R36 = 36
+ , H_REGISTERS_R37 = 37, H_REGISTERS_R38 = 38, H_REGISTERS_R39 = 39, H_REGISTERS_R40 = 40
+ , H_REGISTERS_R41 = 41, H_REGISTERS_R42 = 42, H_REGISTERS_R43 = 43, H_REGISTERS_R44 = 44
+ , H_REGISTERS_R45 = 45, H_REGISTERS_R46 = 46, H_REGISTERS_R47 = 47, H_REGISTERS_R48 = 48
+ , H_REGISTERS_R49 = 49, H_REGISTERS_R50 = 50, H_REGISTERS_R51 = 51, H_REGISTERS_R52 = 52
+ , H_REGISTERS_R53 = 53, H_REGISTERS_R54 = 54, H_REGISTERS_R55 = 55, H_REGISTERS_R56 = 56
+ , H_REGISTERS_R57 = 57, H_REGISTERS_R58 = 58, H_REGISTERS_R59 = 59, H_REGISTERS_R60 = 60
+ , H_REGISTERS_R61 = 61, H_REGISTERS_R62 = 62, H_REGISTERS_R63 = 63, H_REGISTERS_A1 = 0
+ , H_REGISTERS_A2 = 1, H_REGISTERS_A3 = 2, H_REGISTERS_A4 = 3, H_REGISTERS_V1 = 4
+ , H_REGISTERS_V2 = 5, H_REGISTERS_V3 = 6, H_REGISTERS_V4 = 7, H_REGISTERS_V5 = 8
+ , H_REGISTERS_V6 = 9, H_REGISTERS_V7 = 10, H_REGISTERS_V8 = 11, H_REGISTERS_SB = 9
+ , H_REGISTERS_SL = 10, H_REGISTERS_IP = 12
 } GR_NAMES;
 
 /* Enum declaration for +/- index register.  */

diff --git a/opcodes/epiphany-opc.c b/opcodes/epiphany-opc.c
index e761061..b97f769 100644 (file)
--- a/opcodes/epiphany-opc.c
+++ b/opcodes/epiphany-opc.c
@@ -2267,22 +2267,22 @@ static const CGEN_IBASE epiphany_cgen_macro_insn_table[] =
 /* ldrb.l $rd6,[$rn6,$direction$rm6] */
   {
     -1, "ldrbx", "ldrb.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldrb.l $rd6,[$rn6],$direction$rm6 */
   {
     -1, "ldrbp", "ldrb.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldrb.l $rd6,[$rn6,$dpmi$disp11] */
   {
     -1, "ldrbd", "ldrb.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldrb.l $rd6,[$rn6],$dpmi$disp11 */
   {
     -1, "ldrbdpm", "ldrb.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldrb $rd,[$rn] */
   {
@@ -2292,32 +2292,32 @@ static const CGEN_IBASE epiphany_cgen_macro_insn_table[] =
 /* ldrb $rd6,[$rn6] */
   {
     -1, "ldrbdl0", "ldrb", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldrb.l $rd6,[$rn6] */
   {
     -1, "ldrbdl0.l", "ldrb.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldrh.l $rd6,[$rn6,$direction$rm6] */
   {
     -1, "ldrhx", "ldrh.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldrh.l $rd6,[$rn6],$direction$rm6 */
   {
     -1, "ldrhp", "ldrh.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldrh.l $rd6,[$rn6,$dpmi$disp11] */
   {
     -1, "ldrhd", "ldrh.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldrh.l $rd6,[$rn6],$dpmi$disp11 */
   {
     -1, "ldrhdpm", "ldrh.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldrh $rd,[$rn] */
   {
@@ -2327,32 +2327,32 @@ static const CGEN_IBASE epiphany_cgen_macro_insn_table[] =
 /* ldrh $rd6,[$rn6] */
   {
     -1, "ldrhdl0", "ldrh", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldrh.l $rd6,[$rn6] */
   {
     -1, "ldrhdl0.l", "ldrh.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldr.l $rd6,[$rn6,$direction$rm6] */
   {
     -1, "ldrx", "ldr.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldr.l $rd6,[$rn6],$direction$rm6 */
   {
     -1, "ldrp", "ldr.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldr.l $rd6,[$rn6,$dpmi$disp11] */
   {
     -1, "ldrd", "ldr.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldr.l $rd6,[$rn6],$dpmi$disp11 */
   {
     -1, "ldrdpm", "ldr.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldr $rd,[$rn] */
   {
@@ -2362,32 +2362,32 @@ static const CGEN_IBASE epiphany_cgen_macro_insn_table[] =
 /* ldr $rd6,[$rn6] */
   {
     -1, "ldrdl0", "ldr", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldr.l $rd6,[$rn6] */
   {
     -1, "ldrdl0.l", "ldr.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldrd.l $rd6,[$rn6,$direction$rm6] */
   {
     -1, "ldrdx", "ldrd.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldrd.l $rd6,[$rn6],$direction$rm6 */
   {
     -1, "ldrdp", "ldrd.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldrd.l $rd6,[$rn6,$dpmi$disp11] */
   {
     -1, "ldrdd", "ldrd.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldrd.l $rd6,[$rn6],$dpmi$disp11 */
   {
     -1, "ldrddpm", "ldrd.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldrd $rd,[$rn] */
   {
@@ -2397,47 +2397,47 @@ static const CGEN_IBASE epiphany_cgen_macro_insn_table[] =
 /* ldrd $rd6,[$rn6] */
   {
     -1, "ldrddl0", "ldrd", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldrd.l $rd6,[$rn6] */
   {
     -1, "ldrddl0.l", "ldrd.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* testsetb.l $rd6,[$rn6,$direction$rm6] */
   {
     -1, "testsetbt.l", "testsetb.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* testseth.l $rd6,[$rn6,$direction$rm6] */
   {
     -1, "testsetht.l", "testseth.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* testset.l $rd6,[$rn6,$direction$rm6] */
   {
     -1, "testsett.l", "testset.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* strb.l $rd6,[$rn6,$direction$rm6] */
   {
     -1, "strbx.l", "strb.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* strb.l $rd6,[$rn6],$direction$rm6 */
   {
     -1, "strbp.l", "strb.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* strb.l $rd6,[$rn6,$dpmi$disp11] */
   {
     -1, "strbd.l", "strb.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* strb.l $rd6,[$rn6],$dpmi$disp11 */
   {
     -1, "strbdpm.l", "strb.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* strb $rd,[$rn] */
   {
@@ -2452,27 +2452,27 @@ static const CGEN_IBASE epiphany_cgen_macro_insn_table[] =
 /* strb.l $rd6,[$rn6] */
   {
     -1, "strbdl0.l", "strb.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* strh.l $rd6,[$rn6,$direction$rm6] */
   {
     -1, "strhx.l", "strh.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* strh.l $rd6,[$rn6],$direction$rm6 */
   {
     -1, "strhp.l", "strh.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* strh.l $rd6,[$rn6,$dpmi$disp11] */
   {
     -1, "strhd.l", "strh.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* strh.l $rd6,[$rn6],$dpmi$disp11 */
   {
     -1, "strhdpm.l", "strh.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* strh $rd,[$rn] */
   {
@@ -2487,27 +2487,27 @@ static const CGEN_IBASE epiphany_cgen_macro_insn_table[] =
 /* strh.l $rd6,[$rn6] */
   {
     -1, "strhdl0.l", "strh.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* str.l $rd6,[$rn6,$direction$rm6] */
   {
     -1, "strx.l", "str.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* str.l $rd6,[$rn6],$direction$rm6 */
   {
     -1, "strp.l", "str.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* str.l $rd6,[$rn6,$dpmi$disp11] */
   {
     -1, "strd.l", "str.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* str.l $rd6,[$rn6],$dpmi$disp11 */
   {
     -1, "strdpm.l", "str.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* str $rd,[$rn] */
   {
@@ -2522,27 +2522,27 @@ static const CGEN_IBASE epiphany_cgen_macro_insn_table[] =
 /* str.l $rd6,[$rn6] */
   {
     -1, "strdl0.l", "str.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* strd.l $rd6,[$rn6,$direction$rm6] */
   {
     -1, "strdx.l", "strd.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* strd.l $rd6,[$rn6],$direction$rm6 */
   {
     -1, "strdp.l", "strd.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* strd.l $rd6,[$rn6,$dpmi$disp11] */
   {
     -1, "strdd.l", "strd.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* strd.l $rd6,[$rn6],$dpmi$disp11 */
   {
     -1, "strddpm.l", "strd.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* strd $rd,[$rn] */
   {
@@ -2557,147 +2557,147 @@ static const CGEN_IBASE epiphany_cgen_macro_insn_table[] =
 /* strd.l $rd6,[$rn6] */
   {
     -1, "strddl0.l", "strd.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* moveq.l $rd6,$rn6 */
   {
     -1, "cmov.lEQ", "moveq.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movne.l $rd6,$rn6 */
   {
     -1, "cmov.lNE", "movne.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movgtu.l $rd6,$rn6 */
   {
     -1, "cmov.lGTU", "movgtu.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movgteu.l $rd6,$rn6 */
   {
     -1, "cmov.lGTEU", "movgteu.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movlteu.l $rd6,$rn6 */
   {
     -1, "cmov.lLTEU", "movlteu.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movltu.l $rd6,$rn6 */
   {
     -1, "cmov.lLTU", "movltu.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movgt.l $rd6,$rn6 */
   {
     -1, "cmov.lGT", "movgt.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movgte.l $rd6,$rn6 */
   {
     -1, "cmov.lGTE", "movgte.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movlt.l $rd6,$rn6 */
   {
     -1, "cmov.lLT", "movlt.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movlte.l $rd6,$rn6 */
   {
     -1, "cmov.lLTE", "movlte.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov.l $rd6,$rn6 */
   {
     -1, "cmov.lB", "mov.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movbeq.l $rd6,$rn6 */
   {
     -1, "cmov.lBEQ", "movbeq.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movbne.l $rd6,$rn6 */
   {
     -1, "cmov.lBNE", "movbne.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movblt.l $rd6,$rn6 */
   {
     -1, "cmov.lBLT", "movblt.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movblte.l $rd6,$rn6 */
   {
     -1, "cmov.lBLTE", "movblte.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movts.l $sn6,$rd6 */
   {
     -1, "movts.l6", "movts.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movts.l $sndma,$rd6 */
   {
     -1, "movts.ldma", "movts.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movts.l $snmem,$rd6 */
   {
     -1, "movts.lmem", "movts.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movts.l $snmesh,$rd6 */
   {
     -1, "movts.lmesh", "movts.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movfs.l $rd6,$sn6 */
   {
     -1, "movfs.l6", "movfs.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movfs.l $rd6,$sndma */
   {
     -1, "movfs.ldma", "movfs.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movfs.l $rd6,$snmem */
   {
     -1, "movfs.lmem", "movfs.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movfs.l $rd6,$snmesh */
   {
     -1, "movfs.lmesh", "movfs.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* add.l $rd6,$rn6,$rm6 */
   {
     -1, "add.l", "add.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* sub.l $rd6,$rn6,$rm6 */
   {
     -1, "sub.l", "sub.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* and.l $rd6,$rn6,$rm6 */
   {
     -1, "and.l", "and.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* orr.l $rd6,$rn6,$rm6 */
   {
     -1, "orr.l", "orr.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* eor.l $rd6,$rn6,$rm6 */
   {
     -1, "eor.l", "eor.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* add $rd,$rn,$simm3 */
   {
@@ -2732,52 +2732,52 @@ static const CGEN_IBASE epiphany_cgen_macro_insn_table[] =
 /* asr.l $rd6,$rn6,$rm6 */
   {
     -1, "asr.l", "asr.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* lsr.l $rd6,$rn6,$rm6 */
   {
     -1, "lsr.l", "lsr.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* lsl.l $rd6,$rn6,$rm6 */
   {
     -1, "lsl.l", "lsl.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* lsr.l $rd6,$rn6,$shift */
   {
     -1, "lsri32.l", "lsr.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* lsl.l $rd6,$rn6,$shift */
   {
     -1, "lsli32.l", "lsl.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* asr.l $rd6,$rn6,$shift */
   {
     -1, "asri32.l", "asr.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bitr.l $rd6,$rn6 */
   {
     -1, "bitrl", "bitr.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* fext.l $rd6,$rn6,$rm6 */
   {
     -1, "fext.l", "fext.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* fdep.l $rd6,$rn6,$rm6 */
   {
     -1, "fdep.l", "fdep.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* lfsr.l $rd6,$rn6,$rm6 */
   {
     -1, "lfsr.l", "lfsr.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov $rd,$imm8 */
   {
@@ -2792,7 +2792,7 @@ static const CGEN_IBASE epiphany_cgen_macro_insn_table[] =
 /* movt.l $rd6,$imm16 */
   {
     -1, "movtl", "movt.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* iadd $rd,$rn,$rm */
   {
@@ -2802,7 +2802,7 @@ static const CGEN_IBASE epiphany_cgen_macro_insn_table[] =
 /* fadd.l $rd6,$rn6,$rm6 */
   {
     -1, "f_addf32.l", "fadd.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* iadd $rd6,$rn6,$rm6 */
   {
@@ -2822,7 +2822,7 @@ static const CGEN_IBASE epiphany_cgen_macro_insn_table[] =
 /* fsub.l $rd6,$rn6,$rm6 */
   {
     -1, "f_subf32.l", "fsub.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* isub $rd6,$rn6,$rm6 */
   {
@@ -2842,7 +2842,7 @@ static const CGEN_IBASE epiphany_cgen_macro_insn_table[] =
 /* fmul.l $rd6,$rn6,$rm6 */
   {
     -1, "f_mulf32.l", "fmul.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* imul $rd6,$rn6,$rm6 */
   {
@@ -2862,7 +2862,7 @@ static const CGEN_IBASE epiphany_cgen_macro_insn_table[] =
 /* fmadd.l $rd6,$rn6,$rm6 */
   {
     -1, "f_maddf32.l", "fmadd.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* imadd $rd6,$rn6,$rm6 */
   {
@@ -2882,7 +2882,7 @@ static const CGEN_IBASE epiphany_cgen_macro_insn_table[] =
 /* fmsub.l $rd6,$rn6,$rm6 */
   {
     -1, "f_msubf32.l", "fmsub.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* imsub $rd6,$rn6,$rm6 */
   {
@@ -2897,27 +2897,27 @@ static const CGEN_IBASE epiphany_cgen_macro_insn_table[] =
 /* fabs.l $rd6,$rn6 */
   {
     -1, "f_absf32.l", "fabs.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* float.l $rd6,$rn6 */
   {
     -1, "f_loatf32.l", "float.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* fix.l $rd6,$rn6 */
   {
     -1, "f_ixf32.l", "fix.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* frecip.l $frd6,$frn6 */
   {
     -1, "f_recipf32.l", "frecip.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* fsqrt.l $frd6,$frn6 */
   {
     -1, "f_sqrtf32.l", "fsqrt.l", 32,
-    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 };