phy: qcom-qmp-pcie: rework regs layout arrays
authorDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Thu, 10 Nov 2022 19:22:38 +0000 (22:22 +0300)
committerVinod Koul <vkoul@kernel.org>
Thu, 12 Jan 2023 17:18:41 +0000 (22:48 +0530)
Use symbolic names for the values inside reg layout arrays.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221110192248.873973-4-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h

index d255c4f..ba83399 100644 (file)
@@ -75,24 +75,24 @@ enum qphy_reg_layout {
 };
 
 static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
-       [QPHY_SW_RESET]                         = 0x00,
-       [QPHY_START_CTRL]                       = 0x44,
-       [QPHY_PCS_STATUS]                       = 0x14,
-       [QPHY_PCS_POWER_DOWN_CONTROL]           = 0x40,
+       [QPHY_SW_RESET]                         = QPHY_V4_PCS_SW_RESET,
+       [QPHY_START_CTRL]                       = QPHY_V4_PCS_START_CONTROL,
+       [QPHY_PCS_STATUS]                       = QPHY_V4_PCS_PCS_STATUS1,
+       [QPHY_PCS_POWER_DOWN_CONTROL]           = QPHY_V4_PCS_POWER_DOWN_CONTROL,
 };
 
 static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-       [QPHY_SW_RESET]                 = 0x00,
-       [QPHY_START_CTRL]               = 0x08,
-       [QPHY_PCS_STATUS]               = 0x174,
-       [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x04,
+       [QPHY_SW_RESET]                 = QPHY_V2_PCS_SW_RESET,
+       [QPHY_START_CTRL]               = QPHY_V2_PCS_START_CONTROL,
+       [QPHY_PCS_STATUS]               = QPHY_V2_PCS_PCI_PCS_STATUS,
+       [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V2_PCS_POWER_DOWN_CONTROL,
 };
 
 static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-       [QPHY_SW_RESET]                 = 0x00,
-       [QPHY_START_CTRL]               = 0x08,
-       [QPHY_PCS_STATUS]               = 0x174,
-       [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x04,
+       [QPHY_SW_RESET]                 = QPHY_V3_PCS_SW_RESET,
+       [QPHY_START_CTRL]               = QPHY_V3_PCS_START_CONTROL,
+       [QPHY_PCS_STATUS]               = QPHY_V3_PCS_PCS_STATUS,
+       [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V3_PCS_POWER_DOWN_CONTROL,
 };
 
 static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
@@ -103,10 +103,10 @@ static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
 };
 
 static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
-       [QPHY_SW_RESET]                 = 0x00,
-       [QPHY_START_CTRL]               = 0x44,
-       [QPHY_PCS_STATUS]               = 0x14,
-       [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
+       [QPHY_SW_RESET]                 = QPHY_V4_PCS_SW_RESET,
+       [QPHY_START_CTRL]               = QPHY_V4_PCS_START_CONTROL,
+       [QPHY_PCS_STATUS]               = QPHY_V4_PCS_PCS_STATUS1,
+       [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V4_PCS_POWER_DOWN_CONTROL,
 };
 
 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
index c8515f5..2624a1e 100644 (file)
@@ -7,7 +7,9 @@
 #define QCOM_PHY_QMP_PCS_V2_H_
 
 /* Only for QMP V2 PHY - PCS registers */
+#define QPHY_V2_PCS_SW_RESET                           0x000
 #define QPHY_V2_PCS_POWER_DOWN_CONTROL                 0x004
+#define QPHY_V2_PCS_START_CONTROL                      0x008
 #define QPHY_V2_PCS_TXDEEMPH_M6DB_V0                   0x024
 #define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0                 0x028
 #define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL               0x034
@@ -43,4 +45,6 @@
 #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB    0x1dc
 #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB    0x1e0
 
+#define QPHY_V2_PCS_PCI_PCS_STATUS                     0x174 /* PCI */
+
 #endif