crypto: qat - abstract writes to arbiter enable

Abstract writes to the service arbiter enable register.

This is in preparation for the introduction of the qat_4xxx driver since
the arbitration enable register differes between QAT GEN2 and QAT GEN4
devices.

Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Reviewed-by: Wojciech Ziemba <wojciech.ziemba@intel.com>
Reviewed-by: Maksim Lukoshkov <maksim.lukoshkov@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/qat/qat_common/adf_accel_devices.h b/drivers/crypto/qat/qat_common/adf_accel_devices.h
index 1fd32c5..a3b63df 100644 (file)
--- a/drivers/crypto/qat/qat_common/adf_accel_devices.h
+++ b/drivers/crypto/qat/qat_common/adf_accel_devices.h
@@ -133,6 +133,8 @@ struct adf_hw_csr_ops {
                                      u32 value);
        void (*write_csr_int_flag_and_col)(void __iomem *csr_base_addr,
                                           u32 bank, u32 value);
+       void (*write_csr_ring_srv_arb_en)(void __iomem *csr_base_addr, u32 bank,
+                                         u32 value);
 };
 
 struct adf_cfg_device_data;

diff --git a/drivers/crypto/qat/qat_common/adf_gen2_hw_data.c b/drivers/crypto/qat/qat_common/adf_gen2_hw_data.c
index 5de3591..1aa1730 100644 (file)
--- a/drivers/crypto/qat/qat_common/adf_gen2_hw_data.c
+++ b/drivers/crypto/qat/qat_common/adf_gen2_hw_data.c
@@ -127,6 +127,12 @@ static void write_csr_int_flag_and_col(void __iomem *csr_base_addr, u32 bank,
        WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value);
 }
 
+static void write_csr_ring_srv_arb_en(void __iomem *csr_base_addr, u32 bank,
+                                     u32 value)
+{
+       WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value);
+}
+
 void adf_gen2_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops)
 {
        csr_ops->build_csr_ring_base_addr = build_csr_ring_base_addr;
@@ -142,6 +148,7 @@ void adf_gen2_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops)
        csr_ops->write_csr_int_col_en = write_csr_int_col_en;
        csr_ops->write_csr_int_col_ctl = write_csr_int_col_ctl;
        csr_ops->write_csr_int_flag_and_col = write_csr_int_flag_and_col;
+       csr_ops->write_csr_ring_srv_arb_en = write_csr_ring_srv_arb_en;
 }
 EXPORT_SYMBOL_GPL(adf_gen2_init_hw_csr_ops);
 

diff --git a/drivers/crypto/qat/qat_common/adf_gen2_hw_data.h b/drivers/crypto/qat/qat_common/adf_gen2_hw_data.h
index 04236a4..3816e65 100644 (file)
--- a/drivers/crypto/qat/qat_common/adf_gen2_hw_data.h
+++ b/drivers/crypto/qat/qat_common/adf_gen2_hw_data.h
@@ -103,6 +103,12 @@ do { \
 #define ADF_ARB_OFFSET                 0x30000
 #define ADF_ARB_WRK_2_SER_MAP_OFFSET   0x180
 #define ADF_ARB_CONFIG                 (BIT(31) | BIT(6) | BIT(0))
+#define ADF_ARB_REG_SLOT               0x1000
+#define ADF_ARB_RINGSRVARBEN_OFFSET    0x19C
+
+#define WRITE_CSR_RING_SRV_ARB_EN(csr_addr, index, value) \
+       ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
+       (ADF_ARB_REG_SLOT * (index)), value)
 
 /* Power gating */
 #define ADF_POWERGATE_PKE              BIT(24)

diff --git a/drivers/crypto/qat/qat_common/adf_hw_arbiter.c b/drivers/crypto/qat/qat_common/adf_hw_arbiter.c
index bd03c8f..9f5240d 100644 (file)
--- a/drivers/crypto/qat/qat_common/adf_hw_arbiter.c
+++ b/drivers/crypto/qat/qat_common/adf_hw_arbiter.c
@@ -6,12 +6,6 @@
 
 #define ADF_ARB_NUM 4
 #define ADF_ARB_REG_SIZE 0x4
-#define ADF_ARB_REG_SLOT 0x1000
-#define ADF_ARB_RINGSRVARBEN_OFFSET 0x19C
-
-#define WRITE_CSR_ARB_RINGSRVARBEN(csr_addr, index, value) \
-       ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
-       (ADF_ARB_REG_SLOT * index), value)
 
 #define WRITE_CSR_ARB_SARCONFIG(csr_addr, arb_offset, index, value) \
        ADF_CSR_WR(csr_addr, (arb_offset) + \
@@ -57,6 +51,7 @@ void adf_update_ring_arb(struct adf_etr_ring_data *ring)
 {
        struct adf_accel_dev *accel_dev = ring->bank->accel_dev;
        struct adf_hw_device_data *hw_data = accel_dev->hw_device;
+       struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(accel_dev);
        u32 tx_ring_mask = hw_data->tx_rings_mask;
        u32 shift = hw_data->tx_rx_gap;
        u32 arben, arben_tx, arben_rx;
@@ -73,14 +68,14 @@ void adf_update_ring_arb(struct adf_etr_ring_data *ring)
        arben_rx = (ring->bank->ring_mask & rx_ring_mask) >> shift;
        arben = arben_tx & arben_rx;
 
-       WRITE_CSR_ARB_RINGSRVARBEN(ring->bank->csr_addr,
-                                  ring->bank->bank_number,
-                                  arben);
+       csr_ops->write_csr_ring_srv_arb_en(ring->bank->csr_addr,
+                                          ring->bank->bank_number, arben);
 }
 
 void adf_exit_arb(struct adf_accel_dev *accel_dev)
 {
        struct adf_hw_device_data *hw_data = accel_dev->hw_device;
+       struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(accel_dev);
        u32 arb_off, wt_off;
        struct arb_info info;
        void __iomem *csr;
@@ -107,6 +102,6 @@ void adf_exit_arb(struct adf_accel_dev *accel_dev)
 
        /* Disable arbitration on all rings */
        for (i = 0; i < GET_MAX_BANKS(accel_dev); i++)
-               WRITE_CSR_ARB_RINGSRVARBEN(csr, i, 0);
+               csr_ops->write_csr_ring_srv_arb_en(csr, i, 0);
 }
 EXPORT_SYMBOL_GPL(adf_exit_arb);