.data = &sh73a0_pinmux_info,
},
#endif
- { },
+ { /* sentinel */ }
};
#endif
#ifdef CONFIG_PINCTRL_PFC_SHX3
{ "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
#endif
- { },
+ { /* sentinel */ }
};
static struct platform_driver sh_pfc_driver = {
FN_SEL_HSI_1_0_00, FN_SEL_HSI_1_0_01, 0, 0,
))
},
- { },
+ { /* sentinel */ }
};
const struct sh_pfc_soc_info emev2_pinmux_info = {
MSEL8CR_00_0, MSEL8CR_00_1,
))
},
- { },
+ { /* sentinel */ }
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT323_DATA, PORT322_DATA, PORT321_DATA, PORT320_DATA,
))
},
- { },
+ { /* sentinel */ }
};
static const struct pinmux_irq pinmux_irqs[] = {
MSEL5CR_0_0, MSEL5CR_0_1,
))
},
- { },
+ { /* sentinel */ }
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
0, 0, 0, 0,
0, 0, 0, 0 ))
},
- { },
+ { /* sentinel */ }
};
static const struct pinmux_irq pinmux_irqs[] = {
/* SEL_SSI0 [2] */
FN_SEL_SSI0_0, FN_SEL_SSI0_1, 0, 0, ))
},
- { },
+ { /* sentinel */ }
};
static int r8a77470_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
FN_SEL_I2C1_A, FN_SEL_I2C1_B,
))
},
- { },
+ { /* sentinel */ }
};
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a7778_pfc_ops = {
/* SEL_I2C1 [2] */
FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 ))
},
- { },
+ { /* sentinel */ }
};
const struct sh_pfc_soc_info r8a7779_pinmux_info = {
/* SEL_I2C1 [2] */
FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, ))
},
- { },
+ { /* sentinel */ }
};
static int r8a7790_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
/* RESERVED [6] */ ))
},
- { },
+ { /* sentinel */ }
};
static int r8a7791_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a7791_pfc_ops = {
/* IP7_1_0 [2] */
FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 ))
},
- { },
+ { /* sentinel */ }
};
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
FN_SEL_SSI9_0, FN_SEL_SSI9_1,
/* RESERVED [12] */ ))
},
- { },
+ { /* sentinel */ }
};
static int r8a7794_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
/* RESERVED 16-1 */
MOD_SEL2_0 ))
},
- { },
+ { /* sentinel */ }
};
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30/USB2_CH3_PWEN */
{ RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31/USB2_CH3_OVC */
} },
- { },
+ { /* sentinel */ }
};
enum ioctrl_regs {
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL] = { 0xe6060380, },
[TDSELCTRL] = { 0xe60603c0, },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static int r8a77951_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a77951_pfc_ops = {
/* RESERVED 16-1 */
MOD_SEL2_0 ))
},
- { },
+ { /* sentinel */ }
};
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
{ RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
} },
- { },
+ { /* sentinel */ }
};
enum ioctrl_regs {
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL] = { 0xe6060380, },
[TDSELCTRL] = { 0xe60603c0, },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static int r8a7796_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a7796_pfc_ops = {
/* RESERVED 16-1 */
MOD_SEL2_0 ))
},
- { },
+ { /* sentinel */ }
};
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
{ RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
} },
- { },
+ { /* sentinel */ }
};
enum ioctrl_regs {
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL] = { 0xe6060380, },
[TDSELCTRL] = { 0xe60603c0, },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static int r8a77965_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a77965_pfc_ops = {
MOD_SEL0_1
MOD_SEL0_0 ))
},
- { },
+ { /* sentinel */ }
};
enum ioctrl_regs {
[POCCTRL1] = { 0xe6060384 },
[POCCTRL2] = { 0xe6060388 },
[TDSELCTRL] = { 0xe60603c0, },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static int r8a77970_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
MOD_SEL0_1
MOD_SEL0_0 ))
},
- { },
+ { /* sentinel */ }
};
enum ioctrl_regs {
[POCCTRL2] = { 0xe6060388, },
[POCCTRL3] = { 0xe606038c, },
[TDSELCTRL] = { 0xe60603c0, },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static int r8a77980_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
MOD_SEL1_4
/* RESERVED 3, 2, 1, 0 */ ))
},
- { },
+ { /* sentinel */ }
};
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(4, 9), 17, 2 }, /* SD3_DAT7 */
{ RCAR_GP_PIN(4, 10), 14, 2 }, /* SD3_DS */
} },
- { },
+ { /* sentinel */ }
};
enum ioctrl_regs {
[POCCTRL0] = { 0xe6060380, },
[POCCTRL2] = { 0xe6060388, },
[TDSELCTRL] = { 0xe60603c0, },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static int r8a77990_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
[30] = RCAR_GP_PIN(6, 9), /* USB30_OVC */
[31] = RCAR_GP_PIN(6, 17), /* USB30_PWEN */
} },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a77990_pfc_ops = {
MOD_SEL1_26
/* RESERVED 25-0 */ ))
},
- { },
+ { /* sentinel */ }
};
enum ioctrl_regs {
[POCCTRL0] = { 0xe6060380, },
[POCCTRL2] = { 0xe6060388, },
[TDSELCTRL] = { 0xe60603c0, },
- { /* sentinel */ },
+ { /* sentinel */ }
};
MOD_SEL2_3_2
/* RESERVED 1-0 */ ))
},
- { },
+ { /* sentinel */ }
};
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(9, 17), 4, 3 }, /* AVB5_LINK */
{ RCAR_GP_PIN(9, 16), 0, 3 }, /* AVB5_PHY_INT */
} },
- { },
+ { /* sentinel */ }
};
enum ioctrl_regs {
[POC8] = { 0xe60690a0, },
[POC9] = { 0xe60698a0, },
[TD1SEL0] = { 0xe6058124, },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static int r8a779a0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a779a0_pfc_ops = {
MOD_SEL1_3_2
MOD_SEL1_1_0))
},
- { /* sentinel */ },
+ { /* sentinel */ }
};
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(3, 17), 4, 3 }, /* TSN0_AVTP_MATCH_B */
{ RCAR_GP_PIN(3, 16), 0, 3 }, /* TSN0_AVTP_PPS */
} },
- { /* sentinel */ },
+ { /* sentinel */ }
};
enum ioctrl_regs {
[POC1] = { 0xe60508a0, },
[POC3] = { 0xe60518a0, },
[TD0SEL1] = { 0xe6050920, },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static int r8a779f0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a779f0_pfc_ops = {
MOD_SEL8_1
MOD_SEL8_0))
},
- { },
+ { /* sentinel */ }
};
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(8, 9), 4, 3 }, /* SDA4 */
{ RCAR_GP_PIN(8, 8), 0, 3 }, /* SCL4 */
} },
- { },
+ { /* sentinel */ }
};
enum ioctrl_regs {
[POC6] = { 0xE60610A0, },
[POC7] = { 0xE60618A0, },
[POC8] = { 0xE60680A0, },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static int r8a779g0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a779g0_pin_ops = {
PF0MD_00, PF0MD_01, PF0MD_10, PF0MD_11,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
},
- {}
+ { /* sentinel */ }
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA ))
},
- { },
+ { /* sentinel */ }
};
const struct sh_pfc_soc_info sh7203_pinmux_info = {
PK1_IN, PK1_OUT,
PK0_IN, PK0_OUT ))
},
- {}
+ { /* sentinel */ }
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA,
PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA ))
},
- { }
+ { /* sentinel */ }
};
const struct sh_pfc_soc_info sh7264_pinmux_info = {
PJ1_IN, PJ1_OUT,
PJ0_IN, PJ0_OUT ))
},
-
- {}
+ { /* sentinel */ }
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA ))
},
-
- { }
+ { /* sentinel */ }
};
const struct sh_pfc_soc_info sh7269_pinmux_info = {
/* RESERVED [1] */
))
},
- { },
+ { /* sentinel */ }
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA ))
},
- { },
+ { /* sentinel */ }
};
static const struct pinmux_irq pinmux_irqs[] = {
PTV1_FN, PTV1_OUT, 0, PTV1_IN,
PTV0_FN, PTV0_OUT, 0, PTV0_IN ))
},
- {}
+ { /* sentinel */ }
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
0, 0, 0, PTV4_DATA,
PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA ))
},
- { },
+ { /* sentinel */ }
};
const struct sh_pfc_soc_info sh7720_pinmux_info = {
MSELB8_RGB, MSELB8_SYS,
/* RESERVED [8] */ ))
},
- {}
+ { /* sentinel */ }
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
0, 0, PTZ5_DATA, PTZ4_DATA,
PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA ))
},
- { },
+ { /* sentinel */ }
};
const struct sh_pfc_soc_info sh7722_pinmux_info = {
PSD3_PSD2_FN1, PSD3_PSD2_FN2, 0, 0,
PSD1_PSD0_FN1, PSD1_PSD0_FN2, 0, 0 ))
},
- {}
+ { /* sentinel */ }
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA ))
},
- { },
+ { /* sentinel */ }
};
const struct sh_pfc_soc_info sh7723_pinmux_info = {
PSE1_0, PSE1_1,
PSE0_0, PSE0_1))
},
- {}
+ { /* sentinel */ }
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA ))
},
- { },
+ { /* sentinel */ }
};
const struct sh_pfc_soc_info sh7724_pinmux_info = {
GP_5_1_IN, GP_5_1_OUT,
GP_5_0_IN, GP_5_0_OUT ))
},
- { },
+ { /* sentinel */ }
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA,
GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA ))
},
- { },
+ { /* sentinel */ }
};
const struct sh_pfc_soc_info sh7734_pinmux_info = {
PS8_8_FN1, PS8_8_FN2,
/* RESERVED [8] */ ))
},
- {}
+ { /* sentinel */ }
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA ))
},
- { },
+ { /* sentinel */ }
};
const struct sh_pfc_soc_info sh7757_pinmux_info = {
P2MSEL1_0, P2MSEL1_1,
P2MSEL0_0, P2MSEL0_1 ))
},
- {}
+ { /* sentinel */ }
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
0, 0, 0, 0,
PR3_DATA, PR2_DATA, PR1_DATA, PR0_DATA ))
},
- { },
+ { /* sentinel */ }
};
const struct sh_pfc_soc_info sh7785_pinmux_info = {
P2MSEL1_0, P2MSEL1_1,
P2MSEL0_0, P2MSEL0_1 ))
},
- {}
+ { /* sentinel */ }
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
PJ3_DATA, PJ2_DATA, PJ1_DATA, 0 ))
},
- { },
+ { /* sentinel */ }
};
const struct sh_pfc_soc_info sh7786_pinmux_info = {
PH1_FN, PH1_OUT, PH1_IN, 0,
PH0_FN, PH0_OUT, PH0_IN, 0, ))
},
- { },
+ { /* sentinel */ }
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
0, 0, PH5_DATA, PH4_DATA,
PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, ))
},
- { },
+ { /* sentinel */ }
};
const struct sh_pfc_soc_info shx3_pinmux_info = {
.compatible = "renesas,r7s72102-ports",
.data = &rza1l_pmx_conf,
},
- { }
+ { /* sentinel */ }
};
static struct platform_driver rza1_pinctrl_driver = {
static const struct of_device_id rzn1_pinctrl_match[] = {
{ .compatible = "renesas,rzn1-pinctrl", },
- {}
+ { /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, rzn1_pinctrl_match);
projects / platform / kernel / linux-starfive.git / commitdiff