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r300: increase maximum number of writemask combinations
authorPavel Ondračka <pavel.ondracka@gmail.com>
Thu, 27 Oct 2022 19:26:03 +0000 (21:26 +0200)
committerMarge Bot <emma+marge@anholt.net>
Mon, 14 Nov 2022 06:53:54 +0000 (06:53 +0000)
We can have up to 6 in vertex shaders.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Tested-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19618>

src/gallium/drivers/r300/compiler/radeon_regalloc.c patch | blob | history
src/gallium/drivers/r300/compiler/radeon_regalloc.h patch | blob | history

diff --git a/src/gallium/drivers/r300/compiler/radeon_regalloc.c b/src/gallium/drivers/r300/compiler/radeon_regalloc.c
index 270f27250dc0200b19cd82352af0e23abe6fefa5..c13c10c47c63a039f890cf01a71c28b3bae0cfb6 100644 (file)
--- a/src/gallium/drivers/r300/compiler/radeon_regalloc.c
+++ b/src/gallium/drivers/r300/compiler/radeon_regalloc.c
@@ -37,79 +37,136 @@ const struct rc_class rc_class_list [] = {
        {RC_REG_CLASS_SINGLE, 3,
                {RC_MASK_X,
                 RC_MASK_Y,
-                RC_MASK_Z}},
+                RC_MASK_Z,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE}},
        {RC_REG_CLASS_DOUBLE, 3,
                {RC_MASK_X | RC_MASK_Y,
                 RC_MASK_X | RC_MASK_Z,
-                RC_MASK_Y | RC_MASK_Z}},
+                RC_MASK_Y | RC_MASK_Z,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE}},
        {RC_REG_CLASS_TRIPLE, 1,
                {RC_MASK_X | RC_MASK_Y | RC_MASK_Z,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
                 RC_MASK_NONE,
                 RC_MASK_NONE}},
        {RC_REG_CLASS_ALPHA, 1,
                {RC_MASK_W,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
                 RC_MASK_NONE,
                 RC_MASK_NONE}},
        {RC_REG_CLASS_SINGLE_PLUS_ALPHA, 3,
                {RC_MASK_X | RC_MASK_W,
                 RC_MASK_Y | RC_MASK_W,
-                RC_MASK_Z | RC_MASK_W}},
+                RC_MASK_Z | RC_MASK_W,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE}},
        {RC_REG_CLASS_DOUBLE_PLUS_ALPHA, 3,
                {RC_MASK_X | RC_MASK_Y | RC_MASK_W,
                 RC_MASK_X | RC_MASK_Z | RC_MASK_W,
-                RC_MASK_Y | RC_MASK_Z | RC_MASK_W}},
+                RC_MASK_Y | RC_MASK_Z | RC_MASK_W,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE}},
        {RC_REG_CLASS_TRIPLE_PLUS_ALPHA, 1,
                {RC_MASK_X | RC_MASK_Y | RC_MASK_Z | RC_MASK_W,
-               RC_MASK_NONE,
-               RC_MASK_NONE}},
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE}},
        {RC_REG_CLASS_X, 1,
                {RC_MASK_X,
-               RC_MASK_NONE,
-               RC_MASK_NONE}},
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE}},
        {RC_REG_CLASS_Y, 1,
                {RC_MASK_Y,
-               RC_MASK_NONE,
-               RC_MASK_NONE}},
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE}},
        {RC_REG_CLASS_Z, 1,
                {RC_MASK_Z,
-               RC_MASK_NONE,
-               RC_MASK_NONE}},
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE}},
        {RC_REG_CLASS_XY, 1,
                {RC_MASK_X | RC_MASK_Y,
-               RC_MASK_NONE,
-               RC_MASK_NONE}},
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE}},
        {RC_REG_CLASS_YZ, 1,
                {RC_MASK_Y | RC_MASK_Z,
-               RC_MASK_NONE,
-               RC_MASK_NONE}},
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE}},
        {RC_REG_CLASS_XZ, 1,
                {RC_MASK_X | RC_MASK_Z,
-               RC_MASK_NONE,
-               RC_MASK_NONE}},
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE}},
        {RC_REG_CLASS_XW, 1,
                {RC_MASK_X | RC_MASK_W,
-               RC_MASK_NONE,
-               RC_MASK_NONE}},
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE}},
        {RC_REG_CLASS_YW, 1,
                {RC_MASK_Y | RC_MASK_W,
-               RC_MASK_NONE,
-               RC_MASK_NONE}},
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE}},
        {RC_REG_CLASS_ZW, 1,
                {RC_MASK_Z | RC_MASK_W,
-               RC_MASK_NONE,
-               RC_MASK_NONE}},
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE}},
        {RC_REG_CLASS_XYW, 1,
                {RC_MASK_X | RC_MASK_Y | RC_MASK_W,
-               RC_MASK_NONE,
-               RC_MASK_NONE}},
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE}},
        {RC_REG_CLASS_YZW, 1,
                {RC_MASK_Y | RC_MASK_Z | RC_MASK_W,
-               RC_MASK_NONE,
-               RC_MASK_NONE}},
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE}},
        {RC_REG_CLASS_XZW, 1,
                {RC_MASK_X | RC_MASK_Z | RC_MASK_W,
-               RC_MASK_NONE,
-               RC_MASK_NONE}}
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE,
+                RC_MASK_NONE}}
 };
 
 static void print_live_intervals(struct live_intervals * src)
diff --git a/src/gallium/drivers/r300/compiler/radeon_regalloc.h b/src/gallium/drivers/r300/compiler/radeon_regalloc.h
index bc082e965884211c53c36c41a0979dfec8343475..c7874a51ea67c0e49fce76cc8936433965984a4d 100644 (file)
--- a/src/gallium/drivers/r300/compiler/radeon_regalloc.h
+++ b/src/gallium/drivers/r300/compiler/radeon_regalloc.h
@@ -94,7 +94,7 @@ struct rc_class {
        unsigned int WritemaskCount;
 
        /** List of writemasks that belong to this class */
-       unsigned int Writemasks[3];
+       unsigned int Writemasks[6];
 };
 
 int rc_find_class(
Domain: Graphics System / GL;