i386.h (SSE_REGNO): Fix check for FIRST_REX_SSE_REG.

	* config/i386/i386.h (SSE_REGNO): Fix check for FIRST_REX_SSE_REG.
	(GET_SSE_REGNO): Rename from SSE_REGNO.  Update all uses for rename.

From-SVN: r264695

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 58a30d0..6a68c18 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,6 +1,11 @@
 2018-09-28  Uros Bizjak  <ubizjak@gmail.com>
 
-       * config/i386/i386.h (CC_REGNO): Remove FPSR_REGS.
+       * config/i386/i386.h (SSE_REGNO): Fix check for FIRST_REX_SSE_REG.
+       (GET_SSE_REGNO): Rename from SSE_REGNO.  Update all uses for rename.
+
+2018-09-28  Uros Bizjak  <ubizjak@gmail.com>
+
+       * config/i386/i386.h (CC_REGNO): Remove FPSR_REG.
        * config/i386/i386.c (ix86_fixed_condition_code_regs): Use
        INVALID_REGNUM instead of FPSR_REG.
        (ix86_md_asm_adjust): Do not clobber FPSR_REG.

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 8018f31..176cce5 100644 (file)
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -7869,7 +7869,7 @@ construct_container (machine_mode mode, machine_mode orig_mode,
       case X86_64_SSEDF_CLASS:
        if (mode != BLKmode)
          return gen_reg_or_parallel (mode, orig_mode,
-                                     SSE_REGNO (sse_regno));
+                                     GET_SSE_REGNO (sse_regno));
        break;
       case X86_64_X87_CLASS:
       case X86_64_COMPLEX_X87_CLASS:
@@ -7885,7 +7885,7 @@ construct_container (machine_mode mode, machine_mode orig_mode,
       && regclass[1] == X86_64_SSEUP_CLASS
       && mode != BLKmode)
     return gen_reg_or_parallel (mode, orig_mode,
-                               SSE_REGNO (sse_regno));
+                               GET_SSE_REGNO (sse_regno));
   if (n == 4
       && regclass[0] == X86_64_SSE_CLASS
       && regclass[1] == X86_64_SSEUP_CLASS
@@ -7893,7 +7893,7 @@ construct_container (machine_mode mode, machine_mode orig_mode,
       && regclass[3] == X86_64_SSEUP_CLASS
       && mode != BLKmode)
     return gen_reg_or_parallel (mode, orig_mode,
-                               SSE_REGNO (sse_regno));
+                               GET_SSE_REGNO (sse_regno));
   if (n == 8
       && regclass[0] == X86_64_SSE_CLASS
       && regclass[1] == X86_64_SSEUP_CLASS
@@ -7905,7 +7905,7 @@ construct_container (machine_mode mode, machine_mode orig_mode,
       && regclass[7] == X86_64_SSEUP_CLASS
       && mode != BLKmode)
     return gen_reg_or_parallel (mode, orig_mode,
-                               SSE_REGNO (sse_regno));
+                               GET_SSE_REGNO (sse_regno));
   if (n == 2
       && regclass[0] == X86_64_X87_CLASS
       && regclass[1] == X86_64_X87UP_CLASS)
@@ -7952,7 +7952,7 @@ construct_container (machine_mode mode, machine_mode orig_mode,
            exp [nexps++]
              = gen_rtx_EXPR_LIST (VOIDmode,
                                   gen_rtx_REG (SFmode,
-                                               SSE_REGNO (sse_regno)),
+                                               GET_SSE_REGNO (sse_regno)),
                                   GEN_INT (i*8));
            sse_regno++;
            break;
@@ -7960,7 +7960,7 @@ construct_container (machine_mode mode, machine_mode orig_mode,
            exp [nexps++]
              = gen_rtx_EXPR_LIST (VOIDmode,
                                   gen_rtx_REG (DFmode,
-                                               SSE_REGNO (sse_regno)),
+                                               GET_SSE_REGNO (sse_regno)),
                                   GEN_INT (i*8));
            sse_regno++;
            break;
@@ -8006,7 +8006,7 @@ construct_container (machine_mode mode, machine_mode orig_mode,
            exp [nexps++]
              = gen_rtx_EXPR_LIST (VOIDmode,
                                   gen_rtx_REG (tmpmode,
-                                               SSE_REGNO (sse_regno)),
+                                               GET_SSE_REGNO (sse_regno)),
                                   GEN_INT (pos*8));
            sse_regno++;
            break;
@@ -9322,7 +9322,7 @@ setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
          set_mem_alias_set (mem, set);
          set_mem_align (mem, GET_MODE_ALIGNMENT (smode));
 
-         emit_move_insn (mem, gen_rtx_REG (smode, SSE_REGNO (i)));
+         emit_move_insn (mem, gen_rtx_REG (smode, GET_SSE_REGNO (i)));
        }
 
       emit_label (label);

diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 6feb671..b0d2f24 100644 (file)
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -1517,10 +1517,10 @@ enum reg_class
 #define FIRST_FLOAT_REG FIRST_STACK_REG
 #define STACK_TOP_P(X) (REG_P (X) && REGNO (X) == FIRST_FLOAT_REG)
 
-#define SSE_REGNO(N) \
-  ((N) < 8 ? FIRST_SSE_REG + (N) \
-         : (N) <= LAST_REX_SSE_REG ? (FIRST_REX_SSE_REG + (N) - 8) \
-                                   : (FIRST_EXT_REX_SSE_REG + (N) - 16))
+#define GET_SSE_REGNO(N)                       \
+  ((N) < 8 ? FIRST_SSE_REG + (N)               \
+   : (N) < 16 ? FIRST_REX_SSE_REG + (N) - 8    \
+   : FIRST_EXT_REX_SSE_REG + (N) - 16)
 
 /* The class value for index registers, and the one for base regs.  */
 

diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index ed3bc7c..de77308 100644 (file)
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -1452,7 +1452,7 @@
       if (GET_CODE (elt) != SET
          || GET_CODE (SET_DEST (elt)) != REG
          || GET_MODE (SET_DEST (elt)) != V8SImode
-         || REGNO (SET_DEST (elt)) != SSE_REGNO (i)
+         || REGNO (SET_DEST (elt)) != GET_SSE_REGNO (i)
          || SET_SRC (elt) != CONST0_RTX (V8SImode))
        return false;
     }

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 1e260c0..0b65572 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -17499,7 +17499,7 @@
 
   for (regno = 0; regno < nregs; regno++)
     XVECEXP (operands[0], 0, regno + 1)
-      = gen_rtx_SET (gen_rtx_REG (V8SImode, SSE_REGNO (regno)),
+      = gen_rtx_SET (gen_rtx_REG (V8SImode, GET_SSE_REGNO (regno)),
                     CONST0_RTX (V8SImode));
 })