arm64: dts: rockchip: add thermal infrastructure to px30

Add tsadc and necessary connections to core px30 components.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Link: https://lore.kernel.org/r/20191116095249.31193-1-heiko@sntech.de

diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index 633eb91..9a0f77e 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -10,6 +10,7 @@
 #include <dt-bindings/pinctrl/rockchip.h>
 #include <dt-bindings/power/px30-power.h>
 #include <dt-bindings/soc/rockchip,boot-mode.h>
+#include <dt-bindings/thermal/thermal.h>
 
 / {
        compatible = "rockchip,px30";
@@ -176,6 +177,49 @@
                             <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
        };
 
+       thermal_zones: thermal-zones {
+               soc_thermal: soc-thermal {
+                       polling-delay-passive = <20>;
+                       polling-delay = <1000>;
+                       sustainable-power = <750>;
+                       thermal-sensors = <&tsadc 0>;
+
+                       trips {
+                               threshold: trip-point-0 {
+                                       temperature = <70000>;
+                                       hysteresis = <2000>;
+                                       type = "passive";
+                               };
+
+                               target: trip-point-1 {
+                                       temperature = <85000>;
+                                       hysteresis = <2000>;
+                                       type = "passive";
+                               };
+
+                               soc_crit: soc-crit {
+                                       temperature = <115000>;
+                                       hysteresis = <2000>;
+                                       type = "critical";
+                               };
+                       };
+
+                       cooling-maps {
+                               map0 {
+                                       trip = <&target>;
+                                       cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                       contribution = <4096>;
+                               };
+                       };
+               };
+
+               gpu_thermal: gpu-thermal {
+                       polling-delay-passive = <100>; /* milliseconds */
+                       polling-delay = <1000>; /* milliseconds */
+                       thermal-sensors = <&tsadc 1>;
+               };
+       };
+
        xin24m: xin24m {
                compatible = "fixed-clock";
                #clock-cells = <0>;
@@ -640,6 +684,26 @@
                };
        };
 
+       tsadc: tsadc@ff280000 {
+               compatible = "rockchip,px30-tsadc";
+               reg = <0x0 0xff280000 0x0 0x100>;
+               interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+               assigned-clocks = <&cru SCLK_TSADC>;
+               assigned-clock-rates = <50000>;
+               clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
+               clock-names = "tsadc", "apb_pclk";
+               resets = <&cru SRST_TSADC>;
+               reset-names = "tsadc-apb";
+               rockchip,grf = <&grf>;
+               rockchip,hw-tshut-temp = <120000>;
+               pinctrl-names = "init", "default", "sleep";
+               pinctrl-0 = <&tsadc_otp_gpio>;
+               pinctrl-1 = <&tsadc_otp_out>;
+               pinctrl-2 = <&tsadc_otp_gpio>;
+               #thermal-sensor-cells = <1>;
+               status = "disabled";
+       };
+
        saradc: saradc@ff288000 {
                compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
                reg = <0x0 0xff288000 0x0 0x100>;