RDMA/mlx5: Support SQD2RTS for modify QP
authorSergey Gorenko <sergeygo@nvidia.com>
Mon, 10 May 2021 10:23:32 +0000 (13:23 +0300)
committerJason Gunthorpe <jgg@nvidia.com>
Thu, 20 May 2021 14:41:07 +0000 (11:41 -0300)
The transition of the QP state from SQD to RTS is allowed by the IB
specification. The hardware also supports that, but it is not
implemented in mlx5_ib.

This commit adds SQD2RTS command to the modify QP in mlx5_ib to support
the missing feature. The feature is required by the signature pipelining
API that will be added to rdma-core.

Link: https://lore.kernel.org/r/ab4876360bfba0e9d64a5e8599438e32e0cb351e.1620641808.git.leonro@nvidia.com
Reviewed-by: Evgenii Kochetov <evgeniik@nvidia.com>
Signed-off-by: Sergey Gorenko <sergeygo@nvidia.com>
Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
drivers/infiniband/hw/mlx5/qp.c
drivers/infiniband/hw/mlx5/qpc.c

index 9282eb10bfaed2ff7cbee86ca0e51ac3da3af2df..38dfe29ba2b39c656baf2dc9b9521c05bffaa2b6 100644 (file)
@@ -3453,6 +3453,17 @@ static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_Q
                                           MLX5_QP_OPTPAR_RRE,
                },
        },
+       [MLX5_QP_STATE_SQD] = {
+               [MLX5_QP_STATE_RTS] = {
+                       [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
+                       [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
+                       [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
+                       [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT    |
+                                         MLX5_QP_OPTPAR_RWE            |
+                                         MLX5_QP_OPTPAR_RAE            |
+                                         MLX5_QP_OPTPAR_RRE,
+               },
+       },
 };
 
 static int ib_nr_to_mlx5_nr(int ib_mask)
@@ -3848,6 +3859,7 @@ static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
                [MLX5_QP_STATE_SQD] = {
                        [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
                        [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
+                       [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_SQD_RTS_QP,
                },
                [MLX5_QP_STATE_SQER] = {
                        [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
index c683d7000168dbce0d36c8aadb806a58d3c8e28d..8844eacf2380e34699fd6707b326baa47e9ad506 100644 (file)
@@ -441,6 +441,12 @@ static int modify_qp_mbox_alloc(struct mlx5_core_dev *dev, u16 opcode, int qpn,
                MOD_QP_IN_SET_QPC(sqerr2rts_qp, mbox->in, opcode, qpn,
                                  opt_param_mask, qpc, uid);
                break;
+       case MLX5_CMD_OP_SQD_RTS_QP:
+               if (MBOX_ALLOC(mbox, sqd2rts_qp))
+                       return -ENOMEM;
+               MOD_QP_IN_SET_QPC(sqd2rts_qp, mbox->in, opcode, qpn,
+                                 opt_param_mask, qpc, uid);
+               break;
        case MLX5_CMD_OP_INIT2INIT_QP:
                if (MBOX_ALLOC(mbox, init2init_qp))
                        return -ENOMEM;